IRF IRF7842

PD - 95864
IRF7842
HEXFET® Power MOSFET
Applications
l Synchronous MOSFET for Notebook
Processor Power
l Secondary Synchronous Rectification
for Isolated DC-DC Converters
l Synchronous Fet for Non-Isolated
DC-DC Converters
Benefits
l Very Low RDS(on) at 4.5V VGS
l Low Gate Charge
l Fully Characterized Avalanche Voltage
and Current
VDSS
RDS(on) max
Qg (typ.)
40V 5.0m:@VGS = 10V
1
8
S
2
7
S
3
6
4
5
S
G
33nC
A
A
D
D
D
D
SO-8
Top View
Absolute Maximum Ratings
Max.
Units
Drain-to-Source Voltage
Parameter
40
V
VGS
Gate-to-Source Voltage
± 20
ID @ TA = 25°C
Continuous Drain Current, VGS @ 10V
18
ID @ TA = 70°C
Continuous Drain Current, VGS @ 10V
14
IDM
Pulsed Drain Current
140
PD @TA = 25°C
Power Dissipation
PD @TA = 70°C
Power Dissipation
TJ
Linear Derating Factor
Operating Junction and
TSTG
Storage Temperature Range
VDS
f
f
c
A
2.5
W
1.6
0.02
-55 to + 150
W/°C
°C
Thermal Resistance
Parameter
RθJL
RθJA
g
Junction-to-Ambient fg
Junction-to-Drain Lead
Typ.
Max.
Units
–––
20
°C/W
–––
50
Notes  through … are on page 9
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1
4/26/04
IRF7842
Static @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
Conditions
BVDSS
Drain-to-Source Breakdown Voltage
40
–––
–––
∆ΒVDSS/∆TJ
Breakdown Voltage Temp. Coefficient
–––
0.037
–––
V/°C Reference to 25°C, ID = 1mA
RDS(on)
Static Drain-to-Source On-Resistance
–––
4.0
5.0
mΩ
–––
4.7
5.9
V
VGS = 0V, ID = 250µA
VGS = 10V, ID = 17A
VGS = 4.5V, ID = 14A
VGS(th)
Gate Threshold Voltage
1.35
–––
2.25
V
∆VGS(th)
Gate Threshold Voltage Coefficient
–––
- 5.6
–––
mV/°C
IDSS
Drain-to-Source Leakage Current
–––
–––
1.0
µA
VDS = 32V, VGS = 0V
–––
–––
150
Gate-to-Source Forward Leakage
–––
–––
100
nA
VGS = 20V
Gate-to-Source Reverse Leakage
–––
–––
-100
Forward Transconductance
81
–––
–––
Total Gate Charge
–––
33
50
Qgs1
Pre-Vth Gate-to-Source Charge
–––
9.6
–––
Qgs2
Post-Vth Gate-to-Source Charge
–––
2.8
–––
Qgd
Gate-to-Drain Charge
–––
10
–––
Qgodr
Gate Charge Overdrive
Switch Charge (Qgs2 + Qgd)
–––
10.6
–––
Qsw
–––
12.8
–––
IGSS
gfs
Qg
VGS = -20V
S
–––
18
–––
nC
Gate Resistance
–––
1.3
TBD
Ω
–––
14
–––
Rise Time
–––
12
–––
td(off)
Turn-Off Delay Time
–––
21
–––
tf
Fall Time
–––
5.0
–––
Ciss
Input Capacitance
–––
4500
–––
Coss
Output Capacitance
–––
680
–––
Crss
Reverse Transfer Capacitance
–––
310
–––
VGS = 4.5V
ID = 14A
Output Charge
Turn-On Delay Time
VDS = 20V, ID = 14A
VDS = 20V
nC
Qoss
td(on)
VDS = VGS, ID = 250µA
VDS = 32V, VGS = 0V, TJ = 125°C
RG
tr
e
e
VDS = 16V, VGS = 0V
VDD = 20V, VGS = 4.5V
e
ID = 14A
ns
Clamped Inductive Load
pF
VDS = 20V
VGS = 0V
ƒ = 1.0MHz
Avalanche Characteristics
EAS
Parameter
Single Pulse Avalanche Energy
IAR
Avalanche Current
c
d
Typ.
–––
Max.
50
Units
mJ
–––
14
A
Diode Characteristics
Parameter
Min. Typ. Max. Units
IS
Continuous Source Current
–––
–––
3.1
ISM
(Body Diode)
Pulsed Source Current
–––
–––
140
VSD
(Body Diode)
Diode Forward Voltage
–––
–––
1.0
V
trr
Reverse Recovery Time
–––
99
150
ns
Qrr
Reverse Recovery Charge
–––
11
17
nC
2
c
Conditions
MOSFET symbol
A
showing the
integral reverse
p-n junction diode.
TJ = 25°C, IS = 14A, VGS = 0V
e
TJ = 25°C, IF = 14A, VDD = 20V
di/dt = 100A/µs
e
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IRF7842
1000
1000
100
BOTTOM
TOP
10
1
2.5V
≤ 60µs PULSE WIDTH
Tj = 25°C
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
VGS
10V
5.0V
4.5V
3.5V
3.3V
3.0V
2.8V
2.5V
100
BOTTOM
2.5V
10
≤ 60µs PULSE WIDTH
Tj = 150°C
0.1
1
0.1
1
10
100
0.1
VDS, Drain-to-Source Voltage (V)
1
10
100
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000.0
2.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID, Drain-to-Source Current (Α)
VGS
10V
5.0V
4.5V
3.5V
3.3V
3.0V
2.8V
2.5V
100.0
T J = 150°C
10.0
T J = 25°C
1.0
VDS = 25V
≤ 60µs PULSE WIDTH
0.1
1.5
2.0
2.5
3.0
3.5
4.0
ID = 18A
VGS = 10V
1.5
1.0
0.5
-60 -40 -20
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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0
20
40
60
80 100 120 140 160
T J , Junction Temperature (°C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRF7842
100000
12
VGS = 0V,
f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED
C rss = C gd
VGS, Gate-to-Source Voltage (V)
ID= 14A
C, Capacitance (pF)
C oss = C ds + C gd
10000
Ciss
1000
Coss
Crss
VDS= 30V
VDS= 20V
10
8
6
4
2
0
100
1
10
0
100
20
40
60
80
QG Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
1000.0
1000
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100
100.0
T J = 150°C
10.0
T J = 25°C
1.0
10
1msec
1
10msec
Tc = 25°C
Tj = 150°C
Single Pulse
VGS = 0V
0.1
0.1
0.2
0.4
0.6
0.8
1.0
VSD, Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
1.2
0
1
10
100
1000
VDS , Drain-toSource Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRF7842
2.4
18
VGS(th) Gate threshold Voltage (V)
16
ID , Drain Current (A)
14
12
10
8
6
4
2
2.0
ID = 250µA
1.6
1.2
0.8
0.4
0
25
50
75
100
125
-75
150
-50
-25
25
50
75
100
125
150
T J , Temperature ( °C )
T J , Junction Temperature (°C)
Fig 9. Maximum Drain Current Vs.
Case Temperature
0
Fig 10. Threshold Voltage Vs. Temperature
100
D = 0.50
0.20
0.10
0.05
0.02
0.01
Thermal Response ( Z thJA )
10
1
R1
R1
0.1
τJ
0.01
τJ
τ1
τ1
R2
R2
τ2
τ2
Ci= τi/Ri
Ci τi/Ri
τ3
τC
τ
τ3
Ri (°C/W) τi (sec)
10.48
0.138167
26.83
1.8582
12.69
44.8
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthja + Tc
SINGLE PULSE
( THERMAL RESPONSE )
0.001
R3
R3
0.0001
1E-006
1E-005
0.0001
0.001
0.01
0.1
1
10
100
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
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5
RDS(on), Drain-to -Source On Resistance ( mΩ)
IRF7842
200
EAS, Single Pulse Avalanche Energy (mJ)
16
ID = 18A
12
8
T J = 125°C
4
T J = 25°C
0
2.0
4.0
6.0
8.0
10.0
ID
6.7A
7.5A
BOTTOM 14A
TOP
160
120
80
40
0
25
VGS, Gate-to-Source Voltage (V)
50
75
100
125
150
Starting T J, Junction Temperature (°C)
Fig 12. On-Resistance Vs. Gate Voltage
Fig 13c. Maximum Avalanche Energy
Vs. Drain Current
15V
LD
VDS
L
VDS
DRIVER
+
VDD -
D.U.T
RG
IAS
VGS
20V
tp
+
V
- DD
D.U.T
A
VGS
0.01Ω
Pulse Width < 1µs
Duty Factor < 0.1%
Fig 13a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
Fig 14a. Switching Time Test Circuit
VDS
90%
10%
VGS
I AS
Fig 13b. Unclamped Inductive Waveforms
6
td(on)
tr
td(off)
tf
Fig 14b. Switching Time Waveforms
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IRF7842
D.U.T
Driver Gate Drive
+
P.W.
ƒ
+
‚
-
-
„
•
•
•
•
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
VDD
P.W.
Period
*

RG
D=
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
Period
+
-
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Id
Current Regulator
Same Type as D.U.T.
Vds
Vgs
50KΩ
12V
.2µF
.3µF
D.U.T.
+
V
- DS
Vgs(th)
VGS
3mA
IG
ID
Current Sampling Resistors
Fig 16. Gate Charge Test Circuit
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Qgs1 Qgs2
Qgd
Qgodr
Fig 17. Gate Charge Waveform
7
IRF7842
SO-8 Package Details
D
5
A
8
6
7
6
5
H
1
6X
2
3
0.25 [.010]
4
A
e
e1
8X b
0.25 [.010]
A
A1
MILLIMET ERS
MIN
MAX
MIN
.0532
.0688
1.35
1.75
A1 .0040
.0098
0.10
0.25
b
.013
.020
0.33
0.51
c
.0075
.0098
0.19
0.25
D
.189
.1968
4.80
5.00
E
.1497
.1574
3.80
4.00
e
.050 BASIC
1.27 BASIC
e1
A
E
INCHES
DIM
B
MAX
.025 BASIC
0.635 BAS IC
H
.2284
.2440
5.80
6.20
K
.0099
.0196
0.25
0.50
L
.016
.050
0.40
1.27
y
0°
8°
0°
8°
K x 45°
C
y
0.10 [.004]
8X L
8X c
7
C A B
FOOT PRINT
NOT ES :
1. DIMENS IONING & T OLERANCING PER AS ME Y14.5M-1994.
8X 0.72 [.028]
2. CONT ROLLING DIMENS ION: MILLIMET ER
3. DIMENS IONS ARE S HOWN IN MILLIMET ERS [INCHES ].
4. OUT LINE CONFORMS T O JEDEC OUT LINE MS -012AA.
5 DIMENS ION DOES NOT INCLUDE MOLD PROT RUS IONS .
MOLD PROT RUS IONS NOT T O EXCEED 0.15 [.006].
6 DIMENS ION DOES NOT INCLUDE MOLD PROT RUS IONS .
MOLD PROT RUS IONS NOT T O EXCEED 0.25 [.010].
6.46 [.255]
7 DIMENS ION IS THE LENGT H OF LEAD F OR S OLDERING T O
A S UBS T RAT E.
3X 1.27 [.050]
8X 1.78 [.070]
SO-8 Part Marking
EXAMPLE: T HIS IS AN IRF7101 (MOS FET)
INT ERNAT IONAL
RECTIFIER
LOGO
XXXX
F7101
DAT E CODE (YWW)
P = DES IGNAT ES LEAD-FREE
PRODUCT (OPT IONAL)
Y = LAS T DIGIT OF T HE YEAR
WW = WEEK
A = AS S EMBLY S IT E CODE
LOT CODE
PART NUMBER
8
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IRF7842
SO-8 Tape and Reel
TERMINAL NUMBER 1
12.3 ( .484 )
11.7 ( .461 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
NOTES:
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS(INCHES).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
330.00
(12.992)
MAX.
14.40 ( .566 )
12.40 ( .488 )
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. OUTLINE CONFORMS TO EIA-481 & EIA-541.
Notes:
 Repetitive rating; pulse width limited by
max. junction temperature.
‚ Starting TJ = 25°C, L = 0.5mH
RG = 25Ω, IAS = 14A.
ƒ Pulse width ≤ 400µs; duty cycle ≤ 2%.
„ When mounted on 1 inch square copper board
… Rθ is measured at TJ approximately 90°C
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.4/04
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