LH52258A FEATURES • Fast Access Times: 20/25 ns • Low-Power Standby when Deselected • TTL Compatible I/O • 5 V ± 10% Supply • Fully-Static Operation • JEDEC Standard Pinout • Packages: 28-Pin, 300-mil DIP 28-Pin, 300-mil SOJ FUNCTIONAL DESCRIPTION The LH52258A is a high-speed 262,144 bit static RAM organized as 32K × 8. A fast, efficient design is obtained with a CMOS periphery and a matrix constructed with polysilicon load memory cells. This RAM is fully static in operation. The Chip Enable (E) control permits Read and Write operations when active (LOW) or places the RAM in a low-power standby mode when inactive (HIGH). Standby power (ISB1) drops to its lowest level if E is raised to within 0.2 V of VCC. Write cycles occur when both Chip Enable (E) and Write Enable (W) are LOW. Data is transferred from the DQ pins to the memory location specified by the 15 address lines. The proper use of the Output Enable control (G) can prevent bus contention. CMOS 32K × 8 Static RAM When E is LOW and W is HIGH, a static Read will occur at the memory location specified by the address lines. G must be brought LOW to enable the outputs. Since the device is fully static in operation, new Read cycles can be performed by simply changing the address. High-frequency design techniques should be employed to obtain the best performance from this device. Solid, low-impedance power and ground planes, with high-frequency decoupling capacitors, are recommended. Series termination of the inputs should be considered when transmission line effects occur. PIN CONNECTIONS 28-PIN DIP 28-PIN SOJ TOP VIEW A14 1 28 VCC A12 2 27 W A7 3 26 A13 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 A3 7 22 G A2 8 21 A10 A1 9 20 E A0 10 19 DQ7 DQ0 11 18 DQ6 DQ1 12 17 DQ5 DQ2 13 16 DQ4 VSS 14 15 DQ3 52258A-1D Figure 1. Pin Connections for DIP and SOJ Packages 1 CMOS 32K × 8 Static RAM LH52258A A5 A1 A2 A6 A7 ROW DECODER A4 MEMORY ARRAY (32,768 x 8) A12 A14 DQ0 - DQ7 8 8 I/O CIRCUIT BLOCK DECODE A0 COLUMN DECODE A10 A3 A11 A9 A8 A13 8 E W G 52258A-2 Figure 2. LH52258A Block Diagram TRUTH TABLE 2 PIN DESCRIPTIONS E G W MODE DQ I CC PIN DESCRIPTION H X X Not Selected High-Z Standby A0 – A14 Address Inputs L H H Selected High-Z Active DQ0 – DQ7 Data Inputs/Outputs L L H Read Data Out Active E Chip Enable L X L Write Data In Active G Output Enable W Write Enable VCC Positive Power Supply VSS Ground CMOS 32K × 8 Static RAM LH52258A ABSOLUTE MAXIMUM RATINGS 1 PARAMETER RATING VCC to VSS Potential –0.5 V to 7 V Input Voltage Range –0.5 V to VCC + 0.5 V DC Output Current ± 40 mA 2 Storage Temperature Range –65o to 150oC Power Dissipation (Package Limit) 1.0 W NOTES: 1. Stresses greater than those listed under ‘Absolute Maximum Ratings’ may cause permanent damage to the device. This is a stress rating for transient conditions only. Functional operation of the device at these or any other conditions above those indicated in the ‘Operating Range’ section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Outputs should not be shorted for more than 30 seconds. No more than one output should be shorted at any time. OPERATING RANGES SYMBOL PARAMETER TA Temperature, Ambient VCC Supply Voltage VSS Supply Voltage VIL Logic ‘0’ Input Voltage VIH Logic ‘1’ Input Voltage MIN TYP 0 1 MAX UNIT 70 oC 4.5 5.0 5.5 V 0 0 0 V –0.5 0.8 V 2.2 VCC + 0.5 V NOTE: 1. Negative undershoot of up to 3.0 V is permitted once per cycle. DC ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER TEST CONDITIONS MIN TYP 1 MAX UNIT ICC1 Operating Current 2 tRC = 20 ns G ≥ VIH, E ≤ VIL, IOUT = 0 mA, tCYCLE = 20 ns 95 150 mA ICC1 Operating Current 2 tRC = 25 ns G ≥ VIH, E ≤ VIL, IOUT = 0 mA, tCYCLE = 25 ns 90 140 mA ISB1 Standby Current E ≥ VCC – 0.2 V 0.005 1 mA ISB2 Standby Current E ≥ VIH 6 15 mA ILI Input Leakage Current VCC = 5.5 V, VIN = 0 V to VCC –2 2 µA ILO I/O Leakage Current VCC = 5.5 V, VIN = 0 V to VCC –2 2 µA VOH Output High Voltage IOH = –4.0 mA 2.4 VOL Output Low Voltage IOL = 8.0 m A VDR Data Retention Voltage E ≥ VCC – 0.2 V IDR Data Retention Current VCC = 3 V, E ≥ VCC – 0.2 V 2 V 0.4 V 5.5 V 250 µA NOTES: 1. Typical values at VCC = 5 V, TA = 25°C. 2. I CC is dependent upon output loading and cycle rates. Specified values are with outputs open, operating at specified cycle times. 3 CMOS 32K × 8 Static RAM LH52258A AC TEST CONDITIONS PARAMETER Input Pulse Levels RATING +5 V V SS to 3 V Input Rise and Fall Times 3 ns Input and Output Timing Ref. Levels 1.5 V Output Load, Timing Tests 480 Ω DQ PINS Figure 3 255 Ω CAPACITANCE 30 pF * 1,2 PARAMETER RATING CIN (Input Capacitance) 7 pF CDQ (I/O Capacitance) 8 pF * INCLUDES JIG AND SCOPE CAPACITANCES NOTES: 1. Capacitances are maximum values at 25oC measured at 1.0 MHz with VBias = 0 V and VCC = 5.0 V. 2. Guaranteed but not tested. 52258A-3 Figure 3. Output Load Circuit DATA RETENTION TIMING E must be held above the lesser of VIH or VCC – 0.2 V to prevent improper operation when VCC < 4.5 V. E must be VCC – 0.2 V or greater to meet IDR specification. All other inputs are ‘Don’t Care.’ 0 ns VCC 4.5 V E VIH VDR VIL tRC MIN E ≥ VDR - 0.2 V 52258A-4 Figure 4. Data Retention Timing 4 CMOS 32K × 8 Static RAM LH52258A AC ELECTRICAL CHARACTERISTICS 1 (Over Operating Range) SYMBOL –2 0 DESCRIPTION MIN –25 MAX MIN UNITS MAX READ CYCLE tRC Read Cycle Time tAA Address Access Time tOH Output Hold from Address Change tEA E Low to Valid Data tELZ E Low to Output Active 2,3 20 20 4 4 4 2,3 E High to Output High-Z tGA G Low to Valid Data tGLZ G Low to Output Active 2,3 0 4 10 0 0 tGHZ G High to Output High-Z tPU E Low to Power Up Time 3 E High to Power Down Time 0 0 3 0 12 ns 12 ns ns 10 0 25 ns ns 0 9 ns ns 25 10 2,3 ns 25 20 tEHZ tPD 25 ns ns 30 ns WRITE CYCLE tWC Write Cycle Time 20 25 ns tEW E Low to End of Write 15 20 ns tAW Address Valid to End of Write 15 20 ns tAS Address Setup 0 0 ns tAH Address Hold from End of Write 0 0 ns tWP W Pulse Width 12 15 ns tDW Input Data Setup Time 10 12 ns tDH Input Data Hold Time 0 0 ns tWHZ W Low to Output High-Z 2,3 tWLZ 2,3 W High to Output Active 8 0 10 0 ns ns NOTES: 1. AC Electrical Characteristics specified at ‘AC Test Conditions’ levels. 2. Active output to High-Z and High-Z to output active tests specified for a ±500 mV transition from steady state levels into the test load. The test load has 5 pF capacitances. 3. Guaranteed by design but not tested. 5 CMOS 32K × 8 Static RAM LH52258A TIMING DIAGRAMS – READ CYCLE Read Cycle No. 2 Read Cycle No. 1 Chip is in Read Mode: W is HIGH. Timing illustrated for the case when addresses are valid before E goes LOW. Data Out is not specified to be valid until tEA or tGA, but may become valid as soon as tELZ or tGLZ. Outputs will transition from High-Z to Valid Data Out. Valid data will be present following tGA only if tEA timing is met. Chip is in Read Mode: W is HIGH, E is LOW and G is LOW. Read cycle timing is referenced from when all addresses are stable until the first address transition. Crosshatched portion of Data Out implies that data lines are in the Low-Z state but the data is not guaranteed to be valid until tAA. tRC ADDRESS VALID ADDRESS tAA DQ tOH VALID DATA PREVIOUS DATA 52258A-5 Figure 5. Read Cycle No. 1 tRC E tPD tEHZ tEA G tGA tGLZ tGHZ tELZ VALID DATA DQ tPU SUPPLY CURRENT 52258A-6 Figure 6. Read Cycle No. 2 6 CMOS 32K × 8 Static RAM LH52258A TIMING DIAGRAMS – WRITE CYCLE Write Cycle No. 1 (W Controlled) Addresses must be stable during Write cycles. The outputs will remain in the High-Z state if W is LOW when E goes LOW. If G is HIGH, the outputs will remain in the High-Z state. Although these examples illustrate timing with G active, it is recommended that G be held HIGH for all Write cycles. This will prevent the LH52258A’s outputs from becoming active, preventing bus contention, thereby reducing system noise. Chip is selected: E is LOW, G is LOW. Using only W to control Write cycles may not offer the best performance since both tWHZ and tDW timing specifications must be met. Write Cycle No. 2 (E Controlled) G is LOW. DQ lines may transition to Low-Z if the falling edge of W occurs after the falling edge of E. tWC ADDRESS VALID ADDRESS tAW tAS tAH tWP W tDW tWHZ tWLZ tDH DQ DATA ON DQ LINES PREVIOUS OUTPUT HIGH-Z INPUT LOW-Z 52258A-7 Figure 7. Write Cycle No. 1 tWC ADDRESS VALID ADDRESS tEW E tAS tWP tAH W tELZ tDW tWHZ tDH DQ DATA ON DQ LINES HIGH-Z LOW-Z HIGH-Z INPUT 52258A-8 Figure 8. Write Cycle No. 2 7 CMOS 32K × 8 Static RAM LH52258A PACKAGE DIAGRAMS 28SK-DIP (DIP028-P-0300) DETAIL 28 15 7.05 [0.278] 6.65 [0.262] 1 0° TO 15° 14 0.35 [0.014] 0.15 [0.006] 35.00 [1.378] 34.40 [1.354] 7.62 [0.300] TYP. 3.65 [0.144] 3.25 [0.128] 4.40 [0.173] 4.00 [0.157] 3.40 [0.134] 3.00 [0.118] 2.54 [0.100] TYP. DIMENSIONS IN MM [INCHES] 0.51 [0.020] MIN. 0.56 [0.022] 0.36 [0.014] MAXIMUM LIMIT MINIMUM LIMIT 28DIP-1 28-pin, 300-mil DIP 28SOJ (SOJ28-P-300) 28 DETAIL 15 7.9 [0.311] 7.5 [0.295] 1 8.63 [0.340] 8.23 [0.324] 14 3.7 [0.146] 3.3 [0.130] 2.6 [0.102] 2.2 [0.087] 0.64 [0.025] MIN 18.7 [0.736] 18.3 [0.720] 0.8 [0.031] 0.6 [0.024] 0.102 [0.004] 0.20 [0.008] 1.27 [0.050] TYP. DIMENSIONS IN MM [INCHES] 0.53 [0.021] 0.33 [0.013] 1.15 [0.045] 0.85 [0.033] MAXIMUM LIMIT MINIMUM LIMIT 28SOJ300 28-pin, 300-mil SOJ 8 7.0 [0.276] 6.6 [0.260] CMOS 32K × 8 Static RAM LH52258A ORDERING INFORMATION LH52258A Device Type X Package - ## Speed 20 25 Access Time (ns) D 28-pin, 300-mil DIP (DIP28-P-300) K 28-pin, 300-mil SOJ (SOJ28-P-300) CMOS 32K x 8 Static RAM Example: LH52258AK-25 (CMOS 32K x 8 Static RAM, 25 ns, 28-pin, 300-mil SOJ) 52258AMD 9