LH5332600 FEATURES • 4,194,304 × 8 bit organization (Byte mode: BYTE = VIL) 2,097,152 × 16 bit organization (Word mode: BYTE = VIH) • Access time: 100 ns (MAX.) CMOS 32M (4M × 8/2M × 16) MROM PIN CONNECTIONS 44-PIN SOP TOP VIEW NC 1 44 A20 A18 2 43 A19 A17 3 42 A8 A7 4 41 A9 • Supply current: – Operating: 100 mA (MAX.) – Standby: 100 µA (MAX.) A6 5 40 A10 A5 6 39 A11 A4 7 38 A12 A3 8 37 A13 • TTL compatible I/O A2 9 36 A14 A1 10 35 • Three-state output A15 A0 11 34 A16 CE 12 33 BYTE GND 13 32 GND OE 14 31 D15/A-1 (NOTE) • Packages: 44-pin, 600-mil SOP 48-pin, 12 mm × 18 mm2 TSOP (Type I) D0 15 30 D7 D8 16 29 D14 D1 17 28 D6 D9 18 27 D13 • Others: – Non programmable – Not designed or rated as radiation hardened – CMOS process (P type silicon substrate) D2 19 26 D5 D10 20 25 D12 D3 21 24 D4 D11 22 23 VCC • Single +5 V power supply • Static operation NOTE: The D15/A-1 pin becomes LSB address input (A-1) when the BYTE pin is set to be LOW in byte mode and data output (D15) when set to be HIGH in word mode. 5332600N-1 DESCRIPTION Figure 1. SOP Pin Connections The LH5332600 is a 32M-bit mask-programmable ROM organized as 4,194,304 × 8 bits (Byte mode) or 2,097,152 × 16 bits (Word mode) that can be selected by a BYTE input pin. It is fabricated using silicon-gate CMOS process technology. 1 LH5332600 CMOS 32M (4M x 8/2M x 16) MROM 48-PIN TSOP (Type I) TOP VIEW BYTE 1 48 A16 2 47 GND A15 3 46 D15/A-1 (NOTE) A14 4 45 D7 A13 5 44 D14 A12 6 43 D6 GND A11 7 42 D13 A10 8 41 D5 A9 9 40 D12 A8 10 39 D4 A19 11 38 VCC GND 12 37 VCC A20 13 36 GND A18 14 35 D11 A17 15 34 D3 A7 16 33 D10 A6 17 32 D2 31 D9 A5 18 A4 19 30 D1 A3 20 29 D8 A2 21 28 D0 A1 22 27 OE A0 23 26 GND CE 24 25 GND NOTE: The D15/A-1 pin becomes LSB address input (A-1) when the BYTE pin is set to be LOW in byte mode and data output (D15) when set to be HIGH in word mode. 5332600T-1 Figure 2. TSOP Pin Connections 2 CMOS 32M (4M x 8/2M x 16) MROM LH5332600 A20 44 DATA SELECTOR/OUTPUT BUFFER A10 40 A9 41 A8 42 A7 4 MEMORY MATRIX (4,194,304 x 8) (2,097,152 x 16) ADDRESS DECODER A14 36 A13 37 A12 38 A11 39 ADDRESS BUFFER A19 43 A18 2 A17 3 A16 34 A15 35 A6 5 A5 6 A4 7 A3 8 COLUMN SELECTOR A2 9 A1 10 A0 11 CE 12 CE BUFFER OE 14 OE BUFFER BYTE 33 BYTE/WORD SWITCHOVER CIRCUIT TIMING GENERATOR 31 D15 29 D14 27 D13 25 D12 22 D11 20 D10 18 D9 16 D8 30 D7 28 D6 26 D5 24 D4 21 D3 19 D2 17 D1 15 D0 SENSE AMPLIFIER ADDRESS BUFFER 31 A-1 23 VCC 13 32 GND 5332600N-2 Figure 3. LH5332600 Block Diagram PIN DESCRIPTION SIGNAL PIN NAME SIGNAL PIN NAME A-1 - A20 Address input OE Output enable input D0 - D15 Data output VCC Power supply ×8bit / ×16 bit (byte/word) mode select input GND Ground BYTE CE NC No connection (Non wire bonding) Chip enable input 3 LH5332600 CMOS 32M (4M x 8/2M x 16) MROM TRUTH TABLE CE OE DATA OUTPUT A-1 (D15) BYTE ADDRESS INPUT D0 - D7 D8 - D15 LSB MSB SUPPLY CURRENT H X X X High-Z High-Z Standby (ISB) L H X X High-Z High-Z Operating L L H D 0 - D7 D8 - D15 A0 A20 Operating L L L L D0 - D7 High-Z A-1 A20 Operating L L L H D8 - D15 High-Z A-1 A20 Operating NOTES: X = Don’t care; High-Z = High-impedance ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING UNIT Supply voltage VCC -0.3 to +7.0 V Input voltage VIN -0.3 to VCC + 0.3 V Output voltage VOUT -0.3 to VCC + 0.3 V Operating temperature TOPR 0 to +70 °C Storage temperature TSTG -65 to +150 °C RECOMMENDED OPERATING CONDITIONS (TA = 0 to +70°C) PARAMETER SYMBOL MIN. TYP. MAX. UNIT VCC 4.5 5.0 5.5 V Supply voltage DC ELECTRICAL CHARACTERISTICS (VCC = 5 V ±10%, TA = 0 to +70°C) PARAMETER SYMBOL CONDITIONS MIN. MAX. UNIT NOTE Input ‘High’ voltage V IH 2.2 VCC + 0.3 V Input ‘Low’ voltage VIL -0.3 0.8 V Output ‘High’ voltage VOH I OH = -400 µA 2.4 V Output ‘Low’ voltage VOL I OL = 2.0 mA 0.4 V Input leakage current | ILI | V IN = 0 V to VCC 10 µA Output leakage current | ILO | V OUT = 0 V to VCC 10 µA 1 ICC1 t RC = 100 ns 100 t RC = 1 µs mA 2 ICC2 90 ISB1 CE = VIH 2 mA ISB2 CE = VCC - 0.2 V 100 µA 10 pF 10 pF Operating current Standby current Input capacitance Output capacitance CIN COUT NOTES: 1. CE = VIH, OE = VIH 2. VIN = VIH or VIL, CE = VIL, output is open 4 f = 1 MHz, t A = 25°C CMOS 32M (4M x 8/2M x 16) MROM LH5332600 AC ELECTICAL CHARACTERISTICS (VCC = 5 V ±10%, TA = 0 to +70°C) PARAMETER SYMBOL MIN. MAX. UNIT NOTE Read cycle time tRC 100 ns Address access time tAA 100 ns Chip enable access time tACE 100 ns Output enable delay time tOE 50 ns Output hold time tOH 5 ns tCHZ 40 ns tOHZ 40 ns Output floating time 1 NOTE: 1. Determined by the time for the output to be opened. (Irrespective of output voltage) AC TEST CONDITIONS PARAMETER Input voltage amplitude RATING 0.4 V to 2.6 V Input rise/fall time 10 ns Input signal fall time 10 ns Input reference level 1.5 V Output reference level 1.5 V Output load condition 1TTL + 100 pF CAUTION It is recommended that a decoupling capacitor be connected between VCC and GND-Pin. 5 LH5332600 CMOS 32M (4M x 8/2M x 16) MROM tRC A-1 - A20 tAA (NOTE) CE tCHZ tACE (NOTE) OE tOE (NOTE) tOHZ tOH tOLZ D0 - D7 DATA VALID NOTE: The output data becomes valid when the last intervals, tAA, tACE, or tOE, have concluded. 5332600N-3 Figure 4. Byte Mode (BYTE = VIL) tRC A-1 - A20 tAA (NOTE) CE tCHZ tACE (NOTE) OE tOE (NOTE) (D0 - D15) tOHZ tOH DATA VALID NOTE: The output data becomes valid when the last intervals, tAA, tACE, or tOE, have concluded. Figure 5. Word Mode (BYTE = VIH) 6 5332600N-4 CMOS 32M (4M x 8/2M x 16) MROM LH5332600 PACKAGE DIAGRAM 44SOP (SOP044-P-0600) 1.27 [0.050] TYP. 0.50 [0.020] 0.30 [0.012] 44 23 16.40 [0.646] 15.60 [0.614] 13.40 [0.528] 13.00 [0.512] 1 14.40 [0.567] SEE DETAIL 22 2.9 [0.114] 2.5 [0.098] 0.20 [0.008] 0.10 [0.004] 28.40 [1.118] 28.00 [1.102] DETAIL 1.275 [0.050] 0.15 [0.006] 1.275 [0.050] 0.25 [0.010] 0.05 [0.002] 2.9 [0.114] 2.5 [0.098] 3.25 [0.128] 2.45 [0.096] 0.25 [0.010] 0.05 [0.002] 0 - 10° 0.80 [0.031] 1.275 [0.050] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 44SOP 48TSOP (TSOP048-P-1218) 0.50 [0.020] TYP. 0.30 [0.012] 0.10 [0.004] 25 48 16.60 [0.654] 16.20 [0.638] 1 18.40 [0.724] 17.60 [0.693] 17.00 [0.669] 24 12.20 [0.480] 11.80 [0.465] 0.15 [0.006] 0.425 [0.017] 0.20 [0.008] 0.10 [0.004] 1.10 [0.043] 0.90 [0.035] 1.20 [0.047] MAX. 0.425 [0.017] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 0.20 [0.008] 0.00 [0.000] 48TSOP 7 LH5332600 CMOS 32M (4M x 8/2M x 16) MROM ORDERING INFORMATION LH5332600 Device Type X Package N 44-pin, 600-mil SOP (SOP044-P-0600) T 48-pin, 12 mm x 18 mm2 TSOP (Type I) (TSOP048-P-1218) CMOS 32M (4M x 8 or 2M x 16) Mask-Programmable ROM Example: LH5332600N (CMOS 32M (4M x 8 or 2M x 16) Mask-Programmable ROM, 44-pin, 600-mil SOP) 5332600N-5 8