AGERE TMXF28155

Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
1 Features
■
■
Versatile IC supports 155/51 Mbits/s SONET/SDH
interface solutions for T3/E3, DS2, T1/E1/J1, and
DS0/E0/J0 applications.
Implementation supports both linear (1 + 1, unprotected) and ring (UPSR) network topologies.
■
Provides full termination of up to 21 E1, 28 T1, or
28 J1.
■
Low power 3.3 V supply.
■
–40 °C to +85 °C industrial temperature range.
■
456-pin ball grid array (PBGA) package.
■
Complies with Bellcore*, ITU, ANSI †, ETSI and Japanese TTC standards: GR-253-CORE, GR-499,
(ATT) TR-62411, ITU-T G.707, G.704, G.706, G.783,
G.962, G.964, G.965, Q.542, T1.105, JT-G704,
JT-G706, JT-G707, JT-I431-a, ETS 300 417-1-1,
ETS 300 011, T1.107, T1.404.
1.2 STS/STM Pointer Interpreter
■
Interprets STS/AU/TU-3 pointers.
■
Synchronizes 8 kHz frame and 2 kHz superframe to
system/shelf timing reference by setting the transmit
STS-3/STM-1 pointers to a fixed value of 522.
■
Monitors/terminates SPE path overhead.
1.3 Telecom Bus Interface
■
Telecom bus interface to mate devices including
clock, data[8], parity, SPE-, J0-, J1-, and V1 timing
indicator.
■
Line and path RDI and REI signals passed to mate
devices.
■
Three Super Mapper devices, two configured as
mate devices, provide full termination of an
STS-3/STM-1. A three-chip solution to terminate
84 DS1s/J1s or 63 E1s.
1.1 SONET/SDH Interface
1.4 VT Termination/Generation (x28/x21)
■
Termination of a single 155 Mbits/s STS-3/STM-1 or
single 51 Mbits/s STS-1/STM-0.
■
Built-in clock and data recovery circuit at
155 Mbits/s STS-3/STM-1 interface (can be deselected if external clock recovery is provided).
■
Supports overhead processing for all transport and
path overhead bytes.
■
Optional insertion and extraction of overhead bytes
via a serial transport overhead access channel. Configurable as dedicated DCC channels.
■
Software controlled linear 1 + 1 protection via dedicated interface to protection card.
■
Full path termination and SPE extraction/insertion.
■
SONET/SDH compliant condition and alarm reporting.
■
Built-in diagnostic loopback modes.
■
8 kHz line frame sync output.
* Bellcore is now Telcordia Technologies. Telcordia Technologies is a
trademark of Telcordia Technologies, Inc.
† ANSI is a registered trademark of American National Standards
Institute, Inc.
■
Monitors/terminates VT path overhead for
28 VT1.5/TU-11 or 21 VT2/TU-12.
■
Synchronizes VT/TU SPE to system/shelf timing reference by setting the transmit VT/TU pointers to fixed
values for asynchronous mapping or by dynamically
changing the transmit VT/TU pointers for byte synchronous mapping.
■
Fixed pointer generation in transmit side for asynchronous mapping.
■
Dynamic pointer generation in transmit side for bytesynchronous mapping.
1.5 Mapping/Multiplexing Modes (x28/x21)
■
Maps DS3 clear channel or framed signal into STS-1
or TUG-3.
■
Maps T1/E1/J1 into VT/TU (including DS1 into
TU-12).
■
Supports asynchronous, byte-synchronous, and bitsynchronous mapping.
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
1 Features (continued)
■
Supports UPSR applications via the dedicated ring
interface and an external tributary selector.
■
Supports all valid T1/E1/J1 multiplexing structures
into STS-1 and STS-3/STM-1:
— STS-3/STS-1/SPE/VTG/VTx
— STM-1/AU-3/TUG-2/TU-1x/VC-1x
— STM-1/AU-4/TUG-3/TUG-2/TU-1x/VC-1x
■
Allows grooming of VTs/TUs in granularity of TUG-2s
within the STS-3/STM-1 signal.
■
Supports J2 trace identifier monitoring/insertion.
■
Configurable VT/TU slot selection for DS1, E1, and
J1 insertion and drop.
■
■
Automatic receive monitor functions include VT/TU
RDI-V, REI-V, BIP-2 errors, AIS-V, LOP-V.
Complies with GR-253-CORE, GR-499, ITU-T
G.707, G.704, G.783, T1.105, JT-G707, ETS 300
417-1-1.
Preliminary Data Sheet
May 2001
■
Sources may be broadcast, looped back, or routed
to/from a test-pattern generator or monitor.
■
Any DS1 or E1 channel may be routed through the
jitter attenuator.
■
DS3 may be configured for the M13 to interconnect
with the SPE, or external I/O to interconnect with the
M13 or SPE.
1.8 Jitter Attenuation
■
PLL-free receive operation using built-in digital jitter
attenuator (in VT/VC mode or M13 mode).
■
Configurable to meet jitter and MTIE requirements.
1.9 PDH Interfaces
■
One DS3, 7x DS2.
■
x28/x21 framed or unframed DS1 or E1 interfaces.
■
One additional dedicated protection channel for
DS2/DS1/E1.
1.6 M13 Features
■
Configurable multiplexer/demultiplexer for 28 DS1
signals, 21 E1 signals, or 7 DS2 signals to/from a
DS3 signal.
■
Operates in either M23 or C-bit parity mode.
■
Provisionable time slot selection for DS1, E1, and
DS2 insertion or drop.
■
■
■
■
Full alarm monitoring and generation (LOS, BPV,
EXZ, OOF, SEF, AIS, RAI, FEAC, P-bit and C-bit parity errors, FEBE).
HDLC transmitter with 128-byte data buffer and
HDLC receiver with 128-byte data FIFO for the C-bit
parity path maintenance data link.
DS3, DS2, DS1, and E1 loopback and loopback
request generation.
1.10 T1/E1/J1 Framing Features (x28/x21)
■
x28/x21 T1/E1/J1 channels.
■
Line coding: B8ZS, HDB3, ZCS, AMI, and
CMI (JJ20-11).
■
T1 framing modes: ESF, D4, SLC ®-96, T1 DM DDS,
and SF (Ft only).
■
E1 framing: G.704 basic and CRC-4 multiframe consistent with G.706.
■
J1 framing modes: JESF (Japan).
■
Supports T1 and E1 unframed and transparent transmission format.
■
T1 signaling modes: transparent;
register and system access for ESF 2-state, 4-state,
and 16-state; D4 2-state, 4-state, and 16-state;
SLC-96 2-state, 4-state, and 16-state; J-ESF handling groups maintenance and signaling; VT 1.5
SPE 2, 4, 16 state.
■
E1 signaling modes: transparent;
register and system access for entire TS16 multiframe structure as per ITU G.732.
■
Signaling debounce and change of state interrupt.
■
V5.2 Sa7 processing.
Complies with T1.102, T1.107, T1.231, T1.403,
T1.404, GR 499, G.747, and G.775.
1.7 DS3/DS2/DS1/E1 Cross Connect
■
Highly configurable interconnect for up to 28 DS1 or
21 E1 signals to/from the framer, external pins, M13,
or VT mappers.
■
Supports up to seven DS2 signals to/from the external pins or M13.
2
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
1 Features (continued)
1.11 System Test and Maintenance
■
Alarm reporting and performance monitoring per
AT&T, ANSI, ITU-T, and ETSI standards.
■
A variety of loopback modes implemented on
SONET/SDH side as well as on framer level.
■
Facility data link features:
— HDLC or transparent access for either ESF or
DDS + FDL frame formats.
— Register/stack access for SLC-96 transmit and receive data.
— Extended superframe (ESF): automatic transmission of the ESF performance report messages
(PRM). Automatic transmission of the ANSI
T1.403 ESF performance report messages. Automatic detection and transmission of the ANSI
T1.403 ESF FDL bit-oriented codes.
— Register/stack access for all CEPT Sa-bits transmit and receive data.
■
Built-in test pattern generator and monitor configurable for simultaneously testing E1, DS1, DS2, and
DS3 (one channel each).
■
■
HDLC features:
— HDLC or transparent mode.
— Programmable logical channel assignment: any
time slot, any bit for ISDN D-channel, also inserts/
extracts C-channels for V5.1, V5.2 interfaces.
— 64 logical channels in both transmit and receive direction (any framing format).
— Maximum channel data rate: 64 kbits/s.
— Minimum channel data rate: 4 kbits/s (DS1-FDL or
E1 Sa bit).
— 128-byte FIFO per channel in both transmit and receive direction.
— Tx to Rx loopback supported.
System interfaces:
— Concentration highway interface: Single clock and
frame sync signals; programmable clock rates at
2.048 MHz, 4.096 MHz, 8.192 MHz, and
16.384 MHz; programmable data rates at 2.048
Mbits/s,
4.096 Mbits/s, and 8.192 Mbits/s; programmable
clock edges and bit/byte offsets.
— Parallel system bus interface at 19.44 MHz for
data and signaling: single clock and frame sync
signals.
— Time-division multiplex data rate serial interface at
1.544 MHz or 2.048 MHz. Twenty-eight receive
data, clock, and frame sync signals. Twenty-eight
transmit data signals with a global clock and frame
sync.
— Network serial multiplexed interface minimal pin
count serial interface at 51.84 MHz optimized for
data and IMA applications.
Agere Systems Inc.
Microprocessor Interface
■
20-bit address and 16-bit data interface with 16 MHz
to 66 MHz read and write access.
■
Compatible with most industry-standard processors.
Chip Testing and Maintenance
■
IEEE * 1149.1 JTAG boundary scan.
Interface to Other Agere ME Devices
Seamless interface to the following Agere Systems’
devices:
■
TADM042G5.
* IEEE is a registered trademark of the Institute of Electrical and
Electronics Engineers, Inc.
3
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
Table of Contents
By Major Sections
Contents
Page
Features ...................................................................................................................................................................1
Product Description .................................................................................................................................................. 5
Preface ...................................................................................................................................................................5
Interface Specifications ............................................................................................................................................ 8
Pin Information .......................................................................................................................................................8
Electrical Characteristics ...................................................................................................................................... 33
Timing Characteristics ......................................................................................................................................... 37
Ordering Information ............................................................................................................................................ 61
Register Description ............................................................................................................................................... 62
Microprocessor Interface and Global Control and Status Registers .................................................................... 62
TMUX Registers ...................................................................................................................................................75
SPE Mapper Registers ...................................................................................................................................... 133
VT/TU Mapper Registers ................................................................................................................................... 153
M13/M23 MUX/DeMUX Registers ..................................................................................................................... 196
28-Channel Framer Registers ............................................................................................................................ 239
Cross Connect (XC) Registers ........................................................................................................................... 321
Digital Jitter Attenuation Controller Registers .................................................................................................... 331
Test-Pattern Generation/Detection Registers ..................................................................................................... 336
Functional Descriptions ........................................................................................................................................ 354
Microprocessor Interface Functional Description ...............................................................................................354
TMUX Functional Description ............................................................................................................................ 359
SPE Mapper Functional Description ..................................................................................................................396
VT/TU Mapper Functional Description ............................................................................................................... 425
M13/M23 MUX/DeMUX Block Functional Description ....................................................................................... 455
28-Channel Framer Block Functional Description .............................................................................................. 475
Cross Connect (XC) Block Functional Description ............................................................................................ 542
Digital Jitter Attenuation Controller Functional Description ................................................................................ 570
Test-Pattern Generation/Detection Functional Description ................................................................................ 574
Philosophies ....................................................................................................................................................... 582
Applications .......................................................................................................................................................... 588
Change History .................................................................................................................................................. 604
4
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Product Description
2 Preface
Table of Contents
Contents
Page
1 Features ............................................................................................................................................................... 1
1.1 SONET/SDH Interface ................................................................................................................................... 1
1.2 STS/STM Pointer Interpreter ......................................................................................................................... 1
1.3 Telecom Bus Interface ................................................................................................................................... 1
1.4 VT Termination/Generation (x28/x21) ............................................................................................................ 1
1.5 Mapping/Multiplexing Modes (x28/x21) ......................................................................................................... 1
1.6 M13 Features ................................................................................................................................................. 2
1.7 DS3/DS2/DS1/E1 Cross Connect .................................................................................................................. 2
1.8 Jitter Attenuation ............................................................................................................................................ 2
1.9 PDH Interfaces ............................................................................................................................................... 2
1.10 T1/E1/J1 Framing Features (x28/x21) ......................................................................................................... 2
1.11 System Test and Maintenance .................................................................................................................... 3
2 Preface ................................................................................................................................................................. 5
2.1 Major Categories ............................................................................................................................................ 6
2.2 Naming Convention for Registers and Parameters ....................................................................................... 6
2.3 Overview ........................................................................................................................................................ 7
Figures
Page
Figure 1. Functional Diagram of Super Mapper ....................................................................................................... 7
Agere Systems Inc.
5
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
2 Preface (continued)
The objective of this data sheet is to define the functionality of the Super Mapper for hardware and software developers. The information contained in this data
sheet is preliminary, and may change without notice;
the reader must therefore ascertain that the latest version is used when a product is under development.
The latest version of this data sheet can be accessed
at: http://www.lucent.com/micro/netcom/products/
pdh.html#super_mapper.
2.1 Major Categories
This data sheet is divided into six major categories with
sub-sections as follows:
■
■
■
■
Features
Product Description
— Features
— Preface
— Overview
Interface Specifications
— Pin Information
— Electrical Characteristics
— Timing Characteristics
— Ordering Information
Register Descriptions
— Microprocessor Interface Registers
— TMUX Registers
— SPE Mapper Registers
— VT/UT Mapper Registers
— M13/M23 MUX/deMUX Registers
— 28-Channel Framer Registers
— Cross Connect (XC) Registers
— Digital Jitter Attenuation Registers
— Test Pattern Generation/Detection Registers
■
Functional Descriptions
— Microprocessor Interface Description
— TMUX Registers Description
— SPE Mapper Registers Description
— VT/UT Mapper Registers Description
— M13/M23 MUX/deMUX Registers Description
— 28-Channel Framer Registers Description
— Cross Connect (XC) Registers Description
— Digital Jitter Attenuation Registers Description
— Test Pattern Generation/Detection Registers Description
■
Applications
— Application Block Diagrams and Descriptions
6
Preliminary Data Sheet
May 2001
2.2 Naming Convention for Registers and
Parameters
There are many provisioning registers for controlling
the Super Mapper. A naming convention for all registers and parameters (bit names) is followed throughout
this data sheet. A prefix is attached to the base name
of each register or parameter, depending on which
functional section the register or parameter is associated with:
■
SMPR_, for the Microprocessor Interface
■
TMUX_, for the TMUX
■
SPE_, for the SPE Mapper
■
VT_, for the VT/VC Mapper
■
M13_, for the M13/M23 MUX/deMUX
■
FRM_, for the 28-Channel Framer
■
XC_, for the Cross Connect
■
DJA_, for the Digital Jitter Attenuator
■
TPG_ and TPM_, for the Test-Pattern Generator/
Detection
A suffix is appended to the base name of three common parameters:
■
_IS, for interrupt signal.
■
_IM, for interrupt mask.
■
_SWRS, for software reset.
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
2 Preface (continued)
2.3 Overview
The SONET/SDH Super Mapper device integrates the SONET/SDH line, path, and tributary termination functions
with M13 multiplex functions and the primary rate framing function. It is designed to drive an OC-3/STM-1 optical
signal directly or to allow for modular growth in terminal or add/drop applications.
It provides a versatile interface for all STS-3/STM-1 and STS-1 termination applications in point-to-point scenarios
and for ring applications. This chip can be used in tributary shelf applications for up to 28 T1 or J1 or 21 E1 line
cards providing all possible mappings into SONET/SDH. Because of the flexibility of the mappings, software
upgrades from M13 mapped connections to VT/TU mapped connections are possible. This device can also be
used for DS3/DS2 applications.
A single Super Mapper is capable of processing the aggregate bandwidth of one STS-1 or DS3. By communicating
to two other mate devices via the telecom bus interface, the Super Mapper is capable of terminating a full
STS-3/STM-1 signal.
RPOAC
SYS
CLK
SYNC
TPOAC
TELECOM BUS
OVERHEAD
TERMINATION
SYSTEM INTERFACE
BUS
TCB AND TDL
DS2AISCLK RCB AND RDL
DS3
T1/E1/J1
FRAMING
MAPPING &
MULTIPLEXING
DS0/E0
(XN)
DS1 (X29)
/E1 (X22)
FRAMER
BANK
M13
MUX
DS2 (X7)
SPE/
STS-1/
AU-3
DS1/E1
(NSMI MODE)
AU-3
MAPPER
STS-3
STM-1
T1/E1
DS2
DS3
TMUX
CROSS
CONNECT
TEST
PATTERN
GEN/MON
DIGITAL
JITTER
ATTENUATOR
MPU INTERFACE
AND CONTROL
RTOAC
DS3/STS1
(NSMI MODE)
LINETX
VT/VC
MAPPER
MSP
1+1
LINERX
DS1XCLK
E1XCLK
TTOAC
MPU INTERFACE
LOPOHIN
LOPOHOUT
MISC
5-8923(F)
Figure 1. Functional Diagram of Super Mapper
Agere Systems Inc.
7
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
Interface Specifications
3 Pin Information
Table of Contents
Contents
Page
3 Pin Information ..................................................................................................................................................... 8
3.1 456-Pin PBGA Pin Diagram ........................................................................................................................... 9
3.2 Pin Assignments ............................................................................................................................................ 9
3.3 Pin Descriptions ........................................................................................................................................... 15
3.3.1 High-speed I/O Pin Descriptions ........................................................................................................ 15
3.3.2 Protection Switch I/O Pin Description ................................................................................................ 16
3.3.3 Telecom Bus (Low-speed I/O) Pin Description .................................................................................. 16
3.3.4 TOAC and POAC ............................................................................................................................... 19
3.3.5 Miscellaneous Signals ........................................................................................................................ 20
3.3.6 DS3 Port ............................................................................................................................................. 20
3.3.7 M13 Multiplexer/Demultiplexer Receive Section ................................................................................ 22
3.3.8 Low-Order Path Overhead Access Channel ...................................................................................... 23
3.3.9 Framer PLL ........................................................................................................................................ 27
3.3.10 Test Pins .......................................................................................................................................... 30
3.4 Outline Diagram ........................................................................................................................................... 32
3.4.1 456-Pin PBGA .................................................................................................................................... 32
List of Figures
Figure 2. Pin Diagram of 456-Pin PBGA (Bottom View)........................................................................................... 9
Figure 3. Protection Switch..................................................................................................................................... 16
Figure 4. DS1/E1 to DXC Block Diagram ............................................................................................................... 23
List of Tables
Table 1. Pin Assignments for 456-Pin PBGA by Pin Number Order ....................................................................... 9
Table 2. Pin Assignments for 456-Pin PBGA by Signal Name .............................................................................. 12
Table 3. High-speed I/O Pin Descriptions ............................................................................................................. 15
Table 4. Protection Switch I/O Pin Description ...................................................................................................... 16
Table 5. Telecom Bus (Low-speed I/O) Pin Description ........................................................................................ 17
Table 6. TOAC and POAC .................................................................................................................................... 19
Table 7. Miscellaneous Signals ............................................................................................................................. 20
Table 8. DS3 Port .................................................................................................................................................. 21
Table 9. DS3 Port, C-Bit, and Datalink Access ..................................................................................................... 22
Table 10. M13 Multiplexer/Demultiplexer Receive Section ................................................................................... 22
Table 11. Low-Order Path Overhead Access Channel ......................................................................................... 23
Table 12. Multifunction System Interface Transmit Path Direction ........................................................................ 24
Table 13. Framer PLL ............................................................................................................................................ 27
Table 14. Microprocessor Interfaces ..................................................................................................................... 28
Table 15. General Purpose Interface .................................................................................................................... 29
Table 16. Test Pins ................................................................................................................................................ 30
Table 17. CDR Power ............................................................................................................................................ 30
Table 18. LVDS Control Pins ................................................................................................................................. 30
8
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
3 Pin Information (continued)
3.1 456-Pin PBGA Pin Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
A1
BALL
CORNER
5-8931(F)
Figure 2. Pin Diagram of 456-Pin PBGA (Bottom View)
3.2 Pin Assignments
r
Table 1. Pin Assignments for 456-Pin PBGA by Pin Number Order
Pin
Signal Name
Pin
Signal Name
Pin
A1
VDD
A21
VSS
B15
A2
VSS
A22
VDD
B16
A3
LINERXDATA17
A23
LINETXSYNC12
B17
A4
LINERXDATA18
A24
LINETXSYNC13
B18
A5
VDD
A25
VSS
A6
VSS
A26
VDD
Signal Name
Pin
Signal Name
LINETXDATA2
C9
LINERXSYNC24
LINETXSYNC4
C10
LINERXCLK25
LINETXSYNC5
C11
LINERXCLK26
LINETXSYNC6
C12
LINERXCLK27
B19
LINETXCLK7
C13
LINERXDATA28
B20
LINETXDATA8
C14
LINETXSYNC2
A7
LINERXDATA21
B1
VSS
B21
LINETXSYNC10
C15
LINETXCLK3
A8
LINERXSYNC23
B2
LINERXCLK15
B22
LINETXDATA10
C16
LINETXCLK4
A9
LINERXCLK24
B3
LINERXSYNC18
B23
LINETXDATA11
C17
LINETXCLK5
A10
VDD
B4
LINERXSYNC19
B24
LINETXDATA12
C18
LINETXDATA6
A11
VSS
B5
LINERXSYNC20
B25
LINETXCLK13
C19
LINETXSYNC8
A12
LINERXDATA27
B6
LINERXDATA20
B26
V SS
C20
LINETXCLK9
A13
LINERXSYNC29
B7
LINERXSYNC22
C1
LINERXSYNC15
C21
LINETXCLK10
A14
LINETXDATA1
B8
LINERXCLK23
C2
LINERXDATA14
C22
LINETXCLK11
A15
LINETXSYNC3
B9
LINERXDATA24
C3
LINERXCLK17
C23
LINETXCLK12
A16
VSS
B10
LINERXDATA25
C4
LINERXCLK18
C24
LINETXCLK14
A17
VDD
B11
LINERXDATA26
C5
LINERXCLK19
C25
LINETXSYNC15
A18
LINETXCLK6
B12
LINERXSYNC28
C6
LINERXCLK20
C26
LINETXDATA14
A19
LINETXDATA7
B13
LINERXCLK29
C7
LINERXCLK21
D1
LINERXSYNC14
A20
LINETXSYNC9
B14
LINETXCLK1
C8
LINERXDATA22
D2
LINERXDATA13
Agere Systems Inc.
9
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
3 Pin Information
Preliminary Data Sheet
May 2001
(continued)
Table 1. Pin Assignments for 456-Pin PBGA by Pin Number Order (continued)
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
D3
LINERXCLK14
E21
LINETXDATA13
J25
LINETXDATA21
N1
LINERXDATA3
D4
VSS
E22
VDD
J26
LINETXCLK21
N2
LINERXCLK3
D5
LINERXDATA19
E23
LINETXDATA16
K1
VDD
N3
LINERXSYNC4
D6
LINERXSYNC21
E24
LINETXCLK16
K2
LINERXSYNC7
N4
LINERXSYNC3
D7
LINERXCLK22
E25
LINETXSYNC17
K3
LINERXCLK7
N5
SCAN_EN
D8
LINERXDATA23
E26
VDD
K4
LINERXDATA6
N11
V SS
D9
LINERXSYNC25
F1
VSS
K5
LINERXSYNC16
N12
V SS
D10
LINERXSYNC26
F2
LINERXSYNC12
K22
DS3NEGDATAIN
N13
V SS
D11
LINERXSYNC27
F3
LINERXCLK12
K23
LINETXSYNC23
N14
V SS
D12
LINERXCLK28
F4
LINERXDATA11
K24
LINETXCLK22
N15
V SS
D13
LINERXDATA29
F5
LINERXDATA15
K25
LINETXDATA22
N16
V SS
D14
LINETXSYNC1
F22
LINETXSYNC14
K26
VDD
N22
DS3DATAOUTCLK
D15
LINETXCLK2
F23
LINETXSYNC18
L1
V SS
N23
LINETXDATA26
D16
LINETXDATA3
F24
LINETXCLK17
L2
LINERXSYNC6
N24
LINETXDATA25
D17
LINETXDATA4
F25
LINETXDATA17
L3
LINERXCLK6
N25
LINETXCLK26
D18
LINETXDATA5
F26
VSS
L4
LINERXDATA5
N26
LINETXSYNC26
D19
LINETXSYNC7
G1
LINERXSYNC11
L5
VDD
P1
LINERXSYNC2
D20
LINETXCLK8
G2
LINERXDATA10
L11
V SS
P2
LINERXCLK2
D21
LINETXDATA9
G3
LINERXCLK11
L12
VSS
P3
LINERXDATA1
D22
LINETXSYNC11
G4
LINERXCLK10
L13
V SS
P4
LINERXDATA2
D23
VSS
G5
VSS
L14
V SS
P5
IDDQ
D24
LINETXCLK15
G22
VSS
L15
V SS
P11
V SS
D25
LINETXSYNC16
G23
LINETXCLK19
L16
V SS
P12
V SS
D26
LINETXDATA15
G24
LINETXCLK18
L22
VDD
P13
V SS
E1
VDD
G25
LINETXSYNC19
L23
LINETXSYNC24
P14
V SS
E2
LINERXDATA12
G26
LINETXDATA18
L24
LINETXCLK23
P15
V SS
E3
LINERXCLK13
H1
LINERXDATA9
L25
LINETXDATA23
P16
VSS
E4
LINERXSYNC13
H2
LINERXCLK9
L26
V SS
P22
DS3NEGDATAOUT
E5
VDD
H3
LINERXSYNC10
M1
LINERXSYNC5
P23
LINETXSYNC27
E6
LINERXSYNC17
H4
LINERXSYNC9
M2
LINERXDATA4
P24
LINETXSYNC28
E7
VSS
H5
LINERXDATA16
M3
LINERXCLK5
P25
LINETXCLK27
E8
TDLDATA
H22
RDLDATA
M4
LINERXCLK4
P26
LINETXDATA27
E9
TDLCLK
H23
LINETXDATA20
M5
SCAN_MODE
R1
RLSDATA7
E10
DS2AISCLK
H24
LINETXDATA19
M11
VSS
R2
LINERXSYNC1
E11
V DD
H25
LINETXCLK20
M12
V SS
R3
RLSDATA6
E12
TCBDATA
H26
LINETXSYNC20
M13
V SS
R4
LINERXCLK1
E13
TCBCLK
J1
LINERXCLK8
M14
V SS
R5
TCK
E14
TCBSYNC
J2
LINERXSYNC8
M15
V SS
R11
V SS
E15
RCBDATA
J3
LINERXDATA8
M16
V SS
R12
V SS
E16
V DD
J4
LINERXDATA7
M22
DS3POSDATAIN
R13
V SS
E17
RCBCLK
J5
LINERXCLK16
M23
LINETXCLK25
R14
V SS
E18
RCBSYNC
J22
DS3DATAINCLK
M24
LINETXCLK24
R15
V SS
E19
RDLCLK
J23
LINETXSYNC22
M25
LINETXSYNC25
R16
VSS
E20
VSS
J24
LINETXSYNC21
M26
LINETXDATA24
R22
DS3POSDATAOUT
10
Agere Systems Inc.
Preliminary Data Sheet
May 2001
3 Pin Information
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
(continued)
Table 1. Pin Assignments for 456-Pin PBGA by Pin Number Order (continued)
Pin
Signal Name
Pin
R23
LINETXCLK28
W5
R24
LINETXCLK29
W22
Signal Name
Pin
Signal Name
Pin
Signal Name
TMSN
AB19
TXDATAEN
AB20
RXDATAEN
AD11
RPSC155N
VDD
AD12
REF14
R25
LINETXDATA28
W23
DATA4
AB21
MODE2_PLL
AD13
TPSC155N
R26
LINETXSYNC29
W24
DATA7
AB22
VDD
AD14
ECSEL
T1
VSS
W25
DATA5
AB23
ADDR19
AD15
TSTSFTLD
T2
RLSDATA4
W26
DATA6
AB24
INTN
AD16
DS1XCLK
T3
RLSDATA3
Y1
TLSDATA2
AB25
DATA15
AD17
MPMODE
T4
RLSDATA5
Y2
TLSDATA3
AB26
VDD
AD18
DSN
T5
VDD
Y3
TLSDATA1
AC1
RLSSYNC52
AD19
ADDR3
T11
VSS
Y4
TLSDATA4
AC2
RLSC52
AD20
ADDR7
T12
VSS
Y5
VSS
AC3
TLSC52
AD21
ADDR10
T13
VSS
Y22
VSS
AC4
V SS
AD22
VDDD_PLL
T14
VSS
Y23
DATA8
AC5
TPOACSYNC
AD23
VSSS_PLL
T15
VSS
Y24
DATA11
AC6
AUTO_AIS1
AD24
CLKIN_PLL
T16
VSS
Y25
DATA9
AC7
RHSCP
AD25
ADDR16
T22
VDD
Y26
DATA10
AC8
THSSYNCP
AD26
ADDR15
T23
LINETXDATA29
AA1
VSS
AC9
VDDA_CDR
AE1
V SS
T24
RSTN
AA2
TLSCLK
AC10
RPSC155P
AE2
TTOACDATA
T25
PMRST
AA3
TLSPAR
AC11
REF10
AE3
RPOACCLK
T26
VSS
AA4
TLSDATA0
AC12
TPSC155P
AE4
TPOACCLK
U1
VDD
AA5
RTOACSYNC
AC13
LOPOHCLKIN
AE5
LOSEXT
U2
RLSDATA1
AA22
ADDR13
AC14
LOPOHDATAIN
AE6
AUTO_AIS2
U3
RLSDATA0
AA23
DATA12
AC15
ETOGGLE
AE7
RHSDN
U4
RLSDATA2
AA24
DATA14
AC16
TSTMUX0
AE8
THSCN
U5
TDI
AA25
DATA13
AC17
E1XCLK
AE9
THSDN
U22
PHASEDETDOWN
AA26
VSS
AC18
CSN
AE10
RPSD155N
U23
DTN
AB1
VDD
AC19
ADDR0
AE11
CTAPTH
U24
PAR1
AB2
TLSSPE
AC20
ADDR4
AE12
RESLO
U25
PAR0
AB3
TLSV1
AC21
ADDR8
AE13
TPSD155N
U26
VDD
AB4
TLSJ0J1V1
AC22
ADDR12
AE14
BYPASS
V1
RLSSPE
AB5
VDD
AC23
VSS
AE15
EXDNUP
V2
RLSPAR
AB6
TTOACCLK
AC24
ADDR17
AE16
TSTMUX1
V3
RLSJ0J1V1
AB7
VSS
AC25
APS_INTN
AE17
MPCLK
V4
RLSCLK
AB8
TRSTN
AC26
ADDR18
AE18
ADSN
V5
TDO
AB9
IC3STATEN
AD1
RTOACCLK
AE19
ADDR1
V22
PHASEDETUP
AB10
CTAPRH
AD2
TLSSYNC52
AE20
ADDR5
V23
DATA0
AB11
VDD
AD3
RTOACDATA
AE21
ADDR9
V24
DATA3
AB12
VSSA_CDR
AD4
RPOACDATA
AE22
ADDR11
V25
DATA1
AB13
CTAPRP
AD5
TPOACDATA
AE23
VDDS_PLL
V26
DATA2
AB14
LOPOHVALIDIN
AD6
AUTO_AIS3
AE24
MODE1_PLL
W1
TLSDATA6
AB15
LOPOHCLKOUT
AD7
RHSFSYNCN
AE25
ADDR14
W2
TLSDATA7
AB16
VDD
AD8
RHSCN
AE26
VSS
W3
TLSDATA5
AB17
LOPOHDATAOUT
AD9
THSSYNCN
AF1
VDD
W4
RLSV1
AB18
LOPOHVALIDOUT
AD10
RPSD155P
AF2
VSS
Agere Systems Inc.
11
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
3 Pin Information
Preliminary Data Sheet
May 2001
(continued)
Table 1. Pin Assignments for 456-Pin PBGA by Pin Number Order (continued)
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
AF3
TTOACSYNC
AF9
THSDP
A15
TSTMODE
AF21
VSS
AF4
RPOACSYNC
AF10
VDD
A16
V SS
AF22
VDD
AF5
VDD
AF11
VSS
A17
VDD
AF23
VSSA_PLL
AF6
VSS
A12
REWSHI
A18
RWMN
AF24
MODE0_PLL
AF7
RHSDP
AF13
TPSD155P
A19
ADDR2
AF8
THSCP
AF14
TSTPHASE
AF20
ADDR6
Table 2. Pin Assignments for 456-Pin PBGA by Signal Name
12
Signal Name
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
Pin
ADDR0
AC19
CTAPRP
AB13
ECSEL
AD14
LINERXCLK24
A9
ADDR1
AE19
CTAPTH
AE11
ETOGGLE
AC15
LINERXCLK25
C10
ADDR2
AF19
DATA0
V23
EXDNUP
AE15
LINERXCLK26
C11
ADDR3
AD19
DATA1
V25
IC3STATEN
AB9
LINERXCLK27
C12
ADDR4
AC20
DATA2
V26
IDDQ
P5
LINERXCLK28
D12
ADDR5
AE20
DATA3
V24
INTN
AB24
LINERXCLK29
B13
ADDR6
AF20
DATA4
W23
LINERXCLK1
R4
LINERXDATA1
P3
ADDR7
AD20
DATA5
W25
LINERXCLK2
P2
LINERXDATA2
P4
ADDR8
AC21
DATA6
W26
LINERXCLK3
N2
LINERXDATA3
N1
ADDR9
AE21
DATA7
W24
LINERXCLK4
M4
LINERXDATA4
M2
ADDR10
AD21
DATA8
Y23
LINERXCLK5
M3
LINERXDATA5
L4
ADDR11
AE22
DATA9
Y25
LINERXCLK6
L3
LINERXDATA6
K4
ADDR12
AC22
DATA10
Y26
LINERXCLK7
K3
LINERXDATA7
J4
ADDR13
AA22
DATA11
Y24
LINERXCLK8
J1
LINERXDATA8
J3
ADDR14
AE25
DATA12
AA23
LINERXCLK9
H2
LINERXDATA9
H1
ADDR15
AD26
DATA13
AA25
LINERXCLK10
G4
LINERXDATA10
G2
ADDR16
AD25
DATA14
AA24
LINERXCLK11
G3
LINERXDATA11
F4
ADDR17
AC24
DATA15
AB25
LINERXCLK12
F3
LINERXDATA12
E2
ADDR18
AC26
DS1XCLK
AD16
LINERXCLK13
E3
LINERXDATA13
D2
ADDR19
AB23
DS2AISCLK
E10
LINERXCLK14
D3
LINERXDATA14
C2
ADSN
AE18
DS3DATAINCLK
J22
LINERXCLK15
B2
LINERXDATA15
F5
APS_INTN
AC25
DS3DATAOUTCLK
N22
LINERXCLK16
J5
LINERXDATA16
H5
AUTO_AIS1
AC6
DS3NEGDATAIN
K22
LINERXCLK17
C3
LINERXDATA17
A3
AUTO_AIS2
AE6
DS3NEGDATAOUT
P22
LINERXCLK18
C4
LINERXDATA18
A4
AUTO_AIS3
AD6
DS3POSDATAIN
M22
LINERXCLK19
C5
LINERXDATA19
D5
BYPASS
AE14
DS3POSDATAOUT
R22
LINERXCLK20
C6
LINERXDATA20
B6
CLKIN_PLL
AD24
DSN
AD18
LINERXCLK21
C7
LINERXDATA21
A7
CSN
AC18
DTN
U23
LINERXCLK22
D7
LINERXDATA22
C8
CTAPRH
AB10
E1XCLK
AC17
LINERXCLK23
B8
LINERXDATA23
D8
Agere Systems Inc.
Preliminary Data Sheet
May 2001
3 Pin Information
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
(continued)
Table 2. Pin Assignments for 456-Pin PBGA by Signal Name (continued)
Signal Name
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
Pin
LINERXDATA24
B9
LINETXCLK7
B19
LINETXDATA19
H24
LOPOHCLKOUT
AB15
LINERXDATA25
B10
LINETXCLK8
D20
LINETXDATA20
H23
LOPOHDATAIN
AC14
LINERXDATA26
B11
LINETXCLK9
C20
LINETXDATA21
J25
LOPOHDATAOUT
AB17
LINERXDATA27
A12
LINETXCLK10
C21
LINETXDATA22
K25
LOPOHVALIDIN
AB14
LINERXDATA28
C13
LINETXCLK11
C22
LINETXDATA23
L25
LOPOHVALIDOUT
AB18
LINERXDATA29
D13
LINETXCLK12
C23
LINETXDATA24
M26
LOSEXT
AE5
LINERXSYNC1
R2
LINETXCLK13
B25
LINETXDATA25
N24
MODE0_PLL
AF24
LINERXSYNC2
P1
LINETXCLK14
C24
LINETXDATA26
N23
MODE1_PLL
AE24
LINERXSYNC3
N4
LINETXCLK15
D24
LINETXDATA27
P26
MODE2_PLL
AB21
LINERXSYNC4
N3
LINETXCLK16
E24
LINETXDATA28
R25
MPCLK
AE17
LINERXSYNC5
M1
LINETXCLK17
F24
LINETXDATA29
T23
MPMODE
AD17
LINERXSYNC6
L2
LINETXCLK18
G24
LINETXSYNC1
D14
PAR0
U25
LINERXSYNC7
K2
LINETXCLK19
G23
LINETXSYNC2
C14
PAR1
U24
LINERXSYNC8
J2
LINETXCLK20
H25
LINETXSYNC3
A15
PHASEDETDOWN
U22
LINERXSYNC9
H4
LINETXCLK21
J26
LINETXSYNC4
B16
PHASEDETUP
V22
LINERXSYNC10
H3
LINETXCLK22
K24
LINETXSYNC5
B17
PMRST
T25
LINERXSYNC11
G1
LINETXCLK23
L24
LINETXSYNC6
B18
RCBCLK
E17
LINERXSYNC12
F2
LINETXCLK24
M24
LINETXSYNC7
D19
RCBDATA
E15
LINERXSYNC13
E4
LINETXCLK25
M23
LINETXSYNC8
C19
RCBSYNC
E18
LINERXSYNC14
D1
LINETXCLK26
N25
LINETXSYNC9
A20
RDLCLK
E19
LINERXSYNC15
C1
LINETXCLK27
P25
LINETXSYNC10
B21
RDLDATA
H22
LINERXSYNC16
K5
LINETXCLK28
R23
LINETXSYNC11
D22
REF10
AC11
LINERXSYNC17
E6
LINETXCLK29
R24
LINETXSYNC12
A23
REF14
AD12
LINERXSYNC18
B3
LINETXDATA1
A14
LINETXSYNC13
A24
RESHI
AF12
LINERXSYNC19
B4
LINETXDATA2
B15
LINETXSYNC14
F22
RESLO
AE12
LINERXSYNC20
B5
LINETXDATA3
D16
LINETXSYNC15
C25
RHSCN
AD8
LINERXSYNC21
D6
LINETXDATA4
D17
LINETXSYNC16
D25
RHSCP
AC7
LINERXSYNC22
B7
LINETXDATA5
D18
LINETXSYNC17
E25
RHSDN
AE7
LINERXSYNC23
A8
LINETXDATA6
C18
LINETXSYNC18
F23
RHSDP
AF7
LINERXSYNC24
C9
LINETXDATA7
A19
LINETXSYNC19
G25
RHSFSYNCN
AD7
LINERXSYNC25
D9
LINETXDATA8
B20
LINETXSYNC20
H26
RLSC52
AC2
LINERXSYNC26
D10
LINETXDATA9
D21
LINETXSYNC21
J24
RLSCLK
V4
LINERXSYNC27
D11
LINETXDATA10
B22
LINETXSYNC22
J23
RLSDATA0
U3
LINERXSYNC28
B12
LINETXDATA11
B23
LINETXSYNC23
K23
RLSDATA1
U2
LINERXSYNC29
A13
LINETXDATA12
B24
LINETXSYNC24
L23
RLSDATA2
U4
LINETXCLK1
B14
LINETXDATA13
E21
LINETXSYNC25
M25
RLSDATA3
T3
LINETXCLK2
D15
LINETXDATA14
C26
LINETXSYNC26
N26
RLSDATA4
T2
LINETXCLK3
C15
LINETXDATA15
D26
LINETXSYNC27
P23
RLSDATA5
T4
LINETXCLK4
C16
LINETXDATA16
E23
LINETXSYNC28
P24
RLSDATA6
R3
LINETXCLK5
C17
LINETXDATA17
F25
LINETXSYNC29
R26
RLSDATA7
R1
LINETXCLK6
A18
LINETXDATA18
G26
LOPOHCLKIN
AC13
RLSJ0J1V1
V3
Agere Systems Inc.
13
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
3 Pin Information
Preliminary Data Sheet
May 2001
(continued)
Table 2. Pin Assignments for 456-Pin PBGA by Signal Name (continued)
Signal Name
14
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
Pin
RLSPAR
V2
TLSPAR
AA3
VDD
AB11
VSS
N12
RLSSPE
V1
TLSSPE
AB2
VDD
AB16
VSS
N13
RLSSYNC52
AC1
TLSSYNC52
AD2
VDD
AB22
VSS
N14
RLSV1
W4
TLSV1
AB3
VDD
AB26
VSS
N15
RPOACCLK
AE3
TMSN
W5
VDD
AF1
VSS
N16
RPOACDATA
AD4
TPOACCLK
AE4
VDD
AF5
VSS
P11
RPOACSYNC
AF4
TPOACDATA
AD5
VDD
AF10
VSS
P12
RPSC155N
AD11
TPOACSYNC
AC5
VDD
AF17
VSS
P13
RPSC155P
AC10
TPSC155N
AD13
VDD
AF22
VSS
P14
RPSD155N
AE10
TPSC155P
AC12
VDD
AF26
VSS
P15
RPSD155P
AD10
TPSD155N
AE13
VDDA_CDR
AC9
V SS
P16
RSTN
T24
TPSD155P
AF13
VDDD_PLL
AD22
V SS
R11
RTOACCLK
AD1
TRSTN
AB8
VDDS_PLL
AE23
V SS
R12
RTOACDATA
AD3
TSTMODE
AF15
V SS
A2
V SS
R13
RTOACSYNC
AA5
TSTMUX0
AC16
VSS
A6
V SS
R14
RWN
AF18
TSTMUX1
AE16
V SS
A11
VSS
R15
RXDATAEN
AB19
TSTPHASE
AF14
VSS
A16
VSS
R16
SCAN_EN
N5
TSTSFTLD
AD15
VSS
A21
VSS
T1
SCAN_MODE
M5
TTOACCLK
AB6
V SS
A25
VSS
T11
TCBCLK
E13
TTOACDATA
AE2
V SS
B1
V SS
T12
TCBDATA
E12
TTOACSYNC
AF3
V SS
B26
VSS
T13
TCBSYNC
E14
TXDATAEN
W22
VSS
D4
V SS
T14
TCK
R5
VDD
A1
V SS
D23
VSS
T15
TDI
U5
VDD
A5
V SS
E7
V SS
T16
TDLCLK
E9
VDD
A10
V SS
E20
VSS
T26
TDLDATA
E8
VDD
A17
V SS
F1
V SS
Y5
TDO
V5
VDD
A22
V SS
F26
VSS
Y22
THSCN
AE8
VDD
A26
V SS
G5
V SS
AA1
THSCP
AF8
VDD
E1
V SS
G22
VSS
AA26
THSDN
AE9
VDD
E5
V SS
L1
V SS
AB7
THSDP
AF9
VDD
E11
V SS
L11
V SS
AB20
THSSYNCN
AD9
VDD
E16
V SS
L12
V SS
AC4
THSSYNCP
AC8
VDD
E22
V SS
L13
V SS
AC23
TLSC52
AC3
VDD
E26
V SS
L14
V SS
AE1
TLSCLK
AA2
VDD
K1
V SS
L15
V SS
AE26
TLSDATA0
AA4
VDD
K26
V SS
L16
V SS
AF2
TLSDATA1
Y3
VDD
L5
V SS
L26
V SS
AF6
TLSDATA2
Y1
VDD
L22
V SS
M11
VSS
AF11
TLSDATA3
Y2
VDD
T5
V SS
M12
VSS
AF16
TLSDATA4
Y4
VDD
T22
V SS
M13
VSS
AF21
TLSDATA5
W3
VDD
U1
V SS
M14
VSS
AF25
TLSDATA6
W1
VDD
U26
VSS
M15
VSSA_CDR
AB12
TLSDATA7
W2
VDD
AB1
VSS
M16
VSSA_PLL
AF23
TLSJ0J1V1
AB4
VDD
AB5
VSS
N11
VSSS_PLL
AD23
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
3 Pin Information (continued)
3.3 Pin Descriptions
3.3.1 High-speed I/O Pin Descriptions
The high speed I/O consists of five LVDS signals (10 pins) that connect the Super Mapper to an external OC-3
optics device. It exchanges an STS-3 or STM-1 signal between the TMUX and an OC-3 transceiver. The Super
Mapper is capable of recovering a clock from the receive data, or can accept a clock recovered externally by the
optics device. If internal clock recovery is used, the Super Mapper uses THSCP/N as a reference.
The high-speed I/O may also run at 52.84 Mbits/s in applications that terminate an STS-1 or EC-1 signal. In this
case, the (electrical) line signals are typically terminated by a line interface unit (LIU) chip. The operating speed of
the high-speed I/O is determined by TMUX_RCV_TX_MODE.
Table 3. High-speed I/O Pin Descriptions
Pin
Symbol
Type
I/O
Description
AF7,
RHSDP
LVDS
I
AE7
RHSDN
Receive High-speed Data. 155.52 Mbits/s serial data input in STS-1 or
STM-1 format, or 51.84 Mbits/s data in STS-1 format. If RHSD is not used
(in a slave Super Mapper, for example) the P input should be pulled high
through a 1 kΩ resistor and the N input pulled low through a 1 kΩ resistor.
RHSD is typically provided by and OC-3 receiver, an STS-1 line interface
unit or an higher order (e.g. STS-12) demultiplexing chip.
AC7,
RHSCP
LVDS
I
AD8
RHSCN
Receive High-speed Clock. 155.52 or 51.84 MHz clock for STS-3 or
STS-1 input data. Typically supplied by an external OC-3 opto-electonic
device, or an STS-1/EC1 line interface unit, synchronous with RHSD. If
the internal clock recovery (CDR) feature is enabled, RHC is not required
and should be connected to through 1 kΩ resistors to VDD (RHCP input)
and VSS (RHCN input).
AF8,
THSCP
LVDS
I
AE8
THSCN
Transmit High-speed Clock. Transmit 155.52 MHz or 51.84 MHz clock.
Master clock for the transmit sections of the TMUX, telecom bus, SPE,
and VT mappers. THSC is also used as a reference clock for the receive
CDR, if it is being used.
AC8,
THSSYNCP
LVDS
I
AD9
THSSYNCN
Transmit High-speed Frame Synchronization. An optional input that
may be used to specify the position of the transmit STS-3, STM-1, or
STS-1 frame. THSSYNC marks the position of bit 1 of the A1 byte, i.e.,
the first bit of the overhead in the THSD output. If THSSYNC is not used,
the P input should be pulled high through a 1 kΩ resistor, and the N input
pulled low through a 1 kΩ resistor. A typical application for this pin may be
to synchronize a group of Super Mappers, so that their STS-3 outputs
may be multiplexed into an STS-12 signal.
AF9,
THSDP
LVDS
O
AE9
THSDN
Transmit High-speed Data. Transmit output for STS-3, STM-1, or STS-1
serial data. Typically connected to an OC-3 module or an LIU, if operating
in STS-1 mode. May also be connected to a higher order multiplexing
device, STS-12 for example.
Agere Systems Inc.
15
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
3 Pin Information (continued)
3.3.2 Protection Switch I/O Pin Description
The protection switch I/O provides additional copies of the high-speed interface signals so that various protection
schemes may be implemented. The protection interface may be used when the high-speed interface is operating in
both STS-3 and STS-1 modes. If the protection port is not used, the input clock and data may be left unconnected,
tied to power (P inputs), or ground (N inputs) through 1 kΩ resistors. Unused protection outputs should be left
unconnected.
Table 4. Protection Switch I/O Pin Description
Pin
AD10,
Symbol
RPSD155P
Type
LVDS
I/O
I
AE10
AC10,
RPSD155N
RPSC155P
Description
Receive Protection Data. Receive side high-speed serial data input
from protection board.
LVDS
I
AD11
AF13,
RPSC155N
TPSD155P
Receive Protection Clock. Receive side high-speed clock input from
protection board.
LVDS
O
AE13
AC12,
TPSD155N
TPSC155P
Transmit Protection Data. Transmit side high-speed serial data output
to protection board.
LVDS
O
AD13
TPSC155N
Transmit Protection Clock. Transmit side high-speed clock output to
protection board.
HIGH-SPEED I/O
TPSMUXSEL2
HIGH-SPEED
PROTECTION
INPUTS
HIGH-SPEED
PROTECTION
OUTPUTS
RPSMUXSEL1
TPSMUXSEL3
STS-3 RECEIVE
FRAMER
STS-3 TRANSMIT
FRAMER
Figure 3. Protection Switch
3.3.3 Telecom Bus (Low-speed I/O) Pin Description
The telecom bus on the Super Mapper is used for interconnecting STS-1 signals. It has two eight-bit data buses,
one for upstream data and one for downstream data, plus clock and frame indication signals for each bus. The telecom bus can operate at 19.44 MHz (space for three STS-1 signals) or 6.48 MHz (space for 1 STS-1 signal).
Super Mappers in OC-3 applications are typically connected together using the telecom bus, and the bus is configured to operate at 19.44 MHz.
16
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
3 Pin Information (continued)
Table 5. Telecom Bus (Low-speed I/O) Pin Description
Pin
R1, R3, T4, T2,
T3, U4, U2, U3
Symbol
RLSDATA[7:0]
Type
—
I/O
I/O
V4
RLSCLK
—
I/O
V2
RLSPAR
—
I/O
V1
RLSSPE
—
I/O
V3
RLSJ0J1V1
—
I/O
W4
RLSV1
—
I/O
Agere Systems Inc.
Description
Receive Low-speed Data (7:0), Parallel Data Bus. Used
to connect the downstream STS-1 signals from the master
to the slave devices. In master mode, RLSDATA is an output bus, eight bits wide. It contains all the received data for
distribution to the two slave devices. Connect to
RLSDATA(7:0) on the slave devices. In slave mode, these
pins are inputs and should be connected to the
RLSDATA(7:0) outputs on the master. RLSDATA contains
three byte-interleaved STS-1 time slots. The slot used by
each SPE mapper in the slaves and the master device, is
determined by programing the SPE_RSTS3_TMSLOT register bits.
Receive Low-speed Clock. This is a 19.44 MHz or
6.48 MHz clock for the receive low speed data bits. In
19.44 MHz master mode, this is a 19.44 MHz clock output
for distribution to the two slave devices. Connect to
RLSCLK on the slaves. RLSCLK is an input signal on slave
devices.
Note: As outputs, these pins have 6 mA drive capability.
Receive Low-speed Parity. Receive data parity bit, may be
configured for odd or even parity generated on
RLSDATA(7:0). The default is odd parity; it may be set to
even by setting bit 2 of the register at 0x4001B an output in
master mode and an input in slave mode. Connect the
RSLPAR (output) on the master to The RLSPAR (input)
pins on the slaves.
Receive Low-speed SPE Marker. Receive synchronous
payload envelope timing indicator. It is high, while there is
SPE data on the RLSDATA(7:0) output bus. Connect to
RLSSPE on the slaves. RLSSPE is an input on slave
devices.
Receive Low-speed J0/J1/V1 Marker. On the master
device, this is an output that is high while J0-1, J1
(1, 2 and 3) and V1 (1, 2 and 3) bytes are present on the
RLSDATA bus. Connect to RLSJ0J1V1 on the slaves, which
is an input.
Receive Low-speed V1 Marker. Receive V1 timing indicator. On the master this is an output that is high while the V1
bytes (1, 2 and 3) are present on RLSDATA(7:0) output bus.
Connect to RLSV1 on the slaves.
17
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
3 Pin Information (continued)
Table 5. Telecom Bus (Low-speed I/O) Pin Description (continued)
Pin
W2, W1, W3, Y4,
Y2, Y1, Y3, AA4
Symbol
TLSDATAI[7:0]
Type
—
I/O
I/O
AA2
TLSCLK
—
I/O
AA3
TLSPAR
—
I/O
AB2
TLSSPE
—
I/O
AB4
TLSJ0J1V1
—
I/O
AB3
TLSV1
—
I/O
AC2
RLSC52
—
I/O
AC1
RLSSYNC52
—
I/O
18
Description
Transmit Low-speed Data (7:0). This is a parallel data
bus. It is used to connect the upstream STS-1 signals from
the slave devices to the master device. In master mode,
TLSDATA is an input bus, eight bits wide. It contains all the
transmit STS-1 data from the slave devices. In slave mode,
these pins are outputs and should be connected to the
TLSDATA(7:0) inputs on the master. TLSDATA contains
three byte-interleaved STS-1 time slots. The slot used by
each SPE mapper in the slaves and the master device, is
determined by programing the SPE_TSTS3_TMSLOT register bits.
Transmit Low-speed Clock. This is a 19.44 MHz or
6.48 MHz clock for the TLSDATA(7:0) bits. TLSCLK is an
output on a master Super Mapper and an input on a slave.
Note: As outputs, these pins have 6 mA drive capability.
Transmit Low-speed Parity. This parity bit is generated on
the TLSDATA(7:0) bits output from slave devices and input
to the master Super Mapper. May be configured for odd or
even parity generation or for checking.
Transmit Low-speed SPE Marker. High while the STS-1
payloads are present on the TLSDATA(7:0) bus. Low while
the STS-1 overhead is present on the TLSDATA(7:0) bus.
An output from the master and input on the slaves.
Transmit Low-speed J0/J1/V1 Marker. Transmit J0, J1, or
V1, timing indicator. High while the J0, J1 or V1 bits are
present on the TLSDATA(7:0) bus. An output on the master
and input on slaves.
Transmit Low-speed V1 Marker 3. Transmit V1 timing indicator. High while the V1 bits are present on the
TLSDATA(7:0) bus. An output on the master and input on
slaves.
Receive Low-speed Clock. When in output (master)
mode, it is the receive side of the 51.84 MHz clock output,
synchronous to the receive high-speed input clock (data).
When in input (slave) mode, it receives a 51.84 MHz clock
input, synchronous to the receive high-speed input clock
(data).
Note: As outputs, these pins have 6 mA drive capability.
Receive Low-speed Sync. When in output (master) mode,
it is the receive side frame sync output synchronous to a
51.84 MHz output. When in input mode, it is the receive
side frame sync input synchronous to a 51.84 MHz input.
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
3 Pin Information (continued)
Table 5. Telecom Bus (Low-speed I/O) Pin Description (continued)
Pin
Symbol
Type
I/O
Description
AC3
TLSC52
—
I/O
Transmit Low-speed Clock. When in output (master) mode,
it is the transmit side 51.84 MHz clock output synchronous to
transmit high-speed input clock. When in input mode, it
receives a 51.84 MHz clock input synchronous to transmit
high-speed input clock
Note: TLSCLK is used as the master clock for the T1/E1
framer and should therefore be provided even if the
TMUX SPE and VT mappers are not used.
AD2
TLSSYNC52
—
I/O
Transmit Low-speed Sync. When in output (master) mode,
it is the transmit side frame sync output synchronous to
51.84 MHz output. When in input (slave) mode, it receives the
transmit side frame sync input synchronous to 51.84 MHz
input.
3.3.4 TOAC and POAC
The transport and path overhead access channels (TOAC and POAC) allow parts of the SONET/SDH overhead to
be examined externally (receive direction) or overwritten (transmit direction) through serial data ports. Each port
has clock and data lines and synchronization signal that marks the last bit of the frame so that the rest of the overhead bytes can be identified.
The receive TOAC and POAC channels contain all of the respective overheads bytes. The transmit channels contain space for all the overhead bytes, but whether they are actually transmitted depend on how the device is programmed. Some overhead bytes can not be modified; others may be modified only through the CPU port; some
may be modified only through the overhead access channels; and some may be modified either through the CPU
port, or through the overhead access channels.
Table 6. TOAC and POAC
Pin
AD1
Symbol
RTOACCLK
AD3
RTOACDATA
AA5
RTOACSYNC
AB6
TTOACCLK
AE2
TTOACDATA
AF3
TTOACSYNC
AE3
RPOACCLK
AD4
RPOACDATA
Agere Systems Inc.
Type
—
I/O
O
Description
Receive TOAC Clock. Receive side serial access channel
clock output for the transport overhead bytes.
—
O
Receive TOAC Data. Receive side serial access channel
data output for the transport overhead bytes.
—
O
Receive TOAC Synchronization. Receive side sync output
for TOAC channel. Active-high during the LSB of the last
byte.
—
O
Transmit TOAC Clock. Transmit side serial access channel
clock output for the transport overhead bytes.
—
I
Transmit TOAC Data. Transmit side serial access channel
Pull down data input for the transport overhead bytes.
—
O
Transmit TOAC Synchronization. Transmit side sync output for TOAC channel. Active-high during the LSB of the last
byte.
Path Overhead Access Channel (POAC)
—
O
Receive POAC Clock. Receive side serial access channel
clock output for the path overhead bytes.
—
O
Receive POAC Data. Receive side serial access channel
data output for the path overhead bytes.
19
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
3 Pin Information
Preliminary Data Sheet
May 2001
(continued)
Table 6. TOAC and POAC (continued)
Pin
AF4
Symbol
RPOACSYNC
Type
—
AE4
TPOACCLK
—
AD5
TPOACDATA
—
AC5
TPOACSYNC
—
I/O
O
Description
Receive POAC Synchronization. Receive side sync output
for POAC channel. Active-high during the last bit of the last
byte of the POAC frame.
O
Transmit POAC Clock. Transmit side serial access channel
clock output for the path overhead bytes.
I
Transmit POAC Data. Transmit side serial access channel
Pull down data input for the path overhead bytes.
O
Transmit POAC Synchronization. Transmit side sync output for POAC channel. Active-high during the last bit of the
last byte.
3.3.5 Miscellaneous Signals
Table 7. Miscellaneous Signals
Pin
Symbol
Type
I/O
Description
AE5
LOSEXT
—
I
AD6, AE6,
AC6
AUTO_AIS
—
I/O
AIS Enable (3:1). Control signal for automatic AIS insertion
on each STS1. The STS-1 AIS is applied down stream on the
telecom bus, i.e., it is an output from masters and an input to
slaves. Active-high.
Input when slave mode.
Output when master mode
If not used, leave open.
AD7
RHSFSYNCN
—
O
Receive High-speed Frame Synchronization. Receive side
frame sync output indicating the frame location of the highspeed data input. May be used as a 8 kHz timing reference
for network synchronization to the receive high-speed data
input (STS-3 or STS-1).
Loss of Signal External. External loss of signal input. If
Pull up external clock and data recovery is used on the high-speed
I/O port, it may be connected to this input which can be configured to assert the LOS register bit normally associated
with the internal LOS detection in the internal CDR block. The
polarity of LOS may be programmed active-high or low.
3.3.6 DS3 Port
If a DS3 output is required in a Super Mapper application and the DS3 signal has been recovered (demapped) from
an STS-1, then it is necessary to smooth the DS3 recovered clock. The DS3 clock extracted from the STS-1 clock
will have considerable jitter introduced when the SONET overhead is removed and pointer adjustments are made.
A phase locked loop is recommended for this purpose. The Super Mapper contains a phase comparator, that can
be used in conjunction with an external low-pass filter and voltage controlled crystal oscillator to implement the
PLL.
20
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
3 Pin Information (continued)
Table 8. DS3 Port
Pin
Symbol
Type
I/O
Description
V22
PHASEDETUP
—
O
Phase Detector Up. Phase error signal out to external filter
and VCXO. This output will generate an error signal when
the VCXO output is slower than the reference signal.
U22
PHASEDETDOWN
—
O
Phase Detector Down. Phase error signal out to external filter and VCXO. This output will generate an error signal when
the VCXO output is faster that the reference signal.
R22
DS3POSDATAOUT
—
O
Positive Data Output. Serial DS3 positive data out to LIU
when the DS3 output port is operating in dual rail-mode.
Nonreturn to zero DS3 data output when the DS3 output is
operating in single ended mode.
P22
DS3NEGDATAOUT
—
O
Negative Data Output. Serial DS3 negative data output to
LIU when the DS3 port is operating in dual rail mode. In single rail mode, this output is not used and may be left unconnected.
N22
DS3DATAOUTCLK
—
I
DS3 Data Out Clock. 44.736 MHz DS3 clock input. If the
Super Mapper is being used to map DS3 data to and from
STS-1, then this clock will be supplied by the external VCXO
that is associated with the DS3 clock recovery PLL. In other
DS3 modes (e.g., M13) this input will be supplied by an
external crystal oscillator, usually associated with a DS3 LIU.
If the DS3 port is not used, this input may be tied to ground
or left open, since it is equipped with an internal pull-down
resistor.
Pull
down
M22
DS3POSDATAIN
—
I
Pull
down
K22
DS3NEGDATAIN
—
I
Pull
down
J22
DS3DATAINCLK
—
I
Pull
down
Agere Systems Inc.
Positive Data Input. If the DS3 port is configured in dual-rail
mode, then this input is serial positive data from an external
DS3 LIU. If the DS3 port is configured in single-rail mode,
then this input is serial nonreturn-to zero data from the external LIU.
Negative Data In. In dual rail mode, this is negative data
from an external DS3 LIU. In single rail mode, it may be connected to the bipolar violation output of the external DS3 LIU,
left unconnected, or tied to ground.
DS3 Data In Clock. This is a 44.736 MHz clock input from
the clock recovery in the external DS3 LIU.
21
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
3 Pin Information (continued)
Table 9. DS3 Port, C-Bit, and Datalink Access
Pin
Symbol
Type
I/O
Description
E14
TCBSYNC
—
O
Transmit C-Bit Sync. In the C-bit parity mode, 10 C-bits may
optionally be input for multiplexing into the transmit DS3 frame
through the TCBDATA input. The TCBSYNC output is low, except
during the rising edge of TCBCLK that is used to input C2.
E13
TCBCLK
—
O
Transmit C-Bit Clock. A gapped clock (nominally 93.983 kHz) for
accepting selected C-bits on input M13_CBDATA.
E12
TCBDATA
—
I
E9
TDLCLK
—
O
E8
TDLDATA
—
I
Transmit C-Bit Data. In the C-bit parity mode, the network requirePull down ments bit (C2), and the unused C-bits (C4, C5, C6, C16, C17, C18,
C19, C20, and C21) may optionally be input for multiplexing into the
transmit DS3 frame through this input.
Transmit Data Link Clock. A gapped clock (nominally 28.195 kHz)
for accepting path maintenance data link C-bits on input TDLDATA.
Transmit Data Link Data. The path maintenance data link C-bits
Pull down (C13, C14, and C15) may optionally be input for multiplexing into the
transmit DS3 frame through this input.
3.3.7 M13 Multiplexer/Demultiplexer Receive Section
Two groups of signals are defined in this section. The first group are reference clocks, used internally in the jitter
attenuation and AIS generation processes. Note that these are typically supplied by free-running crystal oscillators.
The outputs below provide access to the received C-bits and data link bits extracted from the received DS3 frame.
These operate in the same way if the source of the DS3 signal is from an SPE or from the external DS3 port.
Table 10. M13 Multiplexer/Demultiplexer Receive Section
22
Pin
Symbol
Type
I/O
AC17
E1XCLK
—
I
AD16
DS1XCLK
—
E10
DS2AISCLK
—
E18
RCBSYNC
—
Description
E1 Reference Clock. This clock is used as a reference for the jitter
Pulldown attenuator when it is operating in the E1 mode. It must have a frequency of 2.048 MHz, 32.768 MHz, or 65.536 MHz and a stability of
50 ppm. It is also used to generate an E1 AIS (all ones). May be left
unconnected, or tied to ground, if no E1 options are being used.
I
DS1 Reference Clock. This clock is used as a reference for the jitter
attenuator
when it is operating in the DS1 or the J1 mode. It must
Pulldown
have a frequency of 1.544 MHz, 24.704 MHz, or 49.408 MHz and a
stability of ±32 ppm. This clock signal is also used to generate DS1
AIS signals. May be left unconnected or tied to ground, if not, no DS1
options are being used.
I
DS2 Reference Clock. A 6.312 MHz ±30 ppm input. In the M23
Pulldown mode, this clock is used to generate DS2 AIS. May be left unconnected or tied to ground if no DS2 options are being used. Note that
C-bit parity mode does no require a DS2 reference clock.
O
Receive C-Bit Sync. Ten C-bits are output on RCD after they are
demultiplexed from the received DS3 signal. The RCS output is low,
except during the rising edge of RCD that is used to output C2.
Agere Systems Inc.
Preliminary Data Sheet
May 2001
3 Pin Information
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
(continued)
Table 10. M13 Multiplexer/Demultiplexer Receive Section (continued)
Pin
Symbol
Type
I/O
Description
E17
RCBCLK
—
O
Receive C-Bit Clock. A gapped clock (nominally 93.983 kHz) for outputting selected C-bits on RCD.
E15
RCBDATA
—
O
Receive C-Bit Data. The received network requirements bit (C2) and
the received unused C-bits (C4, C5, C6, C16, C17, C18, C19, C20,
and C21) are output after they are demultiplexed from the received
DS3 signal.
E19
RDLCLK
—
O
Receive Data Link Clock. A gapped clock (nominally 28.195 kHz)
for outputting path maintenance data link C-bits on RDLD.
H22
RDLDATA
—
O
Receive Data Link Data. The received path maintenance data link
C-bits (C13, C14, and C15) that are demultiplexed from the received
DS3 signal.
3.3.8 Low-Order Path Overhead Access Channel
Each VT has a low-order path overhead, and this interface allows access to all LOPOH bits for all VTs. Note that
the purpose of doing this is slightly different form the transport and path overhead access. These are used to cross
couple the bits between links in a protection scheme, rather than provide access for examination or modification of
the overhead, although that is possible too.
Table 11. Low-Order Path Overhead Access Channel
Pin
Symbol
Type
AC13
AC14
LOPOHCLKIN
LOPOHDATAIN
—
—
AB14
LOPOHVALIDIN
—
AB15
AB17
LOPOHCLKOUT
LOPOHDATAOUT
—
—
AB18
LOPOHVALIDOUT
—
I/O
Description
Transmit Direction
I Pull down 6.48 MHz Low Order Path Overhead Clock.
I Pull down Low-Order Path Overhead Data. (O-bits, V5, J2,
Z6/N2, Z7, and K4 byte.)
I Pull down Valid LOPOH_DATA.
Receive Direction
O
6.48 MHz Low Order Path Overhead Clock.
O
Low-Order Path Overhead Data. (O-bits,V5, J2,
Z6/N2, Z7/K4 byte.)
O
Valid VTMPR_LOPOH_DATA Output.
TELECOM BUS
LOPOH
OUTPUTS
LOPOH
OUTPUTS
VT MAPPER
VT MAPPER
LOPOH
INPUTS
LOPOH
INPUTS
DS1/E1 TO DXC
Figure 4. DS1/E1 to DXC Block Diagram
Agere Systems Inc.
23
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
3 Pin Information (continued)
Table 12. Multifunction System Interface Transmit Path Direction
Pin
Symbol
Type
C13, A12,
B11, B10, B9,
D8, C8, A7,
B6, D5, A4,
A3, H5, F5,
C2, D2, E2,
F4, G2, H1,
J3, J4, K4, L4,
M2, N1, P4,
P3
LINERXDATA[28:1]
—
D13
LINERXDATA29
I/O
Description
I
Line Receive Data (28:1). Configurable inputs to the
Pull down internal cross connect. The use depends on the application. Generally, these inputs are used for the received
positive-rail or single-rail DS1/E1 line data input. If operating in dual rail mode, the negative rail will be expected
on LINERXSYNC(28:1). Using dual rail mode implies
that the internal B8ZS or HDB3 decoders are enabled,
and line code violations can be detected and counted
inside the Super Mapper.
These data inputs may be assigned, using the cross
connect block, to the DS1 or E1 inputs on the VT mapper, M13 or DS1/E1 framers. It is also possible to use
the inputs for DS2 data, in which case they may be
assigned to the M23 multiplexer inputs.
—
I
Receive Data 29. Configurable input to the internal
Pull down cross connect. May be used as an additional line
receive data input, for a protection channel. Other possible uses are as follows:
Global transmit line clock input. Externally supplied
1.544 MHz or 2.048 MHz low jitter clock phase-locked
to the TDM system clock. Used for transmit line clock on
the DS1/E1 framers. This is not normally used, because
the DS1/E1 framer has a PLL which can generate a
1.544 MHz clock from the TDM system clock (CHI
clock). This applies in PSB and CHI modes.
Receive data input. If NSMI mode is used, this will be a
51.84 Mbits/s serial data input.
D12, C12,
C11, C10, A9,
B8, D7, C7,
C6, C5, C4,
C3, J5, B2,
D3, E3, F3,
G3, G4, H2,
J1, K3, L3,
M3, M4, N2,
P2, R4
LINERXCLK[28:1]
—
B13
LINERXCLK29
—
24
I/O
Receive Clock (28:1). Configurable inputs/outputs to
Pull down the internal cross connect. Typically a line clock associated with the corresponding LINERXDATA input. It can
therefore be running at DS1, E1 or DS2 rate. The cross
connect is used to assign these inputs to the VT mapper, M13 or DS1/E1 framers.
I/O
Receive Clock 29. May be used as additional receive
Pull down clock input for a DS1/E1 protection channel. Also has
special use as a master clock. In CHI mode, it is the
receive clock input (2.048 MHz, 4.096 MHz, 8.192 MHz,
or 16.384 MHz). In PSB mode, it is the receive clock
input (19.44 MHz). In NSMI mode, it is the receive clock
output. (51.84 MHz).
Agere Systems Inc.
Preliminary Data Sheet
May 2001
3 Pin Information
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
(continued)
Table 12. Multifunction System Interface Transmit Path Direction (continued)
Pin
Symbol
Type
I/O
Description
B12, D11,
D10, D9, C9,
A8, B7, D6,
B5, B4, B3,
E6, K5, C1,
D1, E4, F2,
G1, H3, H4,
J2, K2, L2,
M1, N3, N4,
P1, R2
LINERXSYNC[28:1]
—
I
Line Receive Synchronous 28:1. Multifunction input.
Channel assignment may be configured through the
internal cross connect. Can be used as the negative rail
of a DS1/E1 signal in conjunction with LINERXDATA(28:1), when operating in dual-rail mode. In CHI
mode these inputs are used for receive TDM highways
that may run at 2.048, 4.096, or 8.192 Mbits/s. In parallel system bus mode the receive system data bus inputs
are assigned to LINERXSYNC 16:1. The PSB is a 16bit wide bus that operates at 19.44 MHz.
A13
LINERXSYNC29
—
I/O
Line Receive Synchronous 29. Multifunction input.
Channel assignment may be configured through the
internal cross connect. Can be used as the negative rail
of a DS1/E1 signal in conjunction with LINERXDATA 29,
when operating in dual-rail mode.
In CHI and PSB modes this input is used as the receive
system frame synchronization input. In NSMI mode, it is
the receive frame sync output
R25, P26,
N23, N24,
M26, L25,
K25, J25,
H23, H24,
G26, F25,
E23, D26,
C26, E21,
B24, B23,
B22, D21,
B20, A19,
C18, D18,
D17, D16,
B15, A14
LINETXDATA[28:1]
—
I/O
Line Transmit Data (28:1) Configurable outputs from
the internal cross connect. Used for transmit positiverail or single-rail DS1/E1 line data outputs. May be connected to the DS1/E1 outputs from the VT mapper, M13
MUX or DS1/E1 frame line outputs. May also be used
as a DS2 output.
T23
LINETXDATA29
—
O
Line Transmit Data 29. Configurable output from the
internal cross connect. An extra DS1 or E1 transmit port
that may be used for protection or as a timing reference
output.
Agere Systems Inc.
25
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
3 Pin Information
Preliminary Data Sheet
May 2001
(continued)
Table 12. Multifunction System Interface Transmit Path Direction (continued)
Pin
Symbol
Type
I/O
Description
R23, P25,
N25, M23,
M24, L24,
K24, J26,
H25, G23,
G24, F24,
E24, D24,
C24, B25,
C23, C22,
C21, C20,
D20, B19,
A18, C17,
C16, C15,
D15, B14
LINETXCLK[28:1]
—
I/O
Line Transmit Clock (28:1). Configurable outputs from
the internal cross connect. Can be used as the clock
signals for LINETXDATA(28:1) in DS1, E1, and DS2
modes.
R24
LINETXCLK29
—
I/O
Line Transmit Clock 29. Configurable output to the
internal cross connect for the protection or timing reference channel. Also used as the transmit global system
clock input for CHI (2.048 MHz, 4.096 MHz, 8.192 MHz,
or 16.384 MHz), PSB (19.44 MHz), and NSMI (51.84
MHz) modes.
P24, P23,
N26, M25,
L23, K23, J23,
J24, H26,
G25, F23,
E25, D25,
C25, F22,
A24, A23,
D22, B21,
A20, C19,
D19, B18,
B17, B16,
A15, C14,
D14
LINETXSYNC[28:1]
—
I/O
Line Transmit Synchronous (28:1). Configurable
inputs/outputs to the internal cross connect. An output
when used as the negative rail of a DS1 or E1 output
port operating in dual-rail mode. In CHI mode, these
pins may be used as output TDM highways. In PSB
mode, bits 16:1 are used for the transmit data bus, and
bits 28:17 are not used. These pins may also be used
as DS2 I/O to the M12 block as follows: 7:1—Tx data
out. 14:8—Tx clock in. 21:16—Rx data in. 28:22—Rx
clock in.
R26
LINETXSYNC29
—
I/O
Line Transmit Synchronous 29. Configurable input/
output to the internal cross connect. An output when
used as the negative rail of a DS1 or E1 output port
operating in dual-rail mode. In CHI and PSB modes, it is
used as the transmit system frame synchronization
input. In NSMI mode, it is the transmit system frame
sync output.
AB19
RXDATAEN
—
O
NSMI Receive Enable. Receive data enable for NSMI
mode.
W22
TXDATAEN
—
O
NMSI Transmit Enable. Transmit data enable for NSMI
mode.
26
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
3 Pin Information (continued)
3.3.9 Framer PLL
The DS1/E1 framer has a phase-locked loop that may be used to generate a transmit line clock at 1.544 MHz or
2.048 MHz. The reference signal for this PLL may be chosen from a number of possible sources, all typically synchronized to the system clock (CHI transmit/receive clock for example.) In order to ensure reliable performance
,this PLL has its own isolated power pins. The PLL also has a number of test control pins that are used for factory
testing only.
The PLL is active when framer bit PLL_BYPAS = 0. When PLL_BYPAS = 1, the PLL is bypassed and an external
clock at the system interface is used as the line clock. An example would be when the framers are programmed for
a CHI interface at 2.048 MHz and the frames are programmed for E1, the PLL may be bypassed and the CHI system clock may be used as the line clock.
Table 13. Framer PLL
Pin
Symbol
Type
I/O
Description
AD22
VDDD_PLL
VDD
—
Digital VDD for PLL.
AE23
VDDS_PLL
VDD
—
Analog VDD for PLL.
AF23
VSSA_PLL
VSS
—
Analog VSS for PLL.
AD23
VSSS_PLL
VSS
—
Digital VSS for PLL.
AD24
CLKIN_PLL
—
AB21
MODE2_PLL
—
AF24
MODE0_PLL
—
I
PLL Mode 0. PLL control input 0.
Pull down
AE24
MODE1_PLL
—
I
PLL Mode 1. PLL control input 1. The PLL mode inputs should
Pull down be hardwired to the logic levels shown in the table below,
depending on the frequency of the reference supplied to
CLKIN_PLL.
I
Clock In PLL. Phase locked-loop reference clock input. FrePull down quency should be consistent with the MODE_PLL pins in the
PLL Mode1 table below. A 1.544 MHz clock for DS1 transmit
outputs is generated synchronous to this clock.
I/O
PLL Mode 2. Control bit that should be tied to the appropriate
state depending on the frequency of CLKIN_PLL consistent
with the PLL Mode1 table below. This pin is also used during
factory testing as an output.
Mode2
0
0
0
0
1
1
1
1
Agere Systems Inc.
Mode1
0
0
1
1
0
0
1
1
Mode0
0
1
0
1
0
1
0
1
CLKIN_PLL
Reserved
51.84 MHz
26.624 MHz
19.44 MHz
16.348 MHz
8.194 MHz
4.096 MHz
2.048 MHz
27
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
3 Pin Information (continued)
Table 14. Microprocessor Interfaces
Pin
Symbol
Type
I/O
Description
AE17
MPCLK
—
I
Processor Clock. This is the synchronous microprocessor
clock (when MPMODE=1). The maximum clock frequency is
66 MHz. This clock is required to properly sample address,
data, and control signals from the microprocessor in both
asynchronous and synchronous modes of operation. This
clock must be within the range of 16 MHz—66 MHz.
AD17
MPMODE
—
I
Control Port Mode. If the microprocessor interface is synchronous, CPM should be set to 1. If the microprocessor
interface is asynchronous, CPM should be set to 0.
AC18
CSN
—
I
Chip Select. Active-low chip select. For synchronous mode,
it should be stable beyond a certain setup time before the rising clock edge when AS is active. For asynchronous mode, it
should be stable before DS is asserted.
Pull up
AE18
ADSN
—
I
Address Strobe. Active-low address strobe that is a 1 PCK
cycle wide pulse for synchronous mode and active for the
entire read/write cycle for asynchronous mode. Address bus
signals, A(19:0), are transparently latched into Super Mapper
when AS is low. The address bus should remain valid for the
duration of AS.
AF18
RWN
—
I
Read/Write Cycle Selection. RW is set high for a read operation, or set low for write operation.
AD18
DSN
—
I
Data Strobe. DS is not used for synchronous mode. For
asynchronous mode, write operation, DS becomes active
after data is stable. For read operation, it is similar to AS.
AB23, AC26,
AC24, AD25,
AD26, AE25,
AA22, AC22,
AE22, AD21,
AE21, AC21,
AD20, AF20,
AE20, AC20,
AD19, AF19,
AE19, AC19
ADDR[19:0]
—
I
Address (19:0). A19 is the most significant and A0 the least
significant bit for addressing all the internal SM registers during CPU access cycles.
AB25, AA24,
AA25, AA23,
Y24, Y26,
Y25, Y23,
W24, W26,
W25, W23,
V24, V26,
V25, V23
DATA[15:0]
—
I/O
Data (15:0). Data bus for all transfers between the CPU and
the internal SM registers. The pins are inputs during write
cycles and outputs during read cycles. DATA15 is the MSB
and DATA0 is the LSB.
U24, U25
PAR[1:0]
—
I/O
CPU Port Parity (1:0). Byte-wide parity bits for data. CPP[1]
is the parity for D[15:8] and CPP[0] is the parity for D[7:0].
28
Note: The Super Mapper is little endian, the least significant
byte is stored in the lowest address and the most significant byte is stored in the highest address. Care
must be exercised in connection to microprocessors
that use big-endian byte ordering.
Agere Systems Inc.
Preliminary Data Sheet
May 2001
3 Pin Information
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
(continued)
Table 14. Microprocessor Interfaces (continued)
Pin
Symbol
Type
I/O
U23
DTN
—
O
AB24
INTN
—
AC25
APS_INTN
—
Description
Data Transfer Acknowledge. In synchronous CPU mode,
Open Drain DTA goes low at 4th cycle for write or 5th cycle for read,
resulting in a fixed 2 wait-states for writes and 3 wait-states
for reads. In asynchronous µP mode, after qualification of AS
and DS by TLSC52 clock, DTA goes low for two TLSC52
clock cycles for writes and three TLSC52 clock cycles for
reads. DTA goes high, along with the rising edge of AS.
O
Interrupt. Super Mapper interrupt request, active-low. An
Open Drain open drain output should be connected to an external pull-up
resistor.
O
APS Interrupt. Automatic protection switch interrupt request,
Open Drain active-low. An open drain output should be connected to an
external pull-up resistor.
Table 15. General Purpose Interface
Pin
Symbol
Type
I/O
Description
T24
RSTN
—
I
Pull up
Reset. Global reset, active-low. Initializes all internal registers
to their default state.
T25
PMRST
—
I/O
Performance Monitor Reset. May be configured as an input
and then used to directly reset all the counters associated with
DS1/E1 performance monitoring. If an internal PM reset is
used, PMRST is configured as an output that indicates when a
PM reset occurred.
Pull down
R5
TCK
—
I
Test Clock. This signal provides timing for the boundary scan
and TAP controller. This signal should be static, except during
boundary scan testing.
U5
TDI
—
I
Test Data In. Data input for the boundary scan; sampled on
the rising edge of TCK.
Pull up
W5
TMSN
—
I
Pull up
AB8
TRSTN
—
I
Pull down
Test Mode Select (Active-Low). Controls boundary scan test
operations. TMS is sampled on the rising edge of TCK.
Test Reset (Active-Low). This signal is an asynchronous
reset for the TAP controller.
V5
TDO
—
O
Test Data Out. Updated on the falling edge of TCK. The TDO
output is high impedance, except when scanning out test data.
AB9
IC3STATEN
—
I
Global Output Enable. All output and bidirectional buffers will
be high impedance when this input is low. Normally pulled high
internally.
Pull up
Agere Systems Inc.
29
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
3 Pin Information (continued)
3.3.10 Test Pins
These pins are for factory test purposes only and must be connected as stated below for normal operation. They
are used to establish special configurations for testing, inserting test data, etc. For normal operation they should be
left unconnected; each is equipped with a pull-up or pull-down to the inactive (normal operation) state.
Table 16. Test Pins
Pin
Symbol
Type
I/O
Description
N5
SCAN_EN
—
I
Pull down
Test Only. Scan enable (active-high).
M5
SCAN_MODE
—
I
Pull down
Test Only. Serial scan input for testing (active-high).
P5
IDDQ
—
I
Pull up
AE14
BYPASS
—
I
Pull down
Test Only. Enables functional bypassing of the clock synthesis
with a test clock (active-high).
AF14
TSTPHASE
—
I
Pull down
Test Only. Controls bypass of 32 PLL-generated phases with
32 low-speed phases, generated by test logic (active-high).
AD14
ECSEL
—
I
Pull down
Test Only. Enables external test control of 155 MHz clock
phase selection through ETOGGLE and EXDNUP inputs
(active-high).
AC15
ETOGGLE
—
I
Pulldown
Test Only. Moves 155 MHz clock selection one phase per positive pulse > 20ns. Active + pulse.
AE15
EXDNUP
—
I
Pulldown
Test Only. Direction of phase changes.
0 = down
1 = up.
AF15
TSTMODE
—
I
Pulldown
Test Only. Enables CDR test mode.
AD15
TSTSFTLD
—
I
Pulldown
Test Only. Enables CDR test mode shift register.
AE16,
AC16
TSTMUX[1:0]
—
O
Test Only. IDDQ input (active-high).
Test Only. CDR test mode output
Table 17. CDR Power
Pin
Symbol
Type
I/O
Description
AC9
VDDA_CDR
—
I
Analog Power. Isolated analog power supply VDD for CDR.
AB12
VSSA_CDR
—
I
Analog Ground. Isolated analog power supply VSS for CDR.
Symbol
Type
I/O
Description
—
I
Resistor 1, 2. A 100 Ω 1% resistor is should be connected between
these two pins as a reference for the LVDS input buffer termination.
Table 18. LVDS Control Pins
Pin
30
AF12
RESHI
AE12
RESLO
AC11
REF10
—
I
Voltage Reference 1. 1.0 V reference voltage input.
AD12
REF14
—
I
Voltage Reference 2. 1.4 V reference voltage input.
Agere Systems Inc.
Preliminary Data Sheet
May 2001
3 Pin Information
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
(continued)
Table 18. LVDS Control Pins (continued)
Pin
Symbol
Type
I/O
AB10
CTAPRH
—
—
Center Tap 1. For RHSD P/N and RHSC P/N. Optional, 0.1 µF
capacitor connected between CTAP pin and ground, to improve the
common mode rejection of the LVDS input buffers.
AE11
CTAPTH
—
—
Center Tap 2. For THSD P/N and THSC P/N. Optional, 0.1 µF
capacitor connected between CTAP pin and ground, to improve the
common mode rejection of the LVDS input buffers.
AB13
CTAPRP
—
—
Center Tap 3. For RPSD155 P/N and RPSC155 P/N. Optional,
0.1 µF capacitor connected between CTAP pin and ground, to
improve the common mode rejection of the LVDS input buffers.
Agere Systems Inc.
Description
31
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
3 Pin Information (continued)
3.4 Outline Diagram
3.4.1 456-Pin PBGA
Dimensions are in millimeters.
35.00 ± 0.20
+0.70
30.00 –0.00
A1 BALL
IDENTIFIER ZONE
30.00 +0.70
–0.00
35.00
± 0.20
MOLD
COMPOUND
PWB
1.17 ± 0.05
0.56 ± 0.06
2.33 ± 0.21
SEATING PLANE
0.20
0.60 ± 0.10
SOLDER BALL
25 SPACES @ 1.27 = 31.75
CENTER ARRAY
FOR THERMAL
ENHANCEMENT
(OPTIONAL)
A1 BALL
CORNER
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
0.75 ± 0.15
25 SPACES
@ 1.27 = 31.75
1 2 3 4 5 6 7 8 9 10
12 14 16 18 20 22 24 26
11 13 15 17 19 21 23 25
5-6216(F)r.1
32
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
4 Electrical Characteristics
Table of Contents
Contents
Page
4 Electrical Characteristics .................................................................................................................................... 33
4.1 Absolute Maximum Ratings ......................................................................................................................... 34
4.2 Handling Precautions ................................................................................................................................... 34
4.3 Operating Conditions ................................................................................................................................... 34
4.4 Logic Interface Characteristics ..................................................................................................................... 35
4.5 LVDS Interface Characteristics .................................................................................................................... 36
List of Figures
Figure 5. Single-Ended Input Specification ............................................................................................................ 35
List of Tables
Table 19. Absolute Maximum Ratings ................................................................................................................... 34
Table 20. Handling Precaution .............................................................................................................................. 34
Table 21. Recommended Operating Conditions ................................................................................................... 34
Table 22. Logic Interface Characteristics .............................................................................................................. 35
Table 23. LVDS Interface Characteristics ............................................................................................................. 36
Agere Systems Inc.
33
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
4 Electrical Characteristics (continued)
4.1 Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.
Table 19. Absolute Maximum Ratings
Parameter
Symbol
Min
Max
Unit
dc Supply Voltage Range
VDD
–0.5
4.6
V
Power Dissipation
PD
—
—
mW
Tstg
–65
125
°C
Ambient Operating Temperature Range
TA
–40
85
°C
Maximum Voltage (digital input pins)
—
—
5.25
V
Minimum Voltage (digital input pins)
—
–0.3
—
V
Storage Temperature Range
4.2 Handling Precautions
Although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge (ESD) during handling and mounting. Agere employs a human-body model (HBM)
and charged-device model (CDM) for ESD-susceptibility testing and protection design evaluation. ESD voltage
thresholds are dependent on the circuit parameters used in the defined model. No industry-wide standard has
been adopted for the CDM. However, a standard HBM (resistance = 1500 Ω, capacitance = 100 pF) is widely used
and, therefore, can be used for comparison purposes. The HBM ESD threshold presented here was obtained by
using these circuit parameters:
Table 20. Handling Precaution
Device
Voltage
TMXF28155
2000 V
4.3 Operating Conditions
The following tables list the voltages required for proper operation of the TMXF28155 device, along with their tolerances.
Table 21. Recommended Operating Conditions
Parameter
Power
Ground
Input Voltage, High
Input Voltage, Low
1.0 V, LVDS Reference*
1.4 V:,LVDS Reference*
Symbol
VDD
VSS
VIH
VIL
LVDS_REF10
LVDS_REF14
Min
3.14
—
VDD – 1.0
VSS
—
—
Typ
3.3
0.0
—
—
1.0
1.4
Max
3.47
—
5.25
1.0
—
—
Unit
V
V
V
V
V
V
* Internal reference voltage is used if SMPR_LVDS_REF_SEL = 1 (Table 70); or else external voltage is used.
34
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
4 Electrical Characteristics (continued)
4.4 Logic Interface Characteristics
Table 22. Logic Interface Characteristics
Parameter
Input Leakage
Output Current:
Low
High
Output Voltage:
Low
High
Input Capacitance
Symbol
IL
Test Conditions
—
Min
—
Max
1.0
Unit
µA
IOL
IOH
—
—
—
—
2
2
mA
mA
VOL
VOH
CI
—
—
—
VSS
VDD – 0.5
—
0.5
5.25
1.5
V
V
pF
The input specification for the remaining (nonbalanced) inputs are specified in Figure 5.
VIH
VIL
tF
tR
5-6032(F)r.2
Figure 5. Single-Ended Input Specification
Agere Systems Inc.
35
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
4 Electrical Characteristics (continued)
4.5 LVDS Interface Characteristics
3.3 V ± 5% VDD, 0—125 °C, slow—fast process.
Table 23. LVDS Interface Characteristics
.
Parameter
Input Voltage Range, VIA or VIB
Input Differential Threshold
Input Differential Hysteresis
Receiver Differential Input
Impedance
Output Voltage:
Low (VOA or VOB)
High (VOA or VOB)
Output Differential Voltage
Output Offset Voltage
Output Impedance, Single Ended
RO Mismatch Between A and B
Change in Differential Voltage
Between Complementary
States
Change in Output Offset Voltage
Between Complementary
States
Output Current
Output Current
Symbol
Test Conditions
Input Buffer Parameters
VI
|VGPD| < 925 mV, dc—1 MHz
VIDTH
|VGPD| < 925 mV, 311 MHz
VHYST
(+VIDTH) – (–VIDTH)
RIN
With built-in termination,
center-tapped
Output Buffer Parameters
Min
Typ
Max
Unit
0.0
–100
—
80
1.2
—
—
100
2.4
100
—*
120
V
mV
mV
Ω
VOL
VOH
|VOD|
VOS
RO
∆RO
|∆VOD|
RLOAD = 100 Ω ±1%
RLOAD = 100 Ω ±1%
RLOAD = 100 Ω ±1%
RLOAD = 100 Ω ±1%
VCM = 1.0 V and 1.4 V
VCM = 1.0 V and 1.4 V
RLOAD = 100 Ω ±1%
—
0.925
0.25
1.125
40
—
—
—
—
—
—
50
—
—
1.475
—
0.40
1.275
60
10
25
V
V
V
V
Ω
%
mV
∆VOS
RLOAD = 100 Ω ±1%
—
—
25
mV
ISA, ISB
ISAB
Driver shorted to VSS
Drivers shorted together
—
—
—
—
24
12
mA
mA
* Buffer will not produce output transition when input is open-circuited.
36
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
5 Timing Characteristics
Table of Contents
Contents
Page
5 Timing Characteristics ........................................................................................................................................ 37
5.1 TMUX Block Timing ..................................................................................................................................... 39
5.2 DS3 Timing .................................................................................................................................................. 43
5.3 M13 Timing .................................................................................................................................................. 44
5.4 VT Mapper Timing ....................................................................................................................................... 45
5.4.1 VT Mapper Lower-Order Path Overhead Interface Timing ................................................................. 45
5.5 Concentration Highway (CHI) Timing .......................................................................................................... 46
5.6 Parallel System Bus Timing ......................................................................................................................... 47
5.7 NSMI Timing Mode 1 ................................................................................................................................... 49
5.8 SMI Timing Mode 2 (8 pin) ........................................................................................................................... 49
5.9 Framer Only Mode Timing ........................................................................................................................... 51
5.10 Framer—LIU Mode Timing ........................................................................................................................ 53
5.11 Microprocessor Interface Timing ................................................................................................................ 54
5.11.1 Synchronous Mode .......................................................................................................................... 54
5.12 Asynchronous Mode .................................................................................................................................. 56
5.13 General Purpose Interface Timing ............................................................................................................. 60
6 Ordering Information............................................................................................................................................ 61
Figures
Page
Figure 6. Generic Clock Timing .............................................................................................................................. 39
Figure 7. Generic Interface Data Timing ................................................................................................................ 41
Figure 8. VT Mapper Transmit Path Overhead Detailed Timing ............................................................................ 45
Figure 9. VT Mapper Receive Path Overhead Detailed Timing ............................................................................. 45
Figure 10. CHI Transmit I/O Timing........................................................................................................................ 46
Figure 11. CHI Receive I/O Timing......................................................................................................................... 47
Figure 12. Parallel System Bus Interface Transmit I/O Timing............................................................................... 48
Figure 13. Parallel System Bus Interface Receive I/O Timing................................................................................ 48
Figure 14. Microprocessor Interface Synchronous Write Cycle (MPMODE (Pin AD17) = 1) ................................. 54
Figure 15. Microprocessor Interface Synchronous Read Cycle (MPMODE (Pin AD17) = 1) ................................. 55
Figure 16. Microprocessor Interface Asynchronous Write Cycle Description (MPMODE (Pin AC18) = 0) ............ 57
Figure 17. Microprocessor Interface Asynchronous Read Cycle (MPMODE (Pin AC18) = 0) ............................... 59
Tables
Page
Table 24. High-speed Input Clock Specifications .................................................................................................. 39
Table 25. Output Clock Specifications ................................................................................................................... 40
Table 26. Input Timing Specifications .................................................................................................................... 41
Table 27. Output Timing Specifications ................................................................................................................. 42
Table 28. DS3 Input Clock Specifications ............................................................................................................. 43
Table 29. Input Timing Specifications .................................................................................................................... 43
Table 30. Output Timing Specifications ................................................................................................................. 43
Table 31. M13 Clock Specifications ...................................................................................................................... 44
Table 32. Input Timing Specifications .................................................................................................................... 44
Table 33. Output Timing Specifications ................................................................................................................. 44
Table 34. VT Mapper Receive Path Overhead Detailed Timing ............................................................................ 45
Table 35. CHI Transmit Timing Characteristics ..................................................................................................... 46
Table 36. CHI Receive Timing Characteristics ...................................................................................................... 47
Table 37. PSB Interface Transmit Timing Characteristics ..................................................................................... 47
Agere Systems Inc.
37
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
5 Timing Characteristics (continued)
Table of Contents (continued)
Tables
Page
Table 38. PSB Interface Receive Timing Characteristics ...................................................................................... 48
Table 39. NSMI (Mode 1) Input Clock Specifications ............................................................................................ 49
Table 40. Input Timing Specifications .................................................................................................................... 49
Table 41. Output Timing Specifications ................................................................................................................. 49
Table 42. SMI (Mode 2) Input Clock Specifications ............................................................................................... 49
Table 43. Input Timing Specifications .................................................................................................................... 50
Table 44. Output Timing Specifications ................................................................................................................. 50
Table 45. Framer Only Mode Clock Specifications ............................................................................................... 51
Table 46. Framer Mode Only Input Timing Specifications ..................................................................................... 52
Table 47. Framer Mode Only Output Timing Specifications .................................................................................. 52
Table 48. Framer—LIU Mode Clock Specifications ............................................................................................... 53
Table 49. Framer—LIU Mode Input Timing Specifications .................................................................................... 54
Table 50. Framer—LIU Mode Output Timing Specifications ................................................................................. 54
Table 51. Microprocessor Interface Synchronous Write Cycle Specifications ...................................................... 55
Table 52. Microprocessor Interface Synchronous Read Cycle Specifications ...................................................... 56
Table 53. Microprocessor Interface Asynchronous Write Cycle Specifications ..................................................... 58
Table 54. Microprocessor Interface Asynchronous Read Cycle Specifications .................................................... 60
Table 55. Input Timing Specifications .................................................................................................................... 60
Table 56. Output Timing Specifications ................................................................................................................. 61
38
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
5 Timing Characteristics (continued)
5.1 TMUX Block Timing
The TMUX (STS-N/STM-1) timing parameters can be grouped separately for clocks, inputs, and outputs. Table 24
shows the input clock specifications for this device. The rise and fall times refer to the transition times from 10% to
90% of full swing.
For definitions of the signal names, see the pin descriptions section at the beginning of this data sheet.
Table 24. High-speed Input Clock Specifications
Symbol Parameter Signal Name
fCK
Operating
Frequency
tCK
Clock
Period
tCLKHI
Clock
Pulse High
Time
tR
Rise Time
tF
Fall Time
THSCP/N
RHSCP/N
RPSC155P/N
THSCP/N
RHSCP/N
RPSC155P/N
THSCP/N
RHSCP/N
RPSC155P/N
THSCP/N
RHSCP/N
RPSC155P/N
THSCP/N
RHSCP/N
RPSC155P/N
155 Clock
Min
Nom
— 155.52 ±30 ppm
— 155.52 ±30 ppm
— 155.52 ±30 ppm
—
6.43 ±0.4%
—
6.43 ±0.5%
—
6.43 ±0.5%
2.5
—
2.5
—
2.5
—
—
—
—
—
—
—
—
—
—
—
—
—
Max Min
—
—
—
—
—
—
—
—
—
—
3.9 7.8
3.9 7.8
3.9
1.5
—
1.5
—
1.5
1.5
—
1.5
—
1.5
51 Clock
Nom
51.84 ±50 ppm
51.84 ±50 ppm
19.29 ±0.4%
19.29 ±0.5%
—
—
—
—
—
—
—
—
—
—
Unit
Max
— MHz
— MHz
MHz
—
ns
—
ns
ns
11.6 ns
11.6 ns
ns
5.0
ns
5.0
ns
ns
5.0
ns
5.0
ns
ns
Note: When the true and complement inputs are floating, the input buffer will not oscillate.
tCK
tCLKHI
tR
tF
5-9077(F)
Figure 6. Generic Clock Timing
Agere Systems Inc.
39
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
5 Timing Characteristics (continued)
The output clock specifications are shown in Table 25, where the symbols match the waveform diagram above.
Table 25. Output Clock Specifications
Signal Name
Reference CLK*
Frequency
TLSCLK
TTOACCLK
RLSCLK
THSCP/N
THSCP/N
RHSCP/N or
Internal CDR Clock
RHSCP/N or
Internal CDR Clock
THSCP/N
THSCP/N
RHSCP/N
THSCP/N
RHSCP/N
RTOACCLK
TPSC155P/N
TPOACCLK
RPOACCLK
TLSC52
RLSC52
19.44 MHz
5.184 MHz
19.44 MHz
Clock Pulse High
Time (tCLKHI)
24.43—27.00 ns
91.62—101.3 ns
24.43—27.00 ns
Test
Condition
CL = 50 pF
CL = 15 pF
CL = 50 pF
Max Rise
Time (tR)
3.5 ns
3.5 ns
3.5 ns
Max Fall
Time (tF)
3.5 ns
3.5 ns
3.5 ns
5.184 MHz
91.62—101.3 ns
CL = 15 pF
3.5 ns
3.5 ns
155.5 MHz
5.184 MHz
5.184 MHz
51.84 MHz
51.84 MHz
3.119—3.311 ns
91.62—101.3 ns
91.62—101.3 ns
9.162—10.13 ns
9.162—10.13 ns
CL = 15 pF
CL = 15 pF
CL = 15 pF
CL = 30 pF
CL = 30 pF
1.5 ns
3.5 ns
3.5 ns
3.0 ns
3.0 ns
1.5 ns
3.5 ns
3.5 ns
3.0 ns
3.0 ns
* The specifications for the table are with all loopbacks disabled.
Note: Any of the telecom signals being used as inputs (slave Super Mapper) need to meet these same output
clock specifications.
40
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
5 Timing Characteristics (continued)
Table 26. Input Timing Specifications
Input Name
Reference CLK
THSSYNC
TLSDATA[7:0]
TLSPAR
TLSSPE
TLSJ0J1V1
TLSV1
TLSSYNC52
TTOACDATA
TPOACDATA
THSC ↑
TLSCLK ↑
TLSCLK ↑
TLSCLK ↑
TLSCLK ↑
TLSCLK ↑
TLSC52 ↑
TTOACCLK ↑
TPOACCLK ↑
RHSDP/N
RPSD155P/N
RLSDATA[7:0]
RLSPAR
RLSSPE
RLSJ0J1V1
RLSV1
RLSSYNC52
RHSCP/N ↑↓
RPSC155P/N
RLSCLK ↑
RLSCLK ↑
RLSCLK ↑
RLSCLK ↑
RLSCLK ↑
RLSC52 ↑
LOSEXT
AUTO_AIS[3:1]
NA
NA
Min Setup Time (tS)
Transmit Signals
2.0 ns
5.0 ns
5.0 ns
5.0 ns
5.0 ns
5.0 ns
4.0 ns
10.0 ns
10.0 ns
Receive Signals
2.0 ns
2.0 ns
5.0 ns
5.0 ns
5.0 ns
5.0 ns
5.0 ns
4.0 ns
Miscellaneous Signals
ASYNC
ASYNC
Min Hold Time (tH)
0.0 ns
0.0 ns
0.0 ns
0.0 ns
0.0 ns
0.0 ns
0.0 ns
0.0 ns
0.0 ns
0.0 ns
0.0 ns
0.0 ns
0.0 ns
0.0 ns
0.0 ns
0.0 ns
0.0 ns
ASYNC
ASYNC
CLOCK
tSU
tH
DATA
CLOCK
tPD
DATA
Figure 7. Generic Interface Data Timing
Agere Systems Inc.
41
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
5 Timing Characteristics (continued)
Table 27. Output Timing Specifications
Output Name
THSDP/N
TPSD155P/N
TLSDATA[7:0]
TLSPAR
TLSSPE
TLSJ0J1V1
TLSV1
TLSSYNC52
TTOACSYNC
TPOACSYNC
RLSDATA[7:0]
RLSPAR
RLSSPE
RLSJOJ1V1
RLSVI
RLSSYNC52
RTOACSYNC
RTOACDATA
RPOACSYNC
RPOACDATA
RHSFSYNCN
AUTO_AIS[3:1]
Reference CLK
Test
Conditions
Propagation Delay*
tPD
Min
Max
Transmit Signals
CL = 15 pF
0.6
CL = 15 pF
0.6
CL = 50 pF
4.0
CL = 50 pF
4.0
CL = 50 pF
4.0
CL = 50 pF
4.0
CL = 50 pF
4.0
CL = 30 pF
0.0
CL = 15 pF
10.0
CL = 15 pF
10.0
Receive Signals
RLSCLK ↑
CL = 50 pF
4.0
RLSCLK ↑
CL = 50 pF
4.0
RLSCLK ↑
CL = 50 pF
4.0
RLSCLK ↑
CL = 50 pF
4.0
RLSCLK ↑
CL = 50 pF
4.0
RLSC52 ↑
CL = 30 pF
0.0
RTOACCLK ↑↓
CL = 15 pF
10.0
RTOACCLK ↑↓
CL = 15 pF
10.0
RPOACCLK ↑↓
CL = 15 pF
10.0
RPOACCLK ↑↓
CL = 15 pF
10.0
RLSCLK ↓
CL = 30 pF
0.0
Miscellaneous Signals
NA
—
ASYNC
THSCP/N ↑
TPSC155P/N
TLSCLK ↑
TLSCLK ↑
TLSCLK ↑
TLSCLK ↑
TLSCLK ↑
TLSC52 ↑
TTOACCLK ↑↓
TPOACCLK ↑↓
Unit
2.9
2.9
12.0
12.0
12.0
12.0
12.0
6.0
30.0
30.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
12.0
12.0
12.0
12.0
12.0
6.0
30.0
30.0
30.0
30.0
8.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ASYNC
—
* Propagation delay skew, tPLH – tPHL, is ±200 ps.
42
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
5 Timing Characteristics (continued)
5.2 DS3 Timing
Table 28. DS3 Input Clock Specifications
Symbol
Parameter
Signal Name
Min
Max
Unit
fCK
Clock Frequency
—
Clock Period
Clock Pulse High Time
tR
Rise Time
22.353
22.353
16
16
2
ns
tCLKHI
—
—
—
—
6
6
0
44.736 MHz ±50 ppm
tCK
ns
tF
Fall Time
DS3DATAINCLK
DS3DATAOUTCLK
DS3DATAINCLK
DS3DATAOUTCLK
DS3DATAINCLK
DS3DATAOUTCLK
DS3DATAINCLK
DS3DATAOUTCLK
DS3DATAINCLK
DS3DATAOUTCLK
0
2
ns
ns
Table 29. Input Timing Specifications
Input Name
Reference CLK
Min Setup Time (tS)
Min Hold Time (tH)
DS3POSDATAIN
DS3DATAINCLK ↑↓
4
0
DS3NEGDATAIN
DS3DATAINCLK ↑↓
4
0
Table 30. Output Timing Specifications
Output Name
Reference CLK
Test Conditions
DS3POSDATAOUT
DS3NEGDATAOUT
DS3DATAOUTCLK ↑↓
DS3DATAOUTCLK ↑↓
CL = 15 pF
CL = 15 pF
Agere Systems Inc.
Propagation Delay tPD
Min
Max
2
6
2
6
Unit
ns
ns
43
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
5 Timing Characteristics (continued)
5.3 M13 Timing
Table 31. M13 Clock Specifications
Symbol
Parameter
Signal Name
Min
Nom
Max
Unit
fCK
Clock
Frequency
tCLKHI
Clock Pulse
High Time
Rise Time
tF
Fall Time
—
—
2.048
1.544
—
—
—
212.19
212.19
212.19
212.19
0
0
0
0
0
0
0
0
0
0
0
0
0
0
93.983 gapped
28.195 gapped
32.768
24.704
6.312
93.983
28.195
223.53
223.53
223.53
223.53
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
65.536
49.408
—
—
—
250.77
250.77
250.77
250.77
3
3
3
3
3
3
3
3
3
3
3
3
3
3
kHz
kHz
MHz
MHz
MHz
kHz
kHz
ns
tR
TCBCLK
TDLCLK
E1XCLK
DS1XCLK
DS2AISCLK
RCBCLK
RDLCLK
TCBCLK
TDLCLK
RCBCLK
RDLCLK
TCBCLK
TDLCLK
E1XCLK
DS1XCLK
DS2AISCLK
RCBCLK
RDLCLK
TCBCLK
TDLCLK
E1XCLK
DS1XCLK
DS2AISCLK
RCBCLK
RDLCLK
ns
ns
Table 32. Input Timing Specifications
Input Name
Reference CLK
TCBDATA
TDLDATA
TCBCLK ↑
TDLCLK ↑
Setup Time (tS)
Min
Max
50
—
50
—
Hold Time (t H)
Min
Max
0
—
0
—
Unit
ns
ns
Table 33. Output Timing Specifications
44
Output Name
Reference CLK
Test Conditions
TCBSYNC
RCBSYNC
RCBDATA
RDLDATA
TCBCLK ↑
RCBCLK ↑
RCBCLK ↑
RDLCLK ↑
CL = 15 pF
CL = 15 pF
CL = 15 pF
CL = 15 pF
Propagation Delay t PD
Min
Max
2
10
2
10
2
10
2
10
Unit
ns
ns
ns
ns
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
5 Timing Characteristics (continued)
5.4 VT Mapper Timing
5.4.1 VT Mapper Lower-Order Path Overhead Interface Timing
Table 34. VT Mapper Receive Path Overhead Detailed Timing
Symbol
fCK
tCK
tCLKHI
tR
tF
tSD
tHD
tSV
tHV
tPDV
tPDD
Parameter
Clock Frequency
Clock Period
Clock Pulse High Time
Clock Rise Time
Clock Fall Time
LOPOH Data Setup Time
LOPOH Data Hold Time
LOPOH Valid Signal Setup Time
LOPOH Valid Signal Hold Time
Clock to LOPOH Valid Signal Out
Clock to LOPOH Data Out
Min
Max
Unit
6.48
154
50
0
0
5
0
5
0
0
0
6.48
154
75
3
3
—
—
—
—
5
5
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tC K
L O PO H C LK IN
tSV
L O P O H VA L ID IN
tHV
tSD
tHD
L O P O H D ATA IN
5-9078(F)
Figure 8. VT Mapper Transmit Path Overhead Detailed Timing
tCK
LOPOHCLKOUT
tPDV
LOPOHVALIDOUT
tPDD
LOPOHDATAOUT
5-9079(F)
Figure 9. VT Mapper Receive Path Overhead Detailed Timing
Agere Systems Inc.
45
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
5 Timing Characteristics (continued)
5.5 Concentration Highway (CHI) Timing
Table 35 and Table 36 with Figure 10 and Figure 11, respectively, illustrate the detailed CHI timing for clock, data,
and frame synchronization.
Table 35. CHI Transmit Timing Characteristics
Symbol
fCK
tCK
tR
tF
tS
tH
tPD
Parameter
Clock Frequency*
Clock Period
Clock Rise Time
Clock Fall Time
Frame Sync Setup Time
Frame Sync Hold Time
Clock to CHI Data Delay
Min
Max
Unit
2.048
488.2
0
0
35
0
—
16.384
61.04
3
3
—
—
25
MHz
ns
ns
ns
ns
ns
ns
* fCK can be either 2.048 MHz, 4.096 MHz, 8.192 MHz, or 16.384 MHz.
tCK
LINETXCLK29
CLOCK
tH
tS
LINETXSYNC29
FRAME SYNC
tPD
LINETXSYNC[28:1]
DATA
5-9080(F)
Figure 10. CHI Transmit I/O Timing
46
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
5 Timing Characteristics (continued)
Table 36. CHI Receive Timing Characteristics
Symbol
Parameter
fCK
tCK
tR
tF
tSSYNC
tHSYNC
tSDATA
Clock Frequency*
Clock Period
Clock Rise Time
Clock Fall Time
Frame Sync Setup Time
Frame Sync Hold Time
CHI Data Setup Time
tHDATA
CHI Data Hold Time
Min
Max
Unit
2.048
488.2
0
0
30
0
25
16.384
61.04
3
3
—
—
—
—
MHz
ns
ns
ns
ns
ns
ns
0
ns
* fCK can be either 2.048 MHz, 4.096 MHz, 8.192 MHz, or 16.384 MHz.
tCK
LINERXCLK29
CLOCK
tSSYNC
tHSYNC
LINERXSYNC29
FRAME SYNC
tSDATA
tHDATA
LINERXSYNC[28:1]
DATA
5-9081(F)
Figure 11. CHI Receive I/O Timing
5.6 Parallel System Bus Timing
Table 37 and Table 38 with Figure 12 and Figure 13, respectively, show the transmit and receive timing. In the
transmit direction (to the system interface) the frame sync is sampled and the data is clocked out on the rising edge
of the clock. In the receive direction (from the switch) the data and frame sync are sampled on the rising edge of
the clock.
Table 37. PSB Interface Transmit Timing Characteristics
Symbol
fCK
tCK
tR
tF
tS
tH
tPD
Agere Systems Inc.
Parameter
Clock Frequency
Clock Period
Clock Rise Time
Clock Fall Time
Frame Sync Setup Time
Frame Sync Hold Time
Clock to PSB Out Delay
Min
Max
Unit
19.44
51.44
0
0
8
0
3
19.44
51.44
3
3
—
—
10
MHz
ns
ns
ns
ns
ns
ns
47
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
5 Timing Characteristics (continued)
LINETXCLK29
CLOCK
tS
tH
tCK
tPD
LINETXSYNC29
FRAME SYNC
6 (3) STUFFED TS IN DS1 (E1)
LINETXSYNC[16:1]
DATA
STUFFED TS
STUFFED TS
DEV #0, TS #1, DEV #0, TS #1,
LINK #0
LINK #1
5-9082(F)
Figure 12. Parallel System Bus Interface Transmit I/O Timing
Table 38. PSB Interface Receive Timing Characteristics
Symbol
fCK
tCK
tR
tF
Parameter
tSSYNC
tHSYNC
tSDATA
Clock Frequency
Clock Period
Clock Rise Time
Clock Fall Time
Frame Sync Setup Time
Frame Sync Hold Time
PSB to Clock Setup Time
tHDATA
PSB Hold Time from Clock
Min
Max
Unit
19.44
51.44
0
0
8
0
8
19.44
51.44
3
3
—
—
—
—
MHz
ns
ns
ns
ns
ns
ns
0
ns
LINERXCLK29
CLOCK
tSSYNC
tHSYNC
tCK
tSDATA
tHDATA
LINERXSYNC29
FRAME SYNC
LINERXSYNC[16:1]
DATA
STUFFED TS
STUFFED TS
DEV #0, TS #1, DEV #0, TS #1,
LINK #0
LINK #1
DATA SAMPLED
5-9083(F)
Figure 13. Parallel System Bus Interface Receive I/O Timing
48
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
5 Timing Characteristics (continued)
5.7 NSMI Timing Mode 1 (6 Pin)
Table 39. NSMI (Mode 1) Input Clock Specifications
Symbol
Parameter
Signal Name
Min
Nom
Max
Unit
tCK
tR
Clock
Frequency
Clock Pulse
High Time
Rise Time
tF
Fall Time
LINE_TXCLK29
LINE_RXCLK29
LINE_TXCLK29
LINE_RXCLK29
LINE_TXCLK29
LINE_RXCLK29
LINE_TXCLK29
LINE_RXCLK29
—
—
6
6
—
—
—
—
51.84/44.736 ±50 ppm
51.84/44.736 ±50 ppm
—
—
—
—
—
—
—
—
12
12
3
3
3
3
MHz
MHz
ns
ns
ns
ns
ns
ns
tCKHI
Table 40. Input Timing Specifications
Input Name
Reference CLK
LINE_RXDATA29
LINE_RXSYNC29
LINE_RXCLK29 ↓
LINE_RXCLK29 ↓
Setup Time (tS)
Min
Max
5
—
5
—
Hold Time
Min
0
0
(t H)
Max
—
—
Unit
ns
ns
Table 41. Output Timing Specifications
Output Name
Reference CLK
Test Conditions
LINE_TXDATA29
LINE_TXSYNC29
RXDATAEN
TXDATAEN
LINE_TXCLK29 ↑
LINE_TXCLK29 ↑
LINE_TXCLK29 ↑
LINE_TXCLK29 ↑
CL = 15 pF
CL = 15 pF
CL = 15 pF
CL = 15 pF
Propagation Delay tPD
Min
Max
0
3.5
0
3.5
0
3.5
0
3.5
Unit
ns
ns
ns
ns
5.8 SMI Timing Mode 2 (8 Pin)
Table 42. SMI (Mode 2) Input Clock Specifications
Symbol
tCK
Parameter
Clock
Period
tCKHI
Clock Pulse
High Time
tR
Rise Time
tF
Fall Time
Agere Systems Inc.
Signal Name
LINE_TXCLK29
LINE_RXCLK29
RXDATAEN
LINE_TXCLK29
LINE_RXCLK29
RXDATAEN
LINE_TXCLK29
LINE_RXCLK29
RXDATAEN
LINE_TXCLK29
LINE_RXCLK29
RXDATAEN
Min
44.736 MHz ±50 ppm
TBD
TBD
6
6
TBD
0
0
0
0
0
0
Nom
19.29
19.29
TBD
1/3 tck
1/3 or 1/2 tck
TBD
—
—
—
—
—
—
Max
TBD
TBD
TBD
TBD
TBD
TBD
3
3
3
3
3
3
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
49
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
5 Timing Characteristics (continued)
Table 43. Input Timing Specifications
Input Name
Reference CLK
LINE_RXDATA29
LINE_RXSYNC29
LINE_RXCLK29 ↓
LINE_RXCLK29 ↓
Setup Time (tS)
Min
Max
5
—
5
—
Hold Time
Min
0
0
(tH)
Max
—
—
Unit
ns
ns
Table 44. Output Timing Specifications
Output Name
Reference CLK
Test Conditions
LINE_TXDATA29
LINE_TXSYNC29
TXDATAEN
LINE_TXCLK29 ↑
LINE_TXCLK29 ↑
RXDATAEN ↑
CL = TBD pF
CL = TBD pF
CL = TBD pF
50
Propagation Delay tPD
Min
Max
0
3.5
0
3.5
0
3.5
Unit
ns
ns
ns
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
5 Timing Characteristics (continued)
5.9 Framer Only Mode Timing
Table 45. Framer Only Mode Clock Specifications
Symbol
tCK
Parameter
Clock
Frequency
Signal Name
TLSC52
LINERXDATA29
LINERXCLK[28:1]
LINERXCLK29
LINETXCLK[28:1]
LINETXCLK29
tCKHI
Clock Pulse
High Time
TLSC52
LINERXDATA29
LINERXCLK[28:1]
LINERXCLK29
LINETXCLK[28:1]
LINETXCLK29
tR
Rise Time
TLSC52
LINERXDATA29
LINERXCLK[28:1]
LINERXCLK29
LINETXCLK[28:1]
LINETXCLK29
Agere Systems Inc.
Min
–50 ppm
–130 ppm
–50 ppm
–130 ppm
–50 ppm
–50 ppm
–50 ppm
–50 ppm
–130 ppm
–50 ppm
–50 ppm
–50 ppm
–50 ppm
6
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
0
0
0
0
0
0
0
0
0
0
0
0
0
Nom
51.84
1.544
or 2.048
1.544
2.048
or 4.096
or 8.192
or 16.384
1.544
or 2.048
or 4.096
or 8.192
or 16.384
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
50 ppm
130 ppm
50 ppm
130 ppm
50 ppm
50 ppm
50 ppm
50 ppm
130 ppm
50 ppm
50 ppm
50 ppm
50 ppm
12
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
3
3
3
3
3
3
3
3
3
3
3
3
3
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
51
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
5 Timing Characteristics (continued)
Table 45. Framer Only Mode Clock Specifications (continued)
Symbol
tF
Parameter
Fall Time
Signal Name
TLSC52
LINERXDATA29
LINERXCLK[28:1]
LINERXCLK29
LINETXCLK[28:1]
LINETXCLK29
Min
0
0
0
0
0
0
0
0
0
0
0
0
0
Nom
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
3
3
3
3
3
3
3
3
3
3
3
3
3
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 46. Framer Mode Only Input Timing Specifications
Input Name
Reference CLK
LINERXDATA[28:1]
LINERXSYNC[28:1]
LINERXSYNC29
LINETXSYNC29
LINERXCLK[28:1] ↑
LINERXCLK[28:1] ↑
LINERXCLK29 ↑
LINETXCLK29 ↑
Setup Time (tS)
Min
Max
25
—
30
—
30
—
35
—
Hold Time
Min
0
0
0
0
(tH)
Max
—
—
—
—
Unit
ns
ns
ns
ns
Table 47. Framer Mode Only Output Timing Specifications
Output Name
Reference CLK
Test Conditions
Propagation Delay tPD
Min
Max
Unit
LINETXDATA[28:1]
LINETXCLK[28:1] ↑
CL = TBD pF
25
TBD
ns
LINETXDATA29
LINETXCLK29 ↑
CL = TBD pF
25
TBD
ns
LINETXSYNC[28:1]
LINETXCLK[28:1] ↑
CL = TBD pF
TBD
TBD
ns
52
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
5 Timing Characteristics (continued)
5.10 Framer—LIU Mode Timing
Table 48. Framer—LIU Mode Clock Specifications
Symbol
tCK
Parameter
Clock
Frequency
Signal Name
TLSC52
LINERXCLK[28:1]
LINERXCLK29
LINETXCLK[28:1]
LINETXCLK29
tCKHI
Clock Pulse
High Time
TLSC52
LINERXDATA29
LINERXCLK[28:1]
LINERXCLK29
LINETXCLK[28:1]
LINETXCLK29
tR
Rise Time
TLSC52
LINERXDATA29
LINERXCLK[28:1]
LINERXCLK29
LINETXCLK[28:1]
LINETXCLK29
tF
Fall Time
TLSC52
LINERXDATA29
LINERXCLK[28:1]
LINERXCLK29
LINETXCLK[28:1]
LINETXCLK29
Agere Systems Inc.
Min
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Nom
51.84
TBD
2.048
or 4.096
or 8.192
or 16.384
TBD
or 2.048
or 4.096
or 8.192
or 16.384
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Unit
MHz
TBD
MHz
MHz
MHz
MHz
TBD
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
53
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
5 Timing Characteristics (continued)
Table 49. Framer—LIU Mode Input Timing Specifications
Input Name
Reference CLK
LINERXDATA[28:1]
LINERXDATA29
LINERXSYNC[28:1]
LINERXSYNC29
LINERXCLK[28:1] ↑↓
LINERXCLK29 ↑↓
LINERXCLK[28:1] ↑↓
LINERXCLK29 ↑↓
Setup Time (tS)
Min
Max
TBD
35
TBD
35
TBD
35
TBD
35
Hold Time (t H)
Min
Max
35
—
35
—
35
—
35
—
Unit
ns
ns
ns
ns
Table 50. Framer—LIU Mode Output Timing Specifications
Output Name
Reference CLK
Test Conditions
LINETXDATA[28:1]
LINETXDATA29
LINETXSYNC[28:1]
LINETXSYNC29
LINETXCLK[28:1] ↑↓
LINETXCLK29 ↑↓
LINETXCLK[28:1] ↑↓
LINETXCLK29 ↑↓
CL = TBD pF
CL = TBD pF
CL = TBD pF
CL = TBD pF
Propagation Delay tPD
Min
Max
–35
35
–35
35
–35
35
–35
35
Unit
ns
ns
ns
ns
5.11 Microprocessor Interface Timing
5.11.1 Synchronous Mode
The synchronous microprocessor interface mode is selected when MPMODE (pin AD17) = 1. Interface timing for
the synchronous mode write cycle is given in Figure 14 and in Table 51 and for the read cycle in Figure 15 and in
Table 52.
Note: In addition to the MPU_CLK, the VT mapper block also requires TLSC52,TLSSYNC52, RLSC52,
RLSSYNC52 signals to access specific portions of the register map. The user needs to make sure that the
VT_RDY bit is set before VT_MAPPER reads/writes can occur.
tCLK
T1
T2
T3
Tn – 2
Tn – 1
Tn
MPCLK
(66 MHz MAX)
tWS
tAPD
tCSNVS
tAPD
ADDR[9:0]
CSN
tADSNVS
tAIPD
ADSN
tAPD
tWS
RWN
tAPD
tWS
DATA[15:0]
(INPUT)
tDTNIPD
tDTNVPD
tADSNVDTF
DTN
HIGH Z
HIGH Z
5-7659(F)a
Figure 14. Microprocessor Interface Synchronous Write Cycle (MPMODE (Pin AD17) = 1)
54
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
5 Timing Characteristics (continued)
MPCLK
16 MHz minimum to 66 MHz maximum frequency.
ADDR [19:0] The address will be available throughout the entire cycle.
DATA[15:0]
Data will be available during cycle T1.
RWN (Input) The read (H) write (L) signal is always high except during a write cycle.
CSN (Input) Chip select is an active-low signal.
DTN (Output) Data transfer acknowledge is active-low for one clock and then driven high before entering a highimpedance state. (This is done with an I/O pad using the input as feedback to qualify the 3-state
term.) DTN will become 3-stated when CSN is high. Typically DTN is active 4 or 5 MPCLK cycles
after ADSN is low.
ADSN (Input) Address strobe is active-low. ADSN must be 1 MPCLK clock period wide.
Table 51. Microprocessor Interface Synchronous Write Cycle Specifications
(See Figure 14 on page 54 for the timing diagram.)
Symbol
Parameter
TCLK
tWS
tAPD
MPCLK 16 MHz Min—66 MHz Max Frequency
ADDR, RWN, DATA (write) Valid to MPCLK
MPCLK to ADDR, RWN, DATA, CSN (write) Invalid
CSN Valid to MPCLK
ADSN Valid to MPCLK
MPCLK to ADSN Invalid
MPCLK to DTN Valid
MPCLK to DTN Invalid
ADSN Valid to DT Falling
tCSNVS
tADSNVS
tAIPD
tDTNVPD
tDTNIPD
TADSNVDTF
T0
T1
T2
Tn – 4
Setup (ns)
(Min)
—
3.5
—
3.5
5.5
—
—
—
—
Tn – 3
Tn – 2
Hold (ns) Delay (ns) Delay (ns)
(Min)
(Max)
(Min)
—
—
—
0
—
—
5
—
—
0
—
—
0
—
—
5
—
—
—
16
4
—
16
4
—
1000
—
Tn – 1
Tn
MPCLK
(66 MHz MAX)
tAPD
tAVS
ADDR[9:0]
tCSNSU
CSN
tADSNSU
tSNIPD
ADSN
RWN
tDVPD
tADSNVDTF
DTN
HIGH Z
tDIPD
HIGH Z
tDAIPD
DATA[15:0]
(OUTPUT)
5-7660(F).a
Figure 15. Microprocessor Interface Synchronous Read Cycle (MPMODE (Pin AD17) = 1)
Agere Systems Inc.
55
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
5 Timing Characteristics (continued)
MPCLK
16 MHz minimum to 66 MHz maximum frequency.
ADDR [19:0] The address will be available throughout the entire cycle, and must be stable before ADSN turns
high.
DATA [15:0]
Read data is stable in Tn –1.
RWN (Input) The read (H) write (L) signal is always high during the read cycle.
CSN (Input) Chip select is an active-low signal.
DTN (Output) Data transfer acknowledge on the host bus interface is initiated on T6. This signal is active for one
clock and then driven high before entering a high-impedance state. (This is done with an I/O pad
using the input as feedback to qualify the 3-state term.) DT will become 3-stated when CS is high.
Typically DTN is active 4 or 5 MPCLK cycles after ADSN is low.
ADSN (Input) Address strobe is active-low. ADSN must be one MPCLK clock period wide.
Table 52. Microprocessor Interface Synchronous Read Cycle Specifications
(See Figure 15 on page 55 for the timing diagram.)
Symbol
Parameter
tCLK
tAVS
tAPD
MPCLK 16 MHz Min—66 MHz Max Frequency
ADDR Valid to MPCLK
MPCLK to ADDR Invalid
CSN Active to MPCLK
ADSN Valid to MPCLK
MPCLK to ADSN Inactive
MPCLK to DTN Valid
MPCLK to DTN Invalid
MPCLK to DATA 3-state
ADSN Valid to DT Falling
tCSNSU
tADSNSU
tSNIPD
tDVPD
tDIPD
tDAIPD
tADSNVDTF
Setup (ns)
(Min)
—
3.5
—
3.5
5.5
—
—
—
—
—
Hold (ns)
(Min)
—
0
5
0
0
5
—
—
—
—
Delay (ns)
(Max)
—
—
—
—
—
—
8
8
8
1000
5.12 Asynchronous Mode
The asynchronous microprocessor interface mode is selected when MPMODE (pin AC18) = 0. Interface timing for
the asynchronous mode write cycle is given in Figure 16 and in Table 53, and for the read cycle in Figure 17 and in
Table 54 (see pages 59—60).
56
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
5 Timing Characteristics (continued)
ADDR[19:0]
tCSFDSF
tAICSR
CSN
tAVADSF
tADSRAI
ADSN
tAVDSF
tDSNRAI
DSN
tRWFDSF
tDSRRWR
tDVDSF
tDSRDI
RWN
DATA[15:0]
(INPUT)
tADSRDTR
tCSFDTR
DTN
HIGH Z
tDSFDTF
tCSRDT3
HIGH Z
5-7661(F).ar.1
Figure 16. Microprocessor Interface Asynchronous Write Cycle Description (MPMODE (Pin AC18) = 0)
ADDR [19:0] Address is asynchronously passed from the host bus to the internal bus. The address will be available throughout the entire cycle.
DATA [15:0]
Write data is asynchronously passed from the host bus to the internal bus. Data will be available
throughout the entire cycle.
RWN (Input) The read (H) write (L) signal is always high except during a write cycle.
CSN (Input) Chip select is an active-low signal.
DTN (Output) Data transfer acknowledge (active-low). DTN is driven asynchronously based on the arrival of CSN.
DTN is driven high until the internal transaction is done. DTN is driven high again when either ADSN
or DSN is deasserted. DTN will become 3-stated when CSN is high.
ADSN (Input) Address strobe is active-low. ADSN must be a minimum of one MPCLK clock period wide.
DSN (Input) Data strobe is active-low.
Agere Systems Inc.
57
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
5 Timing Characteristics (continued)
Table 53. Microprocessor Interface Asynchronous Write Cycle Specifications
(See Figure 16 on page 57 for the timing diagram.)
Symbol
tCSFDSF
tAICSR
tAVADSF
tADSRAI
tAVDSF
tDSNRAI
tRWFDSF
tDSRRWR
tDVDSF
tDSRDI
tCSFDTR
tDSFDTF
tADSRDTR
tCSRDT3
Parameter
CSN Fall to DSN Fall
ADDR Invalid to CSN Rise
ADDR Valid to ADSN Fall
ADSN Rise to ADDR Invalid
ADDR Valid to DSN Fall
DSN Rise to ADDR Invalid
RWN Fall to DSN Fall
DSN Rise to RWN Rise
DATA Valid to DSN Fall
DSN Rise to DATA Invalid
CSN Fall to DTN Rise
DSN Fall to DTN Fall
ADSN Rise to DTN Rise
CSN Rise to DTN 3-state
Min Interval (ns)
0
0
0
0
0
0
0*
0*
0*
0*
20
120
20§
10
Max Interval (ns)
—
—
—
—
—
—
—
—
—
—
—
280†‡
—
—
* Simulation results.
† Falling edges of ADSN and DSN determine falling edge of DTN.
‡ DTN fall is variable, depending on the block selected for access, and may be longer than the typical maximum specified.
§ Rising edge of ADSN determines rising edge of DTN.
Note: Specifications are valid for 50 MHz MPCLK with MPMODE = 0. Address strobe (ADSN) and chip select
(CSN) may be connected and driven from the same source. In this configuration, the setup and hold times
for ADSN must be satisfied.
58
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
5 Timing Characteristics (continued)
ADDR[19:0]
tAICSR
tCSFDSF
CSN
tADSRAI
tAVADSF
ADSN
tDSNRAI
tAVDSF
DSN
RWN
tCSFDTR
tCSRDT3
tDSFDTF
DTN
tADSRDTR
HIGH Z
HIGH Z
tDTVDV
HIGH Z
tADSRD3
HIGH Z
DATA[15:0]
5-7662(F).ar.1
Figure 17. Microprocessor Interface Asynchronous Read Cycle (MPMODE (Pin AC18) = 0)
ADDR [19:0] Address is asynchronously passed from the host bus to the internal bus. The address will be available throughout the entire cycle.
DATA [15:0]
Read data on the internal bus is only valid for one clock cycle; therefore, a latch is necessary to meet
the correct timing on the host bus.
RWN (Input) The read (H) write (L) signal is always high during a read cycle.
CSN (Input) Chip select is an active-low signal.
DTN (Output) Data transfer acknowledge (active-low). DTN is driven asynchronously based on the arrival of CSN,
DSN, and ADSN. DTN is driven high while the internal bus transaction is in progress. There is no
need to provide synchronization to outgoing signals in this mode. DTN is driven high and then placed
in a high-impedance state when either ADSN or DSN is deasserted. DTN will become 3-stated when
CSN is high.
ADSN (Input) Address strobe is active-low.
DSN (Input) Data strobe is active-low.
Agere Systems Inc.
59
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
5 Timing Characteristics (continued)
Table 54. Microprocessor Interface Asynchronous Read Cycle Specifications
(See Figure 17 on page 59 for the timing diagram.)
Symbol
tCSFDSF
tAICSR
tAVADSF
tADSRAI
tAVDSF
tDSNRAI
tCSFDTR
tDSFDTF
Parameter
CSN Fall to DSN Fall
ADDR Invalid to CSN Rise
ADDR Valid to ADSN Fall
ADSN Rise to ADDR Invalid
ADDR Valid to DSN Fall
DSN Rise to ADDR Invalid
CSN Fall to DTN Rise
DSN Fall to DTN Fall
tADSRDTR ADSN Rise to DTN Rise
tCSRDT3 CSN Rise to DTN 3-state
tDTVDV
DTN Valid to DATA Valid
tADSRD3 ADSN Rise to DATA 3-state
Min Interval (ns)
01
0
0
0
0
0
20
100
20
10
06
20
Max Interval (ns)
—
—
60 2
—
—
—
—
2803, 4
—5
—
—
—
Notes:
1 DSN can be asserted up to 20 ns (1 clk at 50 MHz) previous to CSN.
2 ADDR can be asserted up to 60 ns (3 clk at 50 MHz) into cycle from ASDN.
3 DTN fall is variable depending on the block selected for access and may be longer than typical maximum specified.
4 Leading edges of ADSN and DSN determine the falling edge of DTN.
5 Rising edge of ADSN determines the rising edge of DTN.
6 Data toggle 20 ns (1 clk at 50 MHz) previous to CSN.
Note: Specifications are valid for 50 MHz MPCLK with MPMODE = 0. Address strobe (ADSN) and chip select
(CSN) may be connected and driven from the same source. In this configuration, the setup and hold times
for ADSN must be satisfied.
5.13 General Purpose Interface Timing
Table 55. Input Timing Specifications
Input Name
TDI
TMSN
TRSTN
SCAN_EN
SCAN_MODE
RSTN
PMRST
IC3STATEN
IDDQ
60
Reference CLK
Min Setup Time (tS)
JTAG Signals
TCLK ↑
15.0 ns
TCLK ↑
15.0 ns
NA
ASYNC
NA
ASYNC
NA
ASYNC
Miscellaneous Signals
NA
ASYNC
NA
ASYNC
NA
ASYNC
NA
ASYNC
Min Hold Time (t H)
2.0 ns
2.0 ns
ASYNC
ASYNC
ASYNC
ASYNC
ASYNC
ASYNC
ASYNC
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
5 Timing Characteristics (continued)
Table 56. Output Timing Specifications
Output Name
Reference CLK
TDO
TLCK ↓
PMRST
NA
Test Conditions
Transmit Signals
CL = 25 pF
Miscellaneous Signals
—
Propagation Delay* (tPD)
Min
Max
Unit
3.0
20.0
ns
ASYNC
ASYNC
—
* Propagation delay skew, tPLH – tPHL, is ±200 ps.
6 Ordering Information
Device Code
TMXF281553BAL-2-DB
Agere Systems Inc.
Package
456-pin PBGA
Temperature
–40 °C to 85 °C
Comcode
108700055
61
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
Register Description
7 Microprocessor Interface and Global Control and Status Registers
Table of Contents
Contents
Page
7 Microprocessor Interface and Global Control and Status Registers ................................................................... 62
7.1 Super Mapper Global Control and Status Registers .................................................................................... 63
7.2 Microprocessor Interface Register Map ........................................................................................................ 73
Tables
Page
Table 57. SMPR_VCR, Super Mapper Version Control Register (RO) ................................................................. 63
Table 58. SMPR_SYMR[4], Super Mapper Symbol Register4 SMPR (RO) ......................................................... 63
Table 59. SMPR_SYMR[3], Super Mapper Symbol Register3 (RO) ..................................................................... 63
Table 60. SMPR_SYMR[2], Super Mapper Symbol Register2 (RO) ..................................................................... 63
Table 61. SMPR_SYMR[1], Super Mapper Symbol Register1 (RO) ..................................................................... 64
Table 62. SMPR_SYMR[0], Super Mapper Symbol Register0 (RO) ..................................................................... 64
Table 63. SMPR_ISR, Super Mapper Interrupt Status Register (RO) ................................................................... 64
Table 64. SMPR_IMR, Super Mapper Interrupt Mask Register (RW) ................................................................... 65
Table 65. SMPR_GTR, Global Trigger Register (RW) .......................................................................................... 66
Table 66. SMPR_MSRR, Block Software Reset Register (RW) ........................................................................... 66
Table 67. SMPR_GCR, Global Control Register (RW) ......................................................................................... 68
Table 68. SMPR_TSCR, TMUX, and SPEMPR Control Register (RW) ................................................................ 69
Table 69. SMPR_FCR, Framer Control Register (RW) ......................................................................................... 69
Table 70. SMPR_CLCR, CDR and LVDS Control Register (RW) ......................................................................... 70
Table 71. SMPR_CPCR, Clock and Power Control Register (RW) ...................................................................... 71
Table 72. SMPR_PMRCHR, PM Reset Count High Register (RW) ...................................................................... 71
Table 73. SMPR_PMRCLR, PM Reset Count Low Register (RW) ....................................................................... 72
Table 74. SMPR_SR, Scratch Register (RW) ....................................................................................................... 72
Table 75. SMPR_TX_LINE_EN1 ........................................................................................................................... 72
Table 76. Microprocessor Interface Register Map ................................................................................................. 73
62
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
7 Microprocessor Interface and Global Control and Status Registers (continued)
7.1 Super Mapper Global Control and Status Registers
This section gives a brief description of each register bit and its functionality. The abbreviations after each register
indicate if the register is read only (RO), clear-on-read/clear-on-write (COR/COW), or read/write (R/W).
Table 57. SMPR_VCR, Super Mapper Version Control Register (RO)
Address Bit
Name
Function
0x00000 15:11
—
Reserved.
10:8 SMPR_VERSION[2:0] Super Mapper Version Number. SMPR version
register will change each time the device is changed.
7:0
SMPR_ID[7:0]
SMPR ID Number.
Reset Default
0x0000
Table 58. SMPR_SYMR[4], Super Mapper Symbol Register4 SMPR (RO)
Address
0x00001
Bit
15:8
7:0
Name
T
M
Function
Super Mapper Symbol Bit.
Super Mapper Symbol Bit.
Reset Default
0x544D
Table 59. SMPR_SYMR[3], Super Mapper Symbol Register3 (RO)
Address
0x00002
Bit
15:8
7:0
Name
X
F
Function
Super Mapper Symbol Bit.
Super Mapper Symbol Bit.
Reset Default
0x5846
Table 60. SMPR_SYMR[2], Super Mapper Symbol Register2 (RO)
Address
0x00003
Bit
15:8
7:0
Agere Systems Inc.
Name
2
8
Function
Super Mapper Symbol Bit.
Super Mapper Symbol Bit.
Reset Default
0x3238
63
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
7 Microprocessor Interface and Global Control and Status Registers (continued)
Table 61. SMPR_SYMR[1], Super Mapper Symbol Register1 (RO)
Address
0x00004
Bit
15:8
7:0
Name
1
5
Function
Super Mapper Symbol Bit.
Super Mapper Symbol Bit.
Reset Default
0x3135
Table 62. SMPR_SYMR[0], Super Mapper Symbol Register0 (RO)
Address
0x00005
Bit
15:8
7:0
Name
5
CR
Function
Super Mapper Symbol Bit.
Super Mapper Symbol Bit.
Reset Default
0x350D
Table 63. SMPR_ISR, Super Mapper Interrupt Status Register (RO)
Address
Bit
0x00008
15
14:10
9
8
7
6
5
Name
Function
Reset
Default
SMPR_APS_IS
APS Interrupt. Active-high signal indicating an interrupt event 0x0000
has occurred in the automatic protection switch (APS) block,
which is within the TMUX block.
—
Reserved.
SMPR_PARITY_IS
Microprocessor Interface Data Bus Parity Error Interrupt.
Active-high signal indicating a µP data bus parity error has
occurred. Summary of errors detected in PAR[1] and PAR[0]
parity detectors.
SMPR_PMRESET_IS Performance Monitor Reset Interrupt. Active-high signal
indicating a 1 second event has occurred.
SMPR_TPG_IS
TPG Interrupt. Active-high signal indicating an interrupt event
has occurred in the test pattern generation block.
SMPR_DJA_IS
DJA Interrupt. Active-high signal indicating an interrupt event
has occurred in the digital jitter attenuation block.
SMPR_FRM_IS
FRM Interrupt. Active-high signal indicating an interrupt
event has occurred in the framer block. However, on device
powerup, this bit is erroneously set. A device initialization routine containing the following sequence should clear the interrupt:
■
Power up the framer block by selecting one of the clock
options in address 0x00012.
■
Set and clear the framer software reset bit, bit of address
0x0000E.
Power down the framer block in address 0x00012.
XC Interrupt. Active-high signal indicating an interrupt event
has occurred in the cross connect block.
M13 Interrupt. Active-high signal indicating an interrupt event
has occurred in the M13 multiplexer/demultiplexer block.
VTMPR Interrupt. Active-high signal indicating an interrupt
event has occurred in the VT mapper block.
SPEMPR Interrupt. Active-high signal indicating an interrupt
event has occurred in the SPE mapper block.
TMUX Interrupt. Active-high signal indicating an interrupt
event has occurred in the TMUX block.
■
64
4
SMPR_XC_IS
3
SMPR_M13_IS
2
SMPR_VTMPR_IS
1
SMPR_SPEMPR_IS
0
SMPR_TMUX_IS
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
7 Microprocessor Interface and Global Control and Status Registers (continued)
Table 64. SMPR_IMR, Super Mapper Interrupt Mask Register (RW)
Address
Bit
0x00009
15
14:10
9
8
7
6
5
4
3
2
1
0
Agere Systems Inc.
Name
Function
Reset
Default
SMPR_APS_IM
APS Interrupt Mask. When this bit is set to 1, the composite 0x83FF
interrupt bit will be inhibited from contributing to the interrupt
pin APS_INTN.
—
Reserved.
SMPR_PARITY_IM Microprocessor Interface Data Bus Parity Error Interrupt
Mask. When this bit is set to 1, the composite interrupt bit will
be inhibited from contributing to the interrupt pin INTN.
SMPR_PMRESET_IM Performance Monitor Reset Interrupt Mask. When this bit
is set to 1, the composite interrupt bit will be inhibited from
contributing to the interrupt pin INTN.
SMPR_TPG_IM
TPG Interrupt Mask. When this bit is set to 1, the composite
interrupt bit will be inhibited from contributing to the interrupt
pin INTN.
SMPR_DJA_IM
DJA Interrupt Mask. When this bit is set to 1, the composite
interrupt bit will be inhibited from contributing to the interrupt
pin INTN.
SMPR_FRM_IM
FRM Interrupt Mask. When this bit is set to 1, the composite
interrupt bit will be inhibited from contributing to the interrupt
pin INTN.
SMPR_XC_IM
XC Interrupt Mask. When this bit is set to 1, the composite
interrupt bit will be inhibited from contributing to the interrupt
pin INTN.
SMPR_M13_IM
M13 Interrupt Mask. When this bit is set to 1, the composite
interrupt bit will be inhibited from contributing to the interrupt
pin INTN.
SMPR_VTMPR_IM VTMPR Interrupt Mask. When this bit is set to 1, the composite interrupt bit will be inhibited from contributing to the
interrupt pin INTN.
SMPR_SPEMPR_IM SPEMPR Interrupt Mask. When this bit is set to 1, the composite interrupt bit will be inhibited from contributing to the
interrupt pin INTN.
SMPR_TMUX_IM
TMUX Interrupt Mask. When this bit is set to 1, the composite interrupt bit will be inhibited from contributing to the interrupt pin INTN.
65
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
7 Microprocessor Interface and Global Control and Status Registers (continued)
Table 65. SMPR_GTR, Global Trigger Register (RW)
Address
0x0000D
Bit
15:10
9
Name
—
SMPR_BER_INSRT
8
SMPR_PMRESET
7:1
0
—
SMPR_SWRS
Function
Reset Default
0x0000
Reserved.
Bit Error Rate Insertion. When this bit is set to 1,
this bit indicates to the Super Mapper that a bit error
has to be inserted in the appropriate frame.
Performance Monitor Reset. When this bit is set to
1, the PMRESET signal will transition from a logic 0
to a logic 1 state. It will stay at a logic 1 state for a
minimum of 100 ns. (Self-clearing.)
Reserved.
Super Mapper Software Reset. When this bit is set
to 1, it will create a software reset of the device. This
reset has the same effect as the hardware reset. All
microprocessor registers are reset to their default
states and all internal data path state machine are
reset. (Self-clearing.)
Table 66. SMPR_MSRR, Block Software Reset Register (RW)
Address
Bit
Name
Function
0x0000E
15:8
7
—
SMPR_TPG_SWRS
6
SMPR_DJA_SWRS
5
SMPR_FRM_SWRS
Reserved.
TPG Block Software Reset. When this bit is set to 1, it will
create a software reset for the test-pattern generation macro.
This reset has the same effects as the hardware reset and
chip-level software reset. All microprocessor registers within
the macro are reset to their default states. All internal data
path state machine within the block are also reset.
DJA Block Software Reset. When this bit is set to 1, it will
create a software reset for the digital jitter attenuation block.
This reset has the same effects as the hardware reset and
chip-level software reset. All microprocessor registers within
the macro are reset to their default states. All internal data
path state machine within the block are also reset.
FRM Block Software Reset. When this bit is set to 1, it will
create a software reset for the framer block. This reset has the
same effects as the hardware reset and chip-level software
reset. All microprocessor registers within the block are reset
to their default states. All internal data path state machine
within the block are also reset.
66
Reset
Default
0x0000
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Preliminary Data Sheet
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TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
7 Microprocessor Interface and Global Control and Status Registers (continued)
Table 66. SMPR_MSRR, Block Software Reset Register (RW) (continued)
Address
Bit
Name
0x0000E
4
SMPR_XC_SWRS
3
SMPR_M13_SWRS
2
1
0
Agere Systems Inc.
Function
Reset
Default
XC Block Software Reset. When this bit is set to 1, it will 0x0000
create a software reset for the cross connect block. This
reset has the same effects as the hardware reset and chiplevel software reset. All microprocessor registers within the
block are reset to their default states. All internal data path
state machine within the block are also reset.
M13 Block Software Reset. When this bit is set to 1, it will
create a software reset for the M13 multiplexer/demultiplexer block. This reset has the same effects as the hardware reset and chip-level software reset.
All microprocessor registers within the block are reset to
their default states. All internal data path state machine
within the block are also reset.
SMPR_VTMPR_SWRS VTMPR Block Software Reset. When this bit is set to 1,
it will create a software reset for the VTMPR block. This
reset has the same effects as the hardware reset and
chip-level software reset. All microprocessor registers
within the block are reset to their default states. All internal data path state machine within the block are also
reset.
SMPR_SPEMPR_SWRS SPEMPR Block Software Reset. When this bit is set
to 1, it will create a software reset for the SPEMPR block.
This reset has the same effects as the hardware reset and
chip-level software reset. All microprocessor registers
within the block are reset to their default states. All internal
data path state machine within the block are also reset.
SMPR_TMUX_SWRS TMUX Block Software Reset. When this bit is set to 1, it
will create a software reset for the TMUX block. This reset
has the same effects as the hardware reset and chip-level
software reset. All microprocessor registers within the
block are reset to their default states. All internal data path
state machine within the block are also reset.
67
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
7 Microprocessor Interface and Global Control and Status Registers (continued)
Table 67. SMPR_GCR, Global Control Register (RW)
Address
Bit
0x0000F 15:10
9:8
Name
—
SMPR_PMMODE[1:0]
Function
Reset
Default
0x0000
Reserved.
Performance Monitor Mode:
00 = PMRST comes from external pin.
10 = PMRST comes from external pin.
01 = PMRST comes from internal 1 second counter.
Note: Please see Table 72 and Table 73.
7:5
4
3
2
1
11 = PMRST is software controlled using the
SMPR_PMREST register bit 8 (Table 65 on
page 66).
—
Reserved.
SMPR_PARITY_EVEN_ODD Even or Odd Parity Indication on the Microprocessor Data Bus. This bit controls the parity setting and
checking on the microprocessor data bus:
SMPR_OH_DEFLT
SMPR_FXD_STFF_DEFLT
SMPR_COR_COW
0 = Even parity on microprocessor byte data/parity bus.
1 = Odd parity on microprocessor byte data/parity bus.
Overhead Default. This bit controls the filling of the
unused overhead bytes:
0 = Filling the unused overhead bits with 0.
1 = Filling the unused overhead bits with 1.
Fixed Stuff Default. This bit control the filling of the
fixed stuff bytes:
0 = Filling the fixed stuff bytes with 0.
1 = Filling the fixed stuff bytes with 1.
Clear On Read or Clear On Write. This bit controls the
way clearing is performed on all delta and event bits in
all registers:
0 = The delta and event bit is cleared by writing a 1 to it.
Note: The clear-on-write (COW) feature does not apply
to all registers in the 28-channel framer block.
The only framer block register that has COW is
transmit FDL link register 8 (address 0x8LTD7).
All other registers in the framer block are only
clear-on-read.
0
SMPR_SAT_ROLLOVER
1 = The delta and event bit is cleared when a microprocessor read is performed on this delta and event bit.
Saturate or Rollover. This bit controls if error counters
hold their values or rollover when they reach their maximum values.
0 = Error counters rollover when reaching maximum values.
1 = Error counters hold their values when reaching maximum values.
68
Agere Systems Inc.
Preliminary Data Sheet
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TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
7 Microprocessor Interface and Global Control and Status Registers (continued)
Table 68. SMPR_TSCR, TMUX, and SPEMPR Control Register (RW)
Address
Bit
Name
Function
—
MPU_RHDZTHD_LB
SMPR_RETIME_CLK_EDGE
Reserved.
Forces Received High-speed to Transmit Highspeed Data Loopback Prior to the CDR.
Retime Clock Edge for the Received High-speed
Data. This bit controls on which clock edge, positive
or negative, the received high-speed data is to
retimed.
SMPR_TELECOMBUS_EDGE
1 = The received data will be clocked into the device
on the negative clock edge.
0 = The received data will be clocked into the device
on the positive clock edge.
Telecom Bus Edge. When the SPE mapper is
enabled to use a time slot on the telecom bus. This
bit selects the clock edge for the data signals transmitted to the telecom bus during the selected time
slot.
0x00010 15:4
3
2
1
0
Reset
Default
0x0000
0 = Clock telecom bus signals out on the falling edge.
1 = Clock telecom bus signals out on the rising edge.
SMPR_TMUX_MASTER_SLAVE SMPR/TMUX Master Slave. This bit controls if the
TMUX block in this Super Mapper is the master
device in the system module that this Super Mapper
is on, or if it is a slave device.
0 = This Super Mapper/TMUX is a slave device in
the module.
1 = This Super Mapper/TMUX is a master device in
the module.
Table 69. SMPR_FCR, Framer Control Register (RW)
Address
Bit
0x00012
15:3
2:0
Name
Function
—
Reserved.
SMPR_FRM_CLK_SEL[2:0] Framer Clock Selection. Selects the source of the
framer high-speed clock the selected clock needs to be
faster than the aggregate throughput of the framer block
for proper operation.
Reset
Default
0x0000
000 = Framer is powered down. No clock required.
001 = Framer receives TLSC52 (pin AC3) clock input
010 = Framer receives DS1XCLK (pin AD16) clock input.
011 = Framer receives E1XCLK (pin AC17) clock input.
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69
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
7 Microprocessor Interface and Global Control and Status Registers (continued)
Table 70. SMPR_CLCR, CDR, and LVDS Control Register (RW)
Address
Bit
Name
Function
0x00013 15:11
—
Reserved.
10 SMPR_MPU_CDR_MODE CDR Mode Selection. This bit controls the operating
mode of the internal CDR; whether it operates at
155 MHz or 51 MHz.
9
8
7:4
3
2
1
0
Reset
Default
0x000C
0 = 155 MHz mode.
1 = 51 MHz mode.
SMPR_MPU_CG_PWRDN PLL Powerdown Selection. This bit controls whether
the internal framer PLL is powered on or off.
SMPR_LVDS_REF_SEL
—
SMPR_RXPWRDN
SMPR_PLLPWRDN
0 = Internal PLL powered on.
1 = Internal PLL powered off.
LVDS Reference Voltage Selection. This bit controls
which reference voltage, internal or external, is used to
power the LVDS buffers.
0 = External reference voltage is used.
1 = Internal reference voltage is used.
Reserved.
CDR Channel Powerdown. This bit controls the power
to the CDR data channel.
0 = Channel is active, power is on.
1 = Channel is inactive, power to the channel is turned off.
CDR Phase-Lock Loop Powerdown. This bit controls
the power to the CDR PLL circuit.
SMPR_MRESET
0 = PLL is active, power to the PLL is turned on.
1 = PLL is inactive, power to the PLL is turned off.
CDR Master Reset. This bit is used for the CDR initialization. It can also be used in test mode to reset test circuitry.
SMPR_CDR_SEL
0 = No reset.
1 = Reset mode.
CDR Selection. This bit controls if the TMUX receives
its high-speed receive clock and data from the on-chip
CDR block or from the pins (bypass the CDR).
0 = Bypass CDR. Receives clock and data directly from
pins.
1 = Use CDR. Receives clock and data through CDR.
70
Agere Systems Inc.
Preliminary Data Sheet
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TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
7 Microprocessor Interface and Global Control and Status Registers (continued)
Table 71. SMPR_CPCR, Clock and Power Control Register (RW)
Address
Bit
Name
0x00014
15:9
8
—
SMPR_M13_TCLK
Reserved.
M13 MUX/Tx Clock Enable.
SMPR_M13_RCLK
0 = M13 MUX/Tx clock is powered down and inactive.
1 = M13 MUX/Tx clock is powered up and active.
M13 DeMUX Rx Clock Enable.
7
6
5
4
SMPR_DJA_CLK
Function
0 = M13 deMUX/Rx clock is powered down and inactive.
1 = M13 deMUX/Rx clock is powered up and active.
Digital Jitter Attenuation Clock Enable.
SMPR_VTMPR_TCLK
0 = DJA DPLL is powered down and inactive.
1 = DJA DPLL is powered up and active.
VT Mapper Tx Clock Enable.
SMPR_VTMPR_RCLK
0 = VT mapper Tx clock is powered down and inactive.
1 = VT mapper Tx clock is powered up and active.
VT Mapper Rx Clock Enable.
3
0 = VT mapper Rx clock is powered and inactive.
1 = VT mapper Rx clock is powered up and active.
SMPR_SPEMPR_TCLK SPE Mapper Tx Clock Enable.
2
0 = SPE mapper Tx clock is powered down and inactive.
1 = SPE mapper Tx clock is powered up and active.
SMPR_SPEMPR_RCLK SPE Mapper Rx Clock Enable.
1
SMPR_TMUX_TCLK
0 = SPE mapper Rx clock is powered down and inactive.
1 = SPE mapper Rx clock is powered up and active.
TMUX Tx Clock Enable.
SMPR_TMUX_RCLK
0 = TMUX Tx clock is powered down and inactive.
1 = TMUX Tx clock is powered up and active.
TMUX Rx Clock Enable.
0
Reset
Default
0x0000
0 = TMUX Rx clock is powered down and inactive.
1 = TMUX Rx clock is powered up and active.
Table 72. SMPR_PMRCHR, PM Reset Count High Register (RW)
Address
Bit
Name
Function
0x00016 15:11
—
Reserved.
10:0 SMPR_PMRESET_HIGH_COUNT[10:0] Performance Monitor Counter Preset. The
preset value of this register determines the
frequency of the internal PM counter. User
should preload an appropriate value based
on the microprocessor interface clock rate in
order to reach the desired PMRST rate.
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Reset
Default
0x01F8
71
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
7 Microprocessor Interface and Global Control and Status Registers (continued)
Table 73. SMPR_PMRCLR, PM Reset Count Low Register (RW)
Address
Bit
Name
Function
0x00017 15:0 SMPR_PMRESET_LOW_COUNT[15:0] Performance Monitor Counter Preset.
The preset value of this register determines
the frequency of the internal PM counter.
User should preload an appropriate value
based on the microprocessor interface
clock rate in order to reach the desired
PMRST rate.
Reset
Default
0x0000
Table 74. SMPR_SR, Scratch Register (RW)
Address
Bit
0x0001F
15:0
Name
Function
SMPR_SCRATCH_REGISTER[15:0] Scratch Register. This register is for test
and diagnostics purpose.
Reset
Default
0x0000
Read/write operations can be performed on
all bits. No SMPR control and status will be
affected by any read/write operations to this
register.
Table 75. SMPR_TX_LINE_EN1
Address
Bit
Name
0x00018
15:0
SMPR_TX_LINE_EN[16:1]
0x00019
12:0
72
Function
3-State Control for LINETXDATA, LINETXCLK,
and LINETXSYNC Output Pins.
SMPR_TX_LINE_EN[29:17] 3-State Control for LINETXDATA, LINETXCLK,
and LINETXSYNC Output Pins.
Reset
Default
0x0000
0x0000
Agere Systems Inc.
Preliminary Data Sheet
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TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
7 Microprocessor Interface and Global Control and Status Registers (continued)
7.2 Microprocessor Interface Register Map
Table 76. Microprocessor Interface Register Map
Address
Symbol
Bit
15
0x00000
SMPR_VCR
0
Bit Bit Bit Bit Bit
14 13 12 11 10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
Super Mapper Version Control Register—RO
0
0
0
0
SMPR_VERSION[2:0]
SMPR_ID[7:0]
Super Mapper Symbol Register—RO
0x00001 SMPR_SYMR4
0x54 = T
0x4D = M
0x00002 SMPR_SYMR3
0x58 = X
0x46 = F
0x00003 SMPR_SYMR2
0x32 = 2
0x38 = 8
0x00004 SMPR_SYMR1
0x31 = 1
0x35 = 5
0x00005 SMPR_SYMR0
0x35 = 5
0x0D = CR
0x00006
—
0x00007
—
0x00008
SMPR_ISR
SMPR_APS_IS
SMPR_
PARITY_IS
SMPR_
PMRESET_IS
0x00009
SMPR_IMR
SMPR_APS_IM
SMPR_
PARITY_IM
SMPR_
PMRESET_IM
0x0000A
—
0x0000C
—
0x0000D
SMPR_GTR
SMPR_BER_
INSRT
SMPR_
PMRESET
Super Mapper Interrupt Status Register—RO
SMPR_TPG_IS
SMPR_DJA_IS
SMPR_FRM_
IS
SMPR_XC_IS
SMPR_M13_ SMPR_VTMPR_
IS
IS
SMPR_
SPEMPR_IS
SMPR_TMUX_
IS
SMPR_XC_IM
SMPR_M13_ SMPR_VTMPR_
IM
IM
SMPR_
SPEMPR_IM
SMPR_TMUX_
IM
Super Mapper Interrupt Mask Register—R/W
SMPR_TPG_IM
SMPR_DJA_
IM
SMPR_FRM_
IM
Global Trigger Register—R/W
SMPR_SWRS
Block Software Reset Register—R/W
0x0000E SMPR_MSRR
SMPR_TPG_SWRS
SMPR_DJA_
SWRS
SMPR_FRM_
SWRS
SMPR_XC_
SWRS
SMPR_M13_ SMPR_VTMPR_ SMPR_SPEMPR_
SWRS
SWRS
SWRS
SMPR_TMUX_
SWRS
Global Control Register (SMPR_GCR)—R/W
0x0000F
SMPR_GCR
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SMPR_PMMODE[1:0]
SMPR_PARITY_
EVEN_ODD
SMPR_OH_
DEFLT
SMPR_FXD_
STFF_DEFLT
SMPR_COR_
COW
SMPR_SAT_
ROLLOVER
73
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
7 Microprocessor Interface and Global Control and Status Registers (continued)
Table 76. Microprocessor Interface Register Map (continued)
Address
Symbol
0x00010
SMPR_TSCR
0x00011
—
0x00012
SMPR_FCR
Bit
15:11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
MP0RH02THD_LB
SMPR_RETIME_
CLK_EDGE
Bit 1
Bit 0
TMUX and SPEMOR CONTROL Register—R/W
SMPR_TELECOMBUS_ SMPR_SMPR_TMUX_
EDGE
MASTER_SLAVE
FRAMER Control Register—R/W
SMPR_FRM_CLK_SEL[2:0]
CDR and LVDS Control Register—R/W
0x00013
SMPR_CLCR
0x00014
SMPR_CPCR
0x00015
—
0x00016
SMPR_PMRCHR
—
SMPR_MPU_C SMPR_MPU_ SMPR_LVDS_
DR_MODE
CG_PWRDN
REF_SEL
SMPR_RXPWRDN
SMPR_
PLLPWRDN
SMPR_MRESET
SMPR_CDR_SEL
SMPR_SPEMPR_
TXCLK
SMPR_SPEMPR_
RXCLK
SMPR_TMUX_
TXCLK
SMPR_TMUX_RXCLK
Clock and Power Control Register—R/W
SMPR_M13_ SMPR_M13_
TXCLK
RXCLK
SMPR_DJA_
CLK
SMPR_VTMPR_ SMPR_VTMPR_
TXCLK
RXCLK
PM Reset Count Register High—R/W
SMPR_PMRESET_HIGH_COUNT[10:0]
PM Reset Count Register Low—R/W
0x00017
SMPR_PMRCLR
SMPR_PMRESET_LOW_COUNT[15:0]
0x00018
TX_LINE_EN1
TX_LINE_EN[16-1]
0x00019
TX_LINE_EN2
TX_LINE_EN[29-17]
Scratch Register—R/W
0x0001F
74
SMPR_SR
SMPR_SCRATCH_REGISTER[15:0]
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
8 TMUX Registers
Table of Contents
Contents
Page
8 TMUX Registers ................................................................................................................................................. 75
8.1 TMUX Register Descriptions ........................................................................................................................ 77
8.2 TMUX Register Map ................................................................................................................................... 124
Tables
Page
Table 77. TMUX_ID_R, TMUX Identification Register (RO) .................................................................................. 77
Table 78. TMUX_ONESHOT, TMUX One-Shot Register 0 to 1 (R/W) ................................................................. 77
Table 79. TMUX_RCV_TX_MODE, TMUX Receive/Transmit Mode (R/W) .......................................................... 77
Table 80. TMUX_TX_DLT, Delta/Event (COR/COW) ........................................................................................... 78
Table 81. TMUX_RPS_DLT, Delta/Event (COR/COW) ........................................................................................ 78
Table 82. TMUX_RHS_DLT, Delta/Event (COR/COW) ........................................................................................ 79
Table 83. TMUX_RPOH[1—3]_DLT, Delta/Event (COR/COW) ............................................................................ 81
Table 84. TMUX_TX_MSK, Mask Bits for INT Interrupt Signal (R/W) (Mask = 1, No Mask = 0) .......................... 87
Table 85. TMUX_RPS_MSK, Mask Bits for INT Interrupt Signal (R/W) (Mask = 1, No Mask = 0) ....................... 88
Table 86. TMUX_RHS_MSK, Mask Bits for INT Interrupt Signal (R/W) (Mask = 1, No Mask = 0) ....................... 88
Table 87. TMUX_RPOH[1—3]_MSK, Mask Bits for Interrupt Signal (R/W) (Mask = 1, No Mask = 0) .................. 89
Table 88. TMUX_APSINT_MSK, Mask Bits for APSINT Interrupt Signal (R/W) (Mask = 1, No Mask = 0) ........... 91
Table 89. TMUX_TX_STATE, State Parameters (RO) ......................................................................................... 91
Table 90. TMUX_RPS_STATE, State and Value Parameters (RO) ..................................................................... 91
Table 91. TMUX_RHS_STATE, State and Value Parameters (RO) ..................................................................... 92
Table 92. TMUX_RPOH[1—3]_STATE, State and Value Parameters (RO) ......................................................... 92
Table 93. TMUX_RHS_CTL, Receive High-speed Control Parameters (R/W) ..................................................... 94
Table 94. TMUX_RLS_BITBLK_CTL, Receive Low-speed Control Parameters (R/W) ........................................ 94
Table 95. TMUX_RLS_MODE_CTL, Receive Low-speed Control Parameters (R/W) .......................................... 95
Table 96. TMUX_RAISINH_CTL, Receive Low-speed Control Parameters (R/W) ............................................... 96
Table 97. TMUX_LOSDETCNT, Receive Low-speed Control Parameters (R/W) ................................................ 97
Table 98. TMUX_CNTD_TOH_[A—B], Continuous N-Times Detect Control Parameters (R/W) .......................... 98
Table 99. TMUX_CNTD_POH_[A—B], Continuous N-Times Detect Control Parameters (R/W) ......................... 99
Table 100. TMUX_C2EXP[1—2_3], Continuous N-Times Detect Control Parameters (R/W) ............................ 100
Table 101. TMUX_RF1MON, Receive Monitor Values (RO) .............................................................................. 100
Table 102. TMUX_RAPSMON, Receive Monitor Values (RO) ........................................................................... 100
Table 103. TMUX_RS1MON, Receive Monitor Values (RO) .............................................................................. 100
Table 104. TMUX_RPOHMON[1—3][A—D], Receive Monitor Values (RO) ....................................................... 101
Table 105. TMUX_TLS_CTL, Transmit Low-speed Control Parameters (R/W) .................................................. 102
Table 106. TMUX_THS_PORT_CTL, Transmit High-speed Port Control Parameters (R/W) ............................. 103
Table 107. TMUX_THS_TOH_CTL, Transmit High-speed Control Parameters (R/W) ....................................... 103
Table 108. TMUX_THS_POH[1—3]_CTL, Transmit High-speed Control Parameters (R/W) ............................. 105
Table 109. TMUX_TLRDI_CTL, Transmit High-speed Line RDI Control Parameters (R/W) .............................. 109
Table 110. TMUX_TPRDI_CTL, Transmit High-speed Path RDI Control Parameters (R/W) ............................. 109
Table 111. TMUX_TZ0_INS_VAL, Transmit TOH and POH Insert Values (R/W) .............................................. 110
Table 112. TMUX_TS1_F1_INS_VAL, Transmit TOH and POH Insert Values (R/W) ........................................ 110
Table 113. TMUX_TAPS_INS_VAL, Transmit TOH and POH Insert Values (R/W) ........................................... 110
Table 114. TMUX_TPOH[1—3]_INS_[A—C], Transmit TOH and POH Insert Values (R/W) ............................. 110
Table 115. TMUX_TBERINS_CTL, Transmit High-speed Error Insertion Control Parameters (R/W) ................ 112
Table 116. TMUX_THS_ERR_CTL, Transmit High-speed Error Insertion Control Parameters (R/W) ............... 113
Table 117. TMUX_TOAC_CTL, Receive/Transmit TOAC/POAC Control Parameters (R/W) ............................. 113
Table 118. TMUX_RPOAC_CTL, Receive/Transmit TOAC/POAC Control Parameters (R/W) .......................... 115
Table 119. TMUX_TFRAMEOFFSET, Transmit High-speed Offset Control Parameters (R/W) ......................... 116
Table 120. TMUX_SD_CTL[1—6], B1/B2 Signal Degrade Set/Clear Control Registers (R/W) .......................... 116
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TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
8 TMUX Registers (continued)
Table of Contents (continued)
Tables
Page
Table 121. TMUX_SF_CTL[1—6], B1/B2 Signal Fail Set/Clear Control Registers (R/W) ................................... 117
Table 122. TMUX_B3SD_CTL[1—6], B3 Signal Degrade Set/Clear Control Registers (R/W) ........................... 117
Table 123. TMUX_B3SF_CTL[1—6], B3 Signal Fail Set/Clear Control Registers (R/W) .................................... 118
Table 124. TMUX_B1ECNT, Receive B1 Error Counts (RO) .............................................................................. 118
Table 125. TMUX_B2ECNT_17_16 and TMUX_B2ECNT_15_0, Receive B2 Error Counts (RO) ..................... 119
Table 126. TMUX_B3ECNT[1—3], Receive B3 Error Counts (RO) .................................................................... 119
Table 127. TMUX_M1ECNT_17_16 and TMUX_M1ECNT_15_0, Receive M1 Error Counts (RO) ................... 120
Table 128. TMUX_G1ECNT[1—3], Receive G1 Error Counts (RO) ................................................................... 120
Table 129. TMUX_RPTR_INCCNT[1—3], Receive Pointer Increment Count (RO) ............................................ 121
Table 130. TMUX_RPTR_DECCNT[1—3], Receive Pointer Decrement Count (RO) ......................................... 121
Table 131. TMUX_RJ0EXPECTED[1—8], Expected J0 Byte Sequence (R/W) ................................................. 121
Table 132. TMUX_RJ0CAPTURED[1—8], Captured J0 Receive Value (RO) .................................................... 121
Table 133. TMUX_TJ0VALUE[1—8], J0 Byte Transmit Insert (R/W) .................................................................. 121
Table 134. TMUX_RJ1EXPECTED1_[1—32], Expected J1 Byte Value for Port 1 (R/W) ................................... 122
Table 135. TMUX_RJ1EXPECTED2_[1—32], Expected J1 Byte Value for Port 2 (R/W) ................................... 122
Table 136. TMUX_RJ1EXPECTED3_[1—32], Expected J1 Byte Value for Port 3 (R/W) ................................... 122
Table 137. TMUX_RJ1CAPTURED1_[1—32], Captured J1 Value for STS #1 (RO) .......................................... 122
Table 138. TMUX_RJ1CAPTURED2_[1—32], Captured J1 Value for STS #2 (RO) .......................................... 122
Table 139. TMUX_RJ1CAPTURED3_[1—32], Captured J1 Value for STS #3 (RO) .......................................... 123
Table 140. TMUX_TJ1VALUE_1[1—32], J1 Byte Transmit Insert for STS #1 (R/W) ......................................... 123
Table 141. TMUX_TJ1VALUE_2[1—32], J1 Byte Transmit Insert for STS #2 (R/W) ......................................... 123
Table 142. TMUX_TJ1VALUE_3[1—32], J1 Byte Transmit Insert for STS #3 (R/W) ......................................... 123
Table 143. TMUX Register Map .......................................................................................................................... 124
76
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
8 TMUX Registers (continued)
8.1 TMUX Register Descriptions
This section provides a brief description of each register bit and its functionality. The abbreviations after each register indicate if the register is read only (RO), clear-on-read/clear-on-write (COR/COW), or read/write (R/W).
Table 77. TMUX_ID_R, TMUX Identification Register (RO)
Address
Bit
Name
0x40000
15:11
—
10:8
7:0
Function
Reserved.
0x0
TMUX_VERSION[2:0] Block Version Number. Block version register will
change each time the device is changed.
TMUX_ID[7:0]
Reset Default
Block ID Number.
0x0
0x04
Table 78. TMUX_ONESHOT, TMUX One-Shot Register 0 to 1 (R/W)
Address
Bit
Name
0x40002
15:8
—
7
6
5
Function
Reserved.
0x00
TMUX_B3SFCLEAR B3 Signal Fail Clear. Allows the signal fail algorithm
to be forced into the normal state.
TMUX_B3SFSET
Reset Default
B3 Signal Fail Set. Allows the signal fail algorithm
to be forced into the failed state.
TMUX_B3SDCLEAR B3 Signal Degrade Clear. Allows the signal
degrade algorithm to be forced into the normal state.
0
0
0
4
TMUX_B3SDSET
B3 Signal Degrade Set. Allows the signal degrade
algorithm to be forced into the degraded state.
0
3
TMUX_SFCLEAR
Signal Fail Clear. Allows the signal fail algorithm to
be forced into the normal state.
0
2
TMUX_SFSET
Signal Fail Set. Allows the signal fail algorithm to be
forced into the failed state.
0
1
TMUX_SDCLEAR
Signal Degrade Clear. Allows the signal degrade
algorithm to be forced into the normal state.
0
0
TMUX_SDSET
Signal Degrade Set. Allows the signal degrade
algorithm to be forced into the degraded state.
0
Table 79. TMUX_RCV_TX_MODE, TMUX Receive/Transmit Mode (R/W)
Address
Bit
Name
0x40003
15:1
—
0
TMUX_STS1MODE
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Function
Reserved.
STS-1 Mode Control Bit. A 1 indicates that the
received and transmitted high-speed data is STS-1
data operating at 52 MHz. A 0 indicates that the
received and transmitted high-speed data operates
at 155 MHz.
Reset Default
0x000
0
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TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
8 TMUX Registers (continued)
Table 80. TMUX_TX_DLT, Delta/Event (COR/COW)
Address
Bit
0x40004
15:7
6:4
3
2
1
0
Name
Function
Reset
Default
—
Reserved.
0x000
TMUX_TLSPARE[3:1] Transmit Low-speed Parity Error Event (Input Port Num0
ber). This event bit indicates a byte transfer parity error was
detected on the respective STS-1/AU-3 input. The mask bits
are TMUX_TLSPARM[3:1] (Table 84).
TMUX_TPOAC_PE Transmit Path Overhead Access Channel (TPOAC) Par0
ity Error Event. This event bit indicates a parity error was
detected on the incoming transmit path overhead access
channel. The mask bit is TMUX_TPOAC_PM (Table 84).
0
TMUX_TTOAC_PE Transmit Transport Overhead Access Channel (TTOAC)
Parity Error Event. This event bit indicates a parity error
was detected on the incoming transmit transport overhead
access channel. The mask bit is TMUX_TTOAC_PM
(Table 84).
TMUX_THSILOFD Transmit High-speed Input Loss of Frame Delta. This
0
delta bit indicates a change of state for the transmit loss of
frame bit TMUX_THSILOF (Table 89). The mask bit is
TMUX_THSILOFM (Table 84).
0
TMUX_THSILOCD Transmit High-speed Input Loss of Clock Delta. This
delta bit indicates a change of state for the transmit loss of
high-speed clock bit TMUX_THSILOC (Table 89). The mask
bit is TMUX_THSILOCM (Table 84).
Table 81. TMUX_RPS_DLT, Delta/Event (COR/COW)
Address
Bit
0x40005
15:6
5
4
3
2
1
0
78
Name
Function
Reset
Default
—
Reserved.
0x000
0
TMUX_RPSLOFD Receive Protection High-speed Loss of Frame Delta. This
delta bit indicates a change in state of TMUX_RPSLOF
(Table 90). The mask bit is TMUX_RPSLOFM (Table 85).
TMUX_RPSOOFD Receive Protection High-speed Out of Frame Delta. This
0
delta bit indicates a change in state of TMUX_RPSOOF
(Table 90). The mask bit is TMUX_RPSOOFM (Table 85).
TMUX_RPSILOCD Receive Protection High-speed Loss of Input Clock
0
Delta. This delta bit indicates a change in state of the
TMUX_RPSILOC (Table 90) state bit. The mask bit is
TMUX_RPSILOCM (Table 85).
TMUX_RPSB2E
Receive Protection High-speed B2 Error Event. This event
0
bit indicates a B2 error was detected in the receive protection
input. The mask bit is TMUX_RPSB2M (Table 85).
0
TMUX_RPSLREIE Receive Protection High-speed Line REI Event. This
event bit indicates a line REI error was detected in the
receive protection input. The mask bit is TMUX_RPSLREIM
(Table 85).
—
Reserved.
0
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
8 TMUX Registers (continued)
Table 82. TMUX_RHS_DLT, Delta/Event (COR/COW)
Address
Bit
Name
0x40006
15
—
14
13
Function
Reset Default
Reserved.
0
TMUX_RS1BABE
Receive S1 Babble Event. This event bit indicates an
inconsistent S1 value is being received. The event is
triggered if TMUX_CNTDS1FRAME[3:0] (Table 98) consecutive frames pass without a validated message
occurring. The mask bit is TMUX_RS1BABM (Table 86).
0
TMUX_RS1MOND
Receive S1 Monitor Delta. This delta bit indicates a
change of state for TMUX_RS1MON[7:0] (Table 103). A
new S1 value is detected after TMUX_CNTDS1[3:0]
(Table 98) consecutive occurrences of a consistent new
value in the S1 byte. The mask bit is TMUX_RS1MONM.
0
12
TMUX_RLRDIMOND Receive Line RDI Monitor Delta. This delta bit indicates a change in state for TMUX_RLRDIMON
(Table 91) when the pattern 110 is detected/not detected
TMUX_CNTDK2[3:0] (Table 98) consecutive times in the
incoming STS-3/STM-1 frame. The mask bit is
TMUX_RLRDIMONM (Table 86).
0
11
TMUX_RLAISMOND Receive Line AIS Monitor Delta. This delta bit indicates a change in state for TMUX_RLAISMON
(Table 91) when the pattern 111 is detected/not detected
TMUX_CNTDK2[3:0] consecutive times in the incoming
STS-3/STM-1 frame. The mask bit is
TMUX_RLAISMONM (Table 86).
0
10
TMUX_RK2MOND
Receive K2 Monitor Delta. This delta bit indicates a
change in state for TMUX_K2MON[2:0] (Table 102 on
page 100). A new K2 value is detected after
TMUX_CNTDK2[3:0] consecutive occurrences of a consistent new value in the three least significant bits of the
incoming K2 byte. Note that this delta bit may be coincident with TMUX_RLRDIMOND and
TMUX_RLAISMOND. The mask bit is
TMUX_RK2MONM (Table 86).
0
9
TMUX_RAPSBABE
Receive APS Babble Event. This event bit indicates
when an inconsistent APS value has been detected
TMUX_CNTDK1K2[3:0] (Table 98) times in the incoming
TMUX_CNTDK1K2FRAME[3:0] (Table 98) consecutive
frames. The mask bit is TMUX_RAPSBABM (Table 86
on page88 ).
0
8
TMUX_RAPSMOND Receive APS Monitor Delta. This delta bit indicates a
change in state in the received APS value
TMUX_RAPSMON[12:0] (Table 102) when a new consistent value is detected TMUX_CNTDK1K2[3:0] times
in the K1 and K2[7:3] bits. The mask bit is
TMUX_RAPSMONM (Table 86).
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0
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TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
8 TMUX Registers (continued)
Table 82. TMUX_RHS_DLT, Delta/Event (COR/COW) (continued)
Address
Bit
0x40006
7
80
Name
Function
Reset Default
TMUX_RF1MOND Receive F1 Monitor Delta. This delta bit indicates a
change in state of TMUX_RF1MON0[7:0] and
TMUX_RF1MON1[7:0] (Table 101) when a consistent
new value is detected in the incoming F1 byte for
TMUX_CNTDF1[3:0] (Table 98) continuous frames. The
current value is stored in TMUX_RF1MON0[7:0] and the
previous value is stored in TMUX_RF1MON0[7:0]. The
mask bit is TMUX_RF1MONM (Table 86).
0
6
TMUX_RTIMSD
Receive Section Trace Identifier Mismatch Delta. This
delta bit indicates a change in state in the received 16byte J0 sequence of bytes if the J0 mode is programmed
to receive a 16-byte sequence. The mask bit is
TMUX_RTIMSM (Table 86).
0
5
TMUX_RHSSFD
Receive High-speed Signal Fail BER Algorithm Delta.
This delta bit indicates a change of state for the signal fail
BER algorithm state bit TMUX_RHSSF (Table 91). The
mask bit for this delta bit is TMUX_RHSSFM (Table 86).
0
4
TMUX_RHSSDD
Receive High-speed Signal Degrade BER Algorithm
Delta. This delta bit indicates a change of state for the
signal degrade BER algorithm state bit TMUX_RHSSD
(Table 91). The mask bit is TMUX_RHSSDM (Table 86).
0
3
TMUX_RHSLOSD Receive High-speed Loss of Signal Delta. This delta
bit indicates a change in state of either TMUX_RHSLOS
(Table 91) or TMUX_RHSLOSEXTI (Table 91).
TMUX_RHSLOSEXTI is an external input from a device
pin. TMUX_RHSLOS is an internally generated state bit
based on monitoring for a consecutive 0/1s pattern in the
data input. The mask bit is TMUX_RHSLOSM (Table 86).
0
2
TMUX_RHSLOFD Receive High-speed Loss of Frame Delta. This delta
bit indicates a change in state of TMUX_RHSLOF
(Table 91). The mask bit is TMUX_RHSLOFM (Table 86).
0
1
TMUX_RHSOOFD Receive High-speed Out of Frame Delta. This delta bit
indicates a change in state of TMUX_RHSOOF
(Table 91). The mask bit is TMUX_RHSOOFM (Table 86).
0
0
TMUX_RHSILOCD Receive High-speed Loss of Input Clock Delta. This
delta bit indicates a change in state of the
TMUX_RHSILOC (Table 91) state bit. The mask bit is
TMUX_RHSILOCM (Table 86).
0
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
8 TMUX Registers (continued)
Table 83. TMUX_RPOH[1—3]_DLT, Delta/Event (COR/COW)
Address
Bit
Name
0x40007
15
TMUX_RSFB3D1
14
13
12
11
10
9
Agere Systems Inc.
Function
Receive Path Signal Fail BER Algorithm Delta. This delta
bit indicates a change of state for the signal fail BER algorithm state bit TMUX_RSFB31 (Table 92) at the path level for
port 1. Only port 1 information is valid in AU-4 mode and in
STS-1 mode. The mask bit is TMUX_RSFB3M1 (Table 87).
TMUX_RSDB3D1 Receive Path Signal Degrade BER Algorithm Delta. This
delta bit indicates a change of state for the signal fail BER
algorithm state bit TMUX_RSDB31 (Table 92) at the path
level for port 1. Only port 1 information is valid in AU-4 mode
and in STS-1 mode. The mask bit is TMUX_RSDB3M1
(Table 87).
TMUX_RUNEQPE1 Receive Path Unequipped Event. This event bit indicates
that the current value of the received C2 (signal label) byte,
TMUX_C2MON1[7:0] (Table 104), has a value 0x00, indicating unequipped payload on port 1. Only port 1 information is
valid in AU-4 mode and in STS-1 mode. The mask bit is
TMUX_RUNEQPM1 (Table 87).
TMUX_RPLMPE1 Receive Path Payload Label Mismatch Event. This event
bit indicates that the current value of the received C2 (signal
label) byte, TMUX_C2MON1[7:0], differs from the expected
C2 value, TMUX_C2EXP1[7:0] (Table 100) for port 1. Only
port 1 information is valid in AU-4 mode and in STS-1 mode.
The mask bit is TMUX_RPLMPM1 (Table 87).
TMUX_RN1MOND1 Receive N1 Monitor Delta. This delta bit indicates a change
in state in TMUX_N1MON1[7:0] (Table 104). The N1 current
value is updated when a consecutive and consistent value is
detected in the incoming N1 byte for TMUX_CNTDN1[3:0]
(Table 99) frames on port 1. Only port 1 information is valid
in AU-4 mode and in STS-1 mode. The mask bit is
TMUX_RN1MONM1 (Table 87).
TMUX_RK3MOND1 Receive K3 Monitor Delta. This delta bit indicates a change
in state in TMUX_K3MON1[7:0] (Table 104), which is
updated when a consecutive and consistent value is
detected in the incoming K3 byte for TMUX_CNTDK3[3:0]
(Table 99) frames on port 1. Only port 1 information is valid
in AU-4 mode and in STS-1 mode. The mask bit is
TMUX_RK3MONM1 (Table 87).
TMUX_RF3MOND1 Receive F3 (Path User Byte) Monitor Delta. This delta bit
indicates a change in state in TMUX_F3MON01[7:0]
(Table 104), which is updated when a consecutive and consistent value is detected in the incoming F3 byte for
TMUX_CNTDF3[3:0] (Table 99) frames on port 1. Only port
1 information is valid in AU-4 mode and in STS-1 mode. The
mask bit is TMUX_RF3MONM1 (Table 87).
Reset
Default
0
0
0
0
0
0
0
81
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
8 TMUX Registers (continued)
Table 83. TMUX_RPOH[1—3]_DLT, Delta/Event (COR/COW) (continued)
Address
Bit
0x40007
8
7
6
5
4
3
2
82
Name
Function
TMUX_RF2MOND1 Receive F2 (Path User Byte) Monitor Delta. This delta bit
indicates a change in state in TMUX_F2MON01[7:0]
(Table 104), which is updated when a consecutive and consistent value is detected in the incoming F2 byte for
TMUX_CNTDF2[3:0] (Table 99) frames on port 1. Only port 1
information is valid in AU-4 mode and in STS-1 mode. The
mask bit is TMUX_RF2MONM1 (Table 87).
TMUX_RRDIPD1 Receive Path RDI (Remote Defect Indication) Monitor
Delta. This delta bit indicates a change in state in
TMUX_RDIPMON1[2:0] (Table 104) that occurs when a consecutive and consistent new value is detected in the incoming G1[3:1] bits for TMUX_CNTDRDIP[3:0] (Table 99) frames
on port 1. The device monitors either G1 bit 3 or G1[3:1]
depending on TMUX_REPRDI_MODE (Table 95). Only port
1 information is valid in AU-4 mode and in STS-1 mode. The
mask bit is TMUX_RRDIPM1 (Table 87).
TMUX_RC2MOND1 Receive C2 (Signal Label) Monitor Delta. This delta bit
indicates a change in state in TMUX_C2MON1[7:0]
(Table 104), which is updated when a consecutive and consistent value is detected in the incoming C2 byte for
TMUX_CNTDC2[3:0] (Table 99) frames on port 1. Only port
1 information is valid in AU-4 mode and in STS-1 mode. The
mask bit is TMUX_RC2MONM1 (Table 87).
TMUX_RTIMPD1 Receive Path Trace Identifier Mismatch Delta. This delta
bit indicates a change in state in the received 16-byte J1
sequence on port 1 if the J1 mode is programmed to receive
a 16-byte sequence. Only port 1 information is valid in AU-4
mode and in STS-1 mode. The mask bit is TMUX_RTIMPM1
(Table 87).
TMUX_RNDFE1
Receive New Data Flag Event. This event bit indicates that
the incoming pointer has the new data flag enabled, causing
a jump in the current pointer location for port 1. Only port 1
information is valid in AU-4 mode and in STS-1 mode. The
mask bit is TMUX_RNDFM1 (Table 87).
TMUX_RDECE1
Receive Pointer Decrement Event. This event bit indicates
that a valid incoming pointer decrement indication was
received on port 1. Only port 1 information is valid in AU-4
mode and in STS-1 mode. The mask bit is TMUX_RDECM1
(Table 87).
TMUX_RINCE1
Receive Pointer Increment Event. This event bit indicates
that a valid incoming pointer increment indication was
received on port 1. Only port 1 information is valid in AU-4
mode and in STS-1 mode. The mask bit is TMUX_RINCM1
(Table 87).
Reset
Default
0
0
0
0
0
0
0
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
8 TMUX Registers (continued)
Table 83. TMUX_RPOH[1—3]_DLT, Delta/Event (COR/COW) (continued)
Address
Bit
0x4007
1
0
0x40008
15
14
13
12
11
10
Agere Systems Inc.
Name
Function
Reset
Default
0
TMUX_RPAISD1
Receive Path AIS Delta. This delta bit indicates a change in
state of the TMUX_RPAIS1 (Table 92) state bit, which designates that the port 1 pointer interpreter is in the alarm indication signal state. Only port 1 information is valid in AU-4
mode and in STS-1 mode. The mask bit is TMUX_RPAISM1
(Table 87).
TMUX_RLOPD1
Receive Loss of Pointer Delta. This delta bit indicates a
0
change in state of the TMUX_RLOP1 (Table 92) state bit,
which designates that the port 1 pointer interpreter is in the
loss of pointer state. Only port 1 information is valid in AU-4
mode. The mask bit is TMUX_RLOPM1 (Table 87).
0
TMUX_RSFB3D2 Receive Path Signal Fail BER Algorithm Delta. This delta
bit indicates a change of state for the signal fail BER algorithm state bit TMUX_RSFB32 (Table 92) at the path level for
port 2. Only port 1 information is valid in AU-4 mode and in
STS-1 mode. The mask bit is TMUX_RSFB3M2 (Table 87).
TMUX_RSDB3D2 Receive Path Signal Degrade BER Algorithm Delta. This
0
delta bit indicates a change of state for the signal fail BER
algorithm state bit TMUX_RSDB32 (Table 92) at the path
level for port 2. Only port 1 information is valid in AU-4 mode
and in STS-1 mode. The mask bit is TMUX_RHSSDB3M2.
0
TMUX_RUNEQPD2 Receive Path Unequipped Delta. This delta bit indicates
that the current value of the received C2 (signal label) byte,
TMUX_C2MON2[7:0] (Table 104), has a value 0x00, indicating unequipped payload for port 2. Only port 1 information is
valid in AU-4 mode and in STS-1 mode.The mask bit is
TMUX_RUNEQPM2 (Table 87).
0
TMUX_RPLMPD2 Receive Path Payload Label Mismatch Delta. This event
bit indicates that the current value of the received C2 (signal
label) byte, TMUX_C2MON2[7:0], differs from the expected
C2 value, TMUX_C2EXP2[7:0] (Table 100) for port 2. Only
port 1 information is valid in AU-4 mode and in STS-1
mode.The mask bit is TMUX_RPLMPM2 (Table 87).
0
TMUX_RN1MOND2 Receive N1 Monitor Delta. This delta bit indicates a change
in state in TMUX_N1MON2[7:0] (Table 104). The N1 current
value is updated when a consecutive and consistent value is
detected in the incoming N1 byte for TMUX_CNTDN1[3:0]
(Table 99) frames on port 2. Only port 1 information is valid in
AU-4 mode and in STS-1 mode. The mask bit is
TMUX_RN1MONM2 (Table 87).
0
TMUX_RK3MOND2 Receive K3 Monitor Delta. This delta bit indicates a change
in state in TMUX_K3MON2[7:0] (Table 104), which is
updated when a consecutive and consistent value is
detected in the incoming K3 byte for TMUX_CNTDK3[3:0]
(Table 99) frames on port 2. Only port 1 information is valid in
AU-4 mode and in STS-1 mode. The mask bit is
TMUX_RK3MONM2 (Table 87).
83
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
8 TMUX Registers (continued)
Table 83. TMUX_RPOH[1—3]_DLT, Delta/Event (COR/COW) (continued)
Address
Bit
0x40008
9
8
7
6
5
4
3
84
Name
Function
Reset
Default
0
TMUX_RF3MOND2 Receive F3 (Path User Byte) Monitor Delta. This delta bit indicates a change in state in TMUX_F3MON02[7:0] (Table 104),
which is updated when a consecutive and consistent value is
detected in the incoming F3 byte for TMUX_CNTDF3[3:0]
(Table 99) frames on port 2. Only port 1 information is valid in
AU-4 mode and in STS-1 mode. The mask bit is
TMUX_RF3MONM2 (Table 87).
0
TMUX_RF2MOND2 Receive F2 (Path User Byte) Monitor Delta. This delta bit indicates a change in state in TMUX_F2MON02[7:0] (Table 104),
which is updated when a consecutive and consistent value is
detected in the incoming F2 byte for TMUX_CNTDF2[3:0]
(Table 99) frames on port 2. Only port 1 information is valid in
AU-4 mode and in STS-1 mode. The mask bit is
TMUX_RF2MONM2 (Table 87).
0
TMUX_RRDIPD2 Receive Path RDI (Remote Defect Indication) Monitor Delta.
This delta bit indicates a change in state in
TMUX_RDIPMON2[2:0] (Table 104) which occurs when a consecutive and consistent new value is detected in the incoming
G1[3:1] bits for TMUX_CNTDRDIP[3:0] (Table 99) frames on
port 2. The device monitors either G1 bit 3 or G1[3:1] depending
on TMUX_REPRDI_MODE (Table 95). Only port 1 information
is valid in AU-4 mode and in STS-1 mode. The mask bit is
TMUX_RRDIPM2 (Table 87).
0
TMUX_RC2MOND2 Receive C2 (Signal Label) Monitor Delta. This delta bit indicates a change in state in TMUX_C2MON2[7:0] (Table 104),
which is updated when a consecutive and consistent value is
detected in the incoming C2 byte for TMUX_CNTDC2[3:0]
(Table 99) frames on port 2. Only port 1 information is valid in
AU-4 mode and in STS-1 mode. The mask bit is
TMUX_RC2MONM2 (Table 87).
0
TMUX_RTIMPD2 Receive Path Trace Identifier Mismatch Delta. This delta bit
indicates a change in state in the received 16-byte J1 sequence
for port 2 if the J1 mode is programmed to receive a 16-byte
sequence. Only port 1 information is valid in AU-4 mode and in
STS-1 mode. The mask bit is TMUX_RTIMPM2 (Table 87).
0
TMUX_RNDFE2
Receive New Data Flag Event. This event bit indicates that the
incoming pointer has the new data flag enabled for port 2, causing a jump in the current pointer location. Only port 1 information
is valid in AU-4 mode and in STS-1 mode. The mask bit is
TMUX_RNDFM2 (Table 87).
0
TMUX_RDECE2
Receive Pointer Decrement Event. This event bit indicates
that a valid incoming pointer decrement indication was received
on port 2. Only port 1 information is valid in AU-4 mode and in
STS-1 mode. The mask bit is TMUX_RDECM2 (Table 87). However, increment and decrement event indication should be
ignored during loss-of-pointer (LOP) condition.
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
8 TMUX Registers (continued)
Table 83. TMUX_RPOH[1—3]_DLT, Delta/Event (COR/COW) (continued)
Address
Bit
Name
Function
0x40008
2
TMUX_RINCE2
1
TMUX_RPAISD2
0
TMUX_RLOPD2
15
TMUX_RSFB3D3
14
TMUX_RSDB3D3
13
TMUX_RUNEQPE3
12
TMUX_RPLMPE3
Receive Pointer Increment Event. This event bit indicates
that a valid incoming pointer increment indication was
received on port 2. Only port 1 information is valid in AU-4
mode and in STS-1 mode. The mask bit is TMUX_RINCM2
(Table 87). However, increment and decrement event indication should be ignored during loss-of-pointer (LOP) condition.
Receive Path AIS Delta. This delta bit indicates a change in
state of the TMUX_RPAIS2 (Table 92) state bit, which designates that the port 2 pointer interpreter is in the alarm indication signal state. Only port 1 information is valid in AU-4
mode and in STS-1 mode. The mask bit is TMUX_RPAISM2
(Table 87).
Receive Loss of Pointer Delta. This delta bit indicates a
change in state of the TMUX_RLOP2 (Table 92) state bit,
which designates that the port 2 pointer interpreter is in the
loss of pointer state. Only port 1 information is valid in AU-4
mode. The mask bit is TMUX_RLOPM2 (Table 87).
Receive Path Signal Fail BER Algorithm Delta. This delta
bit indicates a change of state for the signal fail BER algorithm state bit TMUX_RSFB32 (Table 92) at the path level for
port 3. Only port 1 information is valid in AU-4 mode and in
STS-1 mode. The mask bit is TMUX_RSFB3M3 (Table 87).
Receive Path Signal Degrade BER Algorithm Delta. This
delta bit indicates a change of state for the signal fail BER
algorithm state bit TMUX_RSDB32 (Table 92) at the path
level for port 3. Only port 1 information is valid in AU-4 mode
and in STS-1 mode. The mask bit is TMUX_RSDB3M3
(Table 87).
Receive Path Unequipped Event. This event bit indicates
that the current value of the received C2 (signal label) byte,
TMUX_C2MON3[7:0] (Table 104), has a value 0x00, indicating unequipped payload for port 3. Only port 1 information is
valid in AU-4 mode and in STS-1 mode. The mask bit is
TMUX_RUNEQPM3 (Table 87).
Receive Path Payload Label Mismatch Event. This event
bit indicates that the current value of the received C2 (signal
label) byte, TMUX_C2MON3[7:0], differs from the expected
C2 value, TMUX_C2EXP3[7:0] (Table 100) for port 3. Only
port 1 information is valid in AU-4 mode and in STS-1 mode.
The mask bit is TMUX_RPLMPM3 (Table 87).
0x40009
Agere Systems Inc.
Reset
Default
0
0
0
0
0
0
0
85
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
8 TMUX Registers (continued)
Table 83. TMUX_RPOH[1—3]_DLT, Delta/Event (COR/COW) (continued)
Address
Bit
Name
0x40009
11
TMUX_RN1MOND3
10
TMUX_RK3MOND3
9
TMUX_RF3MOND3
8
TMUX_RF2MOND3
7
TMUX_RDIPD3
6
TMUX_RC2MOND3
5
TMUX_RTIMPD3
86
Function
Reset
Default
0
Receive N1 Monitor Delta. This delta bit indicates a change in
state in TMUX_N1MON3[7:0] (Table 104). The N1 current
value is updated when a consecutive and consistent value is
detected in the incoming N1 byte for TMUX_CNTDN1[3:0]
(Table 99) frames on port 3. Only port 1 information is valid in
AU-4 mode and in STS-1 mode. The mask bit is
TMUX_RN1MONM3 (Table 87).
0
Receive K3 Monitor Delta. This delta bit indicates a change in
state in TMUX_K3MON3[7:0] (Table 104), which is updated
when a consecutive and consistent value is detected in the
incoming K3 byte for TMUX_CNTDK3[3:0] (Table 99) frames
on port 2. Only port 1 information is valid in AU-4 mode and in
STS-1 mode. The mask bit is TMUX_RK3MONM3 (Table 87).
0
Receive F3 (Path User Byte) Monitor Delta. This delta bit
indicates a change in state in TMUX_F3MON03[7:0]
(Table 104), which is updated when a consecutive and consistent value is detected in the incoming F3 byte for
TMUX_CNTDF3[3:0] (Table 99) frames on port 3. Only port 1
information is valid in AU-4 mode and in STS-1 mode. The
mask bit is TMUX_RF3MONM3 (Table 87).
Receive F2 (Path User Byte) Monitor Delta. This delta bit
0
indicates a change in state in TMUX_F2MON03[7:0]
(Table 104), which is updated when a consecutive and consistent value is detected in the incoming F2 byte for
TMUX_CNTDF2[3:0] (Table 99) frames on port 3. Only port 1
information is valid in AU-4 mode and in STS-1 mode. The
mask bit is TMUX_RF2MONM3 (Table 87).
Receive Path RDI (Remote Defect Indication) Monitor
0
Delta. This delta bit indicates a change in state in
TMUX_RDIPMON3[2:0] (Table 104) which occurs when a consecutive and consistent new value is detected in the incoming
G1[3:1] bits for TMUX_CNTDRDIP[3:0] (Table 99) frames on
port 3. The device monitors either G1 bit 3 or G1[3:1] depending on TMUX_REPRDI_MODE (Table 95). Only port 1 information is valid in AU-4 mode and in STS-1 mode. The mask bit is
TMUX_RRDIPM3 (Table 87).
Receive C2 (Signal Label) Monitor Delta. This delta bit indi0
cates a change in state in TMUX_C2MON3[7:0] (Table 104),
which is updated when a consecutive and consistent value is
detected in the incoming C2 byte for TMUX_CNTDC2[3:0]
(Table 99) frames on port 3. Only port 1 information is valid in
AU-4 mode and in STS-1 mode. The mask bit is
TMUX_RC2MONM3 (Table 87).
Receive Path Trace Identifier Mismatch Delta. This delta bit
0
indicates a change in state in the received 16-byte J1 sequence
for port 3 if the J1 mode is programmed to receive a 16-byte
sequence. Only port 1 information is valid in AU-4 mode and in
STS-1 mode. The mask bit is TMUX_RTIMPM3 (Table 87).
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
8 TMUX Registers (continued)
Table 83. TMUX_RPOH[1—3]_DLT, Delta/Event (COR/COW) (continued)
Address
Bit
Name
0x40009
4
TMUX_RNDFE3
3
TMUX_RDECE3
2
TMUX_RINCE3
1
TMUX_RPAISD3
0
TMUX_RLOPD3
Function
Reset
Default
Receive New Data Flag Event. This event bit indicates that the
0
incoming pointer has the new data flag enabled, causing a jump
in the current pointer location for port 3. Only port 1 information
is valid in AU-4 mode and in STS-1 mode. The mask bit is
TMUX_RNDFM3 (Table 87).
Receive Pointer Decrement Event. This event bit indicates
0
that a valid incoming pointer decrement indication was received
on port 3. Only port 1 information is valid in AU-4 mode and in
STS-1 mode. The mask bit is TMUX_RDECM3 (Table 87).
0
Receive Pointer Increment Event. This event bit indicates that
a valid incoming pointer increment indication was received on
port 3. Only port 1 information is valid in AU-4 mode and in
STS-1 mode. The mask bit is TMUX_RINCM3 (Table 87).
Receive Path AIS Delta. This delta bit indicates a change in
0
state of the TMUX_RPAIS3 (Table 92) state bit, which designates that the port 3 pointer interpreter is in the alarm indication
signal state. Only port 1 information is valid in AU-4 mode and in
STS-1 mode. The mask bit is TMUX_RPAISM3 (Table 87).
0
Receive Loss of Pointer Delta. This delta bit indicates a
change in state of the TMUX_RLOP3 (Table 92) state bit, which
designates that the port 3 pointer interpreter is in the loss of
pointer state. Only port 1 information is valid in AU-4 mode. The
mask bit is TMUX_RLOPM3 (Table 87).
Note: In Table 84, the mask bits are set to suppress an interrupt when the corresponding event has occurred or
change in state has taken place.
Table 84. TMUX_TX_MSK, Mask Bits for INT Interrupt Signal (R/W) (Mask = 1, No Mask = 0)
Address
Bit
0x4000A
15:7
6:4
3
2
1
0
Agere Systems Inc.
Name
Function
Reset
Default
—
Reserved.
0x000
TMUX_TLSPARM[3:1] Transmit Low-speed Parity Error Mask (Input Port Num1
ber). See Table 80 for description.
TMUX_TPOAC_PM Transmit Path Overhead Access Channel (TPOAC) Par1
ity Error Mask. See Table 80 for description.
TMUX_TTOAC_PM Transmit Transport Overhead Access Channel (TTOAC)
1
Parity Error Mask. See Table 80 for description.
TMUX_THSILOFM Transmit High-speed Input Loss of Frame Mask. See
1
Table 80 for description.
TMUX_THSILOCM Transmit High-speed Input Loss of Clock Mask. See
1
Table 80 for description.
87
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
8 TMUX Registers (continued)
Note: In Table 85, the mask bits are set to suppress an interrupt when the corresponding event has occurred or
change in state has taken place.
Table 85. TMUX_RPS_MSK, Mask Bits for INT Interrupt Signal (R/W) (Mask = 1, No Mask = 0)
Address
Bit
0x4000B
15:6
5
4
3
2
1
Name
Function
—
Reserved.
TMUX_RPSLOFM Receive Protection High-speed Loss of Frame Mask. See
Table 81 for description.
TMUX_RPSOOFM Receive Protection High-speed Out of Frame Mask. See
Table 81 for description.
TMUX_RPSILOCM Receive Protection High-speed Loss of Input Clock Mask.
See Table 81 for description.
TMUX_RPSB2M Receive Protection High-speed B2 Error Mask. See
Table 81 for description.
TMUX_RPSLREIM Receive Protection High-speed Line REI Mask. See
Table 81 for description.
Reset
Default
0x000
1
1
1
1
1
Note: In Table 86, the mask bits are set to suppress an interrupt when the corresponding event has occurred or
change in state has taken place.
Table 86. TMUX_RHS_MSK, Mask Bits for INT Interrupt Signal (R/W) (Mask = 1, No Mask = 0)
Address
Bit
0x4000C
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
88
Name
Function
Reset
Default
—
Reserved.
0
TMUX_RS1BABM Receive S1 Babble Mask. See Table 82 for description.
1
TMUX_RS1MONM Receive S1 Monitor Mask. See Table 82 for description.
1
TMUX_RLRDIMONM Receive Line RDI Monitor Mask. See Table 82 for descrip1
tion.
TMUX_RLAISMONM Receive Line AIS Monitor Mask. See Table 82 for descrip1
tion.
TMUX_RK2MONM Receive K2 Monitor Mask. See Table 82 for description.
1
TMUX_RAPSBABM Receive APS Babble Mask. See Table 82 for description.
1
TMUX_RAPSMONM Receive APS Monitor Mask. See Table 82 for description.
1
TMUX_RF1MONM Receive F1 Monitor Mask. See Table 82 for description.
1
TMUX_RTIMSM
Receive Section Trace Identifier Mismatch Mask. See
1
Table 82 for description.
TMUX_RHSSFM
Receive High-speed Signal Fail BER Algorithm Mask.
1
See Table 82 for description.
TMUX_RHSSDM
Receive High-speed Signal Degrade BER Algorithm
1
Mask. See Table 82 for description.
TMUX_RHSLOSM Receive High-speed Loss of Signal Mask. See Table 82
1
for description.
TMUX_RHSLOFM Receive High-speed Loss of Frame Mask. See Table 82
1
for description.
TMUX_RHSOOFM Receive High-speed Out of Frame Mask. See Table 82 for
1
description.
TMUX_RHSILOCM Receive High-speed Loss of Input Clock Mask. See
1
Table 82 for description.
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
8 TMUX Registers (continued)
Note: In Table 87, the mask bits are set to suppress an interrupt when the corresponding event has occurred or
change in state has taken place.
Table 87. TMUX_RPOH[1—3]_MSK, Mask Bits for Interrupt Signal (R/W) (Mask = 1, No Mask = 0)
Address
Bit
Name
0x4000D
15
TMUX_RSFB3M1
14
TMUX_RSDB3M1
13
12
TMUX_RUNEQPM1
TMUX_RPLMPM1
11
10
9
TMUX_RN1MONM1
TMUX_RK3MONM1
TMUX_RF3MONM1
8
TMUX_RF2MONM1
7
TMUX_RRDIPM1
6
TMUX_RC2MONM1
5
TMUX_RTIMPM1
4
3
TMUX_RNDFM1
TMUX_RDECM1
2
TMUX_RINCM1
1
0
15
TMUX_RPAISM1
TMUX_RLOPM1
TMUX_RSFB3M2
14
TMUX_RSDB3M2
13
12
TMUX_RUNEQPM2
TMUX_RPLMPM2
11
10
9
TMUX_RN1MONM2
TMUX_RK3MONM2
TMUX_RF3MONM2
8
TMUX_RF2MONM2
7
TMUX_RRDIPM2
0x4000E
Agere Systems Inc.
Function
Reset
Default
Receive Path Signal Fail BER Algorithm Mask. See Table 83
1
for description.
Receive Path Signal Degrade BER Algorithm Mask. See
1
Table 83 for description.
Receive Path Unequipped Mask. See Table 83 for description.
1
Receive Path Payload Label Mismatch Mask. See Table 83
1
for description.
Receive N1 Monitor Mask. See Table 83 for description.
1
Receive K3 Monitor Mask. See Table 83 for description.
1
Receive F3 (Path User Byte) Monitor Mask. See Table 83 for
1
description.
Receive F2 (Path User Byte) Monitor Mask. See Table 83 for
1
description.
Receive Path RDI (Remote Defect Indication) Monitor Mask.
1
See Table 83 for description.
1
Receive C2 (Signal Label) Monitor Mask. See Table 83 for
description.
Receive Path Trace Identifier Mismatch Mask. See Table 83
1
for description.
Receive New Data Flag Mask. See Table 83 for description.
1
Receive Pointer Decrement Mask. See Table 83 for descrip1
tion.
Receive Pointer Increment Mask. See Table 83 for descrip1
tion.
Receive Path AIS Mask. See Table 83 for description.
1
Receive Loss of Pointer Mask. See Table 83 for description.
1
Receive Path Signal Fail BER Algorithm Mask. See Table 83
1
for description.
Receive Path Signal Degrade BER Algorithm Mask. See
1
Table 83 for description.
Receive Path Unequipped Mask. See Table 83 for description.
1
Receive Path Payload Label Mismatch Mask. See Table 83
1
for description.
Receive N1 Monitor Mask. See Table 83 for description.
1
Receive K3 Monitor Mask. See Table 83 for description.
1
Receive F3 (Path User Byte) Monitor Mask. See Table 83 for
1
description.
Receive F2 (Path User Byte) Monitor Mask. See Table 83 for
1
description.
Receive Path RDI (Remote Defect Indication) Monitor Mask.
1
See Table 83 for description.
89
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
8 TMUX Registers (continued)
Note: In Table 87, the mask bits are set to suppress an interrupt when the corresponding event has occurred or
change in state has taken place.
Table 87. TMUX_RPOH[1—3]_MSK, Mask Bits for Interrupt Signal (R/W) (Mask = 1, No Mask = 0) (continued)
Address
Bit
0x4000E
6
5
4
3
2
0x4000F
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
90
Name
Function
TMUX_RC2MONM2 Receive C2 (Signal Label) Monitor Mask. See Table 83 for
description.
TMUX_RTIMPM2 Receive Path Trace Identifier Mismatch Mask. See
Table 83 for description.
TMUX_RNDFM2 Receive New Data Flag Mask. See Table 83 for description.
TMUX_RDECM2 Receive Pointer Decrement Mask. See Table 83 for
description.
TMUX_RINCM2
Receive Pointer Increment Mask. See Table 83 for description.
TMUX_RPAISM2 Receive Path AIS Mask. See Table 83 for description.
TMUX_RLOPM2 Receive Loss of Pointer Mask. See Table 83 for description.
TMUX_RSFB3M3 Receive Path Signal Fail BER Algorithm Mask. See
Table 83 for description.
TMUX_RSDB3M3 Receive Path Signal Degrade BER Algorithm Mask. See
Table 83 for description.
TMUX_RUNEQPM3 Receive Path Unequipped Mask. See Table 83 for description.
TMUX_RPLMPM3 Receive Path Payload Label Mismatch Mask. See Table 83
for description.
TMUX_RN1MONM3 Receive N1 Monitor Mask. See Table 83 for description.
TMUX_RK3MONM3 Receive K3 Monitor Mask. See Table 83 for description.
TMUX_RF3MONM3 Receive F3 (Path User Byte) Monitor Mask. See Table 83
for description.
TMUX_RF2MONM3 Receive F2 (Path User Byte) Monitor Mask. See Table 83
for description.
TMUX_RRDIPM3 Receive Path RDI (Remote Defect Indication) Monitor
Mask. See Table 83 for description.
TMUX_RC2MONM3 Receive C2 (Signal Label) Monitor Mask. See Table 83 for
description.
TMUX_RTIMPM3 Receive Path Trace Identifier Mismatch Mask. See
Table 83 for description.
TMUX_RNDFM3 Receive New Data Flag Mask. See Table 83 for description.
TMUX_RDECM3 Receive Pointer Decrement Mask. See Table 83 for
description.
TMUX_RINCM3
Receive Pointer Increment Mask. See Table 83 for description.
TMUX_RPAISM3 Receive Path AIS Mask. See Table 83 for description.
TMUX_RLOPM3 Receive Loss of Pointer Mask. See Table 83 for description.
Reset
Default
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
8 TMUX Registers (continued)
Note: In Table 88, the mask bits are set to suppress an interrupt when the corresponding event has occurred or
change in state has taken place.
Table 88. TMUX_APSINT_MSK, Mask Bits for APSINT Interrupt Signal (R/W) (Mask = 1, No Mask = 0)
Address
Bit
Name
0x40011
15:8
7
—
TMUX_RHSSF_APSM
6
5
4
3
2
1
0
Function
Reserved.
Receive High-speed Signal Fail BER Algorithm
APSINT Mask. See Table 82 for description.
TMUX_RHSSD_APSM
Receive High-speed Signal Degrade BER Algorithm APSINT Mask. See Table 82 for description.
TMUX_RAPSMON_APSM Receive APS Monitor APSINT Mask. See Table 83
for description.
TMUX_RLAISMON_APSM Receive Line AIS Monitor APSINT Mask. See
Table 82 for description.
TMUX_RHSLOS_APSM Receive High-speed Loss of Signal APSINT Mask.
See Table 82 for description.
TMUX_RHSLOF_APSM Receive High-speed Loss of Frame APSINT Mask.
See Table 82 for description.
TMUX_RHSOOF_APSM Receive High-speed Out of Frame APSINT Mask.
See Table 82 for description.
TMUX_RHSILOC_APSM Receive High-speed Loss of Input Clock APSINT
Mask. See Table 82 for description.
Reset
Default
0x000
1
1
1
1
1
1
1
1
Note: When state bits are set in Table 89, the corresponding function has occurred.
Table 89. TMUX_TX_STATE, State Parameters (RO)
Address
Bit
0x40012
15:2
1
0
Name
Function
—
Reserved.
TMUX_THSILOF Transmit High-speed Input Loss of Frame State. See
Table 80 for description.
TMUX_THSILOC Transmit High-speed Input Loss of Clock State. See
Table 80 for description.
Reset
Default
0x000
0
0
Note: When state bits are set in Table 90, the corresponding function has occurred.
Table 90. TMUX_RPS_STATE, State and Value Parameters (RO)
Address
Bit
0x40013
15:6
5
4
3
2:0
Agere Systems Inc.
Name
Function
—
Reserved.
TMUX_RPSLOF Receive Protection High-speed Loss of Frame State. See
Table 81 for description.
TMUX_RPSOOF Receive Protection High-speed Out of Frame State. See
Table 81 for description.
TMUX_RPSILOC Receive Protection High-speed Loss of Input Clock State.
See Table 81 for description.
—
Reserved.
Reset
Default
0x000
0
0
0
000
91
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
8 TMUX Registers (continued)
Note: When state bits are set in Table 91, the corresponding function has occurred.
Table 91. TMUX_RHS_STATE, State and Value Parameters (RO)
Address
Bit
Name
0x40014
15:13
—
12
TMUX_RLRDIMON
Receive Line RDI Monitor State. See Table 82 for
description.
0
11
TMUX_RLAISMON
Receive Line AIS Monitor State. See Table 82 for
description.
0
10:8
—
7
Function
Reset
Default
Reserved.
000
Reserved.
000
TMUX_RHSLOSEXTI Reflects LOSEXT Pin (AE5) Input.
—
6
TMUX_RTIMS
Reflects Section-Level Trace Identifier Mismatch State.
—
5
TMUX_RHSSF
Receive High-speed Signal Fail BER Algorithm State.
See Table 82 for description.
0
4
TMUX_RHSSD
Receive High-speed Signal Degrade BER Algorithm
State. See Table 82 for description.
0
3
TMUX_RHSLOS
Receive High-speed Loss of Signal State. See Table 82
for description.
0
2
TMUX_RHSLOF
Receive High-speed Loss of Frame State. See Table 82
for description.
0
1
TMUX_RHSOOF
Receive High-speed Out of Frame State. See Table 82
for description.
0
0
TMUX_RHSILOC
Receive High-speed Loss of Input Clock State. See
Table 82 for description.
0
Note: When state bits are set in Table 92, the corresponding function has occurred.
Table 92. TMUX_RPOH[1—3]_STATE, State and Value Parameters (RO )
Address
Bit
Name
Function
0x40015
15
TMUX_RSFB31
14
TMUX_RSDB31
13
TMUX_RUNEQP1
12
TMUX_RPLMP1
11:6
5
—
TMUX_RTIMP1
4:2
1
—
TMUX_RPAIS1
0
TMUX_RLOP1
Receive Path Signal Fail BER Algorithm State.
See Table 83 for description.
Receive Path Signal Degrade BER Algorithm
State. See Table 83 for description.
Receive Path Unequipped State. See Table 83
for description.
Receive Path Payload Label Mismatch State.
See Table 83 for description.
Reserved.
Receive Path Trace Identifier Mismatch State.
See Table 83 for description.
Reserved.
Receive Path AIS State. See Table 83 for description.
Receive Loss of Pointer State. See Table 83 for
description.
92
Reset
Default
0
0
0
0
0x00
0
000
0
0
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
8 TMUX Registers (continued)
Table 92. TMUX_RPOH[1—3]_STATE, State and Value Parameters (RO) (continued)
Address
Bit
Name
0x40016
15
TMUX_RSFB32
14
13
12
11:6
5
4
3:2
1
0
0x40017
15
14
13
12
11:6
5
4
3:2
1
0
Agere Systems Inc.
Function
Receive Path Signal Fail BER Algorithm State.
See Table 83 for description.
TMUX_RSDB32
Receive Path Signal Degrade BER Algorithm
State. See Table 83 for description.
TMUX_RUNEQP2
Receive Path Unequipped State. See Table 83
for description.
TMUX_RPLMP2
Receive Path Payload Label Mismatch State.
See Table 83 for description.
—
Reserved.
TMUX_RTIMP2
Receive Path Trace Identifier Mismatch State.
See Table 83 for description.
—
Reserved.
TMUX_CONCAT_STATE2[1:0] Concatenation Pointer State Machine State.
State bits indicate the state of the concatenation
state machine (LOPC = 10, AISC = 01,
CONC = 00) for port 2. These values only have
meaning in the AU-4 mode with the
TMUX_RCONCATMODE bit (Table 95) set to the
concatenation mode (1).
TMUX_RPAIS2
Receive Path AIS State. See Table 83 for description.
TMUX_RLOP2
Receive Loss of Pointer State. See Table 83 for
description.
TMUX_RSFB33
Receive Path Signal Fail BER Algorithm State.
See Table 83 for description.
TMUX_RSDB33
Receive Path Signal Degrade BER Algorithm
State. See Table 83 for description.
TMUX_RUNEQP3
Receive Path Unequipped State. See Table 83
for description.
TMUX_RPLMP3
Receive Path Payload Label Mismatch State.
See Table 83 for description.
—
Reserved.
TMUX_RTIMP3
Receive Path Trace Identifier Mismatch State.
See Table 83 for description.
—
Reserved.
TMUX_CONCAT_STATE3[1:0] Concatenation Pointer State Machine State.
State bits indicate the state of the concatenation
state machine (LOPC = 10, AISC = 01,
CONC = 00) for port 3. These values only have
meaning in the AU-4 mode and the
TMUX_RCONCATMODE bit (Table 95) set to the
concatenation mode (1).
TMUX_RPAIS3
Receive Path AIS State. See Table 83 for description.
TMUX_RLOP3
Receive Loss of Pointer State. See Table 83 for
description.
Reset
Default
0
0
0
0
0x000
0
0
00
0
0
0
0
0
0
0x000
0
0
00
0
0
93
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
8 TMUX Registers (continued)
Table 93. TMUX_RHS_CTL, Receive High-speed Control Parameters (R/W)
Address
0x40019
Bit
15:4
3
2
1
0
Name
Function
—
Reserved.
TMUX_LOSEXT_LEVEL Controls External LOSEXT Polarity.
0 = active-low. 1 = active-high.
TMUX_RPSMUXSEL1 Receive Protection Switch Control. Control bit,
when set to a logic 1, causes the receive protection switch data and clock inputs to be selected;
otherwise, the normal receive high-speed data
input is selected.
TMUX_THS2RHSLB
Transmit High-speed to Receive High-speed
Loopback Control. Control bit, when set to a
logic 1, causes the transmit output STS-3/STM-1
(AU-4) signal to be looped back to the receive
input; otherwise, the loopback is disabled.
TMUX_RHSDSCR
Receive High-speed Descramble Enable. Control bit, when set to a logic 1, causes the input
STS-3/STM-1 (AU-4) signal to be descrambled;
otherwise, the signal is not descrambled.
Reset Default
0x000
0
0
0
0
Table 94. TMUX_RLS_BITBLK_CTL, Receive Low-speed Control Parameters (R/W)
Address
0x4001A
94
Bit
Name
Function
Reset Default
15:9
—
Reserved.
0x00
8:7 TMUX_RCV_SS_EXP[1:0] Expected Receive Pointer Size Bits Value.
00
Expected value of incoming pointer SS bits.
6
TMUX_RCV_SS_ENB
Receive Size Bits Enable. Control bit, when set to
0
a logic 0, causes the received size bits to be
ignored by the pointer interpreter; otherwise, the
received size bits must equal the expected size bits
or the received pointer value will be invalid.
5
—
Reserved.
0
4
TMUX_BITBLKG1
Receive Bit/Block Error Count Control. Control
0
bit, when set to a logic 0, causes the receive error
counter to count bit errors; otherwise, count block
errors (a block equals one frame).
3
TMUX_BITBLKM1
Receive Bit/Block Error Count Control. Control
0
bit, when set to a logic 0, causes the receive error
counter to count bit errors; otherwise, count block
errors (a block equals one frame).
2
TMUX_BITBLKB3
Receive Bit/Block Error Count Control. Control
0
bit, when set to a logic 0, causes the receive error
counter to count bit errors; otherwise, count block
errors (a block equals one frame).
1
TMUX_BITBLKB2
Receive Bit/Block Error Count Control. Control
0
bit, when set to a logic 0, causes the receive error
counter to count bit errors; otherwise, count block
errors (a block equals one frame).
0
TMUX_BITBLKB1
Receive Bit/Block Error Count Control. Control
0
bit, when set to a logic 0, causes the receive error
counter to count bit errors; otherwise, count block
errors (a block equals one frame).
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
8 TMUX Registers (continued)
Table 95. TMUX_RLS_MODE_CTL, Receive Low-speed Control Parameters (R/W)
Address
Bit
Name
0x4001B
15:14
—
13
Function
Reset
Default
Reserved.
00
TMUX_RPAIS_INS
Receive Force Path AIS Insertion. Control bit, when
set to a logic 1, causes the receive low-speed signal to
carry PAIS as well as asserting all AUTO_AIS[1—3]
(pins AC6, AE6, and AD6) (Table 3) outputs.
0
12
TMUX_8ORMAJORITY
Receive Control Bit for Pointer Justifications. Control bit, when set to a logic 1, causes the pointer interpreter to accept an increment or decrement only if 8 out
of 10 bits are correct; otherwise, it will accept an increment or decrement based on majority vote only.
0
11
TMUX_SDB1B2SEL
Receive Signal Degrade Algorithm Input Selection.
Control bit, when set to a logic 1, causes the B2 errors
to contribute to the signal degrade calculation; otherwise, the B1 error count is used.
0
10
TMUX_SFB1B2SEL
Receive Signal Fail Algorithm Input Selection. Control bit, when set to a logic, causes the B2 errors to contribute to the signal degrade calculation; otherwise, the
B1 error count is used.
0
9:7
TMUX_J1MONMODE[2:0] Receive J1 Monitor Mode. There are six modes, as
defined in J1 monitor on page 377.
000
6:4
TMUX_J0MONMODE[2:0] Receive J0 Monitor Mode. There are six modes, as
defined in Section 17.5.5 J0 Monitor on page 370.
000
3
TMUX_S1MODE4
Receive S1 Monitor Mode. Control bit, when set to a
logic 1, causes the most significant nibble of the S1 byte
to be monitored; otherwise, the entire S1 byte is monitored.
0
2
TMUX_RLSPAROEG
Receive Low-speed Parity Odd or Even Generation.
Control bit, when set to a logic 1, forces the output parity
bit to be even; otherwise, the parity is odd.
0
1
TMUX_RCONCATMODE Receive Concatenation Mode. Control bit, when set to
a logic 1, causes the input pointer interpreter to operate
in concatenation mode. This mode is most likely used in
AU-4 mode; otherwise, three independent pointers are
expected.
0
0
TMUX_REPRDI_MODE
0
Agere Systems Inc.
Receive Enhanced Path RDI Mode. Control bit, when
set to a logic 1, causes the receive path RDI monitor to
monitor the enhanced (3-bit found in G1[3:1]) value of
path RDI; otherwise, a 1-bit value (G1[3]) is monitored.
95
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
8 TMUX Registers (continued)
Table 96. TMUX_RAISINH_CTL, Receive Low-speed Control Parameters (R/W)
Address
Bit
Name
Function
Reset
Default
0x4001C
15
TMUX_R_M1_BIT7
Receive M1 MSB Mode. Control bit, when set to a logic
1, causes the most significant bit in the M1 byte to be
ignored for line REI accumulation; otherwise, the MSB is
included.
0
14
TMUX_RSDB3_AISINH
Receive B3 Signal Degrade AIS Inhibit. Control bit,
when set to a logic 1, inhibit the associated alarm from
causing the assertion of the AUTO_AIS output; otherwise, the associated failure causes assertion of the corresponding AUTO_AIS output signal.
0
13
TMUX_RSFB3_AISINH
Receive B3 Signal Fail AIS Inhibit. Control bit, when
set to a logic 1, inhibit the associated alarm from causing
the assertion of the AUTO_AIS output; otherwise, the
associated failure causes assertion of the corresponding
AUTO_AIS output signal.
0
12:10 TMUX_RTIMP_AISINH[3:1] Receive Path Trace Identifier Mismatch AIS Inhibit
Bits. Control bits, when set to a logic 1, inhibit the associated alarm from causing the assertion of the
AUTO_AIS output; otherwise, the associated failure
causes assertion of the corresponding AUTO_AIS output
signal.
0
9
TMUX_RUNEQP_AISINH
Receive Path Unequip AIS Inhibit. Control bit, when
set to a logic 1, inhibit the associated alarm from causing
the assertion of the AUTO_AIS output; otherwise, the
associated failure causes assertion of the corresponding
AUTO_AIS output signal.
0
8
TMUX_RPLMP_AISINH
Receive Path Payload Label Mismatch AIS Inhibit.
Control bit, when set to a logic 1, inhibit the associated
alarm from causing the assertion of the AUTO_AIS output; otherwise, the associated failure causes assertion of
the corresponding AUTO_AIS output signal.
0
7
TMUX_RHSSD_AISINH
Receive High-speed Signal Degrade AIS Inhibit. Control bits, when set to a logic 1, inhibit the associated
alarm from causing AIS generation; otherwise, the associated failure causes AIS generation on all STS-1/AU-3
outputs as well as the assertion of AUTO_AIS outputs.
0
6
TMUX_RHSSF_AISINH
Receive High-speed Signal Fail AIS Inhibit. Control
bits, when set to a logic 1, inhibit the associated alarm
from causing AIS generation; otherwise, the associated
failure causes AIS generation on all STS-1/AU-3 outputs
as well as the assertion of AUTO_AIS outputs.
0
TMUX_RPAISLOP_AISINH Receive Path AIS or LOP AIS Inhibit. Control bits,
when set to a logic 1, inhibit the associated alarm from
causing AIS generation; otherwise, the associated failure
causes AIS generation on all STS-1/AU-3 outputs as well
as the assertion of AUTO_AIS outputs.
0
5
96
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
8 TMUX Registers (continued)
Table 96. TMUX_RAISINH_CTL, Receive Low-speed Control Parameters (R/W) (continued)
Address
Bit
0x4001C
4
Name
Function
TMUX_RLAISMON_AISINH Receive Line AIS Monitor AIS Inhibit. Control bit,
when set to a logic 1, inhibits the associated alarm
from causing AIS generation; otherwise, the associated failure causes AIS generation on all STS-1/AU-3
outputs as well as the assertion of AUTO_AIS outputs.
Reset
Default
0
3
TMUX_RLOF_AISINH
Receive Loss-of-Frame AIS Inhibit. Control bit,
when set to a logic 1, inhibits the associated alarm
from causing AIS generation; otherwise, the associated failure causes AIS generation on all STS-1/AU-3
outputs as well as the assertion of AUTO_AIS outputs.
0
2
TMUX_ROOF_AISINH
Receive High-speed Out-of-Frame AIS Inhibit.
Control bit, when set to a logic 1, inhibits the associated alarm from causing AIS generation; otherwise,
the associated failure causes AIS generation on all
STS-1/AU-3 outputs as well as the assertion of
AUTO_AIS outputs.
0
1
TMUX_RHSLOS_AISINH
Receive High-speed Loss-of-Signal AIS Inhibit.
Control bit, when set to a logic 1, inhibits the associated alarm from causing AIS generation; otherwise,
the associated failure causes AIS generation on all
STS-1/AU-3 outputs as well as the assertion of
AUTO_AIS outputs.
0
0
TMUX_RILOC_AISINH
Receive Input Loss-of-Clock AIS Inhibit. Control
bit, when set to a logic 1, inhibits the associated alarm
from causing the assertion of the AUTO_AIS outputs;
otherwise, the associated failure causes assertion of
all AUTO_AIS output signals.
0
Table 97. TMUX_LOSDETCNT, Receive Low-speed Control Parameters (R/W)
Address
Bit
Name
0x4001D
15:14
—
Function
Reserved.
13:11 TMUX_FORCEC2DEF[2:0] Force TMUX_RPLMP Defects. These bits (one for
each STS-1 in an STS-3) will force TMUX_RPLMP
defects on certain conditions as shown in Table 524
(STS Signal Label Defect Conditions).
10:0
Agere Systems Inc.
TMUX_LOSDETCNT[10:0] Loss-of-Signal Detection Count. Control bits are the
number of consecutive all-0s/1s pattern detected to
declare LOS state in the unscrambled STS-3/STM-1
(AU-4) input frame. A value of 0x02D equals 2.3 µs
while a value of 0x798 equals 100 µs.
Reset
Default
00
000
0x02D
97
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
8 TMUX Registers (continued)
Table 98. TMUX_CNTD_TOH_[A—B], Continuous N-Times Detect Control Parameters (R/W)
Address
Bit
Name
Function
Reset
Default
0x4001E 15:12 TMUX_CNTDK1K2FRAME[3:0] Continuous N-Times Detect for APS Frame
Bytes. Sets the number of CNTD frames within
which an inconsistent APS value is detected in the
incoming STS-3/STM-1 (AU-4). This value is used in
the APS babble algorithm. The valid range for this
register is 0x3—0xF. Invalid values will be mapped to
a value of 0x3.
11:8
TMUX_CNTDK1K2[3:0]
Continuous N-Times Detect for APS (K1, K2[7:3])
Bytes. Sets the number of CNTD occurrences of a
consistent APS value in the incoming STS-3/STM-1
(AU-4) frame. The valid range for this register is
0x3—0xF. Invalid values will be mapped to a value of
0x3.
0x3
7:4
TMUX_CNTDF1[3:0]
Continuous N-Times Detect for F1 Byte. Sets the
number of CNTD occurrences of a consistent F1
value in the incoming STS-3/STM-1 (AU-4) frame.
The valid range for this register is 0x3—0xF. Invalid
values will be mapped to a value of 0x3.
0x3
3:0
TMUX_CNTDJ0[3:0]
Continuous N-Times Detect for J0 Byte. Sets the
number of CNTD occurrences of a consistent J0
value in the incoming STS-3/STM-1 (AU-4) frame.
The valid range for this register is 0x3—0xF. Invalid
values will be mapped to a value of 0x3.
0x3
Reserved.
00
0x4001F 15:14
98
0xC
—
13:12
TMUX_CTDLOPCNT[1:0]
Continuous N-Times Detect for Loss of Pointer
State. Control bits are the number of consecutive
conditions for invalid pointer and invalid concatenation indication (pointer interpretation). Valid values
are the following: 00 = 8, 01 = 9, 10 = 10, and 11 = 8.
0x0
11:8
TMUX_CNTDS1FRAME[3:0]
Continuous N-Times Detect for S1 Frame Bytes.
Sets the number of CNTD frames within which an
inconsistent S1 value is detected in the incoming
STS-3/STM-1 (AU-4). This value is used in the S1
babble algorithm. The valid range for this register is
0x3—0xF. Invalid values will be mapped to a value of
0x3.
0x3
7:4
TMUX_CNTDS1[3:0]
Continuous N-Times Detect for S1 Byte. Sets the
number of CNTD occurrences of a consistent S1
value in the incoming STS-3/STM-1 (AU-4) frame.
The valid range for this register is 0x3—0xF. Invalid
values will be mapped to a value of 0x3.
0x3
3:0
TMUX_CNTDK2[3:0]
Continuous N-Times Detect for K2[2:0] Byte.
Sets the number of CNTD occurrences of a consistent K2[2:0] value in the incoming STS-3/STM-1
(AU-4) frame. The valid range for this register is
0x3—0xF. Invalid values will be mapped to a value of
0x3.
0xC
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
8 TMUX Registers (continued)
Table 99. TMUX_CNTD_POH_[A—B], Continuous N-Times Detect Control Parameters (R/W)
Address
Bit
Name
Function
Reset
Default
0x40020
15:12
TMUX_CNTDF2[3:0]
Continuous N-Times Detect for F2 Byte. Sets the number of CNTD occurrences of a consistent F2 value in the
incoming STS-3/STM-1 (AU-4) frame. The valid range for
this register is 0x3—0xF. Invalid values will be mapped to
a value of 0x3.
0x3
TMUX_CNTDRDIP[3:0] Continuous N-Times Detect for G1[3:1] Byte. Sets the
number of CNTD occurrences of a consistent G1[3:1]
value in the incoming STS-3/STM-1 (AU-4) frame. The
valid range for this register is 0x3—0xF. Invalid values will
be mapped to a value of 0x3.
0x3
11:8
0x40021
7:4
TMUX_CNTDC2[3:0]
Continuous N-Times Detect for C2 Byte. Sets the number of CNTD occurrences of a consistent C2 value in the
incoming STS-3/STM-1 (AU-4) frame. The valid range for
this register is 0x3—0xF. Invalid values will be mapped to
a value of 0x3.
0x3
3:0
TMUX_CNTDJ1[3:0]
Continuous N-Times Detect for J1 Byte. Sets the number of CNTD occurrences of a consistent J1 value in the
incoming STS-3/STM-1 (AU-4) frame. The valid range for
this register is 0x3—0xF. Invalid values will be mapped to
a value of 0x3.
0x3
15:13
—
Reserved.
000
12
TMUX_CTDB1SEL
11:8
TMUX_CNTDN1[3:0]
Continuous N-Times Detect for N1 Byte. Sets the number of CNTD occurrences of a consistent N1 value in the
incoming STS-3/STM-1 (AU-4) frame. The valid range for
this register is 0x3—0xF. Invalid values will be mapped to
a value of 0x3.
0x3
7:4
TMUX_CNTDK3[3:0]
Continuous N-Times Detect for K3 Byte. Sets the number of CNTD occurrences of a consistent K3 value in the
incoming STS-3/STM-1 (AU-4) frame. The valid range for
this register is 0x3—0xF. Invalid values will be mapped to
a value of 0x3.
0x3
3:0
TMUX_CNTDF3[3:0]
Continuous N-Times Detect for F3 Byte. Sets the number of CNTD occurrences of a consistent F3 value in the
incoming STS-3/STM-1 (AU-4) frame. The valid range for
this register is 0x3—0xF. Invalid values will be mapped to
a value of 0x3.
0x3
Agere Systems Inc.
Continuous N-Times AUTO AIS Select. Control bit,
when set to a logic 1, causes TOH CNTD counters to be
reset whenever the AUTO_AIS signal is asserted.
0
99
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
8 TMUX Registers (continued)
Table 100. TMUX_C2EXP[1—2_3], Continuous N-Times Detect Control Parameters (R/W)
Address
Bit
Name
0x40022
15:8
—
7:0
0x40023
Function
Reset
Default
Reserved.
0x00
TMUX_C2EXP1[7:0]
Expected C2 Byte for Port 1. Should be programmed to
contain expected signal label (C2) for port 1.
0x00
15:8
TMUX_C2EXP3[7:0]
Expected C2 Byte for Port 3. Should be programmed to
contain expected signal label (C2) for port 3.
0x00
7:0
TMUX_C2EXP2[7:0]
Expected C2 Byte for Port 2. Should be programmed to
contain expected signal label (C2) for port 2.
0x00
Table 101. TMUX_RF1MON, Receive Monitor Values (RO)
Address
Bit
Name
Function
Reset
Default
0x40024
15:8
TMUX_RF1MON1[7:0] Receive F1 Previous Monitor Value. See Section 17.5.7
F1 Monitor on page 371.
0x00
7:0
TMUX_RF1MON0[7:0] Receive F1 Current Monitor Value. See Section 17.5.7
F1 Monitor on page 371.
0x00
Table 102. TMUX_RAPSMON, Receive Monitor Values (RO)
Address
Bit
Name
0x40025
15:3
TMUX_
RAPSMON[12:0]
2:0
TMUX_K2MON[2:0]
Function
Reset
Default
Receive APS Monitor Value. See Section 17.5.9 Automatic Protection Switch (APS) Monitor on page 371.
0x00
Receive K2 Monitor Value. See Section 17.5.9 Automatic
Protection Switch (APS) Monitor on page 371.
0x0
Table 103. TMUX_RS1MON, Receive Monitor Values (RO)
Address
Bit
Name
0x40026
15:8
—
7:0
TMUX_RS1MON[7:0]
100
Function
Reset
Default
Reserved.
0x00
Receive S1 Monitor Value. See Section 17.5.12 Sync
Status Monitor on page 372.
0x00
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
8 TMUX Registers (continued)
Table 104. TMUX_RPOHMON[1—3][A—D], Receive Monitor Values (RO)
Address
0x40027
0x40028
0x40029
0x4002A
0x4002B
0x4002C
0x4002D
0x4002E
0x4002F
0x40030
Bit
Name
Function
15:11
—
Reserved.
10:8 TMUX_RDIPMON1[2:0] Receive Path RDI Monitor Value for Port 1. See RDI-P
Detection on page 379.
7:0
TMUX_C2MON1[7:0] Receive C2 Monitor Value for Port 1. See Signal Label
C2 Byte Monitor on page 378.
15:8
TMUX_F2MON11[7:0] Receive F2 Previous Monitor Value for Port 1. See
Path User Byte F2 Monitor on page 380.
7:0
TMUX_F2MON01[7:0] Receive F2 Current Monitor Value for Port 1. See Path
User Byte F2 Monitor on page 380.
15:8
TMUX_F3MON11[7:0] Receive F3 Previous Monitor Value for Port 1. See
Path User Byte F3 Monitor on page 380.
7:0
TMUX_F3MON01[7:0] Receive F3 Current Monitor Value for Port 1. See Path
User Byte F3 Monitor on page 380.
15:8
TMUX_N1MON1[7:0] Receive N1 Monitor Value for Port 1. See N1 Byte Monitor on page 381.
7:0
TMUX_K3MON1[7:0] Receive K3 Monitor Value for Port 1. See K3 Byte Monitor on page 381.
15:11
—
Reserved.
10:8 TMUX_RDIPMON2[2:0] Receive Path RDI Monitor Value for Port 2. See RDI-P
Detection on page 379.
7:0
TMUX_C2MON2[7:0] Receive C2 Monitor Value for Port 2. See Signal Label
C2 Byte Monitor on page 378.
15:8
TMUX_F2MON12[7:0] Receive F2 Previous Monitor Value for Port 2. See
Path User Byte F2 Monitor on page 380.
7:0
TMUX_F2MON02[7:0] Receive F2 Current Monitor Value for Port 2. See Path
User Byte F2 Monitor on page 380.
15:8
TMUX_F3MON12[7:0] Receive F3 Previous Monitor Value for Port 2. See
Path User Byte F3 Monitor on page 380.
7:0
TMUX_F3MON02[7:0] Receive F3 Current Monitor Value for Port 2. See Path
User Byte F3 Monitor on page 380.
15:8
TMUX_N1MON2[7:0] Receive N1 Monitor Value for Port 2. See N1 Byte Monitor on page 381.
7:0
TMUX_K3MON2[7:0] Receive K3 Monitor Value for Port 2. See K3 Byte Monitor on page 381.
15:11
—
Reserved.
10:8 TMUX_RDIPMON3[2:0] Receive Path RDI Monitor Value for Port 3. See RDI-P
Detection on page 379.
7:0
TMUX_C2MON3[7:0] Receive C2 Monitor Value for Port 3. See Signal Label
C2 Byte Monitor on page 378.
15:8
TMUX_F2MON13[7:0] Receive F2 Previous Monitor Value for Port 3. See
Path User Byte F2 Monitor on page 380.
7:0
TMUX_F2MON03[7:0] Receive F2 Current Monitor Value for Port 3. See Path
User Byte F2 Monitor on page 380.
Agere Systems Inc.
Reset
Default
0x00
0x0
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x0
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x0
0x00
0x00
0x00
101
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
8 TMUX Registers (continued)
Table 104. TMUX_RPOHMON[1—3][A—D], Receive Monitor Values (RO) (continued)
Address
Bit
Name
0x40031
15:8
TMUX_F3MON13[7:0]
Receive F3 Previous Monitor Value for Port 3. See
Path User Byte F3 Monitor on page 380.
0x00
7:0
TMUX_F3MON03[7:0]
Receive F3 Current Monitor Value for Port 3. See Path
User Byte F3 Monitor on page 380.
0x00
15:8
TMUX_N1MON3[7:0]
Receive N1 Monitor Value for Port 3. See N1 Byte Monitor on page 381.
0x00
7:0
TMUX_K3MON3[7:0]
Receive K3 Monitor Value for Port 3. See K3 Byte Monitor on page 381.
0x00
0x40032
Function
Reset
Default
Table 105. TMUX_TLS_CTL, Transmit Low-speed Control Parameters (R/W)
Address
Bit
Name
0x40033
15:7
—
Reset
Default
Reserved.
0x000
6:4
TMUX_TLS_UNEQP[3:1] Transmit Low-speed Unequipped Insert Control.
Control bit, when set to a logic 1, causes an unequip
signal to be generated in the selected STS-1/AU-3 time
slot in the STS-3/STM-1 (AU-4) output signal; normal
data is sent when set to a logic 0. Only
TMUX_TLS_UNEQP1 is used in AU-4 mode.
0
3:1
TMUX_TLS_PAISINS[3:1] Transmit Low-speed Path AIS Insert Control. Control
bit, when set to a logic 1, causes path AIS to be
inserted into the selected STS-1/TUG-3 time slot in the
STS-3/STM-1 (AU-4) output signal; normal data is sent
when set to a logic 0. Only TMUX_TLS_PAISINS1 is
used in AU-4 mode.
0
0
102
Function
TMUX_TLSVOEPAR
Transmit Low-speed Verify Odd or Even Parity. Control bit, when set to a logic 0, causes odd parity to be
verified per byte transfer per STS-1/AU-3 input; otherwise, even parity is verified.
0
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
8 TMUX Registers (continued)
Table 106. TMUX_THS_PORT_CTL, Transmit High-speed Port Control Parameters (R/W)
Address
Bit
0x40034
15:4
3
2
1
0
Name
Function
Reset
Default
—
Reserved.
0x000
0
TMUX_TPSMUXSEL3 Transmit High-speed Protection MUX Selection. Control
bit, when set to a logic 1, causes the receive side working
input STS-3/STM-1 (AU-4) signal to be selected; otherwise,
the signal coming in from the transmit low-speed side (telecom bus) and POH MUX is selected. The output of this
MUX is sent to a transport overhead MUX and eventually
out the TPSD155P/N (pins AF13, AE13) and TPSC155P/N
(pins AC12, AD13) outputs.
0
TMUX_TPSMUXSEL2 Transmit High-speed Protection MUX Selection. Control
bit, when set to a logic 1, causes the receive side protection
input STS-3/STM-1 (AU-4) signal to be selected; otherwise,
the signal coming in from the transmit low-speed side (telecom bus) and POH MUX is selected. The output of this
MUX is sent to a transport overhead MUX and eventually
out the THSDP/N (pins AF9, AE9) output.
TMUX_RHS2THSLB Receive High-speed to Transmit High-speed Loopback
0
Control. Control bit, when set to a logic 1, causes the
receive STS-3/STM-1(AU-4) input signal to be looped back
to the transmit high-speed output; loopback is disabled
when set to a logic 0.
0
TMUX_THSSCR
Transmit High-speed Scramble Enable. Control bit, when
set to a logic 1, causes the output STS-3/STM-1
(AU-4) signal to be scrambled; the signal is not scrambled if
set to a logic 0.
Table 107. TMUX_THS_TOH_CTL, Transmit High-speed Control Parameters (R/W)
Address
0x40035
Bit
Reset
Default
15:13
—
Reserved.
0x0
0
12
TMUX_TCONCATMODE Transmit a Concatenated Signal. Control bit, when set
to a logic 1, causes the outgoing STS-3/STM-1 signal to
be concatenated; otherwise, the outgoing signal is three
independent STS-1s (for a 155 MHz signal).
11
TMUX_TPREIRDISEL Transmit MUX Selection Control for Outgoing Path
0
REI and RDI. Control bit, when set to a logic 1, causes
the path REI and RDI signals to be selected from the
protection board; otherwise, they are derived from the
receive side of the same TMUX.
0
10
TMUX_TLREIRDISEL Transmit MUX Selection Control for Outgoing Line
REI and RDI. Control bit, when set to a logic 1, causes
the line REI and RDI signals to be selected from the protection board; otherwise, they are derived from the
receive side of the same TMUX.
9:8
TMUX_TSS[1:0]
Transmit SS (Bits). These bits are inserted into the out00
going pointer value (but not in the concatenation values).
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Name
Function
103
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
8 TMUX Registers (continued)
Table 107. TMUX_THS_TOH_CTL, Transmit High-speed Control Parameters (R/W) (continued)
Address
Bit
0x40035
7
TMUX_THSLREIINH Transmit Line REI Inhibit. Control bit, when set to a logic 1,
disables hardware insertion of line REI (B2 errors) in the outgoing STM-1 (AU-4) frame M1 byte; a logic 0 enables hardware
insertion of line REI.
0
6
TMUX_THSLAISINS Transmit High-speed Line AIS Insertion. Control bit, when
set to a logic 1, causes line AIS to be inserted into the outgoing
STS-3/STM-1 (AU-4) signal; otherwise, line AIS is not sent.
0
5
TMUX_THSAPSINS Transmit APS Value Insert (Control). Control bit, when set to
a logic 1, inserts the value in TMUX_TAPSINS[12:0]
(Table 113) into the outgoing K1 and K2[7:3] bytes in the STS3/STM-1 (AU-4) frame; a logic 0 inserts the default value based
on SMPR_OH_DEFLT (Table 67).
0
104
Name
Function
Reset
Default
4
TMUX_THSK2INS
Transmit K2[2:0] Insert (Control). Control bit, when set to a
logic 1, inserts the value in TMUX_TK2INS[2:0] (Table 113)
into the outgoing K2 byte in the STS-3/STM-1 (AU-4) frame; a
logic 0 inserts the default value based on SMPR_OH_DEFLT.
0
3
TMUX_THSS1INS
Transmit S1 Insert (Control). Control bit, when set to a
logic 1, inserts the value in TMUX_TS1INS[7:0] (Table 112)
into the outgoing S1 byte in the STS-3/STM-1 (AU-4) frame; a
logic 0 allows insertion from the TTOAC channel or a default
value.
0
2
TMUX_THSF1INS
Transmit F1 Insert (Control). Control bit, when set to a logic
1, inserts the value in TMUX_TF1INS[7:0] (Table 112) into the
outgoing S1 byte in the STS-3/STM-1 (AU-4) frame; a logic 0
allows insertion from the TTOAC channel or a default value.
0
1
TMUX_THSZ0INS
Transmit Z0-2 and Z0-3 Insert (Control). Control bit, when
set to a logic 1, inserts the values in TMUX_TZ02INS[7:0]
(Table 111) and TMUX_TZ03INS[7:0] (Table 111) into the outgoing Z0-2 and Z0-3 bytes in the STS-3/STM-1 (AU-4) frame; a
logic 0 inserts the default value based on SMPR_OH_DEFLT.
0
0
TMUX_THSJ0INS
Transmit J0 Insert (Control). Control bit, when set to a logic
1, inserts the 16-byte sequence TMUX_TJ0DINS[16—1][7:0]
(Table 133) into the outgoing STS-3/STM-1 (AU-4) frame; a
logic 0 inserts the default value based on SMPR_OH_DEFLT.
0
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
8 TMUX Registers (continued)
Table 108. TMUX_THS_POH[1—3]_CTL, Transmit High-Speed Control Parameters (R/W)
Address
Bit
Name
0x40036
15:9
—
Function
Reserved.
Reset
Default
0x00
8
TMUX_THSPREIINH1 Transmit Path REI Inhibit for Port 1. Control bit, when set to
a logic 1, disables hardware insertion of path REI (B3 errors)
in the outgoing STM-1 (AU-4) frame G1 byte; a logic 0
enables hardware insertion of path REI. Only port 1 control is
valid in AU-4 mode.
0
7
TMUX_TPOHTHRU1 Transmit High-speed Path Overhead Insertion from Lowspeed Input (Telecom Bus). Control bit, when set to a logic
1, causes all path overhead bytes, and H1, H2, and H3, to be
passed through from the low-speed telecom bus to the highspeed output signal. Only port 1 control is valid in AU-4 mode.
0
6
TMUX_THSN1INS1
Transmit N1 Insert (Control) for Port 1. Control bit, when
set to a logic 1, inserts the value in TMUX_TN1INS1[7:0]
(Table 114) into the outgoing N1 byte in the STS-3/STM-1
(AU-4) frame; a logic 0 allows insertion from the TPOAC channel or a default value. Only port 1 control is valid in AU-4
mode.
0
5
TMUX_THSK3INS1
Transmit K3 Insert (Control) for Port 1. Control bit, when
set to a logic 1, inserts the value in TMUX_TK3INS1[7:0]
(Table 114) into the outgoing K3 byte in the STS-3/STM-1
(AU-4) frame; a logic 0 allows insertion from the TPOAC channel or a default value. Only port 1 control is valid in AU-4
mode.
0
4
TMUX_THSF3INS1
Transmit F3 Insert (Control) for Port 1. Control bit, when set
to a logic 1, inserts the value in TMUX_TF3INS1[7:0]
(Table 114) into the outgoing F3 byte in the STS-3/STM-1
(AU-4) frame; a logic 0 allows insertion from the TPOAC channel or a default value. Only port 1 control is valid in AU-4
mode.
0
3
TMUX_THSF2INS1
Transmit F2 Insert (Control) for Port 1. Control bit, when set
to a logic 1, inserts the value in TMUX_TF2INS1[7:0]
(Table 114) into the outgoing F2 byte in the STS-3/STM-1
(AU-4) frame; a logic 0 allows insertion from the TPOAC channel or a default value. Only port 1 control is valid in AU-4
mode.
0
2
TMUX_THSRDIPINS1 Transmit Path RDI Insert (Control) for Port 1. Control bit,
when set to a logic 1, inserts the value in
TMUX_TRDIPINS1[2:0] (Table 114) into the outgoing G1[3:1]
bits in the STS-3/STM-1 (AU-4) frame; a logic 0 allows insertion from the TPOAC channel or a default value. Only port 1
control is valid in AU-4 mode.
Agere Systems Inc.
0
105
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
8 TMUX Registers (continued)
Table 108. TMUX_THS_POH[1—3]_CTL, Transmit High-Speed Control Parameters (R/W) (continued)
Address
Bit
Name
Function
Reset
Default
0x40036
1
TMUX_THSC2INS1
Transmit C2 Insert (Control) for Port 1. Control bit, when
set to a logic 1, inserts the value in TMUX_TC2INS1[7:0]
(Table 114) into the outgoing C2 byte in the STS-3/STM-1
(AU-4) frame; a logic 0 allows insertion from the TPOAC channel or a default value. Only port 1 control is valid in AU-4
mode.
0
0
TMUX_THSJ1INS1
Transmit J1 Insert (Control) for Port 1. Control bit, when set
to a logic 1, inserts the 64-byte sequence
TMUX_TJ1DINS1[64—1][7:0] (Table 140) into the outgoing
STS-3/STM-1 (AU-4) frame; a logic 0 allows insertion from the
TPOAC channel or a default value. Only port 1 control is valid
in AU-4 mode.
0
15:9
—
0x40037
106
Reserved.
8
TMUX_THSPREIINH2 Transmit Path REI Inhibit for Port 2. Control bit, when set to
a logic 1, disables hardware insertion of path REI (B3 errors)
in the outgoing STS-3/STM-1 (AU-4) frame G1 byte; a logic 0
enables hardware insertion of path REI. Only port 1 control is
valid in AU-4 mode.
7
TMUX_TPOHTHRU2 Transmit High-speed Path Overhead Insertion from Lowspeed Input (Telecom Bus). Control bit, when set to a logic
1, causes all path overhead bytes for port 2 and, H1, H2, and
H3, to be passed through from the low-speed telecom bus to
the high-speed output signal. Only port 1 control is valid in
AU-4 mode.
6
TMUX_THSN1INS2
Transmit N1 Insert (Control) for Port 2. Control bit, when
set to a logic 1, inserts the value in TMUX_TN1INS2[7:0]
(Table 114) into the outgoing N1 byte in the STS-3/STM-1
(AU-4) frame; a logic 0 allows insertion from the TPOAC channel or a default value. Only port 1 control is valid in AU-4
mode.
5
TMUX_THSK3INS2
Transmit K3 Insert (Control) for Port 2. Control bit, when
set to a logic 1, inserts the value in TMUX_TK3INS2[7:0]
(Table 114) into the outgoing K3 byte in the STS-3/STM-1
(AU-4) frame; a logic 0 allows insertion from the TPOAC channel or a default value. Only port 1 control is valid in AU-4
mode.
4
TMUX_THSF3INS2
Transmit F3 Insert (Control) for Port 2. Control bit, when set
to a logic 1, inserts the value in TMUX_TF3INS2[7:0]
(Table 114) into the outgoing F3 byte in the STS-3/STM-1
(AU-4) frame; a logic 0 allows insertion from the TPOAC channel or a default value. Only port 1 control is valid in AU-4
mode.
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
8 TMUX Registers (continued)
Table 108. TMUX_THS_POH[1—3]_CTL, Transmit High-Speed Control Parameters (R/W) (continued)
Address
Bit
Name
Function
Reset
Default
0x40037
3
TMUX_THSF2INS2
Transmit F2 Insert (Control) for Port 2. Control bit, when set
to a logic 1, inserts the value in TMUX_TF2INS2[7:0]
(Table 114) into the outgoing F2 byte in the STS-3/STM-1
(AU-4) frame; a logic 0 allows insertion from the TPOAC channel or a default value. Only port 1 control is valid in AU-4
mode.
0
2
0x40038
TMUX_THSRDIPINS2 Transmit Path RDI Insert (Control) for Port 2. Control bit,
when set to a logic 1, inserts the value in
TMUX_TRDIPINS2[2:0] (Table 114) into the outgoing G1[3:1]
bits in the STS-3/STM-1 (AU-4) frame; a logic 0 allows insertion from the TPOAC channel or a default value. Only port 1
control is valid in AU-4 mode.
0
1
TMUX_THSC2INS2
Transmit C2 Insert (Control) for Port 2. Control bit, when
set to a logic 1, inserts the value in TMUX_TC2INS2[7:0]
(Table 114) into the outgoing C2 byte in the STS-3/STM-1
(AU-4) frame; a logic 0 allows insertion from the TPOAC channel or a default value. Only port 1 control is valid in AU-4
mode.
0
0
TMUX_THSJ1INS2
Transmit J1 Insert (Control) for Port 2. Control bit, when set
to a logic 1, inserts the 64-byte sequence
TMUX_TJ1DINS2[64—1][7:0] (Table 141) into the outgoing
STS-3/STM-1 (AU-4) frame; a logic 0 allows insertion from the
TPOAC channel or a default value. Only port 1 control is valid
in AU-4 mode.
0
15:9
—
Reserved.
0x00
8
TMUX_THSPREIINH3 Transmit Path REI Inhibit for Port 3. Control bit, when set to
a logic 1, disables hardware insertion of path REI (B3 errors)
in the outgoing STS-3/STM-1 (AU-4) frame G1 byte; a logic 0
enables hardware insertion of path REI. Only port 1 control is
valid in AU-4 mode.
0
7
TMUX_TPOHTHRU3 Transmit High-speed Path Overhead Insertion from Lowspeed Input (Telecom Bus). Control bit, when set to a logic
1, causes all path overhead bytes for port 3, and H1, H2, and
H3, to be passed through from the low-speed telecom bus to
the high-speed output signal. Only port 1 control is valid in
AU-4 mode.
0
6
TMUX_THSN1INS3
Transmit N1 Insert (Control) for Port 3. Control bit, when
set to a logic 1, inserts the value in TMUX_TN1INS3[7:0]
(Table 114) into the outgoing N1 byte in the STS-3/STM-1
(AU-4) frame; a logic 0 allows insertion from the TPOAC channel or a default value. Only port 1 control is valid in
AU-4 mode.
0
5
TMUX_THSK3INS3
Transmit K3 Insert (Control) for Port 3. Control bit, when
set to a logic 1, inserts the value in TMUX_TK3INS3[7:0]
(Table 114) into the outgoing K3 byte in the STS-3/STM-1
(AU-4) frame; a logic 0 allows insertion from the TPOAC channel or a default value. Only port 1 control is valid in
AU-4 mode.
0
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TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
8 TMUX Registers (continued)
Table 108. TMUX_THS_POH[1—3]_CTL, Transmit High-Speed Control Parameters (R/W) (continued)
Address
Bit
Name
0x40038
4
TMUX_THSF3INS3
3
2
1
0
108
Function
Transmit F3 Insert (Control) for Port 3. Control bit, when
set to a logic 1, inserts the value in TMUX_TF3INS3[7:0]
(Table 114) into the outgoing F3 byte in the STS-3/STM-1
(AU-4) frame; a logic 0 allows insertion from the TPOAC
channel or a default value. Only port 1 control is valid in
AU-4 mode.
TMUX_THSF2INS3 Transmit F2 Insert (Control) for Port 3. Control bit, when
set to a logic 1, inserts the value in TMUX_TF2INS3[7:0]
(Table 114) into the outgoing F2 byte in the STS-3/STM-1
(AU-4) frame; a logic 0 allows insertion from the TPOAC
channel or a default value. Only port 1 control is valid in
AU-4 mode.
TMUX_THSRDIPINS3 Transmit Path RDI Insert (Control) for Port 3. Control bit,
when set to a logic 1, inserts the value in
TMUX_TRDIPINS3[2:0] (Table 114) into the outgoing
G1[3:1] bits in the STS-3/STM-1 (AU-4) frame; a logic 0
allows insertion from the TPOAC channel or a default value.
Only port 1 control is valid in AU-4 mode.
TMUX_THSC2INS3 Transmit C2 Insert (Control) for Port 3. Control bit, when
set to a logic 1, inserts the value in TMUX_TC2INS3[7:0]
(Table 114) into the outgoing C2 byte in the STS-3/STM-1
(AU-4) frame; a logic 0 allows insertion from the TPOAC
channel or a default value. Only port 1 control is valid in
AU-4 mode.
TMUX_THSJ1INS3 Transmit J1 Insert (Control) for Port 3. Control bit, when
set to a logic 1, inserts the 64-byte sequence
TMUX_TJ1DINS3[64—1][7:0] (Table 142) into the outgoing
STS-3/STM-1 (AU-4) frame; a logic 0 allows insertion from
the TPOAC channel or a default value. Only port 1 control is
valid in AU-4 mode.
Reset
Default
0
0
0
0
0
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
8 TMUX Registers (continued)
Table 109. TMUX_TLRDI_CTL, Transmit High-Speed Line RDI Control Parameters (R/W)
Address
0x4003A
Bit
15:7
6
5
4
3
2
1
0
Name
—
TMUX_TRHSSD_LRDIINH
Function
Reserved.
Transmit Receive High-speed Signal
Degrade L-RDI Inhibit. Control bit, when
set to a logic 1, causes the associated failure not to contribute to the automatic insertion of RDI-L; otherwise, the associated
alarm contributes to the generation of RDI-L.
TMUX_TRHSSF_LRDIINH
Transmit Receive High-speed Signal Fail
L-RDI Inhibit. Control bit, when set to a
logic 1, causes the associated failure not to
contribute to the automatic insertion of RDIL; otherwise, the associated alarm contributes to the generation of RDI-L.
TMUX_TRLAISMON_LRDIINH Transmit Receive Line AIS Line RDI
Inhibit. Same as above.
TMUX_TRHSLOF_LRDIINH Transmit Receive High-speed Loss-ofFrame Line RDI Inhibit. Same as above.
TMUX_TRHSOOF_LRDIINH Transmit Receive High-speed Out-ofFrame Line RDI Inhibit. Same as above.
TMUX_TRHSLOS_LRDIINH Transmit Receive High-speed Loss-ofSignal Line RDI Inhibit. Same as above.
TMUX_TRILOC_LRDIINH
Transmit Receive Input Loss-of-Clock
Line RDI Inhibit. Same as above.
Reset Default
0x000
0
0
0
0
0
0
0
Table 110. TMUX_TPRDI_CTL, Transmit High-Speed Path RDI Control Parameters (R/W)
Address
Bit
Reset
Default
0x4003B 15:8
—
Reserved.
0x000
7:5 TMUX_TRTIM_PRDIINH[3:1] Transmit Receive Trace Identifier Mismatch Path RDI
0
Inhibit. When a 1, causes the associated failure not to
contribute to the automatic insertion of RDI-P; otherwise, the associated alarm contributes to the generation
of RDI-P.
0
4
TMUX_TRUEQ_PRDIINH
Transmit Receive Unequipped Path RDI Inhibit.
When a 1, causes the associated failure not to contribute to the automatic insertion of RDI-P; otherwise, the
associated alarm contributes to the generation of RDI-P.
3
TMUX_TRPLM_PRDIINH
Transmit Receive Payload Label Mismatch Path RDI
0
Inhibit. When a 1, causes the associated failure not to
contribute to the automatic insertion of RDI-P; otherwise, the associated alarm contributes to the generation
of RDI-P.
2
TMUX_TRLOP_PRDIINH
Transmit Receive Loss-of-Pointer RDI Inhibit. When
0
a 1, causes the associated failure not to contribute to
the automatic insertion of RDI-P; otherwise, the associated alarm contributes to the generation of RDI-P.
1
TMUX_TRPAIS_PRDIINH Transmit Receive Path AIS RDI Inhibit. Same as
0
above.
0
TMUX_TEPRDI_MODE
Transmit Enhanced RDI Mode. When a 1, causes the
0
enhanced 3-bit path RDI value to be transmitted in
G1[3:1]; otherwise, a one-bit value (G1[3]) is sent.
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Name
Function
109
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
8 TMUX Registers (continued)
Table 111. TMUX_TZ0_INS_VAL, Transmit TOH and POH Insert Values (R/W)
Address
Bit
Name
Function
Reset
Default
0x4003C
15:8
TMUX_TZ03INS[7:0]
Transmit Z0-3 Data Insert Value. Register value is
inserted into the STS-3/STM-1 (AU-4) output Z0-3 byte
if TMUX_THSZ0INS (Table 107) is asserted.
0x00
7:0
TMUX_TZ02INS[7:0]
Transmit Z0-2 Data Insert Value. Register value is
inserted into the STS-3/STM-1 (AU-4) output Z0-2 byte
if TMUX_THSZ0INS is asserted.
0x00
Table 112. TMUX_TS1_F1_INS_VAL, Transmit TOH and POH Insert Values (R/W)
Address
Bit
Name
Function
Reset
Default
0x4003D
15:8
TMUX_TS1INS[7:0]
Transmit S1 Data Insert Value. Register value is
inserted into the STS-3/STM-1 (AU-4) output S1 byte if
TMUX_THSS1INS (Table 107) is asserted.
0x00
7:0
TMUX_TF1INS[7:0]
Transmit F1 Data Insert Value. Register value is
inserted into the STS-3/STM-1 (AU-4) output F1 byte if
TMUX_THSF1INS (Table 107) is asserted.
0x00
Table 113. TMUX_TAPS_INS_VAL, Transmit TOH and POH Insert Values (R/W)
Address
Bit
0x4003E
15:3
2:0
Name
Function
Reset
Default
TMUX_TAPSINS[12:0] Transmit APS Data Insert Value. Register value is
inserted into the STS-3/STM-1 (AU-4) output K1[7:0] and
K2[7:3] bits if TMUX_THSAPSINS (Table 107) is asserted.
TMUX_TK2INS[2:0]
Transmit K2 Data Insert Value. Register value is inserted
into the STS-3/STM-1 (AU-4) output K2[2:0] bits if
TMUX_THSK2INS (Table 107) is asserted.
0x00
000
Table 114. TMUX_TPOH[1—3]_INS_[A—C], Transmit TOH and POH Insert Values (R/W)
Address
Bit
Name
Function
0x4003F 15:11
—
Reserved.
10:8 TMUX_TRDIPINS1[2:0] Transmit Path RDI Data Insert Value for Port 1. Register
value is inserted into the STS-3/STM-1 (AU-4) output
G1[3:1] bits if TMUX_THSRDIPINS1 (Table 108) is
asserted, regardless of the value of TMUX_TEPRDI_MODE
(Table 110).
7:0
TMUX_TC2INS1[7:0] Transmit C2 Data Insert Value for Port 1. Register value is
inserted into the STM-1(AU-4) output C2 byte if
TMUX_THSC2INS1 (Table 108) is asserted.
0x40040 15:8
TMUX_TF3INS1[7:0] Transmit F3 Data Insert Value for Port 1. Register value is
inserted into the STM-1(AU-4) output F3 byte if
TMUX_THSF3INS1 (Table 108) is asserted.
0x40040 7:0
TMUX_TF2INS1[7:0] Transmit F2 Data Insert Value for Port 1. Register value is
inserted into the STM-1(AU-4) output F2 byte if
TMUX_THSF2INS1 (Table 108) is asserted.
110
Reset
Default
0x00
000
0x00
0x00
0x00
Agere Systems Inc.
Preliminary Data Sheet
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TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
8 TMUX Registers (continued)
Table 114. TMUX_TPOH[1—3]_INS_[A—C], Transmit TOH and POH Insert Values (R/W) (continued)
Address
0x40041
0x40042
0x40043
0x40044
0x40045
0x40046
0x40047
Bit
Reset
Default
15:8 TMUX_TN1INS1[7:0] Transmit N1 Data Insert Value for Port 1. Register value is
0x00
inserted into the STM-1(AU-4) output N1 byte if
TMUX_THSN1INS1 (Table 108) is asserted.
7:0
TMUX_TK3INS1[7:0] Transmit K3 Data Insert Value for Port 1. Register value is
0x00
inserted into the STM-1(AU-4) output K3 byte if
TMUX_THSK3INS1 (Table 108) is asserted.
15:11
—
Reserved.
0x00
10:8 TMUX_TRDIPINS2[2:0] Transmit Path RDI Data Insert Value for Port 2. Register
000
value is inserted into the STS-3/STM-1 (AU-4) output
G1[3:1] bits if TMUX_THSRDIPINS2 (Table 108) is
asserted, regardless of the value of
TMUX_TEPRDI_MODE.
7:0
TMUX_TC2INS2[7:0] Transmit C2 Data Insert Value for Port 2. Register value is
0x00
inserted into the STM-1(AU-4) output C2 byte if
TMUX_THSC2INS1 is asserted.
15:8
TMUX_TF3INS2[7:0] Transmit F3 Data Insert Value for Port 2. Register value is
0x00
inserted into the STM-1(AU-4) output F3 byte if
TMUX_THSF3INS1 is asserted.
7:0
TMUX_TF2INS2[7:0] Transmit F2 Data Insert Value for Port 2. Register value is
0x00
inserted into the STM-1(AU-4) output F2 byte if
TMUX_THSF2INS1 is asserted.
15:8 TMUX_TN1INS2[7:0] Transmit N1 Data Insert Value for Port 2. Register value is
0x00
inserted into the STM-1(AU-4) output N1 byte if
TMUX_THSN1INS1 (Table 108) is asserted.
0x00
7:0
TMUX_TK3INS2[7:0] Transmit K3 Data Insert Value for Port 2. Register value is
inserted into the STM-1(AU-4) output K3 byte if
TMUX_THSK3INS1 (Table 108) is asserted.
15:11
—
Reserved.
0x00
000
10:8 TMUX_TRDIPINS3[2:0] Transmit Path RDI Data Insert Value for Port 3. Register
value is inserted into the STS-3/STM-1 (AU-4) output
G1[3:1] bits if TMUX_THSRDIPINS3 (Table 108) is
asserted, regardless of the value of
TMUX_TEPRDI_MODE.
7:0
TMUX_TC2INS3[7:0] Transmit C2 Data Insert Value for Port 3. Register value is
0x00
inserted into the STM-1(AU-4) output C2 byte if
TMUX_THSC2INS1 (Table 108) is asserted.
15:8
TMUX_TF3INS3[7:0] Transmit F3 Data Insert Value for Port 3. Register value is
0x00
inserted into the STM-1(AU-4) output F3 byte if
TMUX_THSF3INS1 (Table 108) is asserted.
0x00
7:0
TMUX_TF2INS3[7:0] Transmit F2 Data Insert Value for Port 3. Register value is
inserted into the STM-1(AU-4) output F2 byte if
TMUX_THSF2INS1 (Table 108) is asserted.
0x00
15:8 TMUX_TN1INS3[7:0] Transmit N1 Data Insert Value for Port 3. Register value is
inserted into the STM-1(AU-4) output N1 byte if
TMUX_THSN1INS1 is asserted.
7:0
TMUX_TK3INS3[7:0] Transmit K3 Data Insert Value for Port 3. Register value is
0x00
inserted into the STM-1(AU-4) output K3 byte if
TMUX_THSK3INS1 is asserted.
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Name
Function
111
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
8 TMUX Registers (continued)
Table 115. TMUX_TBERINS_CTL, Transmit High-Speed Error Insertion Control Parameters (R/W)
Address
Bit
Name
0x40048
15:13
—
12
TMUX_TPSLREIINS
Transmit Protection Signal Line REI Insert. Control bit, when set to a logic 1, causes one line REI
error in the outgoing protection STS-3/STM-1 (AU-4)
signal when there is a rising edge observed on the
SMPR_BER_INSRT (Table 65) input signal.
0
11
TMUX_TPSB2EIINS
Transmit Protection Signal B2 Error Insert. Control bit, when set to a logic 1, causes one B2 error in
the outgoing protection STS-3/STM-1 (AU-4) signal
when there is a rising edge observed on the
SMPR_BER_INSRT (Table 65) input signal.
0
10:8
TMUX_TPREIINS[3:1]
Transmit Path REI Error Insert. Control bit, when
set to a logic 1, causes one path REI error in the outgoing STS-3/STM-1 (AU-4) signal when there is a
rising edge observed on the SMPR_BER_INSRT
(Table 65) input signal. Only port 1 control is valid in
AU-4 mode.
0
7:5
4
3:1
0
112
Function
Reset
Default
Reserved.
0x0
TMUX_THSB3ERRINS[3:1] Transmit High-speed B3 Error Insert. Control bit,
when set to a logic 1, causes the output B3 byte in
the outgoing STS-3/STM-1 (AU-4) signal to be
inverted when there is a rising edge observed on the
SMPR_BER_INSRT (Table 65) input signal. Only
port 1 control is valid in AU-4 mode.
TMUX_TLREIINS
Transmit High-speed Line REI Insert. Control bit,
when set to a logic 1, causes one line REI error in
the outgoing STS-3/STM-1 (AU-4) signal when there
is a rising edge observed on the
SMPR_BER_INSRT (Table 65) input signal.
TMUX_THSB2ERRINS[3:1] Transmit High-speed B2 Error Insert. Control bit,
when set to a logic 1, causes the output B2 bytes in
the outgoing STS-3/STM-1 (AU-4) signal to be
inverted when there is a rising edge observed on the
SMPR_BER_INSRT (Table 65) input signal.
TMUX_THSB1ERRINS
Transmit High-speed B1 Error Insert. Control bit,
when set to a logic 1, causes the output B1 byte in
the outgoing STS-3/STM-1 (AU-4) signal to be
inverted when there is a rising edge observed on the
SMPR_BER_INSRT (Table 65) input signal.
0
0
000
0
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Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
8 TMUX Registers (continued)
Table 116. TMUX_THS_ERR_CTL, Transmit High-Speed Error Insertion Control Parameters (R/W)
Address
Bit
Name
0x40049 15:10
—
9
TMUX_TAPSBABINS
Function
Reserved.
Reset
Default
0x00
Transmit APS Babble Insert. When 1, causes an
inconsistent APS byte (K1[7:0], K2[7:3]) to be inserted
into the outgoing STS-3/STM-1 (AU-4) frame.
0
8:6
TMUX_TH1H2INVEN[3:1] Transmit H1 H2 Corrupt Enable. When 1, cause the
output H1 and H2 bytes of the STS-3/STM-1 (AU-4) signal to be corrupted on a per STS-1 basis. In the AU-4
mode, only control bit 1 is used.
000
5
TMUX_TH1H2INVORNDF Transmit H1 H2 Corrupt or NDF. When 0, causes an
invalid pointer to be inserted into the output H1 and H2
bytes; otherwise, a continuous NDF condition (1001) is
sent.
0
4:0
TMUX_TA2ERRINS[4:0]
Transmit Frame Error Insert Value. These bits specify
the number of consecutive frames to be inserted with a
frame error is inserted in the outgoing A2 byte. This
number of errored frames is sent each time a rising edge
is observed on the SMPR_BER_INSRT (Table 65) input
signal.
0x0
Table 117. TMUX_TOAC_CTL, Receive/Transmit TOAC/POAC Control Parameters (R/W )
Address
Bit
0x4004A
15
14
13
12:10
9
Agere Systems Inc.
Name
Function
TMUX_RTOAC_D412MODE Receive TOAC DCC4 to DCC12 Only Mode. When
1, causes the RTOAC data signal to carry only a parity byte followed by DCC4 to DCC12 bytes. The clock
rate is 640 kHz. If this control bit is a logic 0 and
TMUX_RTOAC_D13MODE is a logic zero, then the
receive TOAC channel is in full access mode.
TMUX_RTOAC_D13MODE Receive TOAC DCC1 to DCC3 Only Mode. When
1, causes the RTOAC data signal to carry only a parity byte followed by DCC1 to DCC3 bytes. The clock
rate is 260 kHz. If this control bit is a logic 0 and
TMUX_RTOAC_D412MODE is a logic zero, then the
receive TOAC channel is in full access mode.
TMUX_RTOAC_OEPINS
Receive TOAC Odd or Even Parity Insert. When 1,
forces receive the output TOAC parity bit to be even;
otherwise, the parity is odd.
—
Reserved.
TMUX_TTOAC_D412MODE Transmit TOAC DCC4 to DCC12 Only Mode.
When 1, causes DCC4 to DCC12 in the outgoing
frame to be inserted from the TTOAC channel. The
TTOAC clock rate is 640 kHz. If this control bit is a
logic 0 and TMUX_TTOAC_D13MODE is a logic
zero, then the transmit TOAC channel is in full
access mode.
Reset
Default
0
0
0
000
0
113
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
8 TMUX Registers (continued)
Table 117. TMUX_TOAC_CTL, Receive/Transmit TOAC/POAC Control Parameters (R/W) (continued)
Address
Bit
Name
Function
0x4004A
8
TMUX_TTOAC_D13MODE
7
TMUX_TTOAC_AVAIL
6
TMUX_TTOAC_S1
5
TMUX_TTOAC_F1
4
TMUX_TTOAC_E2
3
TMUX_TTOAC_E1
2
TMUX_TTOAC_D4TO12
1
TMUX_TTOAC_D1TO3
0
TMUX_TTOAC_OEPMON
Transmit TOAC DCC1 to DCC3 Only Mode.
When 1, causes DCC1 to DCC3 in the outgoing
frame to be inserted from the TTOAC channel. The
TTOAC clock rate is 260 kHz. If this control bit is a
logic 0 and TMUX_TTOAC_D13MODE is a logic
zero, then the transmit TOAC channel is in full
access mode.
Transmit TOAC Available Byte Control. When 1,
causes the incoming TOAC values for undefined
bytes (bold-faced bytes in Table 523) to be inserted
into the outgoing STS-3/STM-1 frame. Otherwise,
their values depend on SMPR_OH_DEFLT
(Table 67).
Transmit TOAC S1 Byte Control. When 1, causes
the incoming TOAC S1 value to be inserted into the
S1 byte of the outgoing STS-3/STM-1 frame if the
TMUX_THSS1INS (Table 107) control bit is deasserted. If the S1 is not inserted from register control
or from the transmit TOAC channel, then its value
depends on SMPR_OH_DEFLT.
Transmit TOAC F1 Byte Control. When 1, causes
the incoming TOAC F1 value to be inserted into the
F1 byte of the outgoing STS-3/STM-1 frame if the
TMUX_THSF1INS (Table 107) control bit is desasserted. If the F1 is not inserted from register control
or from the transmit TOAC channel, then its value
depends on SMPR_OH_DEFLT.
Transmit TOAC E1 Byte Control. When 1, causes
the incoming TOAC E1 value to be inserted into the
E1 byte of the outgoing STS-3/STM-1 frame. Otherwise, the E1 value depends on SMPR_OH_DEFLT.
Transmit TOAC E1 Byte Control. When 1, causes
the incoming TOAC E1 value to be inserted into the
E1 byte of the outgoing STS-3/STM-1 frame. Otherwise, the E1 value depends on SMPR_OH_DEFLT.
Transmit TOAC D4 to D12 Byte Control. When 1,
causes the TTOAC values to be inserted into the D4
to D12 bytes of the outgoing frame. If this control bit
is a logic zero, then the outgoing D4 to D12 values
depend on SMPR_OH_DEFLT.
Transmit TOAC D1 to D3 Byte Control. When 1,
causes the TTOAC values to be inserted into the D1
to D3 bytes of the outgoing frame. If this control bit is
a logic zero, then the outgoing D1 to D3 values
depend on SMPR_OH_DEFLT.
Transmit TOAC Odd or Even Parity Monitor. When
1, forces the input TOAC parity checker to check for
odd parity; otherwise, even parity is checked on the
transmit TOAC channel.
114
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Reset
Default
0
0
0
0
0
0
0
0
0
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
8 TMUX Registers (continued)
Table 118. TMUX_RPOAC_CTL, Receive/Transmit TOAC/POAC Control Parameters (R/W)
Address
Bit
Name
Function
0x4004B 15:14 TMUX_RPOAC_SEL[1:0] Receive POAC STS-1 Port Selection. Designates which
STS-1 inserts its path overhead bytes onto the receive
POAC channel. Values of 00 or 01 designate STS-1 #1, 10
designates STS-1 #2, 11 designates STS-1 #3.
13
TMUX_RPOAC_OEPINS Receive POAC Odd or Even Parity Insert. When 1,
forces receive the output POAC parity bit to be even; otherwise, the parity is odd.
12:10
9:8
—
Reserved.
TMUX_TPOAC_SEL[1:0] Transmit POAC STS-1 Port Selection. Designates which
STS-1 obtains path overhead bytes from the transmit
POAC channel. Values of 00 or 01 designate STS-1 #1, 10
designates STS-1 #2, 11 designates STS-1 #3.
7
—
6
Reset
Default
00
0
000
00
Reserved.
0
TMUX_TPOAC_N1
Transmit POAC N1 Byte Control. When 1, causes the
incoming POAC N1 value to be inserted into the N1 byte of
the selected TPOAC STS-1 if the corresponding
TMUX_THSN1INS (Table 108) control bit is desasserted.
If the N1 is not inserted from register control or from the
transmit POAC channel, then its value depends on
SMPR_OH_DEFLT (Table 67).
0
5
TMUX_TPOAC_K3
Transmit POAC K3 Byte Control. When 1, causes the
incoming POAC K3 value to be inserted into the K3 byte of
the selected TPOAC STS-1 if the corresponding
TMUX_THSK3INS (Table 108) control bit is desasserted.
If the K3 is not inserted from register control or from the
transmit POAC channel, then its value depends on
SMPR_OH_DEFLT.
0
4
TMUX_TPOAC_F3
Transmit POAC F3 Byte Control. When 1, causes the
incoming POAC F3 value to be inserted into the F3 byte of
the selected TPOAC STS-1 if the corresponding
TMUX_THSF3INS (Table 108) control bit is desasserted. If
the F3 is not inserted from register control or from the
transmit POAC channel, then its value depends on
SMPR_OH_DEFLT.
0
3
TMUX_TPOAC_F2
Transmit POAC F2 Byte Control. When 1, causes the
incoming POAC F2 value to be inserted into the F2 byte of
the selected TPOAC STS-1 if the corresponding
TMUX_THSF2INS (Table 108) control bit is desasserted. If
the F2 is not inserted from register control or from the
transmit POAC channel, then its value depends on
SMPR_OH_DEFLT (Table 67).
0
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TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
8 TMUX Registers (continued)
Table 118. TMUX_RPOAC_CTL, Receive/Transmit TOAC/POAC Control Parameters (R/W) (continued)
Address
Bit
Name
Function
Reset
Default
0x4004B
2
TMUX_TPOAC_C2
Transmit POAC C2 Byte Control. When 1, causes
the incoming POAC C2 value to be inserted into the C2
byte of the selected TPOAC STS-1 if the corresponding TMUX_THSC2INS (Table 108) control bit is desasserted. If the C2 is not inserted from register control or
from the transmit POAC channel, then its value
depends on SMPR_OH_DEFLT.
0
1
TMUX_TPOAC_J1
Transmit POAC J1 Byte Control. Control bit, when
set to a logic 1, causes the incoming POAC J1 value to
be inserted into the J1 byte of the selected TPOAC
STS-1 if the corresponding TMUX_THSJ1INS
(Table 108) control bit is desasserted. If the J1 is not
inserted from register control or from the transmit
POAC channel, then its value depends on
SMPR_OH_DEFLT.
0
0
TMUX_TPOAC_OEPMON Transmit TOAC Odd or Even Parity Monitor. Control
bit, when set to a logic 1, forces the input TOAC parity
checker to check for odd parity; otherwise, even parity
is checked on the transmit TOAC channel.
0
Table 119. TMUX_TFRAMEOFFSET, Transmit High-Speed Offset Control Parameters (R/W)
Address
Bit
Name
Function
Reset
Default
0x4004D
15:13
TMUX_TLBITCNT[2:0]
Transmit Load Bit Count. Allows the output
STS-3/STM-1 (AU-4) frame to have any relationship to
the input frame sync pulse (THSSJ0J1V1I).
000
12:11
TMUX_TLSTSCNT[1:0]
Transmit Load STS-1 Count. Same as above.
00
10:4
TMUX_TLCOLCNT[6:0]
Transmit Load Column Count. Same as above.
3:0
TMUX_TLROWCNT[3:0]
Transmit Load Row Count. Same as above.
0000000
0000
)
Table 120. TMUX_SD_CTL[1—6], B1/B2 Signal Degrade Set/Clear Control Registers (R/W)
Address
Bit
Name
0x4004E
0x4004F
0x4004F
15:0
2:0
14:7
TMUX_SDNSSET[18:3]
TMUX_SDNSSET[2:0]
0x40050
0x40051
0x40052
116
Function
Reset
Default
0x00000
Signal Degrade Ns Set. Number of frames in a
monitoring block for signal degrade (SD).
0x00
TMUX_SDMSET[7:0]
Signal Degrade M Set. Threshold of the number of bad
monitoring blocks in an observation interval. If the
number of bad blocks is above this threshold, then SD is
set.
6:3
TMUX_SDLSET[3:0]
Signal Degrade L Set. Error threshold for determining
0x0
if a monitoring block is bad.
15:0
TMUX_SDBSET[15:0]
Signal Degrade B Set. Number of monitoring blocks.
0x0000
15:0 TMUX_SDNSCLEAR[18:3] Signal Degrade Ns Clear. Number of frames in a
0x00000
2:0 TMUX_SDNSCLEAR[2:0] monitoring block for SD.
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Preliminary Data Sheet
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TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
8 TMUX Registers (continued)
Table 120. TMUX_SD_CTL[1—6], B1/B2 Signal Degrade Set/Clear Control Registers (R/W) (continued)
Address
Bit
Name
Function
0x40052
0x40052
14:7
TMUX_SDMCLEAR[7:0]
6:3
TMUX_SDLCLEAR[3:0]
15:0
TMUX_SDBCLEAR[15:0]
Signal Degrade M Clear. Threshold of the number of
bad monitoring blocks in an observation interval. If the
number of bad blocks is below this threshold, then SD is
cleared.
Signal Degrade L Clear. Error threshold for
determining if a monitoring block is bad.
Signal Degrade B Clear. Number of monitoring blocks.
0x40053
Reset
Default
0x00
0x0
0x0000
Table 121. TMUX_SF_CTL[1—6], B1/B2 Signal Fail Set/Clear Control Registers (R/W)
Address
Bit
Name
0x40054
0x40055
0x40055
15:0
2:0
14:7
TMUX_SFNSSET[18:3]
TMUX_SFNSSET[2:0]
0x40055
6:3
0x40056
0x40057
0x40058
0x40058
15:0
15:0
2:0
14:7
0x40058
6:3
0x40059
15:0
Function
Reset
Default
0x0000
0
0x00
Signal Fail Ns Set. Number of frames in a monitoring
block for signal fail (SF).
TMUX_SFMSET[7:0]
Signal Fail M Set. Threshold of the number of bad
monitoring blocks in an observation interval. If the
number of bad blocks is above this threshold, then SF is
set.
TMUX_SFLSET[3:0]
Signal Fail L Set. Error threshold for determining if a
0x0
monitoring block is bad.
TMUX_SFBSET[15:0]
Signal Fail B Set. Number of monitoring blocks.
0x0000
TMUX_SFNSCLEAR[18:3] Signal Fail Ns Clear. Number of frames in a monitoring 0x0000
TMUX_SFNSCLEAR[2:0] block for SF.
0
TMUX_SFMCLEAR[7:0] Signal Fail M Clear. Threshold of the number of bad
0x00
monitoring blocks in an observation interval. If the
number of bad blocks is below this threshold, then SF is
cleared.
TMUX_SFLCLEAR[3:0] Signal Fail L Clear. Error threshold for determining if a
0x0
monitoring block is bad.
TMUX_SFBCLEAR[15:0] Signal Fail B Clear. Number of monitoring blocks.
0x0000
Table 122. TMUX_B3SD_CTL[1—6], B3 Signal Degrade Set/Clear Control Registers (R/W)
Address
Bit
Name
0x4005A
0x4005B
0x4005B
15:0
2:0
14:7
TMUX_B3SDNSSET[18:3]
TMUX_B3SDNSSET[2:0]
0x4005B
0x4005C
0x4005D
0x4005E
Function
B3 Signal Degrade Ns Set. Number of frames in a
monitoring block for signal degrade (SD).
TMUX_B3SDMSET[7:0]
B3 Signal Degrade M Set. Threshold of the number
of bad monitoring blocks in an observation interval. If
the number of bad blocks is above this threshold,
then SD is set.
6:3
TMUX_B3SDLSET[3:0]
B3 Signal Degrade L Set. Error threshold for
determining if a monitoring block is bad.
15:0
TMUX_B3SDBSET[15:0]
B3 Signal Degrade B Set. Number of monitoring
blocks.
15:0 TMUX_B3SDNSCLEAR[18:3] B3 Signal Degrade Ns Clear. Number of frames in a
2:0 TMUX_B3SDNSCLEAR[2:0] monitoring block for SD.
Agere Systems Inc.
Reset
Default
0x0000
0
0x00
0x0
0x0000
0x0000
0
117
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
8 TMUX Registers (continued)
Table 122. TMUX_B3SD_CTL[1—6], B3 Signal Degrade Set/Clear Control Registers (R/W) (continued)
Address
Bit
Name
0x4005E
14:7
TMUX_B3SDMCLEAR[7:0]
6:3
TMUX_B3SDLCLEAR[3:0]
15:0
TMUX_B3SDBCLEAR[15:0]
0x4005F
Function
B3 Signal Degrade M Clear. Threshold of the
number of bad monitoring blocks in an observation
interval. If the number of bad blocks is below this
threshold, then SD is cleared.
B3 Signal Degrade L Clear. Error threshold for
determining if a monitoring block is bad.
B3 Signal Degrade B Clear. Number of monitoring
blocks.
Reset
Default
0x00
0x0
0x0000
Table 123. TMUX_B3SF_CTL[1—6], B3 Signal Fail Set/Clear Control Registers (R/W)
Address
Bit
Name
Function
Reset
Default
0x40060
0x40061
15:0
2:0
TMUX_B3SFNSSET[18:3]
TMUX_B3SFNSSET[2:0]
0x40061
14:7
TMUX_B3SFMSET[7:0]
B3 Signal Fail M Set. Threshold of the number of
bad monitoring blocks in an observation interval. If
the number of bad blocks is above this threshold,
then SF is set.
0x00
0x40061
6:3
TMUX_B3SFLSET[3:0]
B3 Signal Fail L Set. Error threshold for
determining if a monitoring block is bad.
0x0
0x40062
15:0
TMUX_B3SFBSET[15:0]
0x40063
0x40064
15:0
2:0
0x40064
14:7
TMUX_B3SFMCLEAR[7:0]
B3 Signal Fail M Clear. Threshold of the number of
bad monitoring blocks in an observation interval. If
the number of bad blocks is below this threshold,
then SF is cleared.
0x00
0x40064
6:3
TMUX_B3SFLCLEAR[3:0]
B3 Signal Fail L Clear. Error threshold for
determining if a monitoring block is bad.
0x0
0x40065
15:0
B3 Signal Fail Ns Set. Number of frames in a
monitoring block for SF.
B3 Signal Fail B Set. Number of monitoring blocks.
TMUX_B3SFNSCLEAR[18:3] B3 Signal Fail Ns Clear. Number of frames in a
TMUX_B3SFNSCLEAR[2:0] monitoring block for SF.
TMUX_B3SFBCLEAR[15:0] B3 Signal Fail B Clear. Number of monitoring
blocks.
0x0000
0
0x0000
0x0000
0
0x0000
Table 124. TMUX_B1ECNT, Receive B1 Error Counts (RO)
Address
Bit
0x40066
15:0
118
Name
Function
Reset
Default
TMUX_B1ECNT[15:0] Receive High-speed B1 Error Count. Counts the number 0x0000
of B1 errors in the received STS-3/STM-1 (AU-4) frame.
This counter can either count actual BIP errors or block
errors; see TMUX_BITBLKB1 (Table 95). This counter
holds at its maximum value or rolls over depending on the
value of SMPR_SAT_ROLLOVER (Table 67) and transfers
its internal count to a holding register when
SMPR_PMRESET (Table 65) transitions from a logic 0 to 1.
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
8 TMUX Registers (continued)
Table 125. TMUX_B2ECNT_17_16 and TMUX_B2ECNT_15_0, Receive B2 Error Counts (RO)
Address
Bit
Name
0x40067
15:2
—
0x40067—
0x40068
1:0
15:0
Function
Reserved.
Reset
Default
0x000
TMUX_B2ECNT[17:16]— Receive High-speed B2 Error Count. Counts the
TMUX_B2ECNT[15:0] number of B2 errors in the received STS-3/STM-1
(AU-4) frame. This counter can either count actual BIP
errors or block errors; see TMUX_BITBLKB2
(Table 95). This counter holds at its maximum value or
rolls over depending on the value of
SMPR_SAT_ROLLOVER and transfers its internal
count to a holding register when SMPR_PMRESET
transitions from a logic 0 to 1.
0x0000
0
Table 126. TMUX_B3ECNT[1—3], Receive B3 Error Counts (RO)
Address
Bit
0x40069
15:0
0x4006A
15:0
0x4006B
15:0
Agere Systems Inc.
Name
Function
Reset
Default
0x0000
TMUX_B3ECNT1[15:0] Receive High-speed B3 Error Count for Port 1. Counts
the number of B3 errors in the receive STS-3/STM-1
(AU-4) frame for port 1. Only counter value 1 is valid in
AU-4 mode. This counter can either count actual BIP errors
or block errors; see TMUX_BITBLKB3 (Table 95). This
counter holds at its maximum value or rolls over depending
on the value of SMPR_SAT_ROLLOVER (Table 67) and
transfers its internal count to a holding register when
SMPR_PMRESET (Table 65) transitions from a logic 0 to 1.
0x0000
TMUX_B3ECNT2[15:0] Receive High-speed B3 Error Count for Port 2. Counts
the number of B3 errors in the receive STS-3/STM-1
(AU-4) frame for port 2. Only counter value 1 is valid in
AU-4 mode. This counter can either count actual BIP errors
or block errors; see TMUX_BITBLKB3 (Table 95). This
counter holds at its maximum value or rolls over depending
on the value of SMPR_SAT_ROLLOVER and transfers its
internal count to a holding register when SMPR_PMRESET
transitions from a logic 0 to 1.
0x0000
TMUX_B3ECNT3[15:0] Receive High-speed B3 Error Count for Port 3. Counts
the number of B3 errors in the receive STS-3/STM-1
(AU-4) frame for port 3. Only counter value 1 is valid in
AU-4 mode. This counter can either count actual BIP errors
or block errors; see TMUX_BITBLKB3 (Table 95). This
counter holds at its maximum value or rolls over depending
on the value of SMPR_SAT_ROLLOVER and transfers its
internal count to a holding register when SMPR_PMRESET
transitions from a logic 0 to 1.
119
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
8 TMUX Registers (continued)
Table 127. TMUX_M1ECNT_17_16 and TMUX_M1ECNT_15_0, Receive M1 Error Counts (RO)
Address
Bit
Name
0x4006C
15:2
—
0x4006C—
0x4006D
1:0
15:0
Function
Reset
Default
Reserved.
0x000
TMUX_M1ECNT[17:16]— Receive Line REI Count. Counts the number of
TMUX_M1ECNT[15:0]
errors received in the M1 byte of the receive
STS-3/STM-1 (AU-4) frame. This counter can either
count actual errors or block errors; see
TMUX_BITBLKM1 (Table 95). This counter holds at
its maximum value or rolls over depending on the
value of SMPR_SAT_ROLLOVER and transfers its
internal count to a holding register when
SMPR_PMRESET transitions from a logic 0 to 1.
0x00000
Table 128. TMUX_G1ECNT[1—3], Receive G1 Error Counts (RO)
Address
Bit
Name
Function
Reset
Default
0x4006E
15:0 TMUX_G1ECNT1[15:0] Receive Path REI Count for Port 1. Counts the number of 0x0000
B3 errors received in the G1[7:4] bits of port 1 in the
received STS-3/STM-1 (AU-4) frame. This counter can
either count actual errors or block errors; see
TMUX_BITBLKB3 (Table 95). This counter holds at its maximum value or rolls over depending on the value of
SMPR_SAT_ROLLOVER (Table 67) and transfers its internal count to a holding register when SMPR_PMRESET
(Table 65) transitions from a logic 0 to 1.
0x4006F 15:0 TMUX_G1ECNT2[15:0] Receive Path REI Count for Port 2. Counts the number of 0x0000
B3 errors received in the G1[7:4] bits of port 2 in the
received STS-3/STM-1 (AU-4) frame. This counter can
either count actual errors or block errors; see
TMUX_BITBLKB3 (Table 95). This counter holds at its maximum value or rolls over depending on the value of
SMPR_SAT_ROLLOVER and transfers its internal count to
a holding register when SMPR_PMRESET transitions from
a logic 0 to 1.
0x40070
120
15:0 TMUX_G1ECNT3[15:0] Receive Path REI Count for Port 3. Counts the number of 0x0000
B3 errors received in the G1[7:4] bits of port 3 in the
received STS-3/STM-1 (AU-4) frame. This counter can
either count actual errors or block errors; see
TMUX_BITBLKB3 (Table 95). This counter holds at its maximum value or rolls over depending on the value of
SMPR_SAT_ROLLOVER and transfers its internal count to
a holding register when SMPR_PMRESET transitions from
a logic 0 to 1.
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
8 TMUX Registers (continued)
Table 129. TMUX_RPTR_INCCNT[1—3], Receive Pointer Increment Count (RO)
Address
Bit
Name
0x40074—
0x40076
15:11
—
0x40074—
0x40076
10:0
Function
Reserved.
Reset
Default
0x000
TMUX_RPTR_INC1[10:0]— Receive Pointer Increment Count. Counts the
TMUX_RPTR_INC3[10:0] number of increments in the incoming pointer values. This counter holds at its maximum value or
rolls over depending on the value of
SMPR_SAT_ROLLOVER (Table 67) and transfers
its internal count to a holding register when
SMPR_PMRESET (Table 65) transitions from a
logic 0 to 1.
0x000
Table 130. TMUX_RPTR_DECCNT[1—3], Receive Pointer Decrement Count (RO)
Address
Bit
0x40077— 15:11
0x40079
0x40077—
0x40079
10:0
Name
—
Function
Reserved.
Reset
Default
0x000
TMUX_RPTR_DEC1[10:0]— Receive Pointer Decrement Count. Counts the
TMUX_RPTR_DEC3[10:0] number of decrements in the incoming pointer values. This counter holds at its maximum value or rolls
over depending on the value of
SMPR_SAT_ROLLOVER and transfers its internal
count to a holding register when SMPR_PMRESET
transitions from a logic 0 to 1.
0x000
Table 131. TMUX_RJ0EXPECTED[1—8], Expected J0 Byte Sequence (R/W)
Address
Bit
0x400A0— 15:0
0x400A7
Name
Function
TMUX_EXPJ0DMON[16—1][7:0] Expected Receive J0 Value. Registers contain either the programmed expected J0 16byte sequence or the previously captured J0
sequence, depending on the J0 mode.
Reset
Default
0x0000
Table 132. TMUX_RJ0CAPTURED[1—8], Captured J0 Receive Value (RO)
Address
Bit
Name
Function
Reset
Default
0x400A8— 15:0 TMUX_J0DMON[16—1][7:0] Received J0 Value. Registers capture a 16-byte
0x0000
0x400AF
sequence from the J0 byte of the receive input signal.
Table 133. TMUX_TJ0VALUE[1—8], J0 Byte Transmit Insert (R/W)
Address
Bit
Name
Function
0x400B0— 15:0 TMUX_TJ0DINS[16—1][7:0] Transmit J0 Data Insert. Registers allow a 16-byte
0x400B7
sequence to be inserted into the J0 byte of the
STS-3/STM-1(AU-4) output signal.
Agere Systems Inc.
Reset
Default
0x0000
121
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
8 TMUX Registers (continued)
Table 134. TMUX_RJ1EXPECTED1_[1—32], Expected J1 Byte Value for Port 1 (R/W)
Address
Bit
0x400E0—
0x400FF
15:0
Name
Function
TMUX_EXPJ1DMON1[64—1][7:0] Expected Receive J1 Value for Port 1.
Registers contain either the programmed
expected J1 16-byte/64-byte sequence or the
previously captured J1 sequence, depending
on the J1 mode.
Reset
Default
0x0000
Table 135. TMUX_RJ1EXPECTED2_[1—32], Expected J1 Byte Value for Port 2 (R/W)
Address
Bit
0x40100— 15:0
0x4011F
Name
TMUX_EXPJ1DMON2[64—1][7:0]
Function
Reset
Default
Expected Receive J1 Value for Port 2. Reg- 0x0000
isters contain either the programmed
expected J1 16-byte/64-byte sequence or the
previously captured J1 sequence, depending
on the J1 mode.
Table 136. TMUX_RJ1EXPECTED3_[1—32], Expected J1 Byte Value for Port 3 (R/W)
Address
Bit
Name
Function
Reset
Default
0x40120— 15:0 TMUX_EXPJ1DMON3[64—1][7:0] Expected Receive J1 Value for Port 3. Regis- 0x0000
0x4013F
ters contain either the programmed expected
J1 16-byte/64-byte sequence or the previously
captured J1 sequence, depending on the J1
mode.
Table 137. TMUX_RJ1CAPTURED1_[1—32], Captured J1 Value for STS #1 (RO)
Address
Bit
0x40140— 15:0
0x4015F
Name
Function
TMUX_J1DMON1[64—1][7:0] Receive J1 Monitor Data for Port 1. Registers
capture a 16-byte/64-byte sequence from the port
1, J1 byte of the STS-3/STM-1 (AU-4) input signal.
Only port 1 information is valid in AU-4 mode.
Reset
Default
0x0000
Table 138. TMUX_RJ1CAPTURED2_[1—32], Captured J1 Value for STS #2 (RO)
Address
Bit
0x40160— 15:0
0x4017F
122
Name
Function
TMUX_J1DMON2[64—1][7:0] Receive J1 Monitor Data for Port 2. Registers
capture a 64-byte sequence from the port 2, J1 byte
of the STS-3/STM-1 (AU-4) input signal. Only port 1
information is valid in AU-4 mode.
Reset
Default
0x0000
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
8 TMUX Registers (continued)
Table 139. TMUX_RJ1CAPTURED3_[1—32], Captured J1 Value for STS #3 (RO)
Address
Bit
0x40180— 15:0
0x4019F
Name
Function
TMUX_J1DMON3[64—1][7:0]
Receive J1 Monitor Data for Port 3. Registers
capture a 64-byte sequence from the port 3 J1
byte of the STS-3/STM-1 (AU-4) input signal.
Only port 1 information is valid in AU-4 mode.
Reset
Default
0x0000
Table 140. TMUX_TJ1VALUE_1[1—32], J1 Byte Transmit Insert for STS #1 (R/W)
Address
0x401A0—
0x401BF
Bit
Name
Function
Reset
Default
15:0 TMUX_TJ1DINS[64—1][7:0] Transmit J1 Data Insert for Port 1. Registers allow 0x0000
a 64-byte sequence to be inserted into the port 1, J1
byte of the STS-3/STM-1(AU-4) output signal. Only
port 1 information is valid in AU-4 mode.
Table 141. TMUX_TJ1VALUE_2[1—32], J1 Byte Transmit Insert for STS #2 (R/W)
Address
0x401C0—
0x401DF
Bit
Name
Function
15:0 TMUX_TJ1DINS2[64—1][7:0] Transmit J1 Data Insert for Port 2. Registers
allow a 64-byte sequence to be inserted into the
port 2, J1 byte of the STS-3/STM-1(AU-4) output
signal. Only port 1 information is valid in AU-4
mode.
Reset
Default
0x0000
Table 142. TMUX_TJ1VALUE_3[1—32], J1 Byte Transmit Insert for STS #3 (R/W)
Address
Bit
0x401E0— 15:0
0x401FF
Agere Systems Inc.
Name
Function
Reset
Default
TMUX_TJ1DINS3[64—1][7:0] Transmit J1 Data Insert for Port 3. Registers allow 0x0000
a 64-byte sequence to be inserted into the port 2,
J1 byte of the STS-3/STM-1(AU-4) output signal.
Only port 1 information is valid in AU-4 mode.
123
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
8 TMUX Registers (continued)
8.2 TMUX Register Map
Table 143. TMUX Register Map
Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.
Addr.
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TMUX_SD
CLEAR
TMUX_SD
SET
ID and Version—RO
0x40000
TMUX_ID_
R
TMUX_VERSION[2:0]
TMUX_TMUX_ID[7:0] = 0X04
0x40002
TMUX_ON
ESHOT
0x40003
TMUX_RC
V_TX_MO
DE
0x40004
TMUX_TX
_DLT
0x40005
TMUX_
RPS_
DLT
0x40006
TMUX_RH
S_DLT
TMUX_RS TMUX_RS
1BABE
1MOND
TMUX_RLRDI
MOND
TMUX_RLAI
SMOND
TMUX_RK2
MOND
TMUX_RAP
SBABE
TMUX_RAP
SMOND
TMUX_RF1
MOND
0x40007
TMUX_RP TMUX_RS TMUX_RS TMUX_RU
OH1_DLT
FB3D1
DB3D1
NEQPD1
TMUX_RPLM
PD1
TMUX_RN1
MOND1
TMUX_RK3
MOND1
TMUX_RF3
MOND1
TMUX_RF2
MOND1
0x40008
TMUX_RP TMUX_RS TMUX_RS TMUX_RU
OH2_
FB3D2
DB3D2
NEQPD2
DLT
TMUX_RPLM
PD2
TMUX_RN1
MOND2
TMUX_RK3
MOND2
TMUX_RF3
MOND2
0x40009
TMUX_RP TMUX_RS TMUX_RS TMUX_RU
OH3_DLT
FB3D3
DB3D3
NEQPD3
TMUX_RPLM
PD3
TMUX_RN1
MOND3
TMUX_RK3
MOND3
TMUX_RF3
MOND3
One-Shot (0 to 1 transition Control Bit Parameters—R/W
TMUX_B3S TMUX_B3S TMUX_B3S TMUX_B3S TMUX_SFC TMUX_SFS
FCLEAR
FSET
DCLEAR
ET
DSET
LEAR
Receive/Transmit Mode—R/W
TMUX_STS
1MODE
Delta and Event Parameters—COR/COW
TMUX_TLS
PARE3
TMUX_TLS
PARE2
TMUX_TLS
PARE1
TMUX_TP
OAC_PE
TMUX_TTO TMUX_THS TMUX_THS
AC_PE
ILOFD
ILOCD
TMUX_RP
SLOFD
TMUX_RP
SOOFD
TMUX_RP
SILOCD
TMUX_RP
SB2E
TMUX_RP
SLREIE
TMUX_RTI
MSD
TMUX_RH
SSFD
TMUX_RH
SSDD
TMUX_RH
SLOSD
TMUX_RH
SLOFD
TMUX_RH
SOOFD
TMUX_RH
SILOCD
TMUX_RR
DIPD1
TMUX_RC2
MOND1
TMUX_RTI
MPD1
TMUX_RN
DFE1
TMUX_RD
ECE1
TMUX_RIN TMUX_RPA
CE1
ISD1
TMUX_RL
OPD1
TMUX_RF2
MOND2
TMUX_RR
DIPD2
TMUX_RC2
MOND2
TMUX_RTI
MPD2
TMUX_RN
DFE2
TMUX_RD
ECE2
TMUX_RIN TMUX_RPA
CE2
ISD2
TMUX_RL
OPD2
TMUX_RF2
MOND3
TMUX_RR
DIPD3
TMUX_RC2
MOND3
TMUX_RTI
MPD3
TMUX_RN
DFE3
TMUX_RD
ECE3
TMUX_RIN TMUX_RPA
CE3
ISD3
TMUX_RL
OPD3
TMUX_TLS
PARM3
TMUX_TLS
PARM2
TMUX_TLS
PARM1
TMUX_TP
OAC_PM
TMUX_TTO TMUX_THS TMUX_THS
AC_PM
ILOFM
ILOCM
TMUX_RP
SLOFM
TMUX_RP
SOOFM
TMUX_RP
SILOCM
TMUX_RP
SB2M
TMUX_RP
SLREIM
Interrupt Mask Parameters for INT Pin—R/W
0x4000A
TMUX_
TX_
MSK
0x4000B
TMUX_RP
S_MSK
0x4000C TMUX_RH
S_MSK
TMUX_RS TMUX_RS
1BABM
1MONM
TMUX_RLRDI
MONM
TMUX_RLAI
SMONM
TMUX_RK2
MONM
TMUX_RAP
SBABM
TMUX_RAP
SMONM
TMUX_RF1
MONM
TMUX_RTI
MSM
TMUX_RH
SSFM
TMUX_RH
SSDM
TMUX_RH
SLOSM
TMUX_RH
SLOFM
TMUX_RH
SOOFM
TMUX_RH
SILOCM
0x4000D
TMUX_RP TMUX_RS TMUX_RS TMUX_RU
OH1_MSK
FB3M1
DB3M1
NEQPM1
TMUX_RPLM
PM1
TMUX_RN1
MONM1
TMUX_RK3
MONM1
TMUX_RF3
MONM1
TMUX_RF2
MONM1
TMUX_RR
DIPM1
TMUX_RC2
MONM1
TMUX_RTI
MPM1
TMUX_RN
DFM1
TMUX_RD
ECM1
TMUX_RIN TMUX_RPA
CM1
ISM1
TMUX_RL
OPM1
0x4000E
TMUX_RP TMUX_RS TMUX_RS TMUX_RU
OH2_MSK
FB3M2
DB3M2
NEQPM2
TMUX_RPLM
PM2
TMUX_RN1
MONM2
TMUX_RK3
MONM2
TMUX_RF3
MONM2
TMUX_RF2
MONM2
TMUX_RR
DIPM2
TMUX_RC2
MONM2
TMUX_RTI
MPM2
TMUX_RN
DFM2
TMUX_RD
ECM2
TMUX_RIN TMUX_RPA
CM2
ISM2
TMUX_RL
OPM2
0x4000F
TMUX_RP TMUX_RS TMUX_RS TMUX_RU
OH3_MSK
FB3M3
DB3M3
NEQPM3
TMUX_RPLM
PM3
TMUX_RN1
MONM3
TMUX_RK3
MONM3
TMUX_RF3
MONM3
TMUX_RF2
MONM3
TMUX_RR
DIPM3
TMUX_RC2
MONM3
TMUX_RTI
MPM3
TMUX_RN
DFM3
TMUX_RD
ECM3
TMUX_RIN TMUX_RPA
CM3
ISM3
TMUX_RL
OPM3
0x40011
TMUX_AP
S_MSK
TMUX_
RHSSD_
APSM
TMUX_
RAPSMON
_APSM
TMUX_
TMUX_
TMUX_
RLAISMON RHSLOS_A RHSLOF_A
_APSM
PSM
PSM
Interrupt Mask Parameters for APSINT Pin—R/W
124
TMUX_RH
SSF_APSM
TMUX_
RHSOOF_
APSM
TMUX_
RHSILOC_
APSM
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
8 TMUX Registers (continued)
Table 143. TMUX Register Map (continued)
Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.
Addr. Symbol Bit 15 Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
State and Value Parameters—RO
0x40012
TMUX_TX_ST
ATE
TMUX_THS TMUX_THS
ILOF
ILOC
0x40013
TMUX_RPS_
STATE
0x40014
TMUX_RHS_
STATE
0x40015
TMUX_RPOH
1_STATE
TMUX_RS
FB31
TMUX_RS
DB31
TMUX_RU
NEQP1
TMUX_RPL
MP1
0x40016
TMUX_RPOH
2_STATE
TMUX_RS
FB32
TMUX_RS
DB32
TMUX_RU
NEQP2
0x40017
TMUX_RPOH
3_STATE
TMUX_RS
FB33
TMUX_RS
DB33
TMUX_RU
NEQP3
0x40019
TMUX_RHS_
CTL
0x4001A
TMUX_RLS_
BITBLK_CTL
0x4001B
TMUX_RLS_
MODE_CTL
0x4001C
TMUX_RAISI
NH_CTL
0x4001D
TMUX_LOSD
ETCNT
0x4001E
TMUX_CNTD
_TOH_A
0x4001F
TMUX_CNTD
_TOH_B
0x40020
TMUX_CNTD
_POH_A
0x40021
TMUX_CNTD
_POH_B
0x40022
TMUX_C2EX
P1
0x40023
TMUX_C2EX
P2_3
TMUX_RLR TMUX_RLA
DIMON
ISMON
TMUX_RH
SLOSEXTI
TMUX_RTI
MS
TMUX_RP
SLOF
TMUX_RP
SOOF
TMUX_RP
SILOC
TMUX_RH
SSF
TMUX_RH
SSD
TMUX_RH
SLOS
TMUX_RH
SLOF
TMUX_RH
SOOF
TMUX_RH
SILOC
TMUX_RTI
MP1
TMUX_RPA
IS1
TMUX_RL
OP1
TMUX_RPL
MP2
TMUX_RTI
MP2
TMUX_CONCAT_STATE2 TMUX_RPA
[1:0]
IS2
TMUX_RL
OP2
TMUX_RPL
MP3
TMUX_RTI
MP3
TMUX_CONCAT_STATE3 TMUX_RPA
[1:0]
IS3
TMUX_RL
OP3
TMUX_LOS TMUX_RP TMUX_THS
EXT_LEVE SMUXSEL1
2RHSLB
L
TMUX_RH
SDSCR
TMUX_BIT
BLKM1
TMUX_BIT
BLKB3
TMUX_BIT
BLKB2
TMUX_BIT
BLKB1
TMUX_S1
MODE4
TMUX_RLS
TMUX_
PAROEG
RCONCATMODE
TMUX_
REPRDI_
MODE
Receive High-speed Control Parameters—R/W
Receive Low-speed Control Parameters—R/W
TMUX_RCV_SS_EXP[1:0
]
TMUX_RPA
IS_INS
TMUX_R_
M1_BIT7
TMUX_
RSDB3_
AISINH
TMUX_8O
RMAJORITY
TMUX_RSF
B3_AISINH
TMUX_SD
B1B2SEL
TMUX_SFB
1B2SEL
TMUX_RTIMP_AISINH[3:1]
TMUX_J1MONMODE[2:0]
TMUX_
RUNEQP_
AISINH
TMUX_RPL
MP_AISINH
TMUX_
RHSSD_
AISINH
TMUX_FORCEC2DEF[2:0]
TMUX_RC
V_SS_ENB
TMUX_BIT
BLKG1
TMUX_J0MONMODE[2:0]
TMUX_
RHSSF_
AISINH
TMUX_
RPAISLOP
_AISINH
TMUX_
TMUX_RL TMUX_RO
RLAISMON OF_AISINH OF_AISINH
_AISINH
TMUX_
RHSLOS_
AISINH
TMUX_RIL
OC_AISINH
TMUX_LOSDETCNT[10:0]
Continuous N-Times Detect Values—R/W
Agere Systems Inc.
TMUX_CNTDK1K2FRAME[3:0]
TMUX_CTDLOPCNT[1:0]
TMUX_CNTDF2[3:0]
TMUX_CT
DB1SEL
TMUX_CNTDK1K2[3:0]
TMUX_CNTDF1[3:0]
TMUX_CNTDJ0[3:0]
TMUX_CNTDS1FRAME[3:0]
TMUX_CNTDS1[3:0]
TMUX_CNTDK2[3:0]
TMUX_CNTDRDIP[3:0]
TMUX_C2[3:0]
TMUX_CNTDJ1[3:0]
TMUX_CNTDN1[3:0]
TMUX_CNTDK3[3:0]
TMUX_CNTDF3[3:0]
TMUX_C2EXP1[7:0]
TMUX_C2EXP3[7:0]
TMUX_C2EXP2[7:0]
125
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
8 TMUX Registers (continued)
Table 143. TMUX Register Map (continued)
Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.
Addr. Symbol Bit 15 Bit 14 Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Receive Monitor Values—RO
0x40024
TMUX_RF1M
ON
TMUX_RF1MON1[7:0]
TMUX_RF1MON0[7:0]
0x40025
TMUX_RAPS
MON
0x40026
TMUX_RS1M
ON
0x40027
TMUX_RPOH
MON1A
0x40028
TMUX_RPOH
MON1B
TMUX_F2MON11[7:0]
TMUX_F2MON01[7:0]
0x40029
TMUX_RPOH
MON1C
TMUX_F3MON11[7:0]
TMUX_F3MON01[7:0]
0x4002A
TMUX_RPOH
MON1D
TMUX_N1MON1[7:0]
TMUX_K3MON1[7:0]
0x4002B
TMUX_RPOH
MON2A
0x4002C
TMUX_RPOH
MON2B
TMUX_F2MON12[7:0]
TMUX_F2MON02[7:0]
0x4002D
TMUX_RPOH
MON2C
TMUX_F3MON12[7:0]
TMUX_F3MON02[7:0]
0x4002E
TMUX_RPOH
MON2D
TMUX_N1MON2[7:0]
TMUX_K3MON2[7:0]
0x4002F
TMUX_RPOH
MON3A
0x40030
TMUX_RPOH
MON3B
TMUX_F2MON13[7:0]
TMUX_F2MON03[7:0]
0x40031
TMUX_RPOH
MON3C
TMUX_F3MON13[7:0]
TMUX_F3MON03[7:0]
0x40032
TMUX_RPOH
MON4D
TMUX_N1MON3[7:0]
TMUX_K3MON3[7:0]
0x40033
TMUX_TLS_C
TL
0x40034
TMUX_THS_
PORT_CTL
TMUX_RAPSMON[12:0]
TMUX_K2MON[2:0]
TMUX_RS1MON[7:0]
TMUX_RDIPMON1[2:0]
TMUX_RDIPMON2[2:0]
TMUX_RDIPMON3[2:0]
TMUX_C2MON1[7:0]
TMUX_C2MON2[7:0]
TMUX_C2MON3[7:0]
Transmit Low-speed Control Parameters—R/W
TMUX_TLS_UNEQP[3:1]
TMUX_TLS_PAISINS[3:1]
TMUX_TLS
VOEPAR
Transmit High-speed Port Control Parameters—R/W
126
TMUX_TPS TMUX_TPS
MUXSEL3
MUXSEL2
TMUX_RH
S2THSLB
TMUX_THS
SCR
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
8 TMUX Registers (continued)
Table 143. TMUX Register Map (continued)
Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.
Addr. Symbol Bit 15 Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Transmit High-speed Control Parameters—R/W
0x40035
TMUX_THS_
TOH_CTL
TMUX_TC
ONCATMODE
TMUX_TPR TMUX_TLR
EIRDISEL
EIRDISEL
TMUX_TSS[1:0]
TMUX_THS TMUX_THS TMUX_THS TMUX_THS TMUX_THS TMUX_THS TMUX_THS TMUX_THS
LREIINH
LAISINS
APSINS
K2INS
S1INS
F1INS
Z0INS
J0INS
0x40036
TMUX_THS_
POH1_CTL
TMUX_THS
PREIINH1
TMUX_TP
OHTHRU1
TMUX_THS TMUX_THS TMUX_THS TMUX_THS TMUX_THS TMUX_THS TMUX_THS
N1INS1
K3INS1
F3INS1
F2INS1
RDIPINS1
C2INS1
J1INS1
0x40037
TMUX_THS_
POH2_CTL
TMUX_THS
PREIINH2
TMUX_TP
OHTHRU2
TMUX_THS TMUX_THS TMUX_THS TMUX_THS TMUX_THS TMUX_THS TMUX_THS
N1INS2
K3INS2
F3INS2
F2INS2
RDIPINS2
C2INS2
J1INS2
0x40038
TMUX_THS_
POH3_CTL
TMUX_THS
PREIINH3
TMUX_TP
OHTHRU3
TMUX_THS TMUX_THS TMUX_THS TMUX_THS TMUX_THS TMUX_THS TMUX_THS
N1INS3
K3INS3
F3INS3
F2INS3
RDIPINS3
C2INS3
J1INS3
0x4003A
TMUX_TLRDI
_CTL
0x4003B
TMUX_TPRDI
_CTL
0x4003C
TMUX_TZ0_I
NS_VAL
TMUX_TZ03INS[7:0]
TMUX_TZ02INS[7:0]
0x4003D
TMUX_TS1_F
1_INS_VAL
TMUX_TS1INS[7:0]
TMUX_TF1INS[7:0]
0x4003E
TMUX_TAPS
_INS_VAL
TMUX_TAPSINS[12:0]
0x4003F
TMUX_TPOH
1_INS_A
TMUX_TRDIPINS1[2:0]
0x40040
TMUX_TPOH
1_INS_B
TMUX_TF3INS1[7:0]
TMUX_TF2INS1[7:0]
0x40041
TMUX_TPOH
1_INS_C
TMUX_TN1INS1[7:0]
TMUX_TK3INS1[7:0]
0x40042
TMUX_TPOH
2_INS_A
0x40043
TMUX_TPOH
2_INS_B
TMUX_TF3INS2[7:0]
TMUX_TF2INS2[7:0]
0x40044
TMUX_TPOH
2_INS_C
TMUX_TN1INS2[7:0]
TMUX_TK3INS2[7:0]
0x40045
TMUX_TPOH
3_INS_A
0x40046
TMUX_TPOH
3_INS_B
TMUX_TF3INS3[7:0]
TMUX_TF2INS3[7:0]
0x40047
TMUX_TPOH
3_INS_C
TMUX_TN1INS3[7:0]
TMUX_TK3INS3[7:0]
Transmit High-speed Line RDI Control Parameters—R/W
TMUX_TRS TMUX_TRS TMUX_TRL TMUX_TRL TMUX_TR TMUX_TRL
D_LRDIINH F_LRDIINH AISMON_L OF_LRDIIN OOF_LRDII OS_LRDIIN
RDIINH
H
NH
H
TMUX_TRI
LOC_LRDII
NH
Transmit High-speed Path RDI Control Parameters—R/W
TMUX_TIM_PRDIINH[3:1]
TMUX_TRU TMUX_TRP TMUX_TRL TMUX_TRP TMUX_TEP
EQ_PRDIIN LM_PRDIIN OP_PRDIIN AIS_PRDII RDI_MODE
H
H
H
NH
Transmit TOH and POH Insert Values—R/W
Agere Systems Inc.
TMUX_TRDIPINS2[2:0]
TMUX_TRDIPINS3[2:0]
TMUX_TK2INS[2:0]
TMUX_TC2INS1[7:0]
TMUX_TC2INS2[7:0]
TMUX_TC2INS3[7:0]
127
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
8 TMUX Registers (continued)
Table 143. TMUX Register Map (continued)
Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.
Addr. Symbol Bit 15 Bit 14 Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Transmit High-speed Error Insertion Control Parameters—R/W
0x40048
TMUX_TBERI
NS_CTL
TMUX_TPS TMUX_TPS
B2EINS
LREIINS
TMUX_TPREIINS[3:1]
0x40049
TMUX_THS_
ERR_CTL
0x4004A
TMUX_TOAC
_CTL
0x4004B
TMUX_RPOA
C_CTL
0x4004D
TMUX_TFRA
MEOFFSET
0x4004E
TMUX_SD_C
TL1
0x4004F
TMUX_SD_C
TL2
0x40050
TMUX_SD_C
TL3
TMUX_SDBSET[15:0]
0x40051
TMUX_SD_C
TL4
TMUX_SDNSCLEAR[18:3]
0x40052
TMUX_SD_C
TL5
0x40053
TMUX_SD_C
TL6
0x40054
TMUX_SF_C
TL1
0x40055
TMUX_SF_C
TL2
0x40056
TMUX_SF_C
TL3
TMUX_SFBSET[15:0]
0x40057
TMUX_SF_C
TL4
TMUX_SFNSCLEAR[18:3]
0x40058
TMUX_SF_C
TL5
0x40059
TMUX_SF_C
TL6
TMUX_TAP
SBABINS
TMUX_THSB3ERRINS[3:1]
TMUX_TH1H2INVEN[3:1]
TMUX_TLR
EIINS
TMUX_TH1
H2INVORN
DF
TMUX_THSB2ERRINS[3:1]
TMUX_THS
B1ERRINS
TMUX_TA2ERRINS[4:0]
Receive/Transmit TOAC/POAC Control Parameters—R/W
TMUX_RT
OAC_D412
MODE
TMUX_RT
OAC_D13
MODE
TMUX_RPOAC_
SEL[1:0]
TMUX_
RTOAC_
OEPINS
TMUX_
TTOAC_
D412MODE
TMUX_
TTOAC_
D13MODE
TMUX_
RPOAC_
OEPINS
TMUX_TPOAC_SEL[1:0]
TMUX_TTO TMUX_TTO TMUX_TTO TMUX_TTO TMUX_TTO
AC_AVAIL
AC_S1
AC_F1
AC_E2
AC_E1
TMUX_TP
OAC_N1
TMUX_TP
OAC_K3
TMUX_TP
OAC_F3
TMUX_TP
OAC_F2
TMUX_
TTOAC_
D4TO12
TMUX_TTO
AC_D1TO3
TMUX_
TTOAC_
OEPMON
TMUX_TP
OAC_C2
TMUX_TP
OAC_J1
TMUX_
TPOAC_
OEPMON
Transmit High-speed Offset Control Parameters —R/W
TMUX_TLBITCNT[2:0]
TMUX_TLSTSCNT[1:0]
TMUX_TLCOLCNT[6:0]
TMUX_TLROWCNT[3:0]
B1/B2 Signal Degrade Set/Clear Control Registers—R/W
TMUX_SDNSSET[18:3]
TMUX_SDMSET[7:0]
TMUX_SDMCLEAR[7:0]
TMUX_SDLSET[3:0]
TMUX_SDNSSET[2:0]
TMUX_SDLCLEAR[3:0]
TMUX_SDNSCLEAR[2:0]
TMUX_SFLSET[3:0]
TMUX_SFNSSET[2:0]
TMUX_SFLCLEAR[3:0]
TMUX_SFNSCLEAR[2:0]
TMUX_SDBCLEAR[15:0]
B1/B2 Signal Fail Set/Clear Control Registers—R/W
128
TMUX_SFNSSET[18:3]
TMUX_SFMSET[7:0]
TMUX_SFMCLEAR[7:0]
TMUX_SFBCLEAR[15:0]
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
8 TMUX Registers (continued)
Table 143. TMUX Register Map (continued)
Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.
Addr. Symbol Bit 15 Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
B3 Signal Degrade Set/Clear Control Registers—R/W
0x4005A
TMUX_B3SD
_CTL1
TMUX_B3SDNSSET[18:3]
0x4005B
TMUX_B3SD
_CTL2
0x4005C
TMUX_B3SD
_CTL3
TMUX_B3SDBSET[15:0]
0x4005D
TMUX_B3SD
_CTL4
TMUX_B3SDNSCLEAR[18:3]
0x4005E
TMUX_B3SD
_CTL5
0x4005F
TMUX_B3SD
_CTL6
0x40060
TMUX_B3SF_
CTL1
0x40061
TMUX_B3SF_
CTL2
0x40062
TMUX_B3SF_
CTL3
TMUX_B3SFBSET[15:0]
0x40063
TMUX_B3SF_
CTL4
TMUX_B3SFNSCLEAR[18:3]
0x40064
TMUX_B3SF_
CTL5
0x40065
TMUX_B3SF_
CTL6
TMUX_B3SDMSET[7:0]
TMUX_B3SDMCLEAR[7:0]
TMUX_B3SDLSET[3:0]
TMUX_B3SDNSSET[2:0]
TMUX_B3SDLCLEAR[3:0]
TMUX_B3SDNSCLEAR[2:0]
TMUX_B3SFLSET[3:0]
TMUX_B3SFNSSET[2:0]
TMUX_B3SFLCLEAR[3:0]
TMUX_B3SFNSCLEAR[2:0]
TMUX_B3SDBCLEAR[15:0]
B3 Signal Fail Set/Clear Control Registers—R/W
Agere Systems Inc.
TMUX_B3SFNSSET[18:3]
TMUX_B3SFMSET[7:0]
TMUX_B3SFMCLEAR[7:0]
TMUX_B3SFBCLEAR[15:0]
129
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
8 TMUX Registers (continued)
Table 143. TMUX Register Map (continued)
Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.
Addr. Symbol Bit 15 Bit 14 Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Receive B1, B2, B3, M1, G1, and N1 Error Counts—RO
0x40066
TMUX_B1EC
NT
TMUX_B1ECNT[15:0]
0x40067
TMUX_B2EC
NT_17_16
0x40068
TMUX_B2EC
NT_15_0
TMUX_B2ECNT[15:0]
0x40069
TMUX_B3EC
NT1
TMUX_B3ECNT1[15:0]
0x4006A
TMUX_B3EC
NT2
TMUX_B3ECNT2[15:0]
0x4006B
TMUX_B3EC
NT3
TMUX_B3ECNT3[15:0]
0x4006C
TMUX_M1EC
NT_17_16
0x4006D
TMUX_M1EC
NT_15_0
TMUX_M1ECNT[15:0]
0x4006E
TMUX_G1EC
NT1
TMUX_G1ECNT1[15:0]
0x4006F
TMUX_G1EC
NT2
TMUX_G1ECNT2[15:0]
0x40070
TMUX_G1EC
NT3
TMUX_G1ECNT3[15:0]
0x40074
TMUX_RPTR
_INCCNT1
TMUX_RPTR_INC1[10:0]
0x40075
TMUX_RPTR
_INCCNT2
TMUX_RPTR_INC2[10:0]
0x40076
TMUX_RPTR
_INCCNT3
TMUX_RPTR_INC3[10:0]
0x40077
TMUX_RPTR
_DECCNT1
TMUX_RPTR_DEC1[10:0]
0x40078
TMUX_RPTR
_DECCNT2
TMUX_RPTR_DEC2[10:0]
0x40079
TMUX_RPTR
_DECCNT3
TMUX_RPTR_DEC3[10:0]
TMUX_B2ECNT[17:16]
TMUX_M1ECNT[17:16]
Receive Pointer Increment and Decrement Counts—RO
130
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
8 TMUX Registers (continued)
Table 143. TMUX Register Map (continued)
Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.
Addr. Symbol Bit 15 Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Expected J0 Receive Value—R/W
0x400A0
—
0x400A7
TMUX_RJ0EX
PECTED
[1—8]
TMUX_EXPJ0DMON[2][7:0]
—
TMUX_EXPJ0DMON[16][7:0]
0x400A8
—
0x400AF
TMUX_RJ0C
APTURED
[1—8]
TMUX_J0DMON[2][7:0]
—
TMUX_J0DMON[16][7:0]
0x400B0
—
0x400B7
TMUX_TJ0VA
LUE[1—8]
TMUX_TJ0DINS[2][7:0]
—
TMUX_TJ0DINS[16][7:0]
0x400E0
—
0x400FF
TMUX_RJ1EX
PECTED_1
[1—32]
TMUX_EXPJ1DMON1[2][7:0]
—
TMUX_EXPJ1DMON1[64][7:0]
0x40100
—
0x4011F
TMUX_RJ1EX
PECTED_2
[1—32]
TMUX_EXPJ1DMON2[2][7:0]
—
TMUX_EXPJ1DMON2[64][7:0]
0x40120
—
0x4013F
TMUX_RJ1EX
PECTED_3
[1—32]
TMUX_EXPJ1DMON3[2][7:0]
—
TMUX_EXPJ1DMON3[64][7:0]
TMUX_EXPJ0DMON[1][7:0]
—
TMUX_EXPJ0DMON[15][7:0]
Captured J0 Receive Value—RO
TMUX_J0DMON[1][7:0]
—
TMUX_J0DMON[15][7:0]
J0 Byte Transmit Insert—R/W
TMUX_TJ0DINS[1][7:0]
—
TMUX_TJ0DINS[15][7:0]
Expected J1 Receive Value for STS #1—R/W
TMUX_EXPJ1DMON1[1][7:0]
—
TMUX_EXPJ1DMON1[63][7:0]
Expected J1 Receive Value for STS #2—R/W
TMUX_EXPJ1DMON2[1][7:0]
—
TMUX_EXPJ1DMON2[63][7:0]
Expected J1 Receive Value for STS #3—R/W
Agere Systems Inc.
TMUX_EXPJ1DMON3[1][7:0]
—
TMUX_EXPJ1DMON3[63][7:0]
131
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
8 TMUX Registers (continued)
Table 143. TMUX Register Map (continued)
Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.
Addr. Symbol Bit 15 Bit 14 Bit 13
Bit 12
Bit 11
0x40140
—
0x4015F
TMUX_RJ1C
APTURED_1
[1—32]
TMUX_J1DMON1[2][7:0]
—
TMUX_J1DMON1[64][7:0]
0x40160
—
0x4017F
TMUX_RJ1C
APTURED_2
[1—32]
TMUX_J1DMON2[2][7:0]
—
TMUX_J1DMON2[64][7:0]
0x40180
—
0x4019F
TMUX_RJ1C
APTURED_3
[1—32]
TMUX_J1DMON3[2][7:0]
—
TMUX_J1DMON3[64][7:0]
0x401A0
—
0x401BF
TMUX_TJ1VA
LUE_1
[1—32]
TMUX_TJ1DINS1[2][7:0]
—
TMUX_TJ1DINS1[64][7:0]
0x401C0
—
0x401DF
TMUX_TJ1VA
LUE_2
[1—32]
TMUX_TJ1DINS2[2][7:0]
—
TMUX_TJ1DINS2[64][7:0]
0x401E0
—
0x401FF
TMUX_TJ1VA
LUE_3
[1—32]
TMUX_TJ1DINS3[2][7:0]
—
TMUX_TJ1DINS3[64][7:0]
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Captured J1 Receive Value for STS #1—RO
TMUX_J1DMON1[1][7:0]
—
TMUX_J1DMON1[63][7:0]
Captured J1 Receive Value for STS #2—RO
TMUX_J1DMON2[1][7:0]
—
TMUX_J1DMON2[63][7:0]
Captured J1 Receive Value for STS #3—RO
TMUX_J1DMON3[1][7:0]
—
TMUX_J1DMON3[63][7:0]
J1 Byte Transmit Insert for STS #1—R/W
TMUX_TJ1DINS1[1][7:0]
—
TMUX_TJ1DINS1[63][7:0]
J1 Byte Transmit Insert for STS #2—R/W
TMUX_TJ1DINS2[1][7:0]
—
TMUX_TJ1DINS2[63][7:0]
J1 Byte Transmit Insert for STS #3—R/W
132
TMUX_TJ1DINS3[1][7:0]
—
TMUX_TJ1DINS3[63][7:0]
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
9 SPE Mapper Registers
Table of Contents
Contents
Page
9 SPE Mapper Registers ..................................................................................................................................... 133
9.1 SPE Mapper Register Descriptions ........................................................................................................... 134
9.2 SPE Mapper Register Map ........................................................................................................................ 149
Contents
Page
Table 144. SPE_VERSION_R, SPE Version and Identification Register (RO) ................................................... 134
Table 145. SPE_ONESHOT, One-Shot (R/W) .................................................................................................... 134
Table 146. SPE_EVENT1—SPE_EVENT3, SPE Deltas/Events (COR/COW) ................................................... 134
Table 147. SPE_MASK1—SPE_MASK3, Mask Bits (R/W) ................................................................................ 136
Table 148. SPE_STATE1—SPE_STATE2, Receive/Transmit State and Value Parameters (RO) .................... 137
Table 149. SPE_RAOH_CTL1—SPE_RAOH_CTL3, Receive Control for Alarm and OH Functions (R/W) ....... 138
Table 150. SPE_CNTD1—SPE_CNTD2, Continuous N-Times Detect Values (R/W) ........................................ 139
Table 151. SPE_ROHC2, Receive Overhead Expected Value for C2 Byte (R/W) ............................................. 140
Table 152. SPE_RMON1—SPE_RMON5, Receive Monitor Values (RO) .......................................................... 140
Table 153. SPE_MAP_CTL1—SPE_MAP_CTL3, Tx/Rx Control for Mapping Functions (R/W) ........................ 140
Table 154. SPE_TAOH_CTL1—SPE_TAOH_CTL3, Tx Control for Alarm/OH Functions (R/W) ....................... 143
Table 155. SPE_TRDIREI_CTL, Transmit Path RDI and REI Control Register (R/W) ....................................... 145
Table 156. SPE_TERRINS_CTL, Transmit Error Insertion Control (R/W) .......................................................... 145
Table 157. SPE_TOHINS1—SPE_TOHINS4, Transmit OH Insert Value (R/W) ................................................ 145
Table 158. SPE_SIGDEG_CTL1—SPE_SIGDEG_CTL6, Signal Degrade BER Algorithm Parameters (R/W) .. 146
Table 159. SPE_SIGFAIL_CTL1—SPE_SIGFAIL_CTL6, Signal Fail BER Algorithm Parameters (R/W) .......... 146
Table 160. SPE_ERRCNT1—SPE_ERRCNT6, B3, G1, Bipolar Violation, and Excess
Zero Error Count (RO) ....................................................................................................................... 147
Table 161. SPE_PTRCNT1—SPE_PTRCNT3, Receive Pointer Increment and Decrement Count (RO) .......... 147
Table 162. SPE_RJ1MON_R1—SPE_RJ1MON_R32, Receive J1 Monitor Values (RO) .................................. 147
Table 163. SPE_TJ1DINS_R1—SPE_TJ1DINS_R32, Transmit J1 Insert Values (R/W) ................................... 148
Table 164. SPE_RJ1DEXP_R1—SPE_RJ1DEXP_R32, Receive J1 Expected Values (R/W) ........................... 148
Table 165. SPE_SCRATCH_R, Scratch Pad (R/W) ........................................................................................... 148
Table 166. SPE Mapper Register Map ................................................................................................................ 149
Agere Systems Inc.
133
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
9 SPE Mapper Registers (continued)
9.1 SPE Mapper Register Descriptions
This section gives a brief description of each register bit and its functionality. The abbreviations after each register
indicate if the register is read only (RO), clear-on-read/clear-on-write (COR/COW), or read/write (R/W).
Table 144. SPE_VERSION_R, SPE Version and Identification Register (RO)
Address
0x30000
Bit
Name
Function
15:11
—
Reserved.
10:8 SPE_VERSION[2:0] Block Version Number. Block version register will change
each time the device is changed.
7:0
SPEMPR_ID[7:0] Block ID Number.
Reset
Default
0x00
0x0
0x03
Table 145. SPE_ONESHOT, One-Shot (R/W)
Address
Bit
Name
Function
Reset
Default
0x30002
15:5
—
4
SPE_BIPOL_ERR
Bipolar Violation Error. A single bipolar violation error for
DS3 output is transmitted each time this bit transitions from a
0 to 1.
0
3
SPE_SFCLEAR
Signal Fail Clear. Allows the signal fail algorithm to be forced
into the normal state.
0
2
SPE_SFSET
Signal Fail Set. Allows the signal fail algorithm to be forced
into the failed state.
0
1
SPE_SDCLEAR
Signal Degrade Clear. Allows the signal degrade algorithm
to be forced into the normal state.
0
0
SPE_SDSET
Signal Degrade Set. Allows the signal degrade algorithm to
be forced into the degraded state.
0
Reserved.
0x000
Note: In Table 122, the mask bits for these delta and event bits are in Table 147, state bits are in Table 148, and
monitor values are in Table 152.
Table 146. SPE_EVENT1—SPE_EVENT3, SPE Deltas/Events (COR/COW)
Address
Bit
Name
0x30003
15:7
6
—
SPE_RDATA_PE
5
SPE_TPOAC_PE
4
3
2
1
0
SPE_K3DMOND
SPE_N1DMOND
SPE_C2DMOND
SPE_F2DMOND
SPE_F3DMOND
134
Function
Reset
Default
Reserved.
0x000
Received Data Parity Error Event. Event bit indicates a parity
0
error was detected on the incoming data.
Transmit POAC Parity Error Event. Event bit indicates a parity
0
error was detected on the incoming POAC.
K3 Data Monitor Delta Bit. The mask bit is SPE_K3DMONM.
0
N1 Data Monitor Delta Bit. The mask bit is SPE_N1DMONM.
0
C2 Data Monitor Delta Bit. The mask bit is SPE_C2DMONM.
0
F2 Data Monitor Delta Bit. The mask bit is SPE_F2DMONM.
0
F3 Data Monitor Delta Bit. The mask bit is SPE_F3DMONM.
0
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
9 SPE Mapper Registers (continued)
Table 146. SPE_EVENT1—SPE_EVENT3, SPE Deltas/Events (COR/COW) (continued)
Address
Bit
0x30004 15:11
10
9
8
7
0x30004
6
5
4
3
2
1
0
0x30005
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Function
—
Reserved.
SPE_PRDIDMOND Path RDI Delta. Delta bit indicates a change of state for the
path RDI state bit SPE_PRDIDMON. The delta bit is cleared
when read. The mask bit for this delta bit is
SPE_PRDIDMONM.
SPE_RNDFE
Pointer Interpreter New Data Flag Event Bit. The mask bit is
SPE_RNDFM.
SPE_RDECE
Pointer Interpreter Decrement Event Bit. The mask bit is
SPE_RDECM. However, increment and decrement event indications should be ignored during LOP condition.
SPE_RINCE
Pointer Interpreter Increment Event Bit. The mask bit is
SPE_RINCM. However, increment and decrement event indications should be ignored during LOP condition.
SPE_RAISD
Delta Bit for the AIS Alarm Detect State Bit. The mask bit is
SPE_RAISM.
SPE_RLOPD
Delta Bit for the Loss of Pointer Alarm State Bit. The mask
bit is SPE_RLOPM.
SPE_SFB3D
Signal Fail BER Algorithm Delta. Indicates a change of state
for the signal fail BER algorithm state bit SFB3. This bit clears
when read. The mask bit is SPE_SFB3M.
SPE_SDB3D
Signal Degrade BER Algorithm Delta. Indicates a change of
state for the signal degrade BER algorithm state bit SDB3. This
bit clears when read. The mask bit is SPE_SDB3M.
SPE_RUNEQD
Delta Bit for the Unequipped Alarm State Bit. The mask bit is
SPE_RUNEQM.
SPE_RPLMD
Delta Bit for the Payload Label Mismatch Alarm State Bit.
The mask bit is SPE_RPLMM.
SPE_RTIMD
Trace Indicator Mismatch Event Bit (J1 Byte). The mask bit is
SPE_RTIMM.
—
Reserved.
SPE_RSY52LOSD Delta Bit for Loss of Sync 52 Signal from Telecom Bus.
SPE_RV1LOSD
Delta Bit for Loss of V1 Sync Signal from Telecom Bus.
SPE_RSPELOSD Delta Bit for Loss of SPE Sync Signal from Telecom Bus.
SPE_RJ0J1V1LOSD Delta Bit for Loss of J0J1V1 Sync Signal from Telecom Bus.
SPE_RDS3LOCD Delta Bit for Loss of DS3 External Clock from External Pin.
SPE_RC52LOCD Delta Bit for Loss of 52 MHz Clock from Telecom Bus.
SPE_RLSLOCD
Delta Bit for Loss of 19 MHz Clock from Telecom Bus.
—
Reserved.
SPE_TSY52LOSD Delta Bit for Loss of Sync 52 Signal from Telecom Bus.
SPE_TV1LOSD
Delta Bit for Loss of V1 Sync Signal from Telecom Bus.
SPE_TSPELOSD Delta Bit for Loss of SPE Sync Signal from Telecom Bus.
SPE_TJ0J1V1LOSD Delta Bit for Loss of J0J1V1 Sync Signal from Telecom Bus.
SPE_TDS3LOCD Delta Bit for Loss of DS3 External Clock from External Pin.
SPE_TC52LOCD Delta Bit for Loss of 52 MHz Clock from Telecom Bus.
SPE_TLSLOCD
Delta Bit for Loss of 19 MHz Clock from Telecom Bus.
Agere Systems Inc.
Reset
Default
0x00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
135
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
9 SPE Mapper Registers (continued)
Table 147. SPE_MASK1—SPE_MASK3, Mask Bits (R/W)
Address
Bit
Name
0x30006
15:7
—
6
SPE_RDATA_PM
Received Data Parity Error Mask. Active-high.
1
5
SPE_TPOAC_PM
Transmit POAC Parity Error Mask. Active-high.
1
4
SPE_K3DMONM
K3 Data Monitor Mask Bit. Active-high.
1
3
SPE_N1DMONM
N1 Data Monitor Mask Bit. Active-high.
1
2
SPE_C2DMONM
C2 Data Monitor Mask Bit. Active-high.
1
1
SPE_F2DMONM
F2 Data Monitor Mask Bit. Active-high.
1
0
SPE_F3DMONM
0x30007 15:11
0x30008
10
SPE_PRDIDMONM
9
Reset
Default
Reserved.
000000
000
F3 Data Monitor Mask Bit. Active-high.
1
Reserved.
00000
Path RDI Mask Bit. Active-high.
1
SPE_RNDFM
Pointer Interpreter New Data Flag Mask Bit. Active-high
1
8
SPE_RDECM
Pointer Interpreter Decrement Mask Bit. Active-high.
1
7
SPE_RINCM
Pointer Interpreter Increment Mask Bit. Active-high
1
6
SPE_RAISM
Mask Bit for the AIS Alarm Detect State Bit. Active-high.
1
5
SPE_RLOPM
Mask Bit for the Loss of Pointer Alarm State Bit. Activehigh.
1
4
SPE_SFB3M
Signal Fail Mask Bit. Active-high.
1
3
SPE_SDB3M
Signal Degrade Mask Bit. Active-high.
1
2
SPE_RUNEQM
Mask Bit for the Unequipped Alarm State Bit. Active-high.
1
1
SPE_RPLMM
Mask Bit for the Payload Label Mismatch Alarm State Bit.
Active-high.
1
0
SPE_RTIMM
Trace Indicator Mismatch Mask Bits. Active-high.
1
15
—
Reserved.
0
14
SPE_RSY52LOSM
Mask Bit for Loss of Sync 52 Signal from Telecom Bus.
Active-high.
1
13
SPE_RV1LOSM
Mask Bit for Loss of V1 Sync Signal from Telecom Bus.
Active-high.
1
12
SPE_RSPELOSM
Mask Bit for Loss of SPE Sync Signal from Telecom Bus.
Active-high.
1
11
136
—
Function
SPE_RJ0J1V1LOSM Mask Bit for Loss of J0J1V1 Sync Signal from Telecom
Bus. Active-high.
1
10
SPE_RDS3LOCM
Mask Bit for Loss of DS3 External Clock from External
PIN. Active-high.
1
9
SPE_RC52LOCM
Mask Bit for Loss of 52 MHz Clock from Telecom Bus.
Active-high.
1
8
SPE_RLSLOCM
Mask Bit for Loss of 19 MHz Clock from Telecom Bus.
Active-high.
1
7
—
Reserved.
0
6
SPE_TSY52LOSM
Mask Bit for Loss of Sync 52 Signal from Telecom Bus.
Active-high.
1
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
9 SPE Mapper Registers (continued)
Table 147. SPE_MASK1—SPE_MASK3, Mask Bits (R/W) (continued)
Address
Bit
Name
Function
Reset
Default
0x30008
5
SPE_TV1LOSM
Mask Bit for Loss of V1 Sync Signal from Telecom Bus.
Active-high.
1
4
SPE_TSPELOSM
Mask Bit for Loss of SPE Sync Signal from Telecom
Bus. Active-high.
1
3
SPE_TJ0J1V1LOSM Mask Bit for Loss of J0J1V1 Sync Signal from Telecom
Bus. Active-high.
2
SPE_TDS3LOCM
Mask Bit for Loss of DS3 External Clock from External
PIN. Active-high.
1
1
SPE_TC52LOCM
Mask Bit for Loss of 52 MHz Clock from Telecom Bus.
Active-high.
1
0
SPE_TLSLOCM
Mask Bit for Loss of 19 MHz Clock from Telecom Bus.
Active-high.
1
Table 148. SPE_STATE1—SPE_STATE2, Receive/Transmit State and Value Parameters (RO)
Address
Bit
0x30009
15:7
6
5
4
3
2
1
0
15
14
13
12
11
0x3000A
10
9
8
7
6
5
4
3
2
1
0
Agere Systems Inc.
Name
Function
Reset
Default
—
Reserved.
0x000
SPE_RAIS
Path AIS State Bit.
0
SPE_RLOP
Path Loss of Pointer State Bit.
0
SPE_SFB3
Signal Fail State Bit.
0
SPE_SDB3
Signal Degrade State Bit.
0
SPE_RUNEQ
Path Unequipped State Bit.
0
SPE_RPLM
Path Payload Label Mismatch State Bit.
0
SPE_RTIM
Path Trace Indicator Mismatch State Bit.
0
—
Reserved.
0
SPE_RSY52LOS State Bit for Loss of Sync 52 Signal from Telecom Bus.
0
SPE_RV1LOS
State Bit for Loss of V1 Sync Signal from Telecom Bus.
0
SPE_RSPELOS
State Bit for Loss of SPE Sync Signal from Telecom Bus.
0
SPE_RJ0J1V1LOS State Bit for Loss of J0J1V1 Sync Signal from Telecom
0
Bus.
SPE_RDS3LOC
State Bit for Loss of DS3 External Clock from External
0
PIN.
SPE_RC52LOC
State Bit for Loss of 52 MHz Clock from Telecom Bus.
0
SPE_RLSLOC
State Bit for Loss of 19 MHz Clock from Telecom Bus.
0
—
Reserved.
0
SPE_TSY52LOS State Bit for Loss of Sync 52 Signal from Telecom Bus.
0
SPE_TV1LOS
State Bit for Loss of V1 Sync Signal from Telecom Bus.
0
SPE_TSPELOS
State Bit for Loss of SPE Sync Signal from Telecom Bus.
0
SPE_TJ0J1V1LOS State Bit for Loss of J0J1V1 Sync Signal from Telecom
0
Bus.
SPE_TDS3LOC
State Bit for Loss of DS3 External Clock from External
0
Pin.
SPE_TC52LOC
State Bit for Loss of 52 MHz Clock from Telecom Bus.
0
SPE_TLSLOC
State Bit for Loss of 19 MHz Clock from Telecom Bus.
0
137
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
9 SPE Mapper Registers (continued)
)
Table 149. SPE_RAOH_CTL1—SPE_RAOH_CTL3, Receive Control for Alarm and OH Functions (R/W)
Address
Bit
0x3000B
15:8
7
6:4
3
2
1
0
0x3000C 15:12
11:10
9
8
7
6
5
4
3
2
1
0
138
Name
Function
Reset
Default
—
Reserved.
0x00
SPE_RD_OEPAR
Received Data Odd/Even Parity Check. If 0, odd parity
0
check for received data; if 1, even parity check.
SPE_J1MONMODE[2:0] J1 Monitoring Mode. There are four monitoring modes
000
as defined in the document.
SPE_RPRDI_MODE
Receive ERDI Mode. When 1, 3-bit enhanced ERDI
0
mode is supported; when 0, the 1-bit RDI mode is
supported.
SPE_G1BITBLKCNT
G1 Error Count in Bit or Block. When 0, G1(7:4)
0
check logic will count bit errors; otherwise, it counts
block errors.
SPE_B3BITBLKCNT
B3 Error Count in Bit or Block. When 0, B3 check
0
logic will count bit errors; otherwise, it counts block
errors.
SPE_RPOAC_OEPINS Receive POAC Odd or Even Parity Insert. When 1,
0
the output POAC parity bit is even; otherwise, the parity
is odd.
—
Reserved.
0x0
SPE_CNTDLOPCNT[1:0] Continuous N-Times Detect for Loss of Pointer. Two
00
bit programmable integration constant for the pointer
interpreter.
—
Reserved.
0
0
SPE_8ORMAJORITY
TU-3 Pointer Interpreter Mode Control. When 1, the
pointer interpreter transitions into the INC and DEC
states based on 8 of the 10 I and D bits. Otherwise, the
pointer interpreter transitions into the INC and DEC
states based on majority rule.
SPE_PAISINS
Path AIS Software Insertion. When 1, path AIS
0
insertion is enabled.
SPE_PAIS_AISINH
Path AIS State bit Inhibit Signal for Generating Path
0
AIS. When 1, the inhibit is on.
SPE_PAIS_LOPINH
Loss of Pointer Inhibit Signal for Generating Path
0
AIS. When 1, the inhibit is on.
SPE_PAIS_SFB3INH
Signal Fail Inhibit Signal for Generating Path AIS.
0
When 1, the inhibit is on.
SPE_PAIS_SDB3INH
Signal Degrade Inhibit Signal for Generating Path
0
AIS. When 1, the inhibit is on.
SPE_PAIS_UNEQINH
Path Unequipped Inhibit Signal for Generating Path
0
AIS. When 1, the inhibit is on.
SPE_PAIS_PLMINH
Path Label Mismatch Inhibit Signal for Generating
0
Path AIS. When 1, the inhibit is on.
SPE_PAIS_TIMINH
Path Trace Indicator Mismatch Inhibit Signal for
0
Generating Path AIS. When 1, the inhibit is on.
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
9 SPE Mapper Registers (continued)
Table 149. SPE_RAOH_CTL1—SPE_RAOH_CTL3, Receive Control for Alarm and OH Functions (R/W)
Address
Bit
0x3000D
15:7
6
5
4
3
2
1
0
Name
Function
Reset
Default
—
Reserved.
0x000
SPE_AIS_LOSSY52INH Loss of Sync 52 State Bit Inhibit Signal for Generat0
ing Path AIS. When 1, the inhibit is on.
SPE_AIS_LOSV1INH
Loss of V1 Sync Inhibit Signal for Generating Path
0
AIS. When 1, the inhibit is on.
SPE_AIS_LOSSPEINH Loss of SPE Sync Inhibit Signal for Generating Path
0
AIS. When 1, the inhibit is on.
SPE_AIS_LOSJ0J1V1INH Loss of J0J1V1 Sync Inhibit Signal for Generating
0
Path AIS. When 1, the inhibit is on.
SPE_AIS_LOCDS3INH Loss of Ext DS3 Clock Inhibit Signal for Generating
0
Path AIS. When 1, the inhibit is on.
SPE_AIS_LOC52INH
Loss of 52 MHz Clock Inhibit Signal for Generating
0
Path AIS. When 1, the inhibit is on.
SPE_AIS_LOCINH
Loss of 19 MHz Clock Inhibit Signal for Generating
0
Path AIS. When 1, the inhibit is on.
Table 150. SPE_CNTD1—SPE_CNTD2, Continuous N-Times Detect Values (R/W)
Address
Bit
Name
Function
Reset
Default
0x3000F
15:12
SPE_CNTDC2[3:0]
Continuous N-Times Detect for C2 Byte. The valid range
for this register is 0x3—0xF. Invalid values will be mapped to
a value of 0x3.
0x3
11:8
SPE_CNTDF3[3:0]
Continuous N-Times Detect for F3 Byte. The valid range
for this register is 0x3—0xF. Invalid values will be mapped to
a value of 0x3.
0x3
7:4
SPE_CNTDF2[3:0]
Continuous N-Times Detect for F2 Byte. The valid range
for this register is 0x3—0xF. Invalid values will be mapped to
a value of 0x3.
0x3
3:0
SPE_CNTDJ1[3:0]
Continuous N-Times Detect for J1 Bytes. The valid range
for this register is 0x3—0xF. Invalid values will be mapped to
a value of 0x3.
0x3
15:12
SPE_CNTDN1[3:0]
Continuous N-Times Detect for N1 Byte. The valid range
for this register is 0x3—0xF. Invalid values will be mapped to
a value of 0x3.
0x3
SPE_CNTDPRDI[3:0] Continuous N-Times Detect for G1 Byte. The valid range
for this register is 0x3—0xF. Invalid values will be mapped to
a value of 0x3.
0x3
0x30010
11:8
7:4
SPE_CNTDK3[3:0]
3:0
—
Agere Systems Inc.
Continuous N-Times Detect for K3[6:4] Byte. The valid
range for this register is 0x3—0xF. Invalid values will be
mapped to a value of 0x3.
0x3
Reserved.
0x0
139
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
9 SPE Mapper Registers (continued)
Table 151. SPE_ROHC2, Receive Overhead Expected Value for C2 Byte (R/W)
Address
Bit
Name
0x30011
15:8
—
7:0
Function
Reset
Default
Reserved.
0x00
SPE_C2DEXP[7:0] Programmable Expected Value for C2 Byte. The
programmed value is checked against the actual received
value to determine payload label mismatch error.
0x00
Table 152. SPE_RMON1—SPE_RMON5, Receive Monitor Values (RO)
Address
Bit
Name
0x30012
15:3
—
2:0
0x30013
0x30014
0x30015
0x30016
Function
Reset
Default
Reserved.
0x000
SPE_PRDIDMON[2:0] Received Byte G1[3:1] Monitor Value.
0x0
15:8
SPE_N1DMON[7:0]
Received Byte N1[7:0] Monitor Value.
0x00
7:0
SPE_K3DMON[7:0]
Received Byte K3[7:0] Monitor Value.
0x00
15:8
SPE_F2DMON1[7:0]
Received Byte F2[7:0] Previous Monitor Value.
0x00
7:0
SPE_F2DMON0[7:0]
Received Byte F2[7:0] Current Monitor Value.
0x00
15:8
SPE_F3DMON1[7:0]
Received Byte F3[7:0] Previous Monitor Value.
0x00
7:0
SPE_F3DMON0[7:0]
Received Byte F3[7:0] Current Monitor Value.
0x00
15:8
—
Reserved.
0x00
7:0
SPE_C2DMON[7:0]
Received Byte C2[7:0] Monitor Value.
0x00
Table 153. SPE_MAP_CTL1—SPE_MAP_CTL3, Tx/Rx Control for Mapping Functions (R/W)
Address
Bit
Name
0x30018
15
SPE_T_STS1_MODE
14
13:12
140
Function
Transmit STS-1 Mode. When 1, STS-1 mode is
selected for transmit data; when 0, STS-3/STM-1.
SPE_T_NSMI_MODE
Transmit Serial STS-1 SPE Mode. When 1, serial
data is accepted through an external serial interface
and mapped to STS-1 SPE.
SPE_TDS3SRCTYP[1:0] Transmit DS3 Source Type. Two bit value selects one
of three DS3 input sources.
11
SPE_T_VT_DS3
10
SPE_T_AU3_TUG3
00 or 01 = DS3 data from M13 block.
10 = DS3 data from loopback (Rx to Tx).
11 = DS3 data from external clear channel.
Transmit VT or DS3 Input. When 1, VT input data is
selected; when 0, DS3 input data is selected.
Transmit AU-3/STS-1 or TUG-3 Mapping. When 1,
AU-3/STS-1 mapping is selected; when 0, TUG-3 mapping is selected.
Reset
Default
0
0
00
0
0
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
9 SPE Mapper Registers (continued)
Table 153. SPE_MAP_CTL1—SPE_MAP_CTL3, Tx/Rx Control for Mapping Functions (R/W) (continued)
Address
Bit
0x30018
9:8
7
6
5:4
3
2
1:0
0x30019
Name
Function
SPE_TSTS3TMSLOT[1:0] Transmit STS-3 Time-Slot Value. Two-bit value
selects one of three STS-1 time slots within an STS-3
in the transmit direction.
00 = No output.
01 = STS-1/TUG-3 data for slot 1 in STS-3/STM-1.
10 = STS-1/TUG-3 data for slot 2 in STS-3/STM-1.
11 = STS-1/TUG-3 data for slot 3 in STS-3/STM-1.
SPE_R_STS1_MODE
Receive STS-1 Mode. When 1, STS-1 mode is
selected for receive data. When 0, STS-3/STM-1.
SPE_R_NSMI_MODE
Receive Serial STS-1 SPE Mode. When 1, serial data
demapped from STS-1 SPE is sent out to an external
serial interface.
SPE_RDS3OUTTYP[1:0] Receive DS3 Output Type. Two-bit value selects one
of three DS3 output devices.
00 or 01 = DS3 data to M13 block.
10 = DS3 data to loopback (RX to TX).
11 = DS3 data to external clear channel.
SPE_R_VT_DS3
Receive VT or DS3 Output. When 1, VT data is output; when 0, DS3 data is output.
SPE_R_AU3_TUG3
Receive AU-3/STS-1 or TUG-3 Demapping. When 1,
AU-3/STS-1 demapping is selected; when 0, TUG-3
demapping is selected.
SPE_RSTS3TMSLOT[1:0] Receive STS-3 Time Slot. Selects one of three STS-1
time slots within an STS-3/STM-1 frame in the receive
direction.
15:13
SPE_T_NSMI_BIT[2:0]
12:10
SPE_R_NSMI_BIT[2:0]
9:6
5
—
SPE_TDS3CLK_EDGE
00 = No selection.
01 = STS-1/TUG-3 data from slot 1 in STS-3/STM-1.
10 = STS-1/TUG-3 data from slot 2 in STS-3/STM-1.
11 = STS-1/TUG-3 data from slot 3 in STS-3/STM-1.
Transmit Serial Sync Position Within a Byte Boundary. Selects one of eight positions for the bit sync of the
serial transmit data stream (previously known as the
NSMI interface data).
Receive Serial Sync Position Within a Byte Boundary. Selects one of eight positions for the bit sync of the
serial receive data stream (previously known as the
NSMI interface data).
Reserved.
External DS3 Clock Edge Select for DS3 Input Data
Retiming.
Reset
Default
00
0
0
00
0
0
00
0x0
0x0
0x0
0x0
0 = Negative edge is selected.
1 = Positive edge is selected.
Agere Systems Inc.
141
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
9 SPE Mapper Registers (continued)
Table 153. SPE_MAP_CTL1—SPE_MAP_CTL3, Tx/Rx Control for Mapping Functions (R/W) (continued)
Address
Bit
Name
Function
Reset
Default
0x30019
4
SPE_PHDETUP_INV
Phase Detector Up Signal Invert. When 1, the phase
detector up signal required for an external PLL in DS3
mode, is inverted from its current phase.
0x0
3
SPE_PHDETDN_INV
Phase Detector Down Signal Invert. When 1, the
phase detector down signal required for an external
PLL in DS3 mode, is inverted from its current phase.
0x0
2
SPE_TDS3BPV_IN
Transmit DS3 BPV/Data In. When 1, DS3NEGDATAIN
(K22) input pin is used as external B3ZS bipolar violation indication instead of negative input pulse.
0x00
1
SPE_TDS3_BIPOLAR
Transmit DS3 Bipolar/Unipolar. When 1, the DS3
input is bipolar; when 0, the DS3 input is unipolar.
0x00
0
SPE_RDS3_BIPOLAR
Receive DS3 Bipolar/Unipolar. When 1, the DS3 output is bipolar; when 0, the DS3 output is unipolar.
0x00
15
—
14:8
SPE_T_NSMI_COL[6:0]
7
—
6:0
SPE_R_NSMI_COL[6:0]
0x3001A
142
Reserved.
Transmit Serial Sync Position. Selects one of
90 positions aligned with 90 SONET columns within
SONET row 9 for the bit sync of the serial transmit data
stream (previously known as the NSMI interface data).
0x0
Reserved.
Receive Serial Sync Position. Selects one of 90 positions aligned with 90 SONET columns within SONET
row 9 for the bit sync of the serial transmit data stream
(previously known as the NSMI interface data).
0x0
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
9 SPE Mapper Registers (continued)
Table 154. SPE_TAOH_CTL1—SPE_TAOH_CTL3, Tx Control for Alarm/OH Functions (R/W)
Address
Bit
Name
0x3001B 15:10
0x3001C
—
9
SPE_TD_OEPAR
8
SPE_ TREIRDISEL
7
SPE_TAISPINS
6
Function
Reserved.
Reset
Default
0x00
Transmit Data Odd/Even Parity Generate. When 0, odd
parity is generated for transmit data; when 1, even parity is
generated.
00
REI and RDI Input Select. Control bit, when 1, inserts
REI/RDI value from the protected channel REI/RDI lines;
otherwise, the value is inserted from the direct feedback
(receive to transmit) lines.
0
Force Path AIS in the Output. Active-high.
0
SPE_TN1INS
Transmit N1 Insert Control. Control bit, when 1, inserts
the value in SPE_TN1DINS[7:0] (Table 157) into the outgoing N1 byte in the STS-1 frame; otherwise, the insert value
depends on SPE_TPOAC_N1 (Table 154) control bit.
1
5
SPE_TK3INS
Transmit K3 Insert Control. Control bit, when 1, inserts
the value in SPE_TK3DINS[7:0] (Table 157) into the outgoing K3 bytes; otherwise, the insert value depends on
SPE_TPOAC_K3 (Table 154) control bit.
0
4
SPE_TH4INS
Transmit H4 Insert Control. Control bit, when 1, inserts
the overhead default value SMPR_OH_DEFLT (Table 67)
into the outgoing H4 bytes; otherwise, the insert value
depends on SPE_TPOAC_H4 (Table 154) control bit.
0
3
SPE_TF3INS
Transmit F3 Insert Control. Control bit, when 1, inserts
the value in SPE_TF3DINS[7:0] (Table 157) into the outgoing F3 byte in the STS-1 frame; otherwise, the insert value
depends on SPE_TPOAC_F3 (Table 154) control bit.
1
2
SPE_TF2INS
Transmit F2 Insert Control. Control bit, when 1, inserts
the value in SPE_TF2DINS[7:0] (Table 157) into the outgoing F2 byte in the STS-1 frame; otherwise, the insert value
depends on SPE_TPOAC_F2 (Table 154) control bit.
1
1
SPE_TC2INS
Transmit C2 Insert Control. Control bit, when 1, inserts
the value in SPE_TC2DINS[7:0] (Table 157) into the outgoing C2 byte in the STS-1 frame; otherwise, the insert value
depends on SPE_TPOAC_C2 (Table 154) control bit.
1
0
SPE_TJ1INS
Transmit J1 Insert Control. Control bit, when 1, inserts
the value in SPE_TJ1DINS[1—64][7:0] (Table 163) into the
outgoing J1 bytes; otherwise, the insert value depends on
SPE_TPOAC_J1 (Table 154) control bit.
0
15:8
—
7
Reserved.
SPE_TPOAC_OEPMON Transmit POAC Odd or Even Parity Monitor. When 1,
even parity is checked for transmit POAC channels; otherwise, odd parity is checked.
6
Agere Systems Inc.
SPE_TPOAC_N1
Transmit POAC N1 Byte Control. Control bit, when 0, the
default value is inserted into the N1 byte in the transmit
frame. When 1, the TPOAC value is inserted in the N1 byte.
0x00
0
0
143
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
9 SPE Mapper Registers (continued)
Table 154. SPE_TAOH_CTL1—SPE_TAOH_CTL3, Tx Control for Alarm/OH Functions (R/W) (continued)
Address
Bit
Name
Function
Reset
Default
0x3001C
5
SPE_TPOAC_K3
Transmit POAC K3 Byte Control. Control bit, when 0, the
default value is inserted into the K3 byte in the transmit
frame. When 1, the TPOAC value is inserted in the K3 byte.
0
4
SPE_TPOAC_H4
Transmit POAC H4 Byte Control. Control bit, when 0, the
default value is inserted into the H4 byte in the transmit
frame. When 1, the TPOAC value is inserted in the H4 byte.
0
3
SPE_TPOAC_F3
Transmit POAC F3 Byte Control. Control bit, when 0, the
default value is inserted into the F3 byte in the transmit
frame. When 1, the TPOAC value is inserted in the F3 byte.
0
2
SPE_TPOAC_F2
Transmit POAC F2 Byte Control. Control bit, when 0, the
default value is inserted into the F2 byte in the transmit
frame. When 1, the TPOAC value is inserted in the F2 byte.
0
1
SPE_TPOAC_C2
Transmit POAC C2 Byte Control. Control bit, when 0, the
default value is inserted into the C2 byte in the transmit
frame. When 1, the TPOAC value is inserted in the C2 byte.
0
0
SPE_TPOAC_J1
Transmit POAC J1 Byte Control. Control bit, when 0, the
default value is inserted into the J1 byte in the transmit
frame. When 1, the TPOAC value is inserted in the J1 byte.
0
0x3001D 15:8
SPE_NPI_BYTE2[7:0]
Transmit NPI Byte 2. Programmable value for NPI byte 2 to
be inserted into the NPI byte location.
0
7:0
SPE_NPI_BYTE1[7:0]
Transmit NPI Byte 1. Programmable value for NPI byte 1 to
be inserted into the NPI byte location.
0
0x3001E 15:8
0x00
1
SPE_TTIM_PRDIINH
Transmit Trace Indicator Mismatch RDI Inhibit. Control
bit, when 1, the TIM failure will not contribute to the automatic insertion of RDI-P; otherwise, the associated alarm
contributes to the generation of RDI-P.
0
SPE_TPLM_PRDIINH
Transmit Path Label Mismatch RDI Inhibit. Control bit,
when 1, the PLM failure will not contribute to the automatic
insertion of RDI-P; otherwise, the associated alarm contributes to the generation of RDI-P.
0
SPE_TUNEQ_PRDIINH Transmit Path Unequipped RDI Inhibit. Control bit, when
1, the unequipped failure will not contribute to the automatic
insertion of RDI-P; otherwise, the associated alarm contributes to the generation of RDI-P.
0
SPE_TPRDIINS
6
5
3
Reserved.
Transmit RDI Software Insert. When 1, the value in
SPE_TG1DINS[3:1] is inserted into G1[3:1] in the transmit
frame; otherwise, hardware insert is enabled for RDI-P insertion.
7
4
144
—
SPE_TLOP_PRDIINH
Transmit Loss of Pointer RDI Inhibit. Control bit, when 1,
the loss of pointer failure will not contribute to the automatic
insertion of RDI-P; otherwise, the associated alarm contributes to the generation of RDI-P.
0
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
9 SPE Mapper Registers (continued)
Table 155. SPE_TRDIREI_CTL, Transmit Path RDI and REI Control Register (R/W)
Address
Bit
Name
Function
Reset
Default
0x3001E
2
SPE_TPAIS_PRDIINH
Transmit Path AIS RDI Inhibit. Control bit, when 1, the
path AIS failure will not contribute to the automatic insertion of RDI-P; otherwise, the associated alarm contributes to the generation of RDI-P.
0
1
SPE_TPRDI_MODE
Transmit PRDI Mode. When 1, 3-bit enhanced ERDI
mode is supported; when 0, the 1-bit RDI mode is
supported.
0
0
SPE_TREIP_INH
Transmit REI-P Inhibit. When 1, inhibits automatic insertion of REI-P.
0
Table 156. SPE_TERRINS_CTL, Transmit Error Insertion Control (R/W)
Address
Bit
Name
Function
0x3001F
15:3
—
2
SPE_BERR_INS
Bit Error Insert Control Bit. When 1, bit errors will be
inserted on selected signals (whose error insert bits are set)
each time a pulse occurs on the BER_INS line.
0
1
SPE_TB3ERRINS
Transmit B3 Error Insertion. When 1, the B3 output will be
inverted.
0
0
SPE_TREIERRINS Transmit G1 Error Insert. When 1, an error will be inserted
continuously into the outgoing G1[7:4] bits, until reset to 0.
0
Reserved.
Reset
Default
0x000
Table 157. SPE_TOHINS1—SPE_TOHINS4, Transmit OH Insert Value (R/W)
Address
Bit
0x30020
15:8
SPE_TF3DINS[7:0] Transmit F3 Byte Value. This value is inserted into the
transmit F3 byte.
0x00
7:0
SPE_TF2DINS[7:0] Transmit F2 Byte Value. This value is inserted into the
transmit F2 byte.
0x00
15:8
SPE_TC2DINS[7:0] Transmit C2 Byte Value. This value is inserted into the
transmit C2 byte.
0x00
7:0
SPE_TK3DINS[7:0] Transmit K3 Byte Value. This value is inserted into the
transmit K3 byte.
0x00
15:8
SPE_TG1DINS[7:0] Transmit G1 Byte Value. This value is inserted into the
transmit G1 byte.
0x00
7:0
SPE_TN1DINS[7:0] Transmit N1 Byte Value. This value is inserted into the
transmit N1 byte.
0x00
0x30021
0x30022
0x30023
15:8
7:0
Agere Systems Inc.
Name
—
Function
Reserved.
SPE_TH4DINS[7:0] Transmit H4 Byte Value. This value is inserted into the
transmit H4 byte.
Reset
Default
0x00
0x00
145
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
9 SPE Mapper Registers (continued)
Table 158. SPE_SIGDEG_CTL1—SPE_SIGDEG_CTL6, Signal Degrade BER Algorithm Parameters (R/W)
Address
Bit
Name
0x30024
0x30025
0x30025
15:0
2:0
15
14:7
SPE_SDNSSET[18:3]
SPE_SDNSSET[2:0]
6:3
0x30026
0x30027
0x30028
0x30028
15:0
15:0
2:0
15
14:7
0x30028
6:3
0x30029
15:0
Function
Signal Degrade Ns Set. Number of frames in a
monitoring block for SD.
—
Reserved.
SPE_SDMSET[7:0]
Signal Degrade M Set. Threshold of the number of bad
monitoring blocks in an observation interval. If the
number of bad blocks is above this threshold, then signal
degrade (SD) is set.
SPE_SDLSET[3:0]
Signal Degrade L Set. Error threshold for determining a
bad monitoring block.
SPE_SDBSET[15:0]
Signal Degrade B Set. Number of monitoring blocks.
SPE_SDNSCLEAR[18:3] Signal Degrade Ns Clear. Number of frames in a
SPE_SDNSCLEAR[2:0] monitoring block for SD.
—
Reserved.
SPE_SDMCLEAR[7:0] Signal Degrade M Clear. Threshold of the number of
bad monitoring blocks in an observation interval. If the
number of bad blocks is below this threshold, then SD is
cleared.
SPE_SDLCLEAR[3:0] Signal Degrade L Clear. Error threshold for determining
a bad monitoring block.
SPE_SDBCLEAR[15:0] Signal Degrade B Clear. Number of monitoring blocks.
Reset
Default
0x0000
0
0
0x00
0x0
0x0000
0x0000
0
0
0x00
0x0
0x0000
Table 159. SPE_SIGFAIL_CTL1—SPE_SIGFAIL_CTL6, Signal Fail BER Algorithm Parameters (R/W)
Address
Bit
Name
0x3002A
0x3002B
0x3002B
15:0
2:0
15
14:7
SPE_SFNSSET[18:3]
SPE_SFNSSET[2:0]
0x3002B
6:3
0x3002C
0x3002D
0x3002E
0x3002E
15:0
15:0
2:0
15
14:7
0x3002E
6:3
0x3002F
15:0
146
Function
Signal Fail Ns Set. Number of frames in a monitoring
block for SF.
—
Reserved.
SPE_SFMSET[7:0]
Signal Fail M Set. Threshold of the number of bad
monitoring blocks in an observation interval. If the
number of bad blocks is above this threshold, then signal
fail (SF) is set.
SPE_SFLSET[3:0]
Signal Fail L Set. Error threshold for determining a bad
monitoring block.
SPE_SFBSET[15:0]
Signal Fail B Set. Number of monitoring blocks.
SPE_SFNSCLEAR[18:3] Signal Fail Ns Clear. Number of frames in a monitoring
SPE_SFNSCLEAR[2:0] block for SF.
—
Reserved.
SPE_SFMCLEAR[7:0] Signal Fail M Clear. Threshold of the number of bad
monitoring blocks in an observation interval. If the
number of bad blocks is below this threshold, then SF is
cleared.
SPE_SFLCLEAR[3:0] Signal Fail L Clear. Error threshold for determining a
bad monitoring block.
SPE_SFBCLEAR[15:0] Signal Fail B Clear. Number of monitoring blocks.
Reset
Default
0x0000
0
0
0x00
0x0
0x0000
0x0000
0
0
0x00
0x0
0x0000
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
9 SPE Mapper Registers (continued)
Table 160. SPE_ERRCNT1—SPE_ERRCNT6, B3, G1, Bipolar Violation, and Excess Zero Error Count (RO)
Address
Bit
Name
Function
Reset
Default
0x30030
15:0
SPE_B3ECNT[15:0]
B3 Error Count. The value of internal running counter is
transferred into this holding register coincident with the
end of a performance monitor interval.
0x0000
0x30031
15:0
SPE_G1ECNT[15:0]
G1 Error Count. The value of internal running counter is
transferred into this holding register coincident with the
end of a performance monitor interval.
0x0000
0x30033
0x30033
0x30034
15:8
7:0
15:0
0x30035
0x30035
0x30036
15:8
7:0
15:0
—
Reserved.
SPE_BIPOL_CNT[23:16] Bipolar Coding Violation Occurrence Count. The
SPE_BIPOL_CNT[15:0] value of internal running counter is transferred into this
holding register coincident with the end of a
performance monitor interval.
—
SPE_EXZ_CNT[23:16]]
SPE_EXZ_CNT[15:0]
Reserved.
Excess Zero Occurrence Count. The value of internal
running counter is transferred into this holding register
coincident with the end of a performance monitor
interval.
0x0000
00
0x0000
00
Table 161. SPE_PTRCNT1—SPE_PTRCNT3, Receive Pointer Increment and Decrement Count (RO)
Address
Bit
Name
0x30037
15:10
—
9:0
SPE_STORED_PTR[9:0]
15:11
—
10:0
SPE_RPTR_INC[10:0]
15:11
—
10:0
SPE_RPTR_DEC[10:0]
0x30038
0x30039
Function
Reset
Default
Reserved.
0x00
Stored TU-3 Pointer Location.
0x000
Reserved.
0x00
Pointer Increment Count from Pointer Interpreter
Block. The value of internal running counter is
transferred into this holding register coincident with
the end of a performance monitor interval.
0x000
Reserved.
0x00
Pointer Decrement Count from Pointer
Interpreter Block. The value of internal running
counter is transferred into this holding register
coincident with the end of a performance monitor
interval.
0x000
Table 162. SPE_RJ1MON_R1—SPE_RJ1MON_R32, Receive J1 Monitor Values (RO)
Address
Bit
0x30042
—
0x30061
15:0
Agere Systems Inc.
Name
Function
SPE_RJ1DMON[1—64][7:0] Receive J1 Monitor Value. These registers capture
a 64-byte sequence from the J1 byte of each frame.
Reset
Default
0x00
147
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
9 SPE Mapper Registers (continued)
Table 163. SPE_TJ1DINS_R1—SPE_TJ1DINS_R32, Transmit J1 Insert Values (R/W)
Address
Bit
Name
0x30062
—
0x30081
15:0
SPE_TJ1DINS[1—64][7:0]
Function
Reset
Default
Transmit J1 Insert Value. These registers allow a
64-byte sequence to be inserted into the J1 byte of
each frame.
0x00
Table 164. SPE_RJ1DEXP_R1—SPE_RJ1DEXP_R32, Receive J1 Expected Values (R/W)
Address
Bit
0x30082
—
0x300A1
15:0
Name
Function
Reset
Default
SPE_RJ1DEXP[1—64][7:0] Receive J1 Expected Value. These registers hold a
programmable 64-byte expected sequence for the J1
byte of each frame.
0x00
Table 165. SPE_SCRATCH_R, Scratch Pad (R/W)
Address
Bit
Name
Function
Reset
Default
0x300A2
15:0
SPE_SCRATCH[15:0]
Scratch Register. Allows the control system to verify
read and write operations to the device without
affecting device operation.
0x0000
148
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
9 SPE Mapper Registers (continued)
9.2 SPE Mapper Register Map
Note: In Table 166, the reset default of all reserved bits is 0. Shading denotes reserved bits.
Table 166. SPE Mapper Register Map
Address
Symbol
0x30000
SPE_
VERSION_R
0x30001
—
0x30002
SPE_
ONESHOT
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SPE Version and Identification Registers—RO
SPE_VERSION[2:0]
SPEMPR_ID[7:0]
One Shot (0 to 1 transition) Control Bit Parameters—R/W
SPE_
BIPOL_ERR
SPE_
SFCLEAR
SPE_SFSET
SPE_
SDCLEAR
SPE_SDSET
SPE_
K3DMOND
SPE_
N1DMOND
SPE_
C2DMOND
SPE_
F2DMOND
SPE_
F3DMOND
Delta and Event Parameters—COR/COW
0x30003 SPE_EVENT1
SPE_
RDATA_PE
0x30004 SPE_EVENT2
0x30005 SPE_EVENT3
SPE_PRDI SPE_RNDFE SPE_RDECE SPE_RINCE
DMOND
SPE_RSY5
2LOSD
SPE_
RV1LOSD
SPE_RSPE SPE_RJ0J1 SPE_RDS3
LOSD
V1LOSD
LOCD
SPE_
RC52LOCD
SPE_
RLSLOCD
SPE_
TPOAC_PE
SPE_RAISD SPE_RLOPD SPE_SFB3D SPE_SDB3D
SPE_
TSY52LOSD
SPE_
TV1LOSD
SPE_
RUNEQD
SPE_RPLMD SPE_RTIMD
SPE_
SPE_TJ0J1V
TSPELOSD
1LOSD
SPE_
TDS3LOCD
SPE_
TC52LOCD
SPE_
TLSLOCD
SPE_
K3DMONM
SPE_
C2DMONM
SPE_
F2DMONM
SPE_
F3DMONM
Interrupt Mask Parameters for INT Pins—R/W
0x30006
SPE_MASK1
0x30007
SPE_MASK2
0x30008
SPE_MASK3
0x30009
SPE_STATE1
SPE_
RDATA_PM
SPE_PRDI SPE_RNDFM
DMONM
SPE_RSY5
2LOSM
SPE_
RV1LOSM
SPE_RSPE SPE_RJ0J1 SPE_RDS3
LOSM
V1LOSM
LOCM
SPE_
RC52LOCM
SPE_
RDECM
SPE_
TPOAC_PM
SPE_
N1DMONM
SPE_RINCM SPE_RAISM SPE_RLOPM SPE_SFB3M SPE_SDB3M
SPE_
RLSLOCM
SPE_
TSY52LOSM
SPE_
TV1LOSM
SPE_
TSPELOSM
SPE_TJ0J1V
1LOSM
SPE_RAIS
SPE_RLOP
SPE_SFB3
SPE_SDB3
SPE_
TSY52LOS
SPE_
TV1LOS
SPE_
TSPELOS
SPE_
TJ0J1V1LOS
SPE_
RUNEQM
SPE_
TDS3LOCM
SPE_RPLMM SPE_RTIMM
SPE_
TC52LOCM
SPE_
TLSLOCM
SPE_RUNEQ SPE_RPLM
SPE_RTIM
State and Value Parameters—RO
0x3000A SPE_STATE2
SPE_
RSY52LOS
SPE_
RV1LOS
SPE_
SPE_RJ0J1
SPE_
RSPELOS
V1LOS
RDS3LOC
SPE_
RC52LOC
SPE_
RLSLOC
SPE_
TDS3LOC
SPE_
TC52LOC
SPE_
TLSLOC
Receive Control Parameters for Alarm and Overhead Functions—R/W
0x3000B
SPE_RAOH_
CTL1
0x3000C
SPE_RAOH_
CTL2
0x3000D
SPE_RAOH_
CTL3
Agere Systems Inc.
SPE_RD_
OEPAR
SPE_CNTDLOPCNT[1:0]
SPE_8ORMA
JORITY
SPE_
PAISINS
SPE_J1MONMODE[2:0]
SPE_PAIS_
AISINH
SPE_PAIS_
LOPINH
SPE_AIS_LO
SSY52INH
SPE_AIS_
LOSV1INH
SPE_PAIS_
SFB3INH
SPE_RPRDI SPE_G1BTB SPE_B3BTB SPE_RPOAC
LKCNT
LKCNT
_MODE
_OEPINS
SPE_PAIS_
SDB3INH
SPE_PAIS_
UNEQINH
SPE_PAIS_
PLMINH
SPE_PAIS_
TIMINH
SPE_AIS_LO SPE_AIS_LO SPE_AIS_
SSPEINH
SJ0J1V1INH LOCDS3INH
SPE_AIS_
LOC52INH
SPE_AIS_
LOCINH
149
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155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
9 SPE Mapper Registers (continued)
Table 166. SPE Mapper Register Map (continued)
Address
Symbol
0x3000E
—
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Continuous N-Times Detect Values—R/W
0x3000F
SPE_CNTD1
SPE_CNTDC2[3:0]
SPE_CNTDF3[3:0]
SPE_CNTDF2[3:0]
0x30010
SPE_CNTD2
SPE_CNTDN1[3:0]
SPE_CNTDPRDI[3:0]
SPE_CNTDK3[3:0]
0x30011
SPE_ROHC2
SPE_CNTDJ1[3:0]
Receive Overhead Expected Value for C2 Byte—R/W
SPE_C2DEXP[7:0]
Receive Monitor Values—RO
0x30012
SPE_RMON1
0x30013
SPE_RMON2
SPE_N1DMON[7:0]
SPE_K3DMON[7:0]
SPE_PRDIDMON[2:0]
0x30014
SPE_RMON3
SPE_F2DMON1[7:0]
SPE_F2DMON0[7:0]
0x30015
SPE_RMON4
SPE_F3DMON1[7:0]
SPE_F3DMON0[7:0]
0x30016
SPE_RMON5
0x30017
—
SPE_C2DMON[7:0]
Transmit/Receive Control Parameters for Mapping Functions—R/W
0x30018
SPE_MAP_CTL1 SPE_T_ST
S1_MODE
0x30019
SPE_MAP_CTL2
0x3001A
SPE_MAP_CTL3
SPE_T_NS
MI_MODE
SPE_TDS3SRCTYP[1:0]
SPE_T_NSMI_BIT[2:0]
SPE_T_
VT_DS3
SPE_T_
SPE_TSTS3TMSLOT[1:0] SPE_R_STS SPE_R_NS
AU3_TUG3
1_MODE
MI_MODE
SPE_R_NSMI_BIT[2:0]
SPE_RDS3OUTTYP[1:0]
SPE_R_
VT_DS3
SPE_R_ SPE_RSTS3TMSLOT[1:0]
AU3_TUG3
SPE_TDS3 SPE_PHDE SPE_PHDE SPE_TDS3
CLK_EDGE TUP_INV
TDN_INV
BPV_IN
SPE_T_NSMI_COL[6:0]
SPE_TDS3 SPE_RDS3
_BIPOLAR _BIPOLAR
SPE_R_NSMI_COL[6:0]
Transmit Control Parameters for Alarm and Overhead Functions—R/W
0x3001B
SPE_TAOH_
CTL1
0x3001C
SPE_TAOH_
CTL2
0x3001D
SPE_TAOH_
CTL3
0x3001E
SPE_TRDIREI_
CTL
SPE_TD_
OEPAR
SPE_TREIR
DISEL
SPE_
TAISPINS
SPE_
TN1INS
SPE_
TK3INS
SPE_
TH4INS
SPE_TPOA
SPE_
SPE_
SPE_
C_OEPMON TPOAC_N1 TPOAC_K3 TPOAC_H4
SPE_NPI_BYTE2[7:0]
SPE_
TF3INS
SPE_
TF2INS
SPE_
TC2INS
SPE_
TJ1INS
SPE_
TPOAC_F3
SPE_
TPOAC_F2
SPE_
TPOAC_C2
SPE_
TPOAC_J1
SPE_NPI_BYTE1[7:0]
Transmit Path RDI and REI Control Parameters—R/W
150
SPE_TPRDII SPE_TTIM_ SPE_TPLM SPE_TUNE SPE_TLOP SPE_TPAIS SPE_TPRDI SPE_TREIP
NS
PRDIINH
_PRDIINH Q_PRDIINH _PRDIINH _PRDIINH
_MODE
_INH
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
9 SPE Mapper Registers (continued)
Table 166. SPE Mapper Register Map (continued)
Address
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Transmit Error Insertion Control Parameters—R/W
0x3001F
SPE_TERRINS_CTL
SPE_BERR_INS
SPE_TB3ERRINS SPE_TREIERRINS
Transmit OH Insert Value—R/W
0x30020
SPE_TOHINS1
SPE_TF3DINS[7:0]
0x30021
SPE_TOHINS2
SPE_TC2DINS[7:0]
SPE_TF2DINS[7:0]
SPE_TK3DINS[7:0]
0x30022
SPE_TOHINS3
SPE_TG1DINS[7:0]
SPE_TN1DINS[7:0]
0x30023
SPE_TOHINS4
SPE_TH4DINS[7:0]
Signal Degrade Set/Clear Control Registers—R/W
0x30024
SPE_SIGDEG_CTL1
0x30025
SPE_SIGDEG_CTL2
0x30026
SPE_SIGDEG_CTL3
0x30027
SPE_SIGDEG_CTL4
0x30028
SPE_SIGDEG_CTL5
0x30029
SPE_SIGDEG_CTL6
0x3002A
SPE_SIGFAIL_CTL1
0x3002B
SPE_SIGFAIL_CTL2
0x3002C
SPE_SIGFAIL_CTL3
0x3002D
SPE_SIGFAIL_CTL4
0x3002E
SPE_SIGFAIL_CTL5
0x3002F
SPE_SIGFAIL_CTL6
SPE_SDNSSET[18:3]
SPE_SDMSET[7:0]
SPE_SDLSET[3:0]
SPE_SDNSSET[2:0]
SPE_SDBSET[15:0]
SPE_SDNSCLEAR[18:3]
SPE_SDMCLEAR[7:0]
SPE_SDLCLEAR[3:0]
SPE_SDNSCLEAR[2:0]
SPE_SDBCLEAR[15:0]
Signal Fail Set/Clear Control Registers—R/W
Agere Systems Inc.
SPE_SFNSSET[18:3]
SPE_SFMSET[7:0]
SPE_SFLSET[3:0]
SPE_SFNSSET[2:0]
SPE_SFBSET[15:0]
SPE_SFNSCLEAR[18:3]
SPE_SFMCLEAR[7:0]
SPE_SFLCLEAR[3:0]
SPE_SFNSCLEAR[2:0]
SPE_SFBCLEAR[15:0]
151
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
9 SPE Mapper Registers (continued)
Table 166. SPE Mapper Register Map (continued)
Addr
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
0x30030
SPE_ERRCNT1
SPE_B3ECNT[15:0]
0x30031
SPE_ERRCNT2
SPE_G1ECNT[15:0]
0x30032
—
0x30033
SPE_ERRCNT3
0x30034
SPE_ERRCNT4
0x30035
SPE_ERRCNT5
0x30036
SPE_ERRCNT6
0x30037
SPE_PTRCNT1
0x30038
SPE_PTRCNT2
SPE_RPTR_INC[10:0]
SPE_RPTR_DEC[10:0]
Bit 3
Bit 2
Bit 1
Bit 0
B3 and G1 Error Counts—RO
Bipolar Violation and Excess Zero Counts for DS3—RO
SPE_BIPOL_CNT[23:16]
SPE_BIPOL_CNT[15:0]
SPE_EXZ_CNT[23:16]
SPE_EXZ_CNT[15:0]
Receive Pointer Increment and Decrement Counts—RO
SPE_STORED_PTR[9:0]
0x30039
SPE_PTRCNT3
0x3003A
—
0x30041
—
0x30042
—
0x30061
SPE_RJ1MON_R1
—
SPE_RJ1MON_R32
SPE_RJ1DMON[2][7:0]
—
SPE_RJ1DMON[64][7:0]
0x30062
—
0x30081
SPE_TJ1DINS_R1
—
SPE_TJ1DINS_R32
SPE_TJ1DINS[2][7:0]
—
SPE_TJ1DINS[64][7:0]
0x30082
—
0x300A1
SPE_RJ1DEXP_R1
—
SPE_RJ1DEXP_R32
SPE_RJ1DEXP[2][7:0]
—
SPE_RJ1DEXP[64][7:0]
0x300A2
SPE_SCRATCH_R
0x300A3
—
0x301FF
—
J1 Byte Receive Monitor—RO
SPE_RJ1DMON[1][7:0]
—
SPE_RJ1DMON[63][7:0]
J1 Byte Transmit Insert—R/W
SPE_TJ1DINS[1][7:0]
—
SPE_TJ1DINS[63][7:0]
J1 Byte Expected Values—R/W
SPE_RJ1DEXP[1][7:0]
—
SPE_RJ1DEXP[63][7:0]
Scratch Register—R/W
152
SPE_SCRATCH[15:0]
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
10 VT/TU Mapper Registers
Table of Contents
Contents
Page
10 VT/TU Mapper Registers ................................................................................................................................ 153
10.1 VT/TU Mapper Register Descriptions ..................................................................................................... 154
10.2 VT/TU Mapper Register Map .................................................................................................................. 171
Tables
Page
Table 167. VT_VERSION_R, VT Mapper Ready, Version, and Identification (RO) ............................................ 154
Table 168. VT_GDELTA, VT Global Deltas (COR/COW) ................................................................................... 154
Table 169. VT_REVENT_DELTA[1—28], Receive Event and Delta Per Channel (COR/COW) ........................ 155
Table 170. VT_LOPOHFAIL_EVENT, Low-Order Path Overhead Failure Event (COR/COW) .......................... 155
Table 171. VT_TEVENT_DELTA[1—28], Transmit Event and Delta Per Channel (COR/COW) ........................ 156
Table 172. VT_GMASK, VT Global Masks (R/W) ............................................................................................... 156
Table 173. VT_RMASK[1—28], Receive Masks Per Channel (R/W) .................................................................. 157
Table 174. VT_LOPOHFAIL_MASK, Low-Order Path Overhead Failure Mask (R/W) ....................................... 158
Table 175. VT_TMASK[1—28], Transmit Masks Per Channel (R/W) ................................................................. 158
Table 176. VT_GSTATE, VT Global State (RO) ................................................................................................. 158
Table 177. VT_RSTATE[1—28], Receive State Per Channel (RO) .................................................................... 159
Table 178. VT_RAPSSTATE[1—28], Receive APS State Per Channel (RO) ..................................................... 159
Table 179. VT_TSTATE[1—28], Transmit State Per Channel (RO) ................................................................... 159
Table 180. VT_GCTL1, VT Global Control Register 1 (R/W) .............................................................................. 160
Table 181. VT_GCTL2, VT Global Control Register 2 (R/W) .............................................................................. 160
Table 182. VT_GCTL3, VT Global Control Register 3 (R/W) .............................................................................. 161
Table 183. VT_GCTL4, VT Global Control Register 4 (R/W) .............................................................................. 161
Table 184. VT_GCTL5, VT Global Control Register 5 (R/W) .............................................................................. 162
Table 185. VT_SIGDEG_CTL1, Signal Degrade Control Register 1 (R/W) ........................................................ 163
Table 186. VT_SIGDEG_CTL2, Signal Degrade Control Register 2 (R/W) ........................................................ 163
Table 187. VT_SIGDEG_CTL3, Signal Degrade Control Register 3 (R/W) ........................................................ 163
Table 188. VT_SIGDEG_CTL4, Signal Degrade Control Register 4 (R/W) ........................................................ 163
Table 189. VT_SIGDEG_CTL5, Signal Degrade Control Register 5 (R/W) ........................................................ 164
Table 190. VT_SIGDEG_CTL6, Signal Degrade Control Register 6 (R/W) ........................................................ 164
Table 191. VT_SIGDEG_CTL7, Signal Degrade Control Register 7 (R/W) ........................................................ 164
Table 192. VT_SIGFAIL_CTL1, Signal Fail Control Register 1 (R/W) ................................................................ 164
Table 193. VT_SIGFAIL_CTL2, Signal Fail Control Register 2 (R/W) ................................................................ 164
Table 194. VT_SIGFAIL_CTL3, Signal Fail Control Register 3 (R/W) ................................................................ 164
Table 195. VT_SIGFAIL_CTL4, Signal Fail Control Register 4 (R/W) ................................................................ 165
Table 196. VT_SIGFAIL_CTL5, Signal Fail Control Register 5 (R/W) ................................................................ 165
Table 197. VT_SIGFAIL_CTL6, Signal Fail Control Register 6 (R/W) ................................................................ 165
Table 198. VT_TCTL[1—28], Transmit Control Per Channel (R/W) ................................................................... 166
Table 199. VT_TTUOH_CTL[1—28], Transmit TU Overhead Control Per Channel (R/W) ................................. 167
Table 200. VT_TAPSRIVAL[1—28], Transmit APS and Remote Indication Per Channel (R/W) ........................ 167
Table 201. VT_TSWOW[1—28], Transmit Software Overwrite Per Channel (R/W) ........................................... 167
Table 202. VT_TSIG_CTL[1—28], Transmit Signaling Control Per Channel (R/W) ........................................... 168
Table 203. VT_J2BYTE_INS_R[1—28][1—16], J2 Insert Values Per Channel (R/W) ........................................ 168
Table 204. VT_RCTL[1—28], Receive Control Per Channel (R/W) .................................................................... 168
Table 205. VT_RTUOH_CTL[1—28], Receive TU Overhead Control Per Channel (RO) ................................... 169
Table 206. VT_RBIP2_CNT[1—28], Receive BIP-2 Error Count Per Channel (RO) .......................................... 169
Table 207. VT_RREIV_CNT[1—28], Receive REI-V Error Count Per Channel (RO) ......................................... 169
Table 208. VT_RPTR_CNT[1—28], Receive Pointer and Count Per Channel (RO) .......................................... 170
Table 209. VT_J2BYTE_EXP_R[1—28][1—16], J2 Expected Values Per Channel (R/W, RO) ......................... 170
Table 210. VT_THRES_CTL[1—28], Transmit Elastic Store Threshold Control (R/W) ...................................... 170
Table 211. VT/TU Mapper Register Map ............................................................................................................. 171
Agere Systems Inc.
153
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
10 VT/TU Mapper Registers (continued)
10.1 VT/TU Mapper Register Descriptions
The following tables describe the functions of all bits in the register map. For each address, the register bits are
indicated as either read/write (R/W) or read only (RO), and the value of the bits on reset is given.
Table 167. VT_VERSION_R, VT Mapper Ready, Version, and Identification (RO)
Address
Bit
Name
Function
0x20000
15
VT_RDY
14:11
10:8
—
VT_VERSION[2:0]
7:0
VT_ID[7:0]
VT/TU Mapper Ready. A 1 indicates that the VT/TU mapper is ready for microprocessor reads and writes.
Reserved.
Block Version Number. These bits identify the version
number of the VT/TU mapper.
Block ID Number. VT_ID returns a fixed value (0x02)
when read.
Reset
Default
0x0
0x0
NA
0x02
Table 168. VT_GDELTA, VT Global Deltas (COR/COW)
Address
Bit
Name
Function
0x20001
15:3
2
—
VT_SD_D
1
VT_SF_D
0
VT_H4LOMF_D
Reserved.
VT/TU Signal Degrade Delta Bit. Logic 1 indicates a
change in the signal degrade condition based on the internal bit error rate detector.
VT/TU Signal Fail Delta Bit. Logic 1 indicates a change
in the signal fail condition based on the internal bit error
rate detector.
H4 Mismatch Delta Bit. Logic 1 indicates a change in the
H4 loss of multiframe condition.
154
Reset
Default
0x000
0x1
0x1
0x1
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
10 VT/TU Mapper Registers (continued)
Table 169. VT_REVENT_DELTA[1—28], Receive Event and Delta Per Channel (COR/COW)
Address
Bit
Name
Function
0x20002
—
0x2001D
15
—
14
VT_RX_VTREI_E[1—28]
Reserved.
Reset
Default
0
Receive REI-V Event Bit. Logic 1 indicates that
REI-V was received.
0x0
13
VT_RX_BIP2ERR_E[1—28] Receive BIP-2 Error Event Bit. Logic 1 indicates
that BIP-2 errors have been detected.
0x0
12
VT_RX_ESOVFL_E[1—28]
Receive Elastic Store Overflow Event Bit. Logic
one indicates an elastic store overflow.
0x0
11
VT_APS_D[1—28]
ERDI-V Delta Bit. Logic 1 indicates a VTAPS
change of value.
0x1
10
VT_ERDI_D[1—28]
ERDI-V Delta Bit. Logic 1 indicates an ERDI-V
change of value.
0x1
9
VT_RDI_D[1—28]
RDI-V Delta Bit. Logic 1 indicates an RDI-V
change of value.
0x1
8
VT_RFI_D[1—28]
RFI-V Delta Bit. Logic 1 indicates an RFI-V
change of value.
0x1
7
—
6
VT_LOPS_D[1—28]
VT Loss of Phase Sync Delta Bit. Logic 1 indicates a change of VTLOPS state.
0x1
5
VT_J2TIM_D[1—28]
J2 Trace Identifier Mismatch. Logic 1 indicates a
change of J2TIM state.
0x1
4
VT_PLM_D[1—28]
VT Payload Label Mismatch Delta Bit. Logic 1
indicates a change of VTPLM state.
0x1
3
VT_UNEQ_D[1—28]
VT Unequip Delta Bit. Logic 1 indicates a change
of VTUNEQ state.
0x1
2
VT_SIZERR_D[1—28]
VT Size Error Delta Bit. Logic 1 indicates a
change of VTSIZERR state.
0x1
1
VT_AIS_D[1—28]
AIS-V Delta Bit. Logic 1 indicates a change of
VTAIS state.
0x0
0
VT_LOP_D[1—28]
LOP-V Delta Bit. Logic 1 indicates a change of
VTLOP state.
0x1
Reserved.
0
Table 170. VT_LOPOHFAIL_EVENT, Low-Order Path Overhead Failure Event (COR/COW)
Address
Bit
Name
0x2001E
15:1
—
0
VT_LOPOH_FAIL_E
Agere Systems Inc.
Function
Reserved.
Low-Order Path Overhead Failure Event Bit. Logic 1
indicates that a failure has occurred on the LOPOH
serial access channel.
Reset
Default
0x000
0x0
155
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
10 VT/TU Mapper Registers (continued)
Table 171. VT_TEVENT_DELTA[1—28], Transmit Event and Delta Per Channel (COR/COW)
Address
Bit
Name
0x2001F
—
0x2003A
15:5
—
4
Function
Reset
Default
Reserved.
0x000
VT_TX_ESOVFL_E[1—28] Transmit Elastic Store Overflow Event Bit. Logic
1 indicates an elastic store overflow.
Reserved.
0x0
3
—
0
2
VT_LOFS_D[1—28]
Loss of Frame Sync Delta Bit. Logic 1 indicates a
change of VT_LOFS[1—28] (Table 179) state.
0x1
1
VT_TX_AIS_D[1—28]
Transmit AIS Delta Bit. Logic 1 indicates a change
of VT_TX_AIS[1—28] (Table 179) state.
0x0
0
VT_TX_LOC_D[1—28]
Transmit Loss of Clock Delta Bit. Logic 1 indicates a change of VT_TX_LOC[1—28] (Table 179)
state.
0x1
Table 172. VT_GMASK, VT Global Masks (R/W)
Address
Bit
Name
0x2003B
15:3
—
2
VT_SD_M
VT/TU Signal Degrade Mask Bit. If set to a logic 1,
VT_SD_D (Table 168) will not contribute to the interrupt.
0x1
1
VT_SF_M
VT/TU Signal Fail Mask Bit. If set to a logic 1, VT_SF_D
(Table 168) will not contribute to the interrupt.
0x1
0
VT_H4LOMF_M
H4 Mismatch Mask Bit. If set to a logic 1,
VT_H4LOMF_D (Table 168) will not contribute to the
interrupt.
0x1
156
Function
Reset
Default
Reserved.
0x000
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
10 VT/TU Mapper Registers (continued)
Table 173. VT_RMASK[1—28], Receive Masks Per Channel (R/W)
Note: The event and delta bits for these mask bits are in Table 169.
Address
Bit
Name
0x2003C
—
0x20057
15
—
14
VT_RX_VTREI_M[1—28]
Function
Reserved.
Receive REI-V Mask Bit. If set to a logic 1,
VT_RX_VTREI_E[1—28] will not contribute to the interrupt.
Reset
Default
0
0x1
13
VT_RX_BIP2ERR_M[1—28] Receive BIP-2 Error Mask Bit. If set to a logic 1,
VT_RX_BIP2ERR_E[1—28] will not contribute to the
interrupt.
0x1
12
VT_RX_ESOVFL_M[1—28] Receive Elastic Store Overflow Mask Bit. If set to a
logic 1, VT_RX_ESOVFL_E[1—28] will not contribute to
the interrupt.
0x1
11
VT_APS_M[1—28]
VT APS Mask Bit. If set to a logic 1, VT_APS_D[1—28]
will not contribute to the interrupt.
0x1
10
VT_ERDI_M[1—28]
ERDI-V Mask Bit. If set to a logic 1, VT_ERDI_D[1—28]
will not contribute to the interrupt.
0x1
9
VT_RDI_M[1—28]
RDI-V Mask Bit. If set to a logic 1, VT_RDI_D[1—28] will
not contribute to the interrupt.
0x1
8
VT_RFI_M[1—28]
RFI-V Mask Bit. If set to a logic 1, VT_RFI_D[1—28] will
not contribute to the interrupt.
0x1
7
—
6
VT_LOPS_M[1—28]
VT Loss of Phase Sync Mask Bit. If set to a logic 1,
VT_LOPS_D[1—28] will not contribute to the interrupt.
0x1
5
VT_J2TIM_M[1—28]
J2 Mismatch Mask Bit. If set to a logic 1,
VT_J2TIM_D[1—28] will not contribute to the interrupt.
0x1
4
VT_PLM_M[1—28]
VT Payload Label Mismatch Mask Bit. If set to a logic
1, VT_PLM_D[1—28] will not contribute to the interrupt.
0x1
3
VT_UNEQ_M[1—28]
VT Unequip Mask Bit. If set to a logic 1,
VT_UNEQ_D[1—28] will not contribute to the interrupt.
0x1
2
VT_SIZERR_M[1—28]
VT Size Error Mask Bit. If set to a logic 1,
VT_SIZERR_D[1—28] will not contribute to the interrupt.
0x1
1
VT_AIS_M[1—28]
AIS-V Mask Bit. If set to a logic 1, VT_AIS_D[1—28] will
not contribute to the interrupt.
0x1
0
VT_LOP_M[1—28]
LOP-V Mask Bit. If set to a logic 1, VT_LOP_D[1—28]
will not contribute to the interrupt.
0x1
Agere Systems Inc.
Reserved.
0
157
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
10 VT/TU Mapper Registers (continued)
Table 174. VT_LOPOHFAIL_MASK, Low-Order Path Overhead Failure Mask (R/W)
Address
Bit
Name
0x20058
15:1
—
0
VT_LOPOH_FAIL_M
Function
Reset
Default
Reserved.
0x000
Low-Order Path Overhead Failure Mask Bit. If set to a
logic 1, VT_LOPOH_FAIL_E (Table 170) will not contribute to the interrupt.
0x1
Table 175. VT_TMASK[1—28], Transmit Masks Per Channel (R/W)
Address
Bit
Name
0x20059
—
0x20074
15:5
—
4
Function
Reset
Default
Reserved.
0x000
VT_TX_ESOVFL_M[1—28] Transmit Elastic Store Overflow Mask Bit. If set
to a logic 1, VT_TX_ESOVFL_E[1—28] (Table 171)
will not contribute to the interrupt.
Reserved.
0x1
3
RESERVED
0
2
VT_LOFS_M[1—28]
Loss of Frame Sync Mask Bit. If set to a logic 1,
VT_LOFS_D[1—28] (Table 171) will not contribute
to the interrupt.
0x1
1
VT_TX_AIS_M[1—28]
Transmit AIS Mask Bit. If set to a logic 1,
VT_TX_AIS_D[1—28] (Table 171) will not contribute to the interrupt.
0x1
0
VT_TX_LOC_M[1—28]
Transmit Loss of Clock Mask Bit. If set to a logic
1, VT_TX_LOC_D[1—28] (Table 171) will not contribute to the interrupt.
0x1
Table 176. VT_GSTATE, VT Global State (RO)
Address
Bit
Name
0x20075
15:3
—
2
VT_SD
VT/TU Signal Degrade. Logic 1 indicates a signal
degrade condition on the selected channel.
0x1
1
VT_SF
VT/TU Signal Fail. Logic 1 indicates a signal fail condition
on the selected channel.
0x1
0
VT_H4LOMF
H4 Loss of Multiframe. Logic 1 indicates a loss of H4
multiframe alignment.
0x1
158
Function
Reset
Default
Reserved.
0x000
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
10 VT/TU Mapper Registers (continued)
Table 177. VT_RSTATE[1—28], Receive State Per Channel (RO)
Address
Bit
Name
Function
Reset
Default
VT_ERDI[1—28][2:0]
Enhanced RDI-V Value. These bits are the stored ERDI-V
bits received in the Z7 byte.
0x000
VT_LAB[1—28][2:0]
VT Signal Label. These bits are the stored VT signal label
bits received in the V5 byte.
0x000
9
VT_RDI[1—28]
RDI-V Value. This bit is the accepted RDI-V bit received in
the V5 byte.
0x00
8
VT_RFI[1—28]
RFI-V Value. This bit is the accepted RFI-V bit received in
the V5 byte.
0x00
7
—
6
VT_LOPS[1—28]
VT Loss of Phase Sync. Logic 1 indicates a loss of P-bit
phase synchronization.
0x1
5
VT_J2TIM[1—28]
J2 Trace Identifier Mismatch. Logic 1 indicates a mismatch between the expected trace and the detected trace.
0x1
4
VT_PLM[1—28]
VT Payload Label Mismatch. Logic 1 indicates PLM-V.
0x1
3
VT_UNEQ[1—28]
VT Unequip. Logic 1 indicates UNEQ-V.
0x1
2
VT_SIZERR[1—28]
VT Size Error. Logic 1 indicates a VT size error.
0x1
1
VT_AIS[1—28]
AIS-V. Logic 1 indicates AIS-V.
0x0
0
VT_LOP[1—28]
LOP-V. Logic 1 indicates LOP-V.
0x1
0x20076 15:13
—
0x20091 12:10
Reserved.
0
Table 178. VT_RAPSSTATE[1—28], Receive APS State Per Channel (RO)
Address
Bit
Name
0x20092
—
0x200AD
15:4
—
3:0
VT_APS[1—28][3:0]
Function
Reserved.
Reset
Default
0x000
VT APS Value. These bits are the stored VT APS bits
received in the Z7/K4 byte.
0x0
Table 179. VT_TSTATE[1—28], Transmit State Per Channel (RO)
Address
Bit
Name
0x200AE
—
0x200C9
15:3
—
2
VT_LOFS[1—28]
1
0
Agere Systems Inc.
Function
Reserved.
Reset
Default
0x000
Loss of Frame Sync. Logic 1 indicates DS1/E1 loss of
frame sync.
0x1
VT_TX_AIS[1—28]
Transmit AIS. Logic 1 indicates DS1/E1 AIS.
0x0
VT_TX_LOC[1—28]
Transmit Loss of Clock. Logic 1 indicates DS1/E1 loss
of clock.
0x1
159
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
10 VT/TU Mapper Registers (continued)
Table 180. VT_GCTL1, VT Global Control Register 1 (R/W)
Address
Bit
Name
0x200CA
15
—
Function
Reset
Default
Reserved.
0
14:8 VT_RX_GRP_TYPE[6:0] Receive Group Type. VT/TU group type selection.
Logic 1 selects VT1.5/TU-11 and logic 0 selects
VT2/TU-12 group type. Group 1 is the LSB.
7
6:0
—
Reserved.
0x7F
0
VT_TX_GRP_TYPE[6:0] Transmit Group Type. VT/TU group type selection.
Logic 1 selects VT1.5/TU-11 and logic 0 selects
VT2/TU-12 group type. Group 1 is the LSB.
0x7F
Table 181. VT_GCTL2, VT Global Control Register 2 (R/W)
Address
Bit
0x200CB 15:11
10
9
—
VT_LOPS_AIS_INH
Function
Reset
Default
Reserved.
0x00
VT/TU Loss of Phase Sync. Contribution to AIS inhibit
control.
0x0
VT_J2TIM_ERDI_INH J2 Trace Identifier Mismatch. Contribution to ERDI
inhibit control.
0x0
8
VT_J2TIM_RDI_INH
J2 Trace Identifier Mismatch. Contribution to RDI inhibit
control.
0x0
7
VT_J2TIM_AIS_INH
J2 Trace Identifier Mismatch. Contribution to AIS inhibit
control.
0x0
6
VT_LOMF_AIS_INH
Loss of Multiframe. Contribution to AIS inhibit control.
0x0
5
VT_PLM_AIS_INH
Payload Label Mismatch. Contribution to AIS inhibit control.
0x0
4
VT_UNEQ_AIS_INH
UNEQ-V. Contribution to AIS inhibit control.
0x0
3
—
2
VT_UPSR
Unidirectional Path Switch Ring Mode Control. Logic 1
activates the UPSR mode of operation. When the device
is programmed for UPSR mode, the transmitted REI-V,
RDI-V, RFI-V, and ERDI-V are based on the receive conditions. Otherwise, the transmitted LOPOH is a copy of the
received overhead bytes.
0x0
1
VT_8ORMAJORITY
VT Pointer Interpreter Mode Control. Logic 1 tells the
pointer interpreter to transition into the inc and dec states
based on 8 of the 10 I and D bits. Otherwise, the pointer
interpreter transitions into the inc and dec states based on
majority rule.
0x1
0
160
Name
Reserved.
0
VT_BIT_BLOCK_CNT Performance Monitor Count Mode Control. Logic 1
activates BIP-2, TC-BIP-2, REI, and TC-CRC-7 counts
based on single bit errors. Otherwise, errors are counted
on a block basis.
0x1
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
10 VT/TU Mapper Registers (continued)
Table 182. VT_GCTL3, VT Global Control Register 3 (R/W)
Address
Bit
Name
0x200CC
15:8
—
7:4
3:0
Function
Reserved.
0x00
VT_LOPS_NTIME[3:0] VT/TU Loss of Phase Sync NTIME Detection Control.
This nibble is programmed to provision the number of consecutive errored phase indications required to transition
into the VT_LOPS[1—28] (Table 177) state. Only valid in
byte synchronous mode.
Note: The valid range of values is 0x1—0xF. A value of
0x0 will be mapped to 0x1.
VT_H4_NTIME[3:0]
Reset
Default
H4 Multiframe Indication NTIME Detection Control.
This nibble is programmed to provision the number of consecutive errored multiframe indications required to transition into the VT_H4LOMF (Table 176) state.
Note: The valid range of values is 0x1—0xF. A value of
0x0 will be mapped to 0x1.
0x6
0x6
Table 183. VT_GCTL4, VT Global Control Register 4 (R/W)
Address
Bit
Name
Function
Reset
Default
0x200CD
15:11
VT_Z6_NTIME[3:0]
Z6 Byte Monitor NTIME Detection Control. This nibble
is programmed to provision the number of consecutive
consistent Z6 bytes required to accept a new value.
Note: The valid range of values is 0x1—0xF. A value of
0x0 will be mapped to 0x1.
0x3
11:8
VT_J2_NTIME[3:0]
J2 Byte Monitor NTIME Detection Control. This nibble
is programmed to provision the number of consecutive
consistent J2 sequences required for the J2 byte monitor
to transition in and out of J2TIM.
Note: The valid range of values is 0x1—0xF. A value of
0x0 will be mapped to 0x1.
0x3
7:4
VT_INV_NTIME[3:0]
Pointer Interpreter Invalid Pointer NTIME Detection
Control. This nibble is programmed to provision the
number of invalid pointers required for the pointer interpreter to go into the VT_LOP[1—28] (Table 177) state.
Note: The valid range of values is 0x1—0xF. A value of
0x0 will be mapped to 0x1.
0x8
3:0
VT_NDF_NTIME[3:0]
Pointer Interpreter NDF Pointer NTIME Detection
Control. This nibble is programmed to provision the
number of consecutive NDF pointers required for the
pointer interpreter to go into the VT_LOP state.
Note: The valid range of values is 0x1—0xF. A value of
0x0 will be mapped to 0x1.
0x8
Agere Systems Inc.
161
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
10 VT/TU Mapper Registers (continued)
Table 184. VT_GCTL5, VT Global Control Register 5 (R/W)
Address
Bit
Name
Function
Reset
Default
0x200CE 15:12
VT_APS_NTIME[3:0]
APS NTIME Detection Control. This nibble is programmed
to provision the number of consecutive consistent new values
required to accept a new VT_APS[1—28][3:0] (Table 178).
Note: The valid range of values is 0x1—0xF. A value of 0x0
will be mapped to 0x1.
0x3
11:8
VT_LAB_NTIME[3:0]
VT Signal Label NTIME Detection Control. This nibble is
programmed to provision the number of consecutive consistent new values required to accept a new
VT_LAB[1—28][2:0] (Table 177).
Note: The valid range of values is 0x1—0xF. A value of 0x0
will be mapped to 0x1.
0x3
7:4
VT_ERDI_NTIME[3:0] ERDI-V NTIME Detection Control. This nibble is programmed to provision the number of consecutive consistent
new values required to accept a new VT_ERDI[1—28][2:0]
(Table 177).
Note: The valid range of values is 0x1—0xF. A value of 0x0
will be mapped to 0x1.
0x3
3:0
162
VT_RDI_NTIME[3:0]
RDI-V NTIME Detection Control. This nibble is programmed to provision the number of consecutive consistent
new values required to accept a new VT_RDI[1—28]
(Table 177).
Note: The valid range of values is 0x1—0xF. A value of 0x0
will be mapped to 0x1.
0x3
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
10 VT/TU Mapper Registers (continued)
Table 185. VT_SIGDEG_CTL1, Signal Degrade Control Register 1 (R/W)
Address
Bit
0x200CF 15:12
Name
—
Function
Reset
Default
Reserved.
0x00
11
VT_SFCLEAR
VT Signal Fail Clear. Allows the signal fail algorithm to be
forced into the normal state. This is a one shot which is
activated by a 0 to 1 transition.
0x0
10
VT_SFSET
VT Signal Fail Set. Allows the signal fail algorithm to be
forced into the failed state. This is a one shot which is activated by a 0 to 1 transition.
0x0
9
VT_SDCLEAR
Signal Degrade Clear. Allows the signal degrade algorithm to be forced into the normal state. This is a one shot
which is activated by a 0 to 1 transition.
0x0
8
VT_SDSET
Signal Degrade Set. Allows the signal degrade algorithm
to be forced into the failed state. This is a one shot which
is activated by a 0 to 1 transition.
0x0
7:5
—
Reserved.
000
4:0
VT_BER_CH_
SEL[4:0]
Bit Error Rate Monitor Channel Select. Selects which
channel (1—28/21) is being monitored by the internal
BER monitor. Valid inputs are 00001—11100.
0x00
Table 186. VT_SIGDEG_CTL2, Signal Degrade Control Register 2 (R/W)
Address
Bit
Name
Function
Reset
Default
0x200D0
15:0
VT_SDNSSET[18:3]
Signal Degrade Ns Set. Number of frames in a monitoring block for SD.
0x0000
Table 187. VT_SIGDEG_CTL3, Signal Degrade Control Register 3 (R/W)
Address
Bit
Name
Function
0x200D1
15
—
14:7
VT_SDMSET[7:0]
Signal Degrade M Set. Threshold of the number of bad
monitoring blocks in an observation interval. If the number
of bad blocks is above this threshold, then signal degrade
SD is set.
0x00
6:3
VT_SDLSET[3:0]
Signal Degrade L Set. Error threshold for determining if a
monitoring block is bad.
0x0
2:0
VT_SDNSSET[2:0]
Signal Degrade Ns Set. Number of frames in a monitoring block for SD.
0x0
Reserved.
Reset
Default
0
Table 188. VT_SIGDEG_CTL4, Signal Degrade Control Register 4 (R/W)
Address
Bit
Name
0x200D2
15:0
VT_SDBSET[15:0]
Agere Systems Inc.
Function
Signal Degrade B Set. Number of monitoring blocks.
Reset
Default
0x0000
163
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
10 VT/TU Mapper Registers (continued)
Table 189. VT_SIGDEG_CTL5, Signal Degrade Control Register 5 (R/W)
Address
Bit
0x200D3
15:0
Name
Function
Reset
Default
VT_SDNSCLEAR[18:3] Signal Degrade Ns Clear. Number of frames in a monitoring block for SD.
0x0000
Table 190. VT_SIGDEG_CTL6, Signal Degrade Control Register 6 (R/W)
Address
Bit
Name
0x200D4
15
—
14:7
VT_SDMCLEAR[7:0]
Signal Degrade M Clear. Threshold of the number of bad
monitoring blocks in an observation interval. If the number
of bad blocks is below this threshold, then SD is cleared.
0x00
6:3
VT_SDLCLEAR[3:0]
Signal Degrade L Clear. Error threshold for determining if
a monitoring block is bad.
0x0
2:0
Function
Reset
Default
Reserved.
0
VT_SDNSCLEAR[2:0] Signal Degrade Ns Clear. Number of frames in a monitoring block for SD.
0x0
Table 191. VT_SIGDEG_CTL7, Signal Degrade Control Register 7 (R/W)
Address
Bit
0x200D5
15:0
Name
Function
Reset
Default
VT_SDBCLEAR[15:0] Signal Degrade B Clear. Number of monitoring blocks.
0x0000
Table 192. VT_SIGFAIL_CTL1, Signal Fail Control Register 1 (R/W)
Address Bit
Name
Function
Reset
Default
0x200D6 15:0 VT_SFNSSET[18:3] Signal Fail Ns Set. Number of frames in a monitoring block for SF. 0x0000
Table 193. VT_SIGFAIL_CTL2, Signal Fail Control Register 2 (R/W)
Address
Bit
Name
0x200D7
15
—
Function
Reset
Default
Reserved.
0
14:7
VT_SFMSET[7:0] Signal Fail M Set. Threshold of the number of bad monitoring
blocks in an observation interval. If the number of bad blocks is
above this threshold, then SF is set.
0x00
6:3
VT_SFLSET[3:0]
0x0
2:0
Signal Fail L Set. Error threshold for determining if a monitoring
block is bad.
VT_SFNSSET[2:0] Signal Fail Ns Set. Number of frames in a monitoring block for SF.
0x0
Table 194. VT_SIGFAIL_CTL3, Signal Fail Control Register 3 (R/W)
Address
Bit
Name
0x200D8
15:0
VT_SFBSET[15:0]
164
Function
Signal Fail B Set. Number of monitoring blocks.
Reset
Default
0x0000
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
10 VT/TU Mapper Registers (continued)
Table 195. VT_SIGFAIL_CTL4, Signal Fail Control Register 4 (R/W)
Address
Bit
Name
Function
Reset
Default
0x200D9
15:0
VT_SFNSCLEAR[18:3]
Signal Fail Ns Clear. Number of frames in a monitoring
block for SF.
0x0000
Table 196. VT_SIGFAIL_CTL5, Signal Fail Control Register 5 (R/W)
Address
Bit
Name
0x200DA
15
—
14:7
VT_SFMCLEAR[7:0]
Signal Fail M Clear. Threshold of the number of bad
monitoring blocks in an observation interval. If the
number of bad blocks is below this threshold, then SF is
cleared.
0x00
6:3
VT_SFLCLEAR[3:0]
Signal Fail L Clear. Error threshold for determining if a
monitoring block is bad.
0x0
2:0
Function
Reserved.
Reset
Default
0
VT_SFNSCLEAR[2:0] Signal Fail Ns Clear. Number of frames in a monitoring
block for SF.
0x0
Table 197. VT_SIGFAIL_CTL6, Signal Fail Control Register 6 (R/W)
Address
Bit
0x200DB
15:0
Agere Systems Inc.
Name
Function
VT_SFBCLEAR[15:0] Signal Fail B Clear. Number of monitoring blocks.
Reset
Default
0x0000
165
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
10 VT/TU Mapper Registers (continued)
Table 198. VT_TCTL[1—28], Transmit Control Per Channel (R/W)
Address
Bit
Name
Function
Reset
Default
0x200DC 15:13
—
Reserved.
—
12
VT_TX_ERDI_EN[1—28] Transmit Path Enhanced RDI-V Enable. Logic one
0x200F7
enables enhanced RDI-V.
11
VT_ERDI_EN[1—28]
10
0x0
Enhanced RDI-V Source Selection. Logic one activates software overwrite of the ERDI-V bits of the Z7
byte. Otherwise, insertion is based on the LOPOH
serial channel or automatic generation.
0x0
VT_RDI_EN[1—28]
RDI-V Source Selection. Logic one activates software
overwrite of the RDI-V bit of the V5 byte. Otherwise,
insertion is based on the LOPOH serial channel or
automatic generation.
0x0
9
VT_RFI_EN[1—28]
RFI-V Source Selection. Logic one activates software
overwrite of the RFI-V bit of the V5 byte. If
VT_V5_INS[1—28] = 0 (Table 199) and the mapping is
set to byte synchronous DS1, a logic zero enables
automatic insertion of RFI-V. If VT_V5_INS[1—28] = 1,
a logic zero inserts RFI-V based on the LOPOH serial
channel.
0x0
8
VT_REI_EN[1—28]
REI-V Enable. Logic one activates automatic generation of REI-V. If VT_V5_INS[1—28] = 0, the generation
is based on the received BIP-2 errors. Otherwise,
insertion is based on the LOPOH serial channel.
0x0
7
—
6
VT_AIS_INS[1—28]
5
166
0x0
Reserved.
0
AIS-V Insertion Control. Logic one forces AIS-V to be
transmitted in the specified channel.
0x0
VT_TX_CLKEDGE[1—28] Transmit Path DS1/E1 Clock Edge Selection. Logic
one forces the DS1/E1 signals to be retimed using the
rising edge of the associated clock. Logic zero forces
the DS1/E1 signals to be retimed using the falling edge
of the associated clock.
0x0
4
VT_LB_SEL[1—28]
Tributary Loopback Selection. Logic one activates
tributary loopback.
0x0
3:0
VT_TX_MAPTYPE
[1—28][3:0]
Transmit Mapping Mode Control. See Table 558.
0x6
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
10 VT/TU Mapper Registers (continued)
Table 199. VT_TTUOH_CTL[1—28], Transmit TU Overhead Control Per Channel (R/W)
Address
Bit
Name
0x200F8
—
0x20113
15:11
—
Function
Reserved.
Reset
Default
0x00
10:9
VT_O_INS[1—28][1:0] O-Bit Insertion Control. See Table 566 on page446 .
0x0
8:7
VT_Z7_INS[1—28][1:0] Z7 Byte Insertion Control. See Table 565, Z7/K4 Overhead Byte Insertion Modes Per Channel on page446 .
0x0
6:5
VT_Z6_INS[1—28][1:0] Z6 Byte Insertion Control. See Table 564, Z6/N2 Overhead Byte Insertion Modes Per Channel on page445 .
0x0
4:3
VT_J2_INS[1—28][1:0] J2 Byte Insertion Control. See Table 563, J2 Overhead
Byte Insertion Modes Per Channel on page 445.
0x0
2
VT_V5_INS[1—28]
1:0
VT_BIP2ERR_
INS[1—28][1:0]
V5 Byte Insertion Control. Logic one forces the V5 byte
to be programmed via the LOPOH serial channel. See
Table 559 on pag e443.
0x0
BIP-2 Error Insertion Control. See Table 560 on
page 443.
0x0
Table 200. VT_TAPSRIVAL[1—28], Transmit APS and Remote Indication Per Channel (R/W)
Address
Bit
Name
Function
0x20114
—
0x2012F
15:12
11:8
—
VT_APS_
INS[1—28][3:0]
7:5
4:2
—
VT_ERDI_
INS[1—28][2:0]
1
VT_RDI_INS[1—28]
0
VT_RFI_INS[1—28]
Reserved.
APS Software Overwrite Value. This nibble is programmed to utilize APS bits in the Z7/K4 byte. This nibble
will be transmitted in bits 1:4 of the Z7/K4 byte.
Reserved.
Enhanced RDI-V Software Overwrite Values. If
VT_ERDI_EN[1—28] (Table 198) is a logic one, these bits
are written into the ERDI-V locations of the Z7 byte.
RDI-V Software Overwrite Values. If VT_RDI_EN[1—28]
(Table 198) is a logic one, this value will be written into the
RDI-V location of the V5 byte.
RFI-V Software Overwrite Values. If VT_RFI_EN[1—28]
(Table 198) is a logic one, this value will be written into the
RFI-V location of the V5 byte.
Reset
Default
0x0
0x0
0x0
0x0
0x0
0x0
Table 201. VT_TSWOW[1—28], Transmit Software Overwrite Per Channel (R/W)
Address
Bit
Name
Function
0x20130
—
0x2014B
15:8
VT_OBIT_
INS[1—28][7:0]
7:0
VT_Z6BYTE_
INS[1—28][7:0]
Overhead Values for Software Overwrite in Asynchronous Mappings. This byte is programmed to utilize
the overhead bits in asynchronous VT/TU mappings.
VT_OBIT_INS[7:4] will be transmitted in the byte following J2 and VT_OBIT_INS[3:0] will be transmitted in the
byte following Z6/N2.
Z6 Software Overwrite Values. This byte is programmed into the outgoing Z6/N2 location when
VT_Z6_INS[1—28][1:0] (Table 199) = 01.
Agere Systems Inc.
Reset
Default
0x00
0x00
167
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
10 VT/TU Mapper Registers (continued)
Table 202. VT_TSIG_CTL[1—28], Transmit Signaling Control Per Channel (R/W)
Address
Bit
Name
0x2014C
—
0x20167
15:11
10
—
VT_USE_FBIT[1—28]
9
8
7:5
4:0
Function
Reserved.
Frame Bit Use Control. Logic one provisions
use of the F bit in the outgoing VT/TU. Otherwise, the F bit is forced to the value of bit
SMPR_OH_DEFLT (Table 67) in the microprocessor interface on the outgoing VT/TU.
VT_USE_PBIT[1—28]
Phase Bit Use Control. Logic one provisions
use of the P bits in the outgoing VT/TU. Otherwise, the P bits are forced to the value of bit
SMPR_OH_DEFLT in the microprocessor interface on the outgoing VT/TU.
VT_USE_SBIT[1—28]
Signaling Bit Use Control. Logic one provisions use of the S bits in the outgoing VT/TU.
Otherwise, the S bits are forced to the value of
bit SMPR_OH_DEFLT in the microprocessor
interface on the outgoing VT/TU.
—
Reserved.
VT_TXSIG_CH_SEL[1—28][4:0] Transmit Input Channel Selection. These bits
are programmed with the same value as the
cross connect for each individual channel. The
bits are only used in byte synchronous mode
and can be set to 0xXX for all other modes. If an
invalid value is programmed,
UNEQ-V will be transmitted in the specified
channel. Invalid decimal values are 0, 29, 30,
and 31.
Reset
Default
000000
0x1
0x1
0x1
000
0x00
Table 203. VT_J2BYTE_INS_R[1—28][1—16], J2 Insert Values Per Channel (R/W)
Address
Bit
0x20168
—
0x20327
15:8
7:0
Name
Function
—
Reserved.
VT_J2BYTE_
J2 Software Overwrite Values. These values are written
INS[1—28][1—16][7:0] into the outgoing J2 byte when VT_J2_INS[1—28][1:0] = 01
(Table 199).
Reset
Default
0x00
0x00
Table 204. VT_RCTL[1—28], Receive Control Per Channel (R/W)
Address
Bit
Name
Function
0x20328
—
0x20343
15
VT_SF_ESF[1—28]
14
VT_WR_FBIT[1—28]
13
VT_SYNC_PBIT[1—28]
DS1 Frame Type for Byte Synchronous Mode. Logic
one provisions an SF frame format. Otherwise, an ESF
frame format is provisioned.
F-Bit Provisioning Control. See Table 556, Rx Signaling Behavior per Channel on page 439.
P-Bit Provisioning Control. See Table 556, Rx Signaling Behavior per Channel on page 439.
168
Reset
Default
0x0
0x0
0x0
Agere Systems Inc.
Preliminary Data Sheet
June 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
10 VT/TU Mapper Registers (continued)
Table 204. VT_RCTL[1—28], Receive Control Per Channel (R/W) (continued)
Address
Bit
0x20328
—
0x20343
12:8
7:5
4
3:0
Name
Function
Reset
Default
VT_RXSIG_CH_
Receive Output Channel Selection. These bits are pro- 0x00
SEL[1—28][4:0]
grammed with the same value as the cross connect for
each individual channel. The bits are only used in byte
synchronous mode and can be set to 0xXX for all other
modes. If an invalid value is programmed, UNEQ-V will
be transmitted in the specified channel. Invalid decimal
values are 0, 29, 30, and 31. See Rx Signaling Behavior
per Channel on page 439.
VT_J2MON_
J2 Trace Monitoring Mode Control. See J2 Byte Moni0x00
MODE[1—28][2:0]
tor and Termination (J2MON) on page 438.
VT_RX_ERDI_EN[1—28] Receive Path Enhanced RDI-V Enable. Logic one
0x0
enables enhanced RDI-V.
VT_RX_
Receive Demapping Mode Control. See Table 555,
0x6
MAPTYPE[1—28][3:0] Receive VT/TU Demapping Selection on page 437.
Table 205. VT_RTUOH_CTL[1—28], Receive TU Overhead Control Per Channel (RO)
Address
Bit
0x20344
—
0x2035F
15:8
7:0
Name
Function
VT_Z6_BYTE[1—28][7:0] Received Z6/N2 Byte Value. Accepted Z6/N2 value.
VT_OBITS[1—28][7:0]
Received O Bits Value. Accepted overhead bits in asynchronous and bit synchronous modes. VT_OBITS[7:4]
are the O bits received in the byte following J2, and
VT_OBITS[3:0] are the O bits received in the byte following Z6/N2.
Reset
Default
0x00
0x00
Table 206. VT_RBIP2_CNT[1—28], Receive BIP-2 Error Count Per Channel (RO)
Address
Bit
Name
0x20360
—
0x2037B
15:12
—
11:0
VT_BIP2ERR_
CNT[1—28][11:0]
Function
Reserved.
Reset
Default
0x0
BIP-2 Error Count. BIP-2 error count updated on a 0 to
1 transition of SMPR_PMRESET (Table 65).
0x000
Table 207. VT_RREIV_CNT[1—28], Receive REI-V Error Count Per Channel (RO)
Address
Bit
Name
0x2037C
—
0x20397
15:11
—
10:0
VT_REI_
CNT[1—28][10:0]
Agere Systems Inc.
Function
Reset
Default
Reserved.
0x00
REI-V Error Count. REI-V error count updated on a 0 to 1
transition of SMPR_PMRESET.
0x000
169
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
10 VT/TU Mapper Registers (continued)
Table 208. VT_RPTR_CNT[1—28], Receive Pointer and Count Per Channel (RO)
Address
Bit
Name
Function
Reset
Default
0x20398
—
0x203B3
15:8
VT_STORED_
PTR[1—28][7:0]
Store VT/TU Pointer Location. This value indicates the
stored location of the V5 byte within the VT/TU mapping.
0x00
7:4
VT_PTR_
DEC[1—28][3:0]
VT Pointer Decrement Count. VT pointer decrement
count updated on a 0 to 1 transition of
SMPR_PMRESET.
0x0
3:0
VT_PTR_
INC[1—28][3:0]
VT Pointer Increment Count. VT pointer increment
count updated on a 0 to 1 transition of
SMPR_PMRESET.
0x0
Table 209. VT_J2BYTE_EXP_R[1—28][1—16], J2 Expected Values Per Channel (R/W, RO)
Address
Bit
Name
Function
Reset
Default
0x203B4
—
0x20573
15:8
VT_J2BYTE_
J2 Expected Values. This value is programmed by the
EXP[1—28][1—16][7:0] user as an expected value for the J2 byte. The hardware
will compare this value to the incoming J2 sequence
when VT_J2MON_MODE[1—28][2:0] = 011 or 100
(Table 204 on pag e168).
0x00
7:0
VT_J2BYTE_
J2 Detected Values. Accepted J2 sequence or value.
DET[1—28][1—16][7:0]
0x00
Table 210. VT_THRES_CTL[1—28], Transmit Elastic Store Threshold Control (R/W)
Address
Bit
Name
0x20574
—
0x2058F
15
—
14:8
VT_HIGH_
THRES[1—28][6:0]
7
—
6:0
VT_LOW_
THRES[1—28][6:0]
170
Function
Reset
Default
Reserved.
0x0
Transmit Elastic Store High Threshold. Programmable
threshold controlling positive justifications.
0x28
Reserved.
0x0
Transmit Elastic Store Low Threshold. Programmable
threshold controlling negative justifications.
0x27
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
10 VT/TU Mapper Registers (continued)
10.2 VT/TU Mapper Register Map
Table 211. VT/TU Mapper Register Map
Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.
Address
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
VT_SD_D
VT_SF_D
VT_H4LOMF_
D
VT Mapper ID—RO
0x20000
VT_VERSION_R
0x20001
VT_GDELETA
0x20002
VT_REVENT_DELTA1
VT_RX_VTREI_E1
VT_RX_BIP2ERR_E1
VT_RX_ESOVFL_E1
VT_APS_D1
VT_ERDI_D1
VT_RDI_D1
VT_RFI_D1
VT_LOPS_D1
VT_J2TIM_D1
VT_PLM_D1
VT_UNEQ_D1
VT_SIZERR_D1
VT_AIS_D1
VT_LOP_D1
0x20003
VT_REVENT_DELTA2
VT_RX_VTREI_E2
VT_RX_BIP2ERR_E2
VT_RX_ESOVFL_E2
VT_APS_D2
VT_ERDI_D2
VT_RDI_D2
VT_RFI_D2
VT_LOPS_D2
VT_J2TIM_D2
VT_PLM_D2
VT_UNEQ_D2
VT_SIZERR_D2
VT_AIS_D2
VT_LOP_D2
0x20004
VT_REVENT_DELTA3
VT_RX_VTREI_E3
VT_RX_BIP2ERR_E3
VT_RX_ESOVFL_E3
VT_APS_D3
VT_ERDI_D3
VT_RDI_D3
VT_RFI_D3
VT_LOPS_D3
VT_J2TIM_D3
VT_PLM_D3
VT_UNEQ_D3
VT_SIZERR_D3
VT_AIS_D3
VT_LOP_D3
0x20005
VT_REVENT_DELTA4
VT_RX_VTREI_E4
VT_RX_BIP2ERR_E4
VT_RX_ESOVFL_E4
VT_APS_D4
VT_ERDI_D4
VT_RDI_D4
VT_RFI_D4
VT_LOPS_D4
VT_J2TIM_D4
VT_PLM_D4
VT_UNEQ_D4
VT_SIZERR_D4
VT_AIS_D4
VT_LOP_D4
0x20006
VT_REVENT_DELTA5
VT_RX_VTREI_E5
VT_RX_BIP2ERR_E5
VT_RX_ESOVFL_E5
VT_APS_D5
VT_ERDI_D5
VT_RDI_D5
VT_RFI_D5
VT_LOPS_D5
VT_J2TIM_D5
VT_PLM_D5
VT_UNEQ_D5
VT_SIZERR_D5
VT_AIS_D5
VT_LOP_D5
0x20007
VT_REVENT_DELTA6
VT_RX_VTREI_E6
VT_RX_BIP2ERR_E6
VT_RX_ESOVFL_E6
VT_APS_D6
VT_ERDI_D6
VT_RDI_D6
VT_RFI_D6
VT_LOPS_D6
VT_J2TIM_D6
VT_PLM_D6
VT_UNEQ_D6
VT_SIZERR_D6
VT_AIS_D6
VT_LOP_D6
0x20008
VT_REVENT_DELTA7
VT_RX_VTREI_E7
VT_RX_BIP2ERR_E7
VT_RX_ESOVFL_E7
VT_APS_D7
VT_ERDI_D7
VT_RDI_D7
VT_RFI_D7
VT_LOPS_D7
VT_J2TIM_D7
VT_PLM_D7
VT_UNEQ_D7
VT_SIZERR_D7
VT_AIS_D7
VT_LOP_D7
0x20009
VT_REVENT_DELTA8
VT_RX_VTREI_E8
VT_RX_BIP2ERR_E8
VT_RX_ESOVFL_E8
VT_APS_D8
VT_ERDI_D8
VT_RDI_D8
VT_RFI_D8
VT_LOPS_D8
VT_J2TIM_D8
VT_PLM_D8
VT_UNEQ_D8
VT_SIZERR_D8
VT_AIS_D8
VT_LOP_D8
0x2000A
VT_REVENT_DELTA9
VT_RX_VTREI_E9
VT_RX_BIP2ERR_E9
VT_RX_ESOVFL_E9
VT_APS_D9
VT_ERDI_D9
VT_RDI_D9
VT_RFI_D9
VT_LOPS_D9
VT_J2TIM_D9
VT_PLM_D9
VT_UNEQ_D9
VT_SIZERR_D9
VT_AIS_D9
VT_LOP_D9
0x2000B
VT_REVENT_DELTA10
VT_RX_VTREI_E10 VT_RX_BIP2ERR_E10 VT_RX_ESOVFL_E10 VT_APS_D10 VT_ERDI_D10 VT_RDI_D10 VT_RFI_D10
VT_LOPS_D10 VT_J2TIM_D10 VT_PLM_D10 VT_UNEQ_D10 VT_SIZERR_D10 VT_AIS_D10 VT_LOP_D10
0x2000C
VT_REVENT_DELTA11
VT_RX_VTREI_E11 VT_RX_BIP2ERR_E11 VT_RX_ESOVFL_E11 VT_APS_D11 VT_ERDI_D11 VT_RDI_D11 VT_RFI_D11
VT_LOPS_D11 VT_J2TIM_D11 VT_PLM_D11 VT_UNEQ_D11 VT_SIZERR_D11 VT_AIS_D11 VT_LOP_D11
0x2000D
VT_REVENT_DELTA12
VT_RX_VTREI_E12 VT_RX_BIP2ERR_E12 VT_RX_ESOVFL_E12 VT_APS_D12 VT_ERDI_D12 VT_RDI_D12 VT_RFI_D12
VT_LOPS_D12 VT_J2TIM_D12 VT_PLM_D12 VT_UNEQ_D12 VT_SIZERR_D12 VT_AIS_D12 VT_LOP_D12
0x2000E
VT_REVENT_DELTA13
VT_RX_VTREI_E13 VT_RX_BIP2ERR_E13 VT_RX_ESOVFL_E13 VT_APS_D13 VT_ERDI_D13 VT_RDI_D13 VT_RFI_D13
VT_LOPS_D13 VT_J2TIM_D13 VT_PLM_D13 VT_UNEQ_D13 VT_SIZERR_D13 VT_AIS_D13 VT_LOP_D13
0x2000F
VT_REVENT_DELTA14
VT_RX_VTREI_E14 VT_RX_BIP2ERR_E14 VT_RX_ESOVFL_E14 VT_APS_D14 VT_ERDI_D14 VT_RDI_D14 VT_RFI_D14
VT_LOPS_D14 VT_J2TIM_D14 VT_PLM_D14 VT_UNEQ_D14 VT_SIZERR_D14 VT_AIS_D14 VT_LOP_D14
0x20010
VT_REVENT_DELTA15
VT_RX_VTREI_E15 VT_RX_BIP2ERR_E15 VT_RX_ESOVFL_E15 VT_APS_D15 VT_ERDI_D15 VT_RDI_D15 VT_RFI_D15
VT_LOPS_D15 VT_J2TIM_D15 VT_PLM_D15 VT_UNEQ_D15 VT_SIZERR_D15 VT_AIS_D15 VT_LOP_D15
0x20011
VT_REVENT_DELTA16
VT_RX_VTREI_E16 VT_RX_BIP2ERR_E16 VT_RX_ESOVFL_E16 VT_APS_D16 VT_ERDI_D16 VT_RDI_D16 VT_RFI_D16
VT_LOPS_D16 VT_J2TIM_D16 VT_PLM_D16 VT_UNEQ_D16 VT_SIZERR_D16 VT_AIS_D16 VT_LOP_D16
0x20012
VT_REVENT_DELTA17
VT_RX_VTREI_E17 VT_RX_BIP2ERR_E17 VT_RX_ESOVFL_E17 VT_APS_D17 VT_ERDI_D17 VT_RDI_D17 VT_RFI_D17
VT_LOPS_D17 VT_J2TIM_D17 VT_PLM_D17 VT_UNEQ_D17 VT_SIZERR_D17 VT_AIS_D17 VT_LOP_D17
0x20013
VT_REVENT_DELTA18
VT_RX_VTREI_E18 VT_RX_BIP2ERR_E18 VT_RX_ESOVFL_E18 VT_APS_D18 VT_ERDI_D18 VT_RDI_D18 VT_RFI_D18
VT_LOPS_D18 VT_J2TIM_D18 VT_PLM_D18 VT_UNEQ_D18 VT_SIZERR_D18 VT_AIS_D18 VT_LOP_D18
0x20014
VT_REVENT_DELTA19
VT_RX_VTREI_E19 VT_RX_BIP2ERR_E19 VT_RX_ESOVFL_E19 VT_APS_D19 VT_ERDI_D19 VT_RDI_D19 VT_RFI_D19
VT_LOPS_D19 VT_J2TIM_D19 VT_PLM_D19 VT_UNEQ_D19 VT_SIZERR_D19 VT_AIS_D19 VT_LOP_D19
0x20015
VT_REVENT_DELTA20
VT_RX_VTREI_E20 VT_RX_BIP2ERR_E20 VT_RX_ESOVFL_E20 VT_APS_D20 VT_ERDI_D20 VT_RDI_D20 VT_RFI_D20
VT_LOPS_D20 VT_J2TIM_D20 VT_PLM_D20 VT_UNEQ_D20 VT_SIZERR_D20 VT_AIS_D20 VT_LOP_D20
0x20016
VT_REVENT_DELTA21
VT_RX_VTREI_E21 VT_RX_BIP2ERR_E21 VT_RX_ESOVFL_E21 VT_APS_D21 VT_ERDI_D21 VT_RDI_D21 VT_RFI_D21
VT_LOPS_D21 VT_J2TIM_D21 VT_PLM_D21 VT_UNEQ_D21 VT_SIZERR_D21 VT_AIS_D21 VT_LOP_D21
0x20017
VT_REVENT_DELTA22
VT_RX_VTREI_E22 VT_RX_BIP2ERR_E22 VT_RX_ESOVFL_E22 VT_APS_D22 VT_ERDI_D22 VT_RDI_D22 VT_RFI_D22
VT_LOPS_D22 VT_J2TIM_D22 VT_PLM_D22 VT_UNEQ_D22 VT_SIZERR_D22 VT_AIS_D22 VT_LOP_D22
0x20018
VT_REVENT_DELTA23
VT_RX_VTREI_E23 VT_RX_BIP2ERR_E23 VT_RX_ESOVFL_E23 VT_APS_D23 VT_ERDI_D23 VT_RDI_D23 VT_RFI_D23
VT_LOPS_D23 VT_J2TIM_D23 VT_PLM_D23 VT_UNEQ_D23 VT_SIZERR_D23 VT_AIS_D23 VT_LOP_D23
0x20019
VT_REVENT_DELTA24
VT_RX_VTREI_E24 VT_RX_BIP2ERR_E24 VT_RX_ESOVFL_E24 VT_APS_D24 VT_ERDI_D24 VT_RDI_D24 VT_RFI_D24
VT_LOPS_D24 VT_J2TIM_D24 VT_PLM_D24 VT_UNEQ_D24 VT_SIZERR_D24 VT_AIS_D24 VT_LOP_D24
0x2001A
VT_REVENT_DELTA25
VT_RX_VTREI_E25 VT_RX_BIP2ERR_E25 VT_RX_ESOVFL_E25 VT_APS_D25 VT_ERDI_D25 VT_RDI_D25 VT_RFI_D25
VT_LOPS_D25 VT_J2TIM_D25 VT_PLM_D25 VT_UNEQ_D25 VT_SIZERR_D25 VT_AIS_D25 VT_LOP_D25
0x2001B
VT_REVENT_DELTA26
VT_RX_VTREI_E26 VT_RX_BIP2ERR_E26 VT_RX_ESOVFL_E26 VT_APS_D26 VT_ERDI_D26 VT_RDI_D26 VT_RFI_D26
VT_LOPS_D26 VT_J2TIM_D26 VT_PLM_D26 VT_UNEQ_D26 VT_SIZERR_D26 VT_AIS_D26 VT_LOP_D26
0x2001C
VT_REVENT_DELTA27
VT_RX_VTREI_E27 VT_RX_BIP2ERR_E27 VT_RX_ESOVFL_E27 VT_APS_D27 VT_ERDI_D27 VT_RDI_D27 VT_RFI_D27
VT_LOPS_D27 VT_J2TIM_D27 VT_PLM_D27 VT_UNEQ_D27 VT_SIZERR_D27 VT_AIS_D27 VT_LOP_D27
0x2001D
VT_REVENT_DELTA28
VT_RX_VTREI_E28 VT_RX_BIP2ERR_E28 VT_RX_ESOVFL_E28 VT_APS_D28 VT_ERDI_D28 VT_RDI_D28 VT_RFI_D28
VT_LOPS_D28 VT_J2TIM_D28 VT_PLM_D28 VT_UNEQ_D28 VT_SIZERR_D28 VT_AIS_D28 VT_LOP_D28
VT_
RDY
VT_VERSION[2:0]
VT_ID[7:0]
VT Global Events—COR/COW
Receive Delta and Event Parameters—COR/COW
Agere Systems Inc.
171
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
10 VT/TU Mapper Registers (continued)
Table 211. VT/TU Mapper Register Map (continued)
Address
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Transmit Delta and Event Parameters—COR/COW
0x2001E
VT_LOPOHFAIL_EVENT
0x2001F
VT_TEVENT_DELTA1
VT_TX_ESOVFL_E1
VT_LOFS_D1
VT_TX_AIS_D1
VT_TX_LOC_D1
0x20020
VT_TEVENT_DELTA2
VT_TX_ESOVFL_E2
VT_LOFS_D2
VT_TX_AIS_D2
VT_TX_LOC_D2
0x20021
VT_TEVENT_DELTA3
VT_TX_ESOVFL_E3
VT_LOFS_D3
VT_TX_AIS_D3
VT_TX_LOC_D3
0x20022
VT_TEVENT_DELTA4
VT_TX_ESOVFL_E4
VT_LOFS_D4
VT_TX_AIS_D4
VT_TX_LOC_D4
0x20023
VT_TEVENT_DELTA5
VT_TX_ESOVFL_E5
VT_LOFS_D5
VT_TX_AIS_D5
VT_TX_LOC_D5
0x20024
VT_TEVENT_DELTA6
VT_TX_ESOVFL_E6
VT_LOFS_D6
VT_TX_AIS_D6
VT_TX_LOC_D6
0x20025
VT_TEVENT_DELTA7
VT_TX_ESOVFL_E7
VT_LOFS_D7
VT_TX_AIS_D7
VT_TX_LOC_D7
0x20026
VT_TEVENT_DELTA8
VT_TX_ESOVFL_E8
VT_LOFS_D8
VT_TX_AIS_D8
VT_TX_LOC_D8
0x20027
VT_TEVENT_DELTA9
VT_TX_ESOVFL_E9
VT_LOFS_D9
VT_TX_AIS_D9
VT_TX_LOC_D9
0x20028
VT_TEVENT_DELTA10
VT_TX_ESOVFL_E10
VT_LOFS_D10
VT_TX_AIS_D10
VT_TX_LOC_D10
VT_LOPOH_FAIL_
E
0x20029
VT_TEVENT_DELTA11
VT_TX_ESOVFL_E11
VT_LOFS_D11
VT_TX_AIS_D11
VT_TX_LOC_D11
0x2002A
VT_TEVENT_DELTA12
VT_TX_ESOVFL_E12
VT_LOFS_D12
VT_TX_AIS_D12
VT_TX_LOC_D12
0x2002B
VT_TEVENT_DELTA13
VT_TX_ESOVFL_E13
VT_LOFS_D13
VT_TX_AIS_D13
VT_TX_LOC_D13
0x2002C
VT_TEVENT_DELTA14
VT_TX_ESOVFL_E14
VT_LOFS_D14
VT_TX_AIS_D14
VT_TX_LOC_D14
0x2002D
VT_TEVENT_DELTA15
VT_TX_ESOVFL_E15
VT_LOFS_D15
VT_TX_AIS_D15
VT_TX_LOC_D15
0x2002E
VT_TEVENT_DELTA16
VT_TX_ESOVFL_E16
VT_LOFS_D16
VT_TX_AIS_D16
VT_TX_LOC_D16
0x2002F
VT_TEVENT_DELTA17
VT_TX_ESOVFL_E17
VT_LOFS_D17
VT_TX_AIS_D17
VT_TX_LOC_D17
0x20030
VT_TEVENT_DELTA18
VT_TX_ESOVFL_E18
VT_LOFS_D18
VT_TX_AIS_D18
VT_TX_LOC_D18
0x20031
VT_TEVENT_DELTA19
VT_TX_ESOVFL_E19
VT_LOFS_D19
VT_TX_AIS_D19
VT_TX_LOC_D19
0x20032
VT_TEVENT_DELTA20
VT_TX_ESOVFL_E20
VT_LOFS_D20
VT_TX_AIS_D20
VT_TX_LOC_D20
0x20033
VT_TEVENT_DELTA21
VT_TX_ESOVFL_E21
VT_LOFS_D21
VT_TX_AIS_D21
VT_TX_LOC_D21
0x20034
VT_TEVENT_DELTA22
VT_TX_ESOVFL_E22
VT_LOFS_D22
VT_TX_AIS_D22
VT_TX_LOC_D22
0x20035
VT_TEVENT_DELTA23
VT_TX_ESOVFL_E23
VT_LOFS_D23
VT_TX_AIS_D23
VT_TX_LOC_D23
0x20036
VT_TEVENT_DELTA24
VT_TX_ESOVFL_E24
VT_LOFS_D24
VT_TX_AIS_D24
VT_TX_LOC_D24
0x20037
VT_TEVENT_DELTA25
VT_TX_ESOVFL_E25
VT_LOFS_D25
VT_TX_AIS_D25
VT_TX_LOC_D25
0x20038
VT_TEVENT_DELTA26
VT_TX_ESOVFL_E26
VT_LOFS_D26
VT_TX_AIS_D26
VT_TX_LOC_D26
0x20039
VT_TEVENT_DELTA27
VT_TX_ESOVFL_E27
VT_LOFS_D27
VT_TX_AIS_D27
VT_TX_LOC_D27
0x2003A
VT_TEVENT_DELTA28
VT_TX_ESOVFL_E28
VT_LOFS_D28
VT_TX_AIS_D28
VT_TX_LOC_D28
172
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
10 VT/TU Mapper Registers (continued)
Table 211. VT/TU Mapper Register Map (continued)
Address
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
VT_SD_M
VT_SF_M
VT_H4LOMF_
M
VT Global Interrupt Masks—R/W
0x2003B
VT_GMASK
Receive Interrupt Masks—R/W
0x2003C
VT_RMASK1
VT_RX_VTREI_M1
VT_RX_BIP2ERR_M1
VT_RX_ESOVFL_M1
VT_APS_M1
VT_ERDI_M1
VT_RDI_M1
VT_RFI_M1
VT_LOPS_M1
VT_J2TIM_M1
VT_PLM_M1
VT_UNEQ_M1
VT_SIZERR_M1
VT_AIS_M1
VT_LOP_M1
0x2003D
VT_RMASK2
VT_RX_VTREI_M2
VT_RX_BIP2ERR_M2
VT_RX_ESOVFL_M2
VT_APS_M2
VT_ERDI_M2
VT_RDI_M2
VT_RFI_M2
VT_LOPS_M2
VT_J2TIM_M2
VT_PLM_M2
VT_UNEQ_M2
VT_SIZERR_M2
VT_AIS_M2
VT_LOP_M2
0x2003E
VT_RMASK3
VT_RX_VTREI_M3
VT_RX_BIP2ERR_M3
VT_RX_ESOVFL_M3
VT_APS_M3
VT_ERDI_M3
VT_RDI_M3
VT_RFI_M3
VT_LOPS_M3
VT_J2TIM_M3
VT_PLM_M3
VT_UNEQ_M3
VT_SIZERR_M3
VT_AIS_M3
VT_LOP_M3
0x2003F
VT_RMASK4
VT_RX_VTREI_M4
VT_RX_BIP2ERR_M4
VT_RX_ESOVFL_M4
VT_APS_M4
VT_ERDI_M4
VT_RDI_M4
VT_RFI_M4
VT_LOPS_M4
VT_J2TIM_M4
VT_PLM_M4
VT_UNEQ_M4
VT_SIZERR_M4
VT_AIS_M4
VT_LOP_M4
0x20040
VT_RMASK5
VT_RX_VTREI_M5
VT_RX_BIP2ERR_M5
VT_RX_ESOVFL_M5
VT_APS_M5
VT_ERDI_M5
VT_RDI_M5
VT_RFI_M5
VT_LOPS_M5
VT_J2TIM_M5
VT_PLM_M5
VT_UNEQ_M5
VT_SIZERR_M5
VT_AIS_M5
VT_LOP_M5
0x20041
VT_RMASK6
VT_RX_VTREI_M6
VT_RX_BIP2ERR_M6
VT_RX_ESOVFL_M6
VT_APS_M6
VT_ERDI_M6
VT_RDI_M6
VT_RFI_M6
VT_LOPS_M6
VT_J2TIM_M6
VT_PLM_M6
VT_UNEQ_M6
VT_SIZERR_M6
VT_AIS_M6
VT_LOP_M6
0x20042
VT_RMASK7
VT_RX_VTREI_M7
VT_RX_BIP2ERR_M7
VT_RX_ESOVFL_M7
VT_APS_M7
VT_ERDI_M7
VT_RDI_M7
VT_RFI_M7
VT_LOPS_M7
VT_J2TIM_M7
VT_PLM_M7
VT_UNEQ_M7
VT_SIZERR_M7
VT_AIS_M7
VT_LOP_M7
0x20043
VT_RMASK8
VT_RX_VTREI_M8
VT_RX_BIP2ERR_M8
VT_RX_ESOVFL_M8
VT_APS_M8
VT_ERDI_M8
VT_RDI_M8
VT_RFI_M8
VT_LOPS_M8
VT_J2TIM_M8
VT_PLM_M8
VT_UNEQ_M8
VT_SIZERR_M8
VT_AIS_M8
VT_LOP_M8
0x20044
VT_RMASK9
VT_RX_VTREI_M9
VT_RX_BIP2ERR_M9
VT_RX_ESOVFL_M9
VT_APS_M9
VT_ERDI_M9
VT_RDI_M9
VT_RFI_M9
VT_LOPS_M9
VT_J2TIM_M9
VT_PLM_M9
VT_UNEQ_M9
VT_SIZERR_M9
VT_AIS_M9
VT_LOP_M9
0x20045
VT_RMASK10
VT_RX_VTREI_M10 VT_RX_BIP2ERR_M10 VT_RX_ESOVFL_M10 VT_APS_M10 VT_ERDI_M10 VT_RDI_M10
VT_RFI_M10
VT_LOPS_M10 VT_J2TIM_M10
VT_PLM_M10 VT_UNEQ_M10 VT_SIZERR_M10
VT_AIS_M10
VT_LOP_M10
0x20046
VT_RMASK11
VT_RX_VTREI_M11 VT_RX_BIP2ERR_M11 VT_RX_ESOVFL_M11 VT_APS_M11 VT_ERDI_M11 VT_RDI_M11
VT_RFI_M11
VT_LOPS_M11 VT_J2TIM_M11
VT_PLM_M11 VT_UNEQ_M11 VT_SIZERR_M11
VT_AIS_M11
VT_LOP_M11
0x20047
VT_RMASK12
VT_RX_VTREI_M12 VT_RX_BIP2ERR_M12 VT_RX_ESOVFL_M12 VT_APS_M12 VT_ERDI_M12 VT_RDI_M12
VT_RFI_M12
VT_LOPS_M12 VT_J2TIM_M12
VT_PLM_M12 VT_UNEQ_M12 VT_SIZERR_M12
VT_AIS_M12
VT_LOP_M12
0x20048
VT_RMASK13
VT_RX_VTREI_M13 VT_RX_BIP2ERR_M13 VT_RX_ESOVFL_M13 VT_APS_M13 VT_ERDI_M13 VT_RDI_M13
VT_RFI_M13
VT_LOPS_M13 VT_J2TIM_M13
VT_PLM_M13 VT_UNEQ_M13 VT_SIZERR_M13
VT_AIS_M13
VT_LOP_M13
0x20049
VT_RMASK14
VT_RX_VTREI_M14 VT_RX_BIP2ERR_M14 VT_RX_ESOVFL_M14 VT_APS_M14 VT_ERDI_M14 VT_RDI_M14
VT_RFI_M14
VT_LOPS_M14 VT_J2TIM_M14
VT_PLM_M14 VT_UNEQ_M14 VT_SIZERR_M14
VT_AIS_M14
VT_LOP_M14
0x2004A
VT_RMASK15
VT_RX_VTREI_M15 VT_RX_BIP2ERR_M15 VT_RX_ESOVFL_M15 VT_APS_M15 VT_ERDI_M15 VT_RDI_M15
VT_RFI_M15
VT_LOPS_M15 VT_J2TIM_M15
VT_PLM_M15 VT_UNEQ_M15 VT_SIZERR_M15
VT_AIS_M15
VT_LOP_M15
0x2004B
VT_RMASK16
VT_RX_VTREI_M16 VT_RX_BIP2ERR_M16 VT_RX_ESOVFL_M16 VT_APS_M16 VT_ERDI_M16 VT_RDI_M16
VT_RFI_M16
VT_LOPS_M16 VT_J2TIM_M16
VT_PLM_M16 VT_UNEQ_M16 VT_SIZERR_M16
VT_AIS_M16
VT_LOP_M16
0x2004C
VT_RMASK17
VT_RX_VTREI_M17 VT_RX_BIP2ERR_M17 VT_RX_ESOVFL_M17 VT_APS_M17 VT_ERDI_M17 VT_RDI_M17
VT_RFI_M17
VT_LOPS_M17 VT_J2TIM_M17
VT_PLM_M17 VT_UNEQ_M17 VT_SIZERR_M17
VT_AIS_M17
VT_LOP_M17
0x2004D
VT_RMASK18
VT_RX_VTREI_M18 VT_RX_BIP2ERR_M18 VT_RX_ESOVFL_M18 VT_APS_M18 VT_ERDI_M18 VT_RDI_M18
VT_RFI_M18
VT_LOPS_M18 VT_J2TIM_M18
VT_PLM_M18 VT_UNEQ_M18 VT_SIZERR_M18
VT_AIS_M18
VT_LOP_M18
0x2004E
VT_RMASK19
VT_RX_VTREI_M19 VT_RX_BIP2ERR_M19 VT_RX_ESOVFL_M19 VT_APS_M19 VT_ERDI_M19 VT_RDI_M19
VT_RFI_M19
VT_LOPS_M19 VT_J2TIM_M19
VT_PLM_M19 VT_UNEQ_M19 VT_SIZERR_M19
VT_AIS_M19
VT_LOP_M19
0x2004F
VT_RMASK20
VT_RX_VTREI_M20 VT_RX_BIP2ERR_M20 VT_RX_ESOVFL_M20 VT_APS_M20 VT_ERDI_M20 VT_RDI_M20
VT_RFI_M20
VT_LOPS_M20 VT_J2TIM_M20
VT_PLM_M20 VT_UNEQ_M20 VT_SIZERR_M20
VT_AIS_M20
VT_LOP_M20
0x20050
VT_RMASK21
VT_RX_VTREI_M21 VT_RX_BIP2ERR_M21 VT_RX_ESOVFL_M21 VT_APS_M21 VT_ERDI_M21 VT_RDI_M21
VT_RFI_M21
VT_LOPS_M21 VT_J2TIM_M21
VT_PLM_M21 VT_UNEQ_M21 VT_SIZERR_M21
VT_AIS_M21
VT_LOP_M21
0x20051
VT_RMASK22
VT_RX_VTREI_M22 VT_RX_BIP2ERR_M22 VT_RX_ESOVFL_M22 VT_APS_M22 VT_ERDI_M22 VT_RDI_M22
VT_RFI_M22
VT_LOPS_M22 VT_J2TIM_M22
VT_PLM_M22 VT_UNEQ_M22 VT_SIZERR_M22
VT_AIS_M22
VT_LOP_M22
0x20052
VT_RMASK23
VT_RX_VTREI_M23 VT_RX_BIP2ERR_M23 VT_RX_ESOVFL_M23 VT_APS_M23 VT_ERDI_M23 VT_RDI_M23
VT_RFI_M23
VT_LOPS_M23 VT_J2TIM_M23
VT_PLM_M23 VT_UNEQ_M23 VT_SIZERR_M23
VT_AIS_M23
VT_LOP_M23
0x20053
VT_RMASK24
VT_RX_VTREI_M24 VT_RX_BIP2ERR_M24 VT_RX_ESOVFL_M24 VT_APS_M24 VT_ERDI_M24 VT_RDI_M24
VT_RFI_M24
VT_LOPS_M24 VT_J2TIM_M24
VT_PLM_M24 VT_UNEQ_M24 VT_SIZERR_M24
VT_AIS_M24
VT_LOP_M24
0x20054
VT_RMASK25
VT_RX_VTREI_M25 VT_RX_BIP2ERR_M25 VT_RX_ESOVFL_M25 VT_APS_M25 VT_ERDI_M25 VT_RDI_M25
VT_RFI_M25
VT_LOPS_M25 VT_J2TIM_M25
VT_PLM_M25 VT_UNEQ_M25 VT_SIZERR_M25
VT_AIS_M25
VT_LOP_M25
0x20055
VT_RMASK26
VT_RX_VTREI_M26 VT_RX_BIP2ERR_M26 VT_RX_ESOVFL_M26 VT_APS_M26 VT_ERDI_M26 VT_RDI_M26
VT_RFI_M26
VT_LOPS_M26 VT_J2TIM_M26
VT_PLM_M26 VT_UNEQ_M26 VT_SIZERR_M26
VT_AIS_M26
VT_LOP_M26
0x20056
VT_RMASK27
VT_RX_VTREI_M27 VT_RX_BIP2ERR_M27 VT_RX_ESOVFL_M27 VT_APS_M27 VT_ERDI_M27 VT_RDI_M27
VT_RFI_M27
VT_LOPS_M27 VT_J2TIM_M27
VT_PLM_M27 VT_UNEQ_M27 VT_SIZERR_M27
VT_AIS_M27
VT_LOP_M27
0x20057
VT_RMASK28
VT_RX_VTREI_M28 VT_RX_BIP2ERR_M28 VT_RX_ESOVFL_M28 VT_APS_M28 VT_ERDI_M28 VT_RDI_M28
VT_RFI_M28
VT_LOPS_M28 VT_J2TIM_M28
VT_PLM_M28 VT_UNEQ_M28 VT_SIZERR_M28
VT_AIS_M28
VT_LOP_M28
Agere Systems Inc.
173
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
10 VT/TU Mapper Registers (continued)
Table 211. VT/TU Mapper Register Map (continued)
Address
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Transmit Interrupt Masks—R/W
0x20058
VT_LOPOHFAIL_MASK
VT_LOPOH_FAIL_
M
0x20059
VT_TMASK1
VT_TX_ESOVFL_M1
VT_LOFS_M1
VT_TX_AIS_M1
VT_TX_LOC_M1
0x2005A
VT_TMASK2
VT_TX_ESOVFL_M2
VT_LOFS_M2
VT_TX_AIS_M2
VT_TX_LOC_M2
0x2005B
VT_TMASK3
VT_TX_ESOVFL_M3
VT_LOFS_M3
VT_TX_AIS_M3
VT_TX_LOC_M3
0x2005C
VT_TMASK4
VT_TX_ESOVFL_M4
VT_LOFS_M4
VT_TX_AIS_M4
VT_TX_LOC_M4
0x2005D
VT_TMASK5
VT_TX_ESOVFL_M5
VT_LOFS_M5
VT_TX_AIS_M5
VT_TX_LOC_M5
0x2005E
VT_TMASK6
VT_TX_ESOVFL_M6
VT_LOFS_M6
VT_TX_AIS_M6
VT_TX_LOC_M6
0x2005F
VT_TMASK7
VT_TX_ESOVFL_M7
VT_LOFS_M7
VT_TX_AIS_M7
VT_TX_LOC_M7
0x20060
VT_TMASK8
VT_TX_ESOVFL_M8
VT_LOFS_M8
VT_TX_AIS_M8
VT_TX_LOC_M8
0x20061
VT_TMASK9
VT_TX_ESOVFL_M9
VT_LOFS_M9
VT_TX_AIS_M9
VT_TX_LOC_M9
0x20062
VT_TMASK10
VT_TX_ESOVFL_M10
VT_LOFS_M10
VT_TX_AIS_M10
VT_TX_LOC_M10
0x20063
VT_TMASK11
VT_TX_ESOVFL_M11
VT_LOFS_M11
VT_TX_AIS_M11
VT_TX_LOC_M11
0x20064
VT_TMASK12
VT_TX_ESOVFL_M12
VT_LOFS_M12
VT_TX_AIS_M12
VT_TX_LOC_M12
0x20065
VT_TMASK13
VT_TX_ESOVFL_M13
VT_LOFS_M13
VT_TX_AIS_M13
VT_TX_LOC_M13
0x20066
VT_TMASK14
VT_TX_ESOVFL_M14
VT_LOFS_M14
VT_TX_AIS_M14
VT_TX_LOC_M14
0x20067
VT_TMASK15
VT_TX_ESOVFL_M15
VT_LOFS_M15
VT_TX_AIS_M15
VT_TX_LOC_M15
0x20068
VT_TMASK16
VT_TX_ESOVFL_M16
VT_LOFS_M16
VT_TX_AIS_M16
VT_TX_LOC_M16
0x20069
VT_TMASK17
VT_TX_ESOVFL_M17
VT_LOFS_M17
VT_TX_AIS_M17
VT_TX_LOC_M17
0x2006A
VT_TMASK18
VT_TX_ESOVFL_M18
VT_LOFS_M18
VT_TX_AIS_M18
VT_TX_LOC_M18
0x2006B
VT_TMASK19
VT_TX_ESOVFL_M19
VT_LOFS_M19
VT_TX_AIS_M19
VT_TX_LOC_M19
0x2006C
VT_TMASK20
VT_TX_ESOVFL_M20
VT_LOFS_M20
VT_TX_AIS_M20
VT_TX_LOC_M20
0x2006D
VT_TMASK21
VT_TX_ESOVFL_M21
VT_LOFS_M21
VT_TX_AIS_M21
VT_TX_LOC_M21
0x2006E
VT_TMASK22
VT_TX_ESOVFL_M22
VT_LOFS_M22
VT_TX_AIS_M22
VT_TX_LOC_M22
0x2006F
VT_TMASK23
VT_TX_ESOVFL_M23
VT_LOFS_M23
VT_TX_AIS_M23
VT_TX_LOC_M23
0x20070
VT_TMASK24
VT_TX_ESOVFL_M24
VT_LOFS_M24
VT_TX_AIS_M24
VT_TX_LOC_M24
0x20071
VT_TMASK25
VT_TX_ESOVFL_M25
VT_LOFS_M25
VT_TX_AIS_M25
VT_TX_LOC_M25
0x20072
VT_TMASK26
VT_TX_ESOVFL_M26
VT_LOFS_M26
VT_TX_AIS_M26
VT_TX_LOC_M26
0x20073
VT_TMASK27
VT_TX_ESOVFL_M27
VT_LOFS_M27
VT_TX_AIS_M27
VT_TX_LOC_M27
0x20074
VT_TMASK28
VT_TX_ESOVFL_M28
VT_LOFS_M28
VT_TX_AIS_M28
VT_TX_LOC_M28
174
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
10 VT/TU Mapper Registers (continued)
Table 211. VT/TU Mapper Register Map (continued)
Address
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Receive State Parameters—RO
0x20075
VT_GSTATE
VT_SD
VT_SF
VT_H4LOMF
0x20076
VT_RSTATE1
VT_ERDI(1)[2:0]
VT_LAB(1)[2:0]
VT_RDI(1)
VT_RFI1
VT_LOPS1
VT_J2TIM1
VT_PLM1
VT_UNEQ1
VT_SIZERR1
VT_AIS1
VT_LOP1
0x20077
VT_RSTATE2
VT_ERDI(2)[2:0]
VT_LAB(2)[2:0]
VT_RDI(2)
VT_RFI2
VT_LOPS2
VT_J2TIM2
VT_PLM2
VT_UNEQ2
VT_SIZERR2
VT_AIS2
VT_LOP2
0x20078
VT_RSTATE3
VT_ERDI(3)[2:0]
VT_LAB(3)[2:0]
VT_RDI(3)
VT_RFI3
VT_LOPS3
VT_J2TIM3
VT_PLM3
VT_UNEQ3
VT_SIZERR3
VT_AIS3
VT_LOP3
0x20079
VT_RSTATE4
VT_ERDI(4)[2:0]
VT_LAB(4)[2:0]
VT_RDI(4)
VT_RFI4
VT_LOPS4
VT_J2TIM4
VT_PLM4
VT_UNEQ4
VT_SIZERR4
VT_AIS4
VT_LOP4
0x2007A
VT_RSTATE5
VT_ERDI(5)[2:0]
VT_LAB(5)[2:0]
VT_RDI(5)
VT_RFI5
VT_LOPS5
VT_J2TIM5
VT_PLM5
VT_UNEQ5
VT_SIZERR5
VT_AIS5
VT_LOP5
0x2007B
VT_RSTATE6
VT_ERDI(6)[2:0]
VT_LAB(6)[2:0]
VT_RDI(6)
VT_RFI6
VT_LOPS6
VT_J2TIM6
VT_PLM6
VT_UNEQ6
VT_SIZERR6
VT_AIS6
VT_LOP6
0x2007C
VT_RSTATE7
VT_ERDI(7)[2:0]
VT_LAB(7)[2:0]
VT_RDI(7)
VT_RFI7
VT_LOPS7
VT_J2TIM7
VT_PLM7
VT_UNEQ7
VT_SIZERR7
VT_AIS7
VT_LOP7
0x2007D
VT_RSTATE8
VT_ERDI(8)[2:0]
VT_LAB(8)[2:0]
VT_RDI(8)
VT_RFI8
VT_LOPS8
VT_J2TIM8
VT_PLM8
VT_UNEQ8
VT_SIZERR8
VT_AIS8
VT_LOP8
0x2007E
VT_RSTATE9
VT_ERDI(9)[2:0]
VT_LAB(9)[2:0]
VT_RDI(9)
VT_RFI9
VT_LOPS9
VT_J2TIM9
VT_PLM9
VT_UNEQ9
VT_SIZERR9
VT_AIS9
VT_LOP9
0x2007F
VT_RSTATE10
VT_ERDI(10)[2:0]
VT_LAB(10)[2:0]
VT_RDI(10)
VT_RFI10
VT_LOPS10
VT_J2TIM10
VT_PLM10
VT_UNEQ10
VT_SIZERR10
VT_AIS10
VT_LOP10
0x20080
VT_RSTATE11
VT_ERDI(11)[2:0]
VT_LAB(11)[2:0]
VT_RDI(11)
VT_RFI11
VT_LOPS11
VT_J2TIM11
VT_PLM11
VT_UNEQ11
VT_SIZERR11
VT_AIS11
VT_LOP11
0x20081
VT_RSTATE12
VT_ERDI(12)[2:0]
VT_LAB(12)[2:0]
VT_RDI(12)
VT_RFI12
VT_LOPS12
VT_J2TIM12
VT_PLM12
VT_UNEQ12
VT_SIZERR12
VT_AIS12
VT_LOP12
0x20082
VT_RSTATE13
VT_ERDI(13)[2:0]
VT_LAB(13)[2:0]
VT_RDI(13)
VT_RFI13
VT_LOPS13
VT_J2TIM13
VT_PLM13
VT_UNEQ13
VT_SIZERR13
VT_AIS13
VT_LOP13
0x20083
VT_RSTATE14
VT_ERDI(14)[2:0]
VT_LAB(14)[2:0]
VT_RDI(14)
VT_RFI14
VT_LOPS14
VT_J2TIM14
VT_PLM14
VT_UNEQ14
VT_SIZERR14
VT_AIS14
VT_LOP14
0x20084
VT_RSTATE15
VT_ERDI(15)[2:0]
VT_LAB(15)[2:0]
VT_RDI(15)
VT_RFI15
VT_LOPS15
VT_J2TIM15
VT_PLM15
VT_UNEQ15
VT_SIZERR15
VT_AIS15
VT_LOP15
0x20085
VT_RSTATE16
VT_ERDI(16)[2:0]
VT_LAB(16)[2:0]
VT_RDI(16)
VT_RFI16
VT_LOPS16
VT_J2TIM16
VT_PLM16
VT_UNEQ16
VT_SIZERR16
VT_AIS16
VT_LOP16
0x20086
VT_RSTATE17
VT_ERDI(17)[2:0]
VT_LAB(17)[2:0]
VT_RDI(17)
VT_RFI17
VT_LOPS17
VT_J2TIM17
VT_PLM17
VT_UNEQ17
VT_SIZERR17
VT_AIS17
VT_LOP17
0x20087
VT_RSTATE18
VT_ERDI(18)[2:0]
VT_LAB(18)[2:0]
VT_RDI(18)
VT_RFI18
VT_LOPS18
VT_J2TIM18
VT_PLM18
VT_UNEQ18
VT_SIZERR18
VT_AIS18
VT_LOP18
0x20088
VT_RSTATE19
VT_ERDI(19)[2:0]
VT_LAB(19)[2:0]
VT_RDI(19)
VT_RFI19
VT_LOPS19
VT_J2TIM19
VT_PLM19
VT_UNEQ19
VT_SIZERR19
VT_AIS19
VT_LOP19
0x20089
VT_RSTATE20
VT_ERDI(20)[2:0]
VT_LAB(20)[2:0]
VT_RDI(20)
VT_RFI20
VT_LOPS20
VT_J2TIM20
VT_PLM20
VT_UNEQ20
VT_SIZERR20
VT_AIS20
VT_LOP20
0x2008A
VT_RSTATE21
VT_ERDI(21)[2:0]
VT_LAB(21)[2:0]
VT_RDI(21)
VT_RFI21
VT_LOPS21
VT_J2TIM21
VT_PLM21
VT_UNEQ21
VT_SIZERR21
VT_AIS21
VT_LOP21
0x2008B
VT_RSTATE22
VT_ERDI(22)[2:0]
VT_LAB(22)[2:0]
VT_RDI(22)
VT_RFI22
VT_LOPS22
VT_J2TIM22
VT_PLM22
VT_UNEQ22
VT_SIZERR22
VT_AIS22
VT_LOP22
0x2008C
VT_RSTATE23
VT_ERDI(23)[2:0]
VT_LAB(23)[2:0]
VT_RDI(23)
VT_RFI23
VT_LOPS23
VT_J2TIM23
VT_PLM23
VT_UNEQ23
VT_SIZERR23
VT_AIS23
VT_LOP23
0x2008D
VT_RSTATE24
VT_ERDI(24)[2:0]
VT_LAB(24)[2:0]
VT_RDI(24)
VT_RFI24
VT_LOPS24
VT_J2TIM24
VT_PLM24
VT_UNEQ24
VT_SIZERR24
VT_AIS24
VT_LOP24
0x2008E
VT_RSTATE25
VT_ERDI(25)[2:0]
VT_LAB(25)[2:0]
VT_RDI(25)
VT_RFI25
VT_LOPS25
VT_J2TIM25
VT_PLM25
VT_UNEQ25
VT_SIZERR25
VT_AIS25
VT_LOP25
0x2008F
VT_RSTATE26
VT_ERDI(26)[2:0]
VT_LAB(26)[2:0]
VT_RDI(26)
VT_RFI26
VT_LOPS26
VT_J2TIM26
VT_PLM26
VT_UNEQ26
VT_SIZERR26
VT_AIS26
VT_LOP26
0x20090
VT_RSTATE27
VT_ERDI(27)[2:0]
VT_LAB(27)[2:0]
VT_RDI(27)
VT_RFI27
VT_LOPS27
VT_J2TIM27
VT_PLM27
VT_UNEQ27
VT_SIZERR27
VT_AIS27
VT_LOP27
0x20091
VT_RSTATE28
VT_ERDI(28)[2:0]
VT_LAB(28)[2:0]
VT_RDI(28)
VT_RFI28
VT_LOPS28
VT_J2TIM28
VT_PLM28
VT_UNEQ28
VT_SIZERR28
VT_AIS28
VT_LOP28
Agere Systems Inc.
175
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
10 VT/TU Mapper Registers (continued)
Table 211. VT/TU Mapper Register Map (continued)
Address
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Receive APS Value Parameters—RO
0x20092
VT_RAPSSTATE1
VT_APS(1)[3:0]
0x20093
VT_RAPSSTATE2
VT_APS(2)[3:0]
0x20094
VT_RAPSSTATE3
VT_APS(3)[3:0]
0x20095
VT_RAPSSTATE4
VT_APS(4)[3:0]
0x20096
VT_RAPSSTATE5
VT_APS(5)[3:0]
0x20097
VT_RAPSSTATE6
VT_APS(6)[3:0]
0x20098
VT_RAPSSTATE7
VT_APS(7)[3:0]
0x20099
VT_RAPSSTATE8
VT_APS(8)[3:0]
0x2009A
VT_RAPSSTATE9
VT_APS(9)[3:0]
0x2009B
VT_RAPSSTATE10
VT_APS(10)[3:0]
0x2009C
VT_RAPSSTATE11
VT_APS(11)[3:0]
0x2009D
VT_RAPSSTATE12
VT_APS(12)[3:0]
0x2009E
VT_RAPSSTATE13
VT_APS(13)[3:0]
0x2009F
VT_RAPSSTATE14
VT_APS(14)[3:0]
0x200A0
VT_RAPSSTATE15
VT_APS(15)[3:0]
0x200A1
VT_RAPSSTATE16
VT_APS(16)[3:0]
0x200A2
VT_RAPSSTATE17
VT_APS(17)[3:0]
0x200A3
VT_RAPSSTATE18
VT_APS(18)[3:0]
0x200A4
VT_RAPSSTATE19
VT_APS(19)[3:0]
0x200A5
VT_RAPSSTATE20
VT_APS(20)[3:0]
0x200A6
VT_RAPSSTATE21
VT_APS(21)[3:0]
0x200A7
VT_RAPSSTATE22
VT_APS(22)[3:0]
0x200A8
VT_RAPSSTATE23
VT_APS(23)[3:0]
0x200A9
VT_RAPSSTATE24
VT_APS(24)[3:0]
0x200AA
VT_RAPSSTATE25
VT_APS(25)[3:0]
0x200AB
VT_RAPSSTATE26
VT_APS(26)[3:0]
0x200AC
VT_RAPSSTATE27
VT_APS(27)[3:0]
0x200AD
VT_RAPSSTATE28
VT_APS(28)[3:0]
176
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
10 VT/TU Mapper Registers (continued)
Table 211. VT/TU Mapper Register Map (continued)
Address
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Transmit State Parameters—RO
0x200AE
VT_TSTATE1
VT_LOFS1
VT_TX_AIS1
VT_TX_LOC1
0x200AF
VT_TSTATE2
VT_LOFS2
VT_TX_AIS2
VT_TX_LOC2
0x200B0
VT_TSTATE3
VT_LOFS3
VT_TX_AIS3
VT_TX_LOC3
0x200B1
VT_TSTATE4
VT_LOFS4
VT_TX_AIS4
VT_TX_LOC4
0x200B2
VT_TSTATE5
VT_LOFS5
VT_TX_AIS5
VT_TX_LOC5
0x200B3
VT_TSTATE6
VT_LOFS6
VT_TX_AIS6
VT_TX_LOC6
0x200B4
VT_TSTATE7
VT_LOFS7
VT_TX_AIS7
VT_TX_LOC7
0x200B5
VT_TSTATE8
VT_LOFS8
VT_TX_AIS8
VT_TX_LOC8
0x200B6
VT_TSTATE9
VT_LOFS9
VT_TX_AIS9
VT_TX_LOC9
0x200B7
VT_TSTATE10
VT_LOFS10
VT_TX_AIS10 VT_TX_LOC10
0x200B8
VT_TSTATE11
VT_LOFS11
VT_TX_AIS11 VT_TX_LOC11
0x200B9
VT_TSTATE12
VT_LOFS12
VT_TX_AIS12 VT_TX_LOC12
0x200BA
VT_TSTATE13
VT_LOFS13
VT_TX_AIS13 VT_TX_LOC13
0x200BB
VT_TSTATE14
VT_LOFS14
VT_TX_AIS14 VT_TX_LOC14
0x200BC
VT_TSTATE15
VT_LOFS15
VT_TX_AIS15 VT_TX_LOC15
0x200BD
VT_TSTATE16
VT_LOFS16
VT_TX_AIS16 VT_TX_LOC16
0x200BE
VT_TSTATE17
VT_LOFS17
VT_TX_AIS17 VT_TX_LOC17
0x200BF
VT_TSTATE18
VT_LOFS18
VT_TX_AIS18 VT_TX_LOC18
0x200C0
VT_TSTATE19
VT_LOFS19
VT_TX_AIS19 VT_TX_LOC19
0x200C1
VT_TSTATE20
VT_LOFS20
VT_TX_AIS20 VT_TX_LOC20
0x200C2
VT_TSTATE21
VT_LOFS21
VT_TX_AIS21 VT_TX_LOC21
0x200C3
VT_TSTATE22
VT_LOFS22
VT_TX_AIS22 VT_TX_LOC22
0x200C4
VT_TSTATE23
VT_LOFS23
VT_TX_AIS23 VT_TX_LOC23
0x200C5
VT_TSTATE24
VT_LOFS24
VT_TX_AIS24 VT_TX_LOC24
0x200C6
VT_TSTATE25
VT_LOFS25
VT_TX_AIS25 VT_TX_LOC25
0x200C7
VT_TSTATE26
VT_LOFS26
VT_TX_AIS26 VT_TX_LOC26
0x200C8
VT_TSTATE27
VT_LOFS27
VT_TX_AIS27 VT_TX_LOC27
0x200C9
VT_TSTATE28
VT_LOFS28
VT_TX_AIS28 VT_TX_LOC28
Agere Systems Inc.
177
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
10 VT/TU Mapper Registers (continued)
Table 211. VT/TU Mapper Register Map (continued)
Address
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
VT Global Control Parameters—R/W
0x200CA
VT_GCTL1
0x200CB
VT_GCTL2
0x200CC
VT_GCTL3
VT_LOPS_NTIME[3:0]
VT_H4_NTIME[3:0]
0x200CD
VT_GCTL4
VT_Z6_NTIME[3:0]
VT_J2_NTIME[3:0]
VT_INV_NTIME[3:0]
VT_NDF_NTIME[3:0]
0x200CE
VT_GCTL5
VT_APS_NTIME[3:0]
VT_LAB_NTIME[3:0]
VT_ERDI_NTIME[3:0]
VT_RDI_NTIME[3:0]
VT_RX_GRP_TYPE[6:0]
VT_TX_GRP_TYPE[6:0]
VT_LOPS_AIS VT_J2TIM_ER VT_J2TIM_RDI VT_J2TIM_AIS VT_LOMF_AIS VT_PLM_AIS_I VT_UNEQ_AIS
_INH
DI_INH
_INH
_INH
_INH
NH
_INH
VT_UPSR
VT_8ORMAJO VT_BIT_BLO
RITY
CK_CNT
Signal Degrade Control—R/W
0x200CF
VT_SIGDEG_
CTL1
0x200D0
VT_SIGDEG_
CTL2
0x200D1
VT_SIGDEG_
CTL3
0x200D2
VT_SIGDEG_
CTL4
0x200D3
VT_SIGDEG_
CTL5
0x200D4
VT_SIGDEG_
CTL6
0x200D5
VT_SIGDEG_
CTL7
0x200D6
VT_SIGFAIL_
CTL1
0x200D7
VT_SIGFAIL_
CTL2
0x200D8
VT_SIGFAIL_
CTL3
0x200D9
VT_SIGFAIL_
CTL4
0x200DA
VT_SIGFAIL_
CTL5
0x200DB
VT_SIGFAIL_
CTL6
VT_SFCLEAR
VT_SFSET
VT_SDCLEAR
VT_SDSET
VT_BER_CH_SEL[4:0]
VT_SDNSSET[18:3]
VT_SDMSET[7:0]
VT_SDLSET[3:0]
VT_SDNSSET[2:0]
VT_SDLCLEAR[3:0]
VT_SDNSCLEAR[2:0]
VT_SFLSET[3:0]
VT_SFNSSET[2:0]
VT_SFLCLEAR[3:0]
VT_SFNSCLEAR[2:0]
VT_SDBSET[15:0]
VT_SDNSCLEAR[18:3]
VT_SDMCLEAR[7:0]
VT_SDBCLEAR[15:0]
Signal Fail Control—R/W
178
VT_SFNSSET[18:3]
VT_SFMSET[7:0]
VT_SFBSET[15:0]
VT_SFNSCLEAR[18:3]
VT_SFMCLEAR[7:0]
VT_SFBCLEAR[15:0]
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
10 VT/TU Mapper Registers (continued)
Table 211. VT/TU Mapper Register Map (continued)
Address
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Transmit Control Parameters—R/W
0x200DC
VT_TCTL1
VT_TX_ERDI_EN1
VT_ERDI_EN1
VT_RDI_EN1
VT_RFI_EN1
VT_REI_EN1
VT_AIS_INS1
VT_TX_CLKEDGE1
VT_LB_SEL1
VT_TX_MAPTYPE(1)[3:0]
0x200DD
VT_TCTL2
VT_TX_ERDI_EN2
VT_ERDI_EN2
VT_RDI_EN2
VT_RFI_EN2
VT_REI_EN2
VT_AIS_INS2
VT_TX_CLKEDGE2
VT_LB_SEL2
VT_TX_MAPTYPE(2)[3:0]
0x200DE
VT_TCTL3
VT_TX_ERDI_EN3
VT_ERDI_EN3
VT_RDI_EN3
VT_RFI_EN3
VT_REI_EN3
VT_AIS_INS3
VT_TX_CLKEDGE3
VT_LB_SEL3
VT_TX_MAPTYPE(3)[3:0]
0x200DF
VT_TCTL4
VT_TX_ERDI_EN4
VT_ERDI_EN4
VT_RDI_EN4
VT_RFI_EN4
VT_REI_EN4
VT_AIS_INS4
VT_TX_CLKEDGE4
VT_LB_SEL4
VT_TX_MAPTYPE(4)[3:0]
0x200E0
VT_TCTL5
VT_TX_ERDI_EN5
VT_ERDI_EN5
VT_RDI_EN5
VT_RFI_EN5
VT_REI_EN5
VT_AIS_INS5
VT_TX_CLKEDGE5
VT_LB_SEL5
VT_TX_MAPTYPE(5)[3:0]
0x200E1
VT_TCTL6
VT_TX_ERDI_EN6
VT_ERDI_EN6
VT_RDI_EN6
VT_RFI_EN6
VT_REI_EN6
VT_AIS_INS6
VT_TX_CLKEDGE6
VT_LB_SEL6
VT_TX_MAPTYPE(6)[3:0]
0x200E2
VT_TCTL7
VT_TX_ERDI_EN7
VT_ERDI_EN7
VT_RDI_EN7
VT_RFI_EN7
VT_REI_EN7
VT_AIS_INS7
VT_TX_CLKEDGE7
VT_LB_SEL7
VT_TX_MAPTYPE(7)[3:0]
0x200E3
VT_TCTL8
VT_TX_ERDI_EN8
VT_ERDI_EN8
VT_RDI_EN8
VT_RFI_EN8
VT_REI_EN8
VT_AIS_INS8
VT_TX_CLKEDGE8
VT_LB_SEL8
VT_TX_MAPTYPE(8)[3:0]
0x200E4
VT_TCTL9
VT_TX_ERDI_EN9
VT_ERDI_EN9
VT_RDI_EN9
VT_RFI_EN9
VT_REI_EN9
VT_AIS_INS9
VT_TX_CLKEDGE9
VT_LB_SEL9
VT_TX_MAPTYPE(9)[3:0]
0x200E5
VT_TCTL10
VT_TX_ERDI_EN10
VT_ERDI_EN10
VT_RDI_EN10
VT_RFI_EN10
VT_REI_EN10
VT_AIS_INS10
VT_TX_CLKEDGE10
VT_LB_SEL10
VT_TX_MAPTYPE(10)[3:0]
0x200E6
VT_TCTL11
VT_TX_ERDI_EN11
VT_ERDI_EN11
VT_RDI_EN11
VT_RFI_EN11
VT_REI_EN11
VT_AIS_INS11
VT_TX_CLKEDGE11
VT_LB_SEL11
VT_TX_MAPTYPE(11)[3:0]
0x200E7
VT_TCTL12
VT_TX_ERDI_EN12
VT_ERDI_EN12
VT_RDI_EN12
VT_RFI_EN12
VT_REI_EN12
VT_AIS_INS12
VT_TX_CLKEDGE12
VT_LB_SEL12
VT_TX_MAPTYPE(12)[3:0]
0x200E8
VT_TCTL13
VT_TX_ERDI_EN13
VT_ERDI_EN13
VT_RDI_EN13
VT_RFI_EN13
VT_REI_EN13
VT_AIS_INS13
VT_TX_CLKEDGE13
VT_LB_SEL13
VT_TX_MAPTYPE(13)[3:0]
0x200E9
VT_TCTL14
VT_TX_ERDI_EN14
VT_ERDI_EN14
VT_RDI_EN14
VT_RFI_EN14
VT_REI_EN14
VT_AIS_INS14
VT_TX_CLKEDGE14
VT_LB_SEL14
VT_TX_MAPTYPE(14)[3:0]
0x200EA
VT_TCTL15
VT_TX_ERDI_EN15
VT_ERDI_EN15
VT_RDI_EN15
VT_RFI_EN15
VT_REI_EN15
VT_AIS_INS15
VT_TX_CLKEDGE15
VT_LB_SEL15
VT_TX_MAPTYPE(15)[3:0]
0x200EB
VT_TCTL16
VT_TX_ERDI_EN16
VT_ERDI_EN16
VT_RDI_EN16
VT_RFI_EN16
VT_REI_EN16
VT_AIS_INS16
VT_TX_CLKEDGE16
VT_LB_SEL16
VT_TX_MAPTYPE(16)[3:0]
0x200EC
VT_TCTL17
VT_TX_ERDI_EN17
VT_ERDI_EN17
VT_RDI_EN17
VT_RFI_EN17
VT_REI_EN17
VT_AIS_INS17
VT_TX_CLKEDGE17
VT_LB_SEL17
VT_TX_MAPTYPE(17)[3:0]
0x200ED
VT_TCTL18
VT_TX_ERDI_EN18
VT_ERDI_EN18
VT_RDI_EN18
VT_RFI_EN18
VT_REI_EN18
VT_AIS_INS18
VT_TX_CLKEDGE18
VT_LB_SEL18
VT_TX_MAPTYPE(18)[3:0]
0x200EE
VT_TCTL19
VT_TX_ERDI_EN19
VT_ERDI_EN19
VT_RDI_EN19
VT_RFI_EN19
VT_REI_EN19
VT_AIS_INS19
VT_TX_CLKEDGE19
VT_LB_SEL19
VT_TX_MAPTYPE(19)[3:0]
0x200EF
VT_TCTL20
VT_TX_ERDI_EN20
VT_ERDI_EN20
VT_RDI_EN20
VT_RFI_EN20
VT_REI_EN20
VT_AIS_INS20
VT_TX_CLKEDGE20
VT_LB_SEL20
VT_TX_MAPTYPE(20)[3:0]
0x200F0
VT_TCTL21
VT_TX_ERDI_EN21
VT_ERDI_EN21
VT_RDI_EN21
VT_RFI_EN21
VT_REI_EN21
VT_AIS_INS21
VT_TX_CLKEDGE21
VT_LB_SEL21
VT_TX_MAPTYPE(21)[3:0]
0x200F1
VT_TCTL22
VT_TX_ERDI_EN22
VT_ERDI_EN22
VT_RDI_EN22
VT_RFI_EN22
VT_REI_EN22
VT_AIS_INS22
VT_TX_CLKEDGE22
VT_LB_SEL22
VT_TX_MAPTYPE(22)[3:0]
0x200F2
VT_TCTL23
VT_TX_ERDI_EN23
VT_ERDI_EN23
VT_RDI_EN23
VT_RFI_EN23
VT_REI_EN23
VT_AIS_INS23
VT_TX_CLKEDGE23
VT_LB_SEL23
VT_TX_MAPTYPE(23)[3:0]
0x200F3
VT_TCTL24
VT_TX_ERDI_EN24
VT_ERDI_EN24
VT_RDI_EN24
VT_RFI_EN24
VT_REI_EN24
VT_AIS_INS24
VT_TX_CLKEDGE24
VT_LB_SEL24
VT_TX_MAPTYPE(24)[3:0]
0x200F4
VT_TCTL25
VT_TX_ERDI_EN25
VT_ERDI_EN25
VT_RDI_EN25
VT_RFI_EN25
VT_REI_EN25
VT_AIS_INS25
VT_TX_CLKEDGE25
VT_LB_SEL25
VT_TX_MAPTYPE(25)[3:0]
0x200F5
VT_TCTL26
VT_TX_ERDI_EN26
VT_ERDI_EN26
VT_RDI_EN26
VT_RFI_EN26
VT_REI_EN26
VT_AIS_INS26
VT_TX_CLKEDGE26
VT_LB_SEL26
VT_TX_MAPTYPE(26)[3:0]
0x200F6
VT_TCTL27
VT_TX_ERDI_EN27
VT_ERDI_EN27
VT_RDI_EN27
VT_RFI_EN27
VT_REI_EN27
VT_AIS_INS27
VT_TX_CLKEDGE27
VT_LB_SEL27
VT_TX_MAPTYPE(27)[3:0]
0x200F7
VT_TCTL28
VT_TX_ERDI_EN28
VT_ERDI_EN28
VT_RDI_EN28
VT_RFI_EN28
VT_REI_EN28
VT_AIS_INS28
VT_TX_CLKEDGE28
VT_LB_SEL28
VT_TX_MAPTYPE(28)[3:0]
Agere Systems Inc.
179
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
10 VT/TU Mapper Registers (continued)
Table 211. VT/TU Mapper Register Map (continued)
Address
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Transmit TU OH Control Parameters—R/W
0x200F8
VT_TTUOH_CTL1
VT_O_INS(1)[1:0]
VT_Z7_INS(1)[1:0]
VT_Z6_INS(1)[1:0]
VT_J2_INS(1)[1:0]
VT_V5_INS1
VT_BIP2ERR_INS(1)[1:0]
0x200F9
VT_TTUOH_CTL2
VT_O_INS(2)[1:0]
VT_Z7_INS(2)[1:0]
VT_Z6_INS(2)[1:0]
VT_J2_INS(2)[1:0]
VT_V5_INS2
VT_BIP2ERR_INS(2)[1:0]
0x200FA
VT_TTUOH_CTL3
VT_O_INS(3)[1:0]
VT_Z7_INS(3)[1:0]
VT_Z6_INS(3)[1:0]
VT_J2_INS(3)[1:0]
VT_V5_INS3
VT_BIP2ERR_INS(3)[1:0]
0x200FB
VT_TTUOH_CTL4
VT_O_INS(4)[1:0]
VT_Z7_INS(4)[1:0]
VT_Z6_INS(4)[1:0]
VT_J2_INS(4)[1:0]
VT_V5_INS4
VT_BIP2ERR_INS(4)[1:0]
0x200FC
VT_TTUOH_CTL5
VT_O_INS(5)[1:0]
VT_Z7_INS(5)[1:0]
VT_Z6_INS(5)[1:0]
VT_J2_INS(5)[1:0]
VT_V5_INS5
VT_BIP2ERR_INS(5)[1:0]
0x200FD
VT_TTUOH_CTL6
VT_O_INS(6)[1:0]
VT_Z7_INS(6)[1:0]
VT_Z6_INS(6)[1:0]
VT_J2_INS(6)[1:0]
VT_V5_INS6
VT_BIP2ERR_INS(6)[1:0]
0x200FE
VT_TTUOH_CTL7
VT_O_INS(7)[1:0]
VT_Z7_INS(7)[1:0]
VT_Z6_INS(7)[1:0]
VT_J2_INS(7)[1:0]
VT_V5_INS7
VT_BIP2ERR_INS(7)[1:0]
0x200FF
VT_TTUOH_CTL8
VT_O_INS(8)[1:0]
VT_Z7_INS(8)[1:0]
VT_Z6_INS(8)[1:0]
VT_J2_INS(8)[1:0]
VT_V5_INS8
VT_BIP2ERR_INS(8)[1:0]
0x20100
VT_TTUOH_CTL9
VT_O_INS(9)[1:0]
VT_Z7_INS(9)[1:0]
VT_Z6_INS(9)[1:0]
VT_J2_INS(9)[1:0]
VT_V5_INS9
VT_BIP2ERR_INS(9)[1:0]
0x20101
VT_TTUOH_CTL10
VT_O_INS(10)[1:0]
VT_Z7_INS(10)[1:0]
VT_Z6_INS(10)[1:0]
VT_J2_INS(10)[1:0]
VT_V5_INS10
VT_BIP2ERR_INS(10)[1:0]
0x20102
VT_TTUOH_CTL11
VT_O_INS(11)[1:0]
VT_Z7_INS(11)[1:0]
VT_Z6_INS(11)[1:0]
VT_J2_INS(11)[1:0]
VT_V5_INS11
VT_BIP2ERR_INS(11)[1:0]
0x20103
VT_TTUOH_CTL12
VT_O_INS(12)[1:0]
VT_Z7_INS(12)[1:0]
VT_Z6_INS(12)[1:0]
VT_J2_INS(12)[1:0]
VT_V5_INS12
VT_BIP2ERR_INS(12)[1:0]
0x20104
VT_TTUOH_CTL13
VT_O_INS(13)[1:0]
VT_Z7_INS(13)[1:0]
VT_Z6_INS(13)[1:0]
VT_J2_INS(13)[1:0]
VT_V5_INS13
VT_BIP2ERR_INS(13)[1:0]
0x20105
VT_TTUOH_CTL14
VT_O_INS(14)[1:0]
VT_Z7_INS(14)[1:0]
VT_Z6_INS(14)[1:0]
VT_J2_INS(14)[1:0]
VT_V5_INS14
VT_BIP2ERR_INS(14)[1:0]
0x20106
VT_TTUOH_CTL15
VT_O_INS(15)[1:0]
VT_Z7_INS(15)[1:0]
VT_Z6_INS(15)[1:0]
VT_J2_INS(15)[1:0]
VT_V5_INS15
VT_BIP2ERR_INS(15)[1:0]
0x20107
VT_TTUOH_CTL16
VT_O_INS(16)[1:0]
VT_Z7_INS(16)[1:0]
VT_Z6_INS(16)[1:0]
VT_J2_INS(16)[1:0]
VT_V5_INS16
VT_BIP2ERR_INS(16)[1:0]
0x20108
VT_TTUOH_CTL17
VT_O_INS(17)[1:0]
VT_Z7_INS(17)[1:0]
VT_Z6_INS(17)[1:0]
VT_J2_INS(17)[1:0]
VT_V5_INS17
VT_BIP2ERR_INS(17)[1:0]
0x20109
VT_TTUOH_CTL18
VT_O_INS(18)[1:0]
VT_Z7_INS(18)[1:0]
VT_Z6_INS(18)[1:0]
VT_J2_INS(18)[1:0]
VT_V5_INS18
VT_BIP2ERR_INS(18)[1:0]
0x2010A
VT_TTUOH_CTL19
VT_O_INS(19)[1:0]
VT_Z7_INS(19)[1:0]
VT_Z6_INS(19)[1:0]
VT_J2_INS(19)[1:0]
VT_V5_INS19
VT_BIP2ERR_INS(19)[1:0]
0x2010B
VT_TTUOH_CTL20
VT_O_INS(20)[1:0]
VT_Z7_INS(20)[1:0]
VT_Z6_INS(20)[1:0]
VT_J2_INS(20)[1:0]
VT_V5_INS20
VT_BIP2ERR_INS(20)[1:0]
0x2010C
VT_TTUOH_CTL21
VT_O_INS(21)[1:0]
VT_Z7_INS(21)[1:0]
VT_Z6_INS(21)[1:0]
VT_J2_INS(21)[1:0]
VT_V5_INS21
VT_BIP2ERR_INS(21)[1:0]
0x2010D
VT_TTUOH_CTL22
VT_O_INS(22)[1:0]
VT_Z7_INS(22)[1:0]
VT_Z6_INS(22)[1:0]
VT_J2_INS(22)[1:0]
VT_V5_INS22
VT_BIP2ERR_INS(22)[1:0]
0x2010E
VT_TTUOH_CTL23
VT_O_INS(23)[1:0]
VT_Z7_INS(23)[1:0]
VT_Z6_INS(23)[1:0]
VT_J2_INS(23)[1:0]
VT_V5_INS23
VT_BIP2ERR_INS(23)[1:0]
0x2010F
VT_TTUOH_CTL24
VT_O_INS(24)[1:0]
VT_Z7_INS(24)[1:0]
VT_Z6_INS(24)[1:0]
VT_J2_INS(24)[1:0]
VT_V5_INS24
VT_BIP2ERR_INS(24)[1:0]
0x20110
VT_TTUOH_CTL25
VT_O_INS(25)[1:0]
VT_Z7_INS(25)[1:0]
VT_Z6_INS(25)[1:0]
VT_J2_INS(25)[1:0]
VT_V5_INS25
VT_BIP2ERR_INS(25)[1:0]
0x20111
VT_TTUOH_CTL26
VT_O_INS(26)[1:0]
VT_Z7_INS(26)[1:0]
VT_Z6_INS(26)[1:0]
VT_J2_INS(26)[1:0]
VT_V5_INS26
VT_BIP2ERR_INS(26)[1:0]
0x20112
VT_TTUOH_CTL27
VT_O_INS(27)[1:0]
VT_Z7_INS(27)[1:0]
VT_Z6_INS(27)[1:0]
VT_J2_INS(27)[1:0]
VT_V5_INS27
VT_BIP2ERR_INS(27)[1:0]
0x20113
VT_TTUOH_CTL28
VT_O_INS(28)[1:0]
VT_Z7_INS(28)[1:0]
VT_Z6_INS(28)[1:0]
VT_J2_INS(28)[1:0]
VT_V5_INS28
VT_BIP2ERR_INS(28)[1:0]
180
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
10 VT/TU Mapper Registers (continued)
Table 211. VT/TU Mapper Register Map (continued)
Address
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Transmit APS and Remote Indication—R/W
0x20114
VT_TAPSRIVAL1
VT_APS_INS(1)[3:0]
VT_ERDI_INS(1)[2:0]
VT_RDI_INS1
VT_RFI_INS1
0x20115
VT_TAPSRIVAL2
VT_APS_INS(2)[3:0]
VT_ERDI_INS(2)[2:0]
VT_RDI_INS2
VT_RFI_INS2
0x20116
VT_TAPSRIVAL3
VT_APS_INS(3)[3:0]
VT_ERDI_INS(3)[2:0]
VT_RDI_INS3
VT_RFI_INS3
0x20117
VT_TAPSRIVAL4
VT_APS_INS(4)[3:0]
VT_ERDI_INS(4)[2:0]
VT_RDI_INS4
VT_RFI_INS4
0x20118
VT_TAPSRIVAL5
VT_APS_INS(5)[3:0]
VT_ERDI_INS(5)[2:0]
VT_RDI_INS5
VT_RFI_INS5
0x20119
VT_TAPSRIVAL6
VT_APS_INS(6)[3:0]
VT_ERDI_INS(6)[2:0]
VT_RDI_INS6
VT_RFI_INS6
0x2011A
VT_TAPSRIVAL7
VT_APS_INS(7)[3:0]
VT_ERDI_INS(7)[2:0]
VT_RDI_INS7
VT_RFI_INS7
0x2011B
VT_TAPSRIVAL8
VT_APS_INS(8)[3:0]
VT_ERDI_INS(8)[2:0]
VT_RDI_INS8
VT_RFI_INS8
0x2011C
VT_TAPSRIVAL9
VT_APS_INS(9)[3:0]
VT_ERDI_INS(9)[2:0]
VT_RDI_INS9
VT_RFI_INS9
0x2011D
VT_TAPSRIVAL10
VT_APS_INS(10)[3:0]
VT_ERDI_INS(10)[2:0]
VT_RDI_INS10
VT_RFI_INS10
0x2011E
VT_TAPSRIVAL11
VT_APS_INS(11)[3:0]
VT_ERDI_INS(11)[2:0]
VT_RDI_INS11
VT_RFI_INS11
0x2011F
VT_TAPSRIVAL12
VT_APS_INS(12)[3:0]
VT_ERDI_INS(12)[2:0]
VT_RDI_INS12
VT_RFI_INS12
0x20120
VT_TAPSRIVAL13
VT_APS_INS(13)[3:0]
VT_ERDI_INS(13)[2:0]
VT_RDI_INS13
VT_RFI_INS13
0x20121
VT_TAPSRIVAL14
VT_APS_INS(14)[3:0]
VT_ERDI_INS(14)[2:0]
VT_RDI_INS14
VT_RFI_INS14
0x20122
VT_TAPSRIVAL15
VT_APS_INS(15)[3:0]
VT_ERDI_INS(15)[2:0]
VT_RDI_INS15
VT_RFI_INS15
0x20123
VT_TAPSRIVAL16
VT_APS_INS(16)[3:0]
VT_ERDI_INS(16)[2:0]
VT_RDI_INS16
VT_RFI_INS16
0x20124
VT_TAPSRIVAL17
VT_APS_INS(17)[3:0]
VT_ERDI_INS(17)[2:0]
VT_RDI_INS17
VT_RFI_INS17
0x20125
VT_TAPSRIVAL18
VT_APS_INS(18)[3:0]
VT_ERDI_INS(18)[2:0]
VT_RDI_INS18
VT_RFI_INS18
0x20126
VT_TAPSRIVAL19
VT_APS_INS(19)[3:0]
VT_ERDI_INS(19)[2:0]
VT_RDI_INS19
VT_RFI_INS19
0x20127
VT_TAPSRIVAL20
VT_APS_INS(20)[3:0]
VT_ERDI_INS(20)[2:0]
VT_RDI_INS20
VT_RFI_INS20
0x20128
VT_TAPSRIVAL21
VT_APS_INS(21)[3:0]
VT_ERDI_INS(21)[2:0]
VT_RDI_INS21
VT_RFI_INS21
0x20129
VT_TAPSRIVAL22
VT_APS_INS(22)[3:0]
VT_ERDI_INS(22)[2:0]
VT_RDI_INS22
VT_RFI_INS22
0x2012A
VT_TAPSRIVAL23
VT_APS_INS(23)[3:0]
VT_ERDI_INS(23)[2:0]
VT_RDI_INS23
VT_RFI_INS23
0x2012B
VT_TAPSRIVAL24
VT_APS_INS(24)[3:0]
VT_ERDI_INS(24)[2:0]
VT_RDI_INS24
VT_RFI_INS24
0x2012C
VT_TAPSRIVAL25
VT_APS_INS(25)[3:0]
VT_ERDI_INS(25)[2:0]
VT_RDI_INS25
VT_RFI_INS25
0x2012D
VT_TAPSRIVAL26
VT_APS_INS(26)[3:0]
VT_ERDI_INS(26)[2:0]
VT_RDI_INS26
VT_RFI_INS26
0x2012E
VT_TAPSRIVAL27
VT_APS_INS(27)[3:0]
VT_ERDI_INS(27)[2:0]
VT_RDI_INS27
VT_RFI_INS27
0x2012F
VT_TAPSRIVAL28
VT_APS_INS(28)[3:0]
VT_ERDI_INS(28)[2:0]
VT_RDI_INS28
VT_RFI_INS28
Agere Systems Inc.
181
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
10 VT/TU Mapper Registers (continued)
Table 211. VT/TU Mapper Register Map (continued)
Address
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Transmit Software Overwrite Parameters—R/W
0x20130
VT_TSWOW1
VT_OBIT_INS(1)[7:0]
VT_Z6BYTE_INS(1)[7:0]
0x20131
VT_TSWOW2
VT_OBIT_INS(2)[7:0]
VT_Z6BYTE_INS(2)[7:0]
0x20132
VT_TSWOW3
VT_OBIT_INS(3)[7:0]
VT_Z6BYTE_INS(3)[7:0]
0x20133
VT_TSWOW4
VT_OBIT_INS(4)[7:0]
VT_Z6BYTE_INS(4)[7:0]
0x20134
VT_TSWOW5
VT_OBIT_INS(5)[7:0]
VT_Z6BYTE_INS(5)[7:0]
0x20135
VT_TSWOW6
VT_OBIT_INS(6)[7:0]
VT_Z6BYTE_INS(6)[7:0]
0x20136
VT_TSWOW7
VT_OBIT_INS(7)[7:0]
VT_Z6BYTE_INS(7)[7:0]
0x20137
VT_TSWOW8
VT_OBIT_INS(8)[7:0]
VT_Z6BYTE_INS(8)[7:0]
0x20138
VT_TSWOW9
VT_OBIT_INS(9)[7:0]
VT_Z6BYTE_INS(9)[7:0]
0x20139
VT_TSWOW10
VT_OBIT_INS(10)[7:0]
VT_Z6BYTE_INS(10)[7:0]
0x2013A
VT_TSWOW11
VT_OBIT_INS(11)[7:0]
VT_Z6BYTE_INS(11)[7:0]
0x2013B
VT_TSWOW12
VT_OBIT_INS(12)[7:0]
VT_Z6BYTE_INS(12)[7:0]
0x2013C
VT_TSWOW13
VT_OBIT_INS(13)[7:0]
VT_Z6BYTE_INS(13)[7:0]
0x2013D
VT_TSWOW14
VT_OBIT_INS(14)[7:0]
VT_Z6BYTE_INS(14)[7:0]
0x2013E
VT_TSWOW15
VT_OBIT_INS(15)[7:0]
VT_Z6BYTE_INS(15)[7:0]
0x2013F
VT_TSWOW16
VT_OBIT_INS(16)[7:0]
VT_Z6BYTE_INS(16)[7:0]
0x20140
VT_TSWOW17
VT_OBIT_INS(17)[7:0]
VT_Z6BYTE_INS(17)[7:0]
0x20141
VT_TSWOW18
VT_OBIT_INS(18)[7:0]
VT_Z6BYTE_INS(18)[7:0]
0x20142
VT_TSWOW19
VT_OBIT_INS(19)[7:0]
VT_Z6BYTE_INS(19)[7:0]
0x20143
VT_TSWOW20
VT_OBIT_INS(20)[7:0]
VT_Z6BYTE_INS(20)[7:0]
0x20144
VT_TSWOW21
VT_OBIT_INS(21)[7:0]
VT_Z6BYTE_INS(21)[7:0]
0x20145
VT_TSWOW22
VT_OBIT_INS(22)[7:0]
VT_Z6BYTE_INS(22)[7:0]
0x20146
VT_TSWOW23
VT_OBIT_INS(23)[7:0]
VT_Z6BYTE_INS(23)[7:0]
0x20147
VT_TSWOW24
VT_OBIT_INS(24)[7:0]
VT_Z6BYTE_INS(24)[7:0]
0x20148
VT_TSWOW25
VT_OBIT_INS(25)[7:0]
VT_Z6BYTE_INS(25)[7:0]
0x20149
VT_TSWOW26
VT_OBIT_INS(26)[7:0]
VT_Z6BYTE_INS(26)[7:0]
0x2014A
VT_TSWOW27
VT_OBIT_INS(27)[7:0]
VT_Z6BYTE_INS(27)[7:0]
0x2014B
VT_TSWOW28
VT_OBIT_INS(28)[7:0]
VT_Z6BYTE_INS(28)[7:0]
182
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
10 VT/TU Mapper Registers (continued)
Table 211. VT/TU Mapper Register Map (continued)
Address
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Transmit Signaling Control Parameters—R/W
0x2014C
VT_TSIG_CTL1
VT_USE_FBIT1
VT_USE_PBIT1
VT_USE_SBIT1
VT_TXSIG_CH_SEL(1)[4:0]
0x2014D
VT_TSIG_CTL2
VT_USE_FBIT2
VT_USE_PBIT2
VT_USE_SBIT2
VT_TXSIG_CH_SEL(2)[4:0]
0x2014E
VT_TSIG_CTL3
VT_USE_FBIT3
VT_USE_PBIT3
VT_USE_SBIT3
VT_TXSIG_CH_SEL(3)[4:0]
0x2014F
VT_TSIG_CTL4
VT_USE_FBIT4
VT_USE_PBIT4
VT_USE_SBIT4
VT_TXSIG_CH_SEL(4)[4:0]
0x20150
VT_TSIG_CTL5
VT_USE_FBIT5
VT_USE_PBIT5
VT_USE_SBIT5
VT_TXSIG_CH_SEL(5)[4:0]
0x20151
VT_TSIG_CTL6
VT_USE_FBIT6
VT_USE_PBIT6
VT_USE_SBIT6
VT_TXSIG_CH_SEL(6)[4:0]
0x20152
VT_TSIG_CTL7
VT_USE_FBIT7
VT_USE_PBIT7
VT_USE_SBIT7
VT_TXSIG_CH_SEL(7)[4:0]
0x20153
VT_TSIG_CTL8
VT_USE_FBIT8
VT_USE_PBIT8
VT_USE_SBIT8
VT_TXSIG_CH_SEL(8)[4:0]
0x20154
VT_TSIG_CTL9
VT_USE_FBIT9
VT_USE_PBIT9
VT_USE_SBIT9
VT_TXSIG_CH_SEL(9)[4:0]
0x20155
VT_TSIG_CTL10
VT_USE_FBIT10
VT_USE_PBIT10
VT_USE_SBIT10
VT_TXSIG_CH_SEL(10)[4:0]
0x20156
VT_TSIG_CTL11
VT_USE_FBIT11
VT_USE_PBIT11
VT_USE_SBIT11
VT_TXSIG_CH_SEL(11)[4:0]
0x20157
VT_TSIG_CTL12
VT_USE_FBIT12
VT_USE_PBIT12
VT_USE_SBIT12
VT_TXSIG_CH_SEL(12)[4:0]
0x20158
VT_TSIG_CTL13
VT_USE_FBIT13
VT_USE_PBIT13
VT_USE_SBIT13
VT_TXSIG_CH_SEL(13)[4:0]
0x20159
VT_TSIG_CTL14
VT_USE_FBIT14
VT_USE_PBIT14
VT_USE_SBIT14
VT_TXSIG_CH_SEL(14)[4:0]
0x2015A
VT_TSIG_CTL15
VT_USE_FBIT15
VT_USE_PBIT15
VT_USE_SBIT15
VT_TXSIG_CH_SEL(15)[4:0]
0x2015B
VT_TSIG_CTL16
VT_USE_FBIT16
VT_USE_PBIT16
VT_USE_SBIT16
VT_TXSIG_CH_SEL(16)[4:0]
0x2015C
VT_TSIG_CTL17
VT_USE_FBIT17
VT_USE_PBIT17
VT_USE_SBIT17
VT_TXSIG_CH_SEL(17)[4:0]
0x2015D
VT_TSIG_CTL18
VT_USE_FBIT18
VT_USE_PBIT18
VT_USE_SBIT18
VT_TXSIG_CH_SEL(18)[4:0]
0x2015E
VT_TSIG_CTL19
VT_USE_FBIT19
VT_USE_PBIT19
VT_USE_SBIT19
VT_TXSIG_CH_SEL(19)[4:0]
0x2015F
VT_TSIG_CTL20
VT_USE_FBIT20
VT_USE_PBIT20
VT_USE_SBIT20
VT_TXSIG_CH_SEL(20)[4:0]
0x20160
VT_TSIG_CTL21
VT_USE_FBIT21
VT_USE_PBIT21
VT_USE_SBIT21
VT_TXSIG_CH_SEL(21)[4:0]
0x20161
VT_TSIG_CTL22
VT_USE_FBIT22
VT_USE_PBIT22
VT_USE_SBIT22
VT_TXSIG_CH_SEL(22)[4:0]
0x20162
VT_TSIG_CTL23
VT_USE_FBIT23
VT_USE_PBIT23
VT_USE_SBIT23
VT_TXSIG_CH_SEL(23)[4:0]
0x20163
VT_TSIG_CTL24
VT_USE_FBIT24
VT_USE_PBIT24
VT_USE_SBIT24
VT_TXSIG_CH_SEL(24)[4:0]
0x20164
VT_TSIG_CTL25
VT_USE_FBIT25
VT_USE_PBIT25
VT_USE_SBIT25
VT_TXSIG_CH_SEL(25)[4:0]
0x20165
VT_TSIG_CTL26
VT_USE_FBIT26
VT_USE_PBIT26
VT_USE_SBIT26
VT_TXSIG_CH_SEL(26)[4:0]
0x20166
VT_TSIG_CTL27
VT_USE_FBIT27
VT_USE_PBIT27
VT_USE_SBIT27
VT_TXSIG_CH_SEL(27)[4:0]
0x20167
VT_TSIG_CTL28
VT_USE_FBIT28
VT_USE_PBIT28
VT_USE_SBIT28
VT_TXSIG_CH_SEL(28)[4:0]
Agere Systems Inc.
183
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
10 VT/TU Mapper Registers (continued)
Table 211. VT/TU Mapper Register Map (continued)
Address
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Channel 1 Transmit J2 Value Parameters—R/W
0x20168
—
0x20177
VT_J2BYTE_INS_R[1][1]
—
VT_J2BYTE_INS_R[1][16]
0x20178
—
0x20187
VT_J2BYTE_INS_R[2][1]
—
VT_J2BYTE_INS_R[2][16]
0x20188
—
0x20197
VT_J2BYTE_INS_R[3][1]
—
VT_J2BYTE_INS_R[3][16]
0x20198
—
0x201A7
VT_J2BYTE_INS_R[4][1]
—
VT_J2BYTE_INS_R[4][16]
0x201A8
—
0x201B7
VT_J2BYTE_INS_R[5][1]
—
VT_J2BYTE_INS_R[5][16]
0x201B8
—
0x201C7
VT_J2BYTE_INS_R[6][1]
—
VT_J2BYTE_INS_R[6][16]
0x201C8
—
0x201D7
VT_J2BYTE_INS_R[7][1]
—
VT_J2BYTE_INS_R[7][16]
0x201D8
—
0x201E7
VT_J2BYTE_INS_R[8][1]
—
VT_J2BYTE_INS_R[8][16]
0x201E8
—
0x201F7
VT_J2BYTE_INS_R[9][1]
—
VT_J2BYTE_INS_R[9][16]
0x201F8
—
0x20207
VT_J2BYTE_INS_R[10][1]
—
VT_J2BYTE_INS_R[10][16]
0x20208
—
0x20217
VT_J2BYTE_INS_R[11][1]
—
VT_J2BYTE_INS_R[11][16]
VT_J2BYTE_INS(1)(1)[7:0]
—
VT_J2BYTE_INS(1)(16)[7:0]
Channel 2 Transmit J2 Value Parameters—R/W
VT_J2BYTE_INS(2)(1)[7:0]
—
VT_J2BYTE_INS(2)(16)[7:0]
Channel 3 Transmit J2 Value Parameters—R/W
VT_J2BYTE_INS(3)(1)[7:0]
—
VT_J2BYTE_INS(3)(16)[7:0]
Channel 4 Transmit J2 Value Parameters—R/W
VT_J2BYTE_INS(4)(1)[7:0]
—
VT_J2BYTE_INS(4)(16)[7:0]
Channel 5 Transmit J2 Value Parameters—R/W
VT_J2BYTE_INS(5)(1)[7:0]
—
VT_J2BYTE_INS(5)(16)[7:0]
Channel 6 Transmit J2 Value Parameters—R/W
VT_J2BYTE_INS(6)(1)[7:0]
—
VT_J2BYTE_INS(6)(16)[7:0]
Channel 7 Transmit J2 Value Parameters—R/W
VT_J2BYTE_INS(7)(1)[7:0]
—
VT_J2BYTE_INS(7)(16)[7:0]
Channel 8 Transmit J2 Value Parameters—R/W
VT_J2BYTE_INS(8)(1)[7:0]
—
VT_J2BYTE_INS(8)(16)[7:0]
Channel 9 Transmit J2 Value Parameters—R/W
VT_J2BYTE_INS(9)(1)[7:0]
—
VT_J2BYTE_INS(9)(16)[7:0]
Channel 10 Transmit J2 Value Parameters—R/W
VT_J2BYTE_INS(10)(1)[7:0]
—
VT_J2BYTE_INS(10)(16)[7:0]
Channel 11 Transmit J2 Value Parameters—R/W
184
VT_J2BYTE_INS(11)(1)[7:0]
—
VT_J2BYTE_INS(11)(16)[7:0]
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
10 VT/TU Mapper Registers (continued)
Table 211. VT/TU Mapper Register Map (continued)
Address
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Channel 12 Transmit J2 Value Parameters—R/W
0x20218
—
0x20227
VT_J2BYTE_INS_R[12][1]
—
VT_J2BYTE_INS_R[12][16]
0x20228
—
0x20237
VT_J2BYTE_INS_R[13][1]
—
VT_J2BYTE_INS_R[13][16]
0x20238
—
0x20247
VT_J2BYTE_INS_R[14][1]
—
VT_J2BYTE_INS_R[14][16]
0x20248
—
0x20257
VT_J2BYTE_INS_R[15][1]
—
VT_J2BYTE_INS_R[15][16]
0x20258
—
0x20267
VT_J2BYTE_INS_R[16][1]
—
VT_J2BYTE_INS_R[16][16]
0x20268
—
0x20277
VT_J2BYTE_INS_R[17][1]
—
VT_J2BYTE_INS_R[17][16]
0x20278
—
0x20287
VT_J2BYTE_INS_R[18][1]
—
VT_J2BYTE_INS_R[18][16]
0x20288
—
0x20297
VT_J2BYTE_INS_R[19][1]
—
VT_J2BYTE_INS_R[19][16]
0x20298
—
0x202A7
VT_J2BYTE_INS_R[20][1]
—
VT_J2BYTE_INS_R[20][16]
0x202A8
—
0x202B7
VT_J2BYTE_INS_R[21][1]
—
VT_J2BYTE_INS_R[21][16]
0x202B8
—
0x202C7
VT_J2BYTE_INS_R[22][1]
—
VT_J2BYTE_INS_R[22][16]
VT_J2BYTE_INS(12)(1)[7:0]
—
VT_J2BYTE_INS(12)(16)[7:0]
Channel 13 Transmit J2 Value Parameters—R/W
VT_J2BYTE_INS(13)(1)[7:0]
—
VT_J2BYTE_INS(13)(16)[7:0]
Channel 14 Transmit J2 Value Parameters—R/W
VT_J2BYTE_INS(14)(1)[7:0]
—
VT_J2BYTE_INS(14)(16)[7:0]
Channel 15 Transmit J2 Value Parameters—R/W
VT_J2BYTE_INS(15)(1)[7:0]
—
VT_J2BYTE_INS(15)(16)[7:0]
Channel 16 Transmit J2 Value Parameters—R/W
VT_J2BYTE_INS(16)(1)[7:0]
—
VT_J2BYTE_INS(16)(16)[7:0]
Channel 17 Transmit J2 Value Parameters—R/W
VT_J2BYTE_INS(17)(1)[7:0]
—
VT_J2BYTE_INS(17)(16)[7:0]
Channel 18 Transmit J2 Value Parameters—R/W
VT_J2BYTE_INS(18)(1)[7:0]
—
VT_J2BYTE_INS(18)(16)[7:0]
Channel 19 Transmit J2 Value Parameters—R/W
VT_J2BYTE_INS(19)(1)[7:0]
—
VT_J2BYTE_INS(19)(16)[7:0]
Channel 20 Transmit J2 Value Parameters—R/W
VT_J2BYTE_INS(20)(1)[7:0]
—
VT_J2BYTE_INS(20)(16)[7:0]
Channel 21 Transmit J2 Value Parameters—R/W
VT_J2BYTE_INS(21)(1)[7:0]
—
VT_J2BYTE_INS(21)(16)[7:0]
Channel 22 Transmit J2 Value Parameters—R/W
Agere Systems Inc.
VT_J2BYTE_INS(22)(1)[7:0]
—
VT_J2BYTE_INS(22)(16)[7:0]
185
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
10 VT/TU Mapper Registers (continued)
Table 211. VT/TU Mapper Register Map (continued)
Address
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Channel 23 Transmit J2 Value Parameters—R/W
0x202C8
—
0x202D7
VT_J2BYTE_INS_R[23][1]
—
VT_J2BYTE_INS_R[23][16]
0x202D8
—
0x202E7
VT_J2BYTE_INS_R[24][1]
—
VT_J2BYTE_INS_R[24][16]
0x202E8
—
0x202F7
VT_J2BYTE_INS_R[25][1]
—
VT_J2BYTE_INS_R[25][16]
0x202F8
—
0x20307
VT_J2BYTE_INS_R[26][1]
—
VT_J2BYTE_INS_R[26][16]
0x20308
—
0x20317
VT_J2BYTE_INS_R[27][1]
—
VT_J2BYTE_INS_R[27][16]
0x20318
—
0x20327
VT_J2BYTE_INS[28][1]
—
VT_J2BYTE_INS[28][16]
VT_J2BYTE_INS(23)(1)[7:0]
—
VT_J2BYTE_INS(23)(16)[7:0]
Channel 24 Transmit J2 Value Parameters—R/W
VT_J2BYTE_INS(24)(1)[7:0]
—
VT_J2BYTE_INS(24)(16)[7:0]
Channel 25 Transmit J2 Value Parameters—R/W
VT_J2BYTE_INS(25)(1)[7:0]
—
VT_J2BYTE_INS(25)(16)[7:0]
Channel 26 Transmit J2 Value Parameters—R/W
VT_J2BYTE_INS(26)(1)[7:0]
—
VT_J2BYTE_INS(26)(16)[7:0]
Channel 27 Transmit J2 Value Parameters—R/W
VT_J2BYTE_INS(27)(1)[7:0]
—
VT_J2BYTE_INS(27)(16)[7:0]
Channel 28 Transmit J2 Value Parameters—R/W
186
VT_J2BYTE_INS(28)(1)[7:0]
—
VT_J2BYTE_INS(28)(16)[7:0]
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
10 VT/TU Mapper Registers (continued)
Table 211. VT/TU Mapper Register Map (continued)
Address
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Receive Control Parameters—R/W
0x20328
VT_RCTL1
VT_SF_ESF1
VT_WR_FBIT1
VT_SYNC_PBIT1
VT_RXSIG_CH_SEL(1)[4:0]
VT_J2MON_MODE(1)[2:0]
VT_RX_ERDI_EN1
VT_RX_MAPTYPE(1)[3:0]
0x20329
VT_RCTL2
VT_SF_ESF2
VT_WR_FBIT2
VT_SYNC_PBIT2
VT_RXSIG_CH_SEL(2)[4:0]
VT_J2MON_MODE(2)[2:0]
VT_RX_ERDI_EN2
VT_RX_MAPTYPE(2)[3:0]
0x2032A
VT_RCTL3
VT_SF_ESF3
VT_WR_FBIT3
VT_SYNC_PBIT3
VT_RXSIG_CH_SEL(3)[4:0]
VT_J2MON_MODE(3)[2:0]
VT_RX_ERDI_EN3
VT_RX_MAPTYPE(3)[3:0]
0x2032B
VT_RCTL4
VT_SF_ESF4
VT_WR_FBIT4
VT_SYNC_PBIT4
VT_RXSIG_CH_SEL(4)[4:0]
VT_J2MON_MODE(4)[2:0]
VT_RX_ERDI_EN4
VT_RX_MAPTYPE(4)[3:0]
0x2032C
VT_RCTL5
VT_SF_ESF5
VT_WR_FBIT5
VT_SYNC_PBIT5
VT_RXSIG_CH_SEL(5)[4:0]
VT_J2MON_MODE(5)[2:0]
VT_RX_ERDI_EN5
VT_RX_MAPTYPE(5)[3:0]
0x2032D
VT_RCTL6
VT_SF_ESF6
VT_WR_FBIT6
VT_SYNC_PBIT6
VT_RXSIG_CH_SEL(6)[4:0]
VT_J2MON_MODE(6)[2:0]
VT_RX_ERDI_EN6
VT_RX_MAPTYPE(6)[3:0]
0x2032E
VT_RCTL7
VT_SF_ESF7
VT_WR_FBIT7
VT_SYNC_PBIT7
VT_RXSIG_CH_SEL(7)[4:0]
VT_J2MON_MODE(7)[2:0]
VT_RX_ERDI_EN7
VT_RX_MAPTYPE(7)[3:0]
0x2032F
VT_RCTL8
VT_SF_ESF8
VT_WR_FBIT8
VT_SYNC_PBIT8
VT_RXSIG_CH_SEL(8)[4:0]
VT_J2MON_MODE(8)[2:0]
VT_RX_ERDI_EN8
VT_RX_MAPTYPE(8)[3:0]
0x20330
VT_RCTL9
VT_SF_ESF9
VT_WR_FBIT9
VT_SYNC_PBIT9
VT_RXSIG_CH_SEL(9)[4:0]
VT_J2MON_MODE(9)[2:0]
VT_RX_ERDI_EN9
VT_RX_MAPTYPE(9)[3:0]
0x20331
VT_RCTL10
VT_SF_ESF10
VT_WR_FBIT10
VT_SYNC_PBIT10
VT_RXSIG_CH_SEL(10)[4:0]
VT_J2MON_MODE(10)[2:0]
VT_RX_ERDI_EN10
VT_RX_MAPTYPE(10)[3:0]
0x20332
VT_RCTL11
VT_SF_ESF11
VT_WR_FBIT11
VT_SYNC_PBIT11
VT_RXSIG_CH_SEL(11)[4:0]
VT_J2MON_MODE(11)[2:0]
VT_RX_ERDI_EN11
VT_RX_MAPTYPE(11)[3:0]
0x20333
VT_RCTL12
VT_SF_ESF12
VT_WR_FBIT12
VT_SYNC_PBIT12
VT_RXSIG_CH_SEL(12)[4:0]
VT_J2MON_MODE(12)[2:0]
VT_RX_ERDI_EN12
VT_RX_MAPTYPE(12)[3:0]
0x20334
VT_RCTL13
VT_SF_ESF13
VT_WR_FBIT13
VT_SYNC_PBIT13
VT_RXSIG_CH_SEL(13)[4:0]
VT_J2MON_MODE(13)[2:0]
VT_RX_ERDI_EN13
VT_RX_MAPTYPE(13)[3:0]
0x20335
VT_RCTL14
VT_SF_ESF14
VT_WR_FBIT14
VT_SYNC_PBIT14
VT_RXSIG_CH_SEL(14)[4:0]
VT_J2MON_MODE(14)[2:0]
VT_RX_ERDI_EN14
VT_RX_MAPTYPE(14)[3:0]
0x20336
VT_RCTL15
VT_SF_ESF15
VT_WR_FBIT15
VT_SYNC_PBIT15
VT_RXSIG_CH_SEL(15)[4:0]
VT_J2MON_MODE(15)[2:0]
VT_RX_ERDI_EN15
VT_RX_MAPTYPE(15)[3:0]
0x20337
VT_RCTL16
VT_SF_ESF16
VT_WR_FBIT16
VT_SYNC_PBIT16
VT_RXSIG_CH_SEL(16)[4:0]
VT_J2MON_MODE(16)[2:0]
VT_RX_ERDI_EN16
VT_RX_MAPTYPE(16)[3:0]
0x20338
VT_RCTL17
VT_SF_ESF17
VT_WR_FBIT17
VT_SYNC_PBIT17
VT_RXSIG_CH_SEL(17)[4:0]
VT_J2MON_MODE(17)[2:0]
VT_RX_ERDI_EN17
VT_RX_MAPTYPE(17)[3:0]
0x20339
VT_RCTL18
VT_SF_ESF18
VT_WR_FBIT18
VT_SYNC_PBIT18
VT_RXSIG_CH_SEL(18)[4:0]
VT_J2MON_MODE(18)[2:0]
VT_RX_ERDI_EN18
VT_RX_MAPTYPE(18)[3:0]
0x2033A
VT_RCTL19
VT_SF_ESF19
VT_WR_FBIT19
VT_SYNC_PBIT19
VT_RXSIG_CH_SEL(19)[4:0]
VT_J2MON_MODE(19)[2:0]
VT_RX_ERDI_EN19
VT_RX_MAPTYPE(19)[3:0]
0x2033B
VT_RCTL20
VT_SF_ESF20
VT_WR_FBIT20
VT_SYNC_PBIT20
VT_RXSIG_CH_SEL(20)[4:0]
VT_J2MON_MODE(20)[2:0]
VT_RX_ERDI_EN20
VT_RX_MAPTYPE(20)[3:0]
0x2033C
VT_RCTL21
VT_SF_ESF21
VT_WR_FBIT21
VT_SYNC_PBIT21
VT_RXSIG_CH_SEL(21)[4:0]
VT_J2MON_MODE(21)[2:0]
VT_RX_ERDI_EN21
VT_RX_MAPTYPE(21)[3:0]
0x2033D
VT_RCTL22
VT_SF_ESF22
VT_WR_FBIT22
VT_SYNC_PBIT22
VT_RXSIG_CH_SEL(22)[4:0]
VT_J2MON_MODE(22)[2:0]
VT_RX_ERDI_EN22
VT_RX_MAPTYPE(22)[3:0]
0x2033E
VT_RCTL23
VT_SF_ESF23
VT_WR_FBIT23
VT_SYNC_PBIT23
VT_RXSIG_CH_SEL(23)[4:0]
VT_J2MON_MODE(23)[2:0]
VT_RX_ERDI_EN23
VT_RX_MAPTYPE(23)[3:0]
0x2033F
VT_RCTL24
VT_SF_ESF24
VT_WR_FBIT24
VT_SYNC_PBIT24
VT_RXSIG_CH_SEL(24)[4:0]
VT_J2MON_MODE(24)[2:0]
VT_RX_ERDI_EN24
VT_RX_MAPTYPE(24)[3:0]
0x20340
VT_RCTL25
VT_SF_ESF25
VT_WR_FBIT25
VT_SYNC_PBIT25
VT_RXSIG_CH_SEL(25)[4:0]
VT_J2MON_MODE(25)[2:0]
VT_RX_ERDI_EN25
VT_RX_MAPTYPE(25)[3:0]
0x20341
VT_RCTL26
VT_SF_ESF26
VT_WR_FBIT26
VT_SYNC_PBIT26
VT_RXSIG_CH_SEL(26)[4:0]
VT_J2MON_MODE(26)[2:0]
VT_RX_ERDI_EN26
VT_RX_MAPTYPE(26)[3:0]
0x20342
VT_RCTL27
VT_SF_ESF27
VT_WR_FBIT27
VT_SYNC_PBIT27
VT_RXSIG_CH_SEL(27)[4:0]
VT_J2MON_MODE(27)[2:0]
VT_RX_ERDI_EN27
VT_RX_MAPTYPE(27)[3:0]
0x20343
VT_RCTL28
VT_SF_ESF28
VT_WR_FBIT28
VT_SYNC_PBIT28
VT_RXSIG_CH_SEL(28)[4:0]
VT_J2MON_MODE(28)[2:0]
VT_RX_ERDI_EN28
VT_RX_MAPTYPE(28)[3:0]
Agere Systems Inc.
187
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
10 VT/TU Mapper Registers (continued)
Table 211. VT/TU Mapper Register Map (continued)
Address
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Receive TU Overhead—RO
0x20344
VT_RTUOH_CTL1
VT_Z6_BYTE(1)[7:0]
VT_OBITS(1)[7:0]
0x20345
VT_RTUOH_CTL2
VT_Z6_BYTE(2)[7:0]
VT_OBITS(2)[7:0]
0x20346
VT_RTUOH_CTL3
VT_Z6_BYTE(3)[7:0]
VT_OBITS(3)[7:0]
0x20347
VT_RTUOH_CTL4
VT_Z6_BYTE(4)[7:0]
VT_OBITS(4)[7:0]
0x20348
VT_RTUOH_CTL5
VT_Z6_BYTE(5)[7:0]
VT_OBITS(5)[7:0]
0x20349
VT_RTUOH_CTL6
VT_Z6_BYTE(6)[7:0]
VT_OBITS(6)[7:0]
0x2034A
VT_RTUOH_CTL7
VT_Z6_BYTE(7)[7:0]
VT_OBITS(7)[7:0]
0x2034B
VT_RTUOH_CTL8
VT_Z6_BYTE(8)[7:0]
VT_OBITS(8)[7:0]
0x2034C
VT_RTUOH_CTL9
VT_Z6_BYTE(9)[7:0]
VT_OBITS(9)[7:0]
0x2034D
VT_RTUOH_CTL10
VT_Z6_BYTE(10)[7:0]
VT_OBITS(10)[7:0]
0x2034E
VT_RTUOH_CTL11
VT_Z6_BYTE(11)[7:0]
VT_OBITS(11)[7:0]
0x2034F
VT_RTUOH_CTL12
VT_Z6_BYTE(12)[7:0]
VT_OBITS(12)[7:0]
0x20350
VT_RTUOH_CTL13
VT_Z6_BYTE(13)[7:0]
VT_OBITS(13)[7:0]
0x20351
VT_RTUOH_CTL14
VT_Z6_BYTE(14)[7:0]
VT_OBITS(14)[7:0]
0x20352
VT_RTUOH_CTL15
VT_Z6_BYTE(15)[7:0]
VT_OBITS(15)[7:0]
0x20353
VT_RTUOH_CTL16
VT_Z6_BYTE(16)[7:0]
VT_OBITS(16)[7:0]
0x20354
VT_RTUOH_CTL17
VT_Z6_BYTE(17)[7:0]
VT_OBITS(17)[7:0]
0x20355
VT_RTUOH_CTL18
VT_Z6_BYTE(18)[7:0]
VT_OBITS(18)[7:0]
0x20356
VT_RTUOH_CTL19
VT_Z6_BYTE(19)[7:0]
VT_OBITS(19)[7:0]
0x20357
VT_RTUOH_CTL20
VT_Z6_BYTE(20)[7:0]
VT_OBITS(20)[7:0]
0x20358
VT_RTUOH_CTL21
VT_Z6_BYTE(21)[7:0]
VT_OBITS(21)[7:0]
0x20359
VT_RTUOH_CTL22
VT_Z6_BYTE(22)[7:0]
VT_OBITS(22)[7:0]
0x2035A
VT_RTUOH_CTL23
VT_Z6_BYTE(23)[7:0]
VT_OBITS(23)[7:0]
0x2035B
VT_RTUOH_CTL24
VT_Z6_BYTE(24)[7:0]
VT_OBITS(24)[7:0]
0x2035C
VT_RTUOH_CTL25
VT_Z6_BYTE(25)[7:0]
VT_OBITS(25)[7:0]
0x2035D
VT_RTUOH_CTL26
VT_Z6_BYTE(26)[7:0]
VT_OBITS(26)[7:0]
0x2035E
VT_RTUOH_CTL27
VT_Z6_BYTE(27)[7:0]
VT_OBITS(27)[7:0]
0x2035F
VT_RTUOH_CTL28
VT_Z6_BYTE(28)[7:0]
VT_OBITS(28)[7:0]
188
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
10 VT/TU Mapper Registers (continued)
Table 211. VT/TU Mapper Register Map (continued)
Address
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Receive BIP-2 Error Count Values—RO
0x20360
VT_RBIP2_CNT1
VT_BIP2ERR_CNT(1)[11:0]
0x20361
VT_RBIP2_CNT2
VT_BIP2ERR_CNT(2)[11:0]
0x20362
VT_RBIP2_CNT3
VT_BIP2ERR_CNT(3)[11:0]
0x20363
VT_RBIP2_CNT4
VT_BIP2ERR_CNT(4)[11:0]
0x20364
VT_RBIP2_CNT5
VT_BIP2ERR_CNT(5)[11:0]
0x20365
VT_RBIP2_CNT6
VT_BIP2ERR_CNT(6)[11:0]
0x20366
VT_RBIP2_CNT7
VT_BIP2ERR_CNT(7)[11:0]
0x20367
VT_RBIP2_CNT8
VT_BIP2ERR_CNT(8)[11:0]
0x20368
VT_RBIP2_CNT9
VT_BIP2ERR_CNT(9)[11:0]
0x20369
VT_RBIP2_CNT10
VT_BIP2ERR_CNT(10)[11:0]
0x2036A
VT_RBIP2_CNT11
VT_BIP2ERR_CNT(11)[11:0]
0x2036B
VT_RBIP2_CNT12
VT_BIP2ERR_CNT(12)[11:0]
0x2036C
VT_RBIP2_CNT13
VT_BIP2ERR_CNT(13)[11:0]
0x2036D
VT_RBIP2_CNT14
VT_BIP2ERR_CNT(14)[11:0]
0x2036E
VT_RBIP2_CNT15
VT_BIP2ERR_CNT(15)[11:0]
0x2036F
VT_RBIP2_CNT16
VT_BIP2ERR_CNT(16)[11:0]
0x20370
VT_RBIP2_CNT17
VT_BIP2ERR_CNT(17)[11:0]
0x20371
VT_RBIP2_CNT18
VT_BIP2ERR_CNT(18)[11:0]
0x20372
VT_RBIP2_CNT19
VT_BIP2ERR_CNT(19)[11:0]
0x20373
VT_RBIP2_CNT20
VT_BIP2ERR_CNT(20)[11:0]
0x20374
VT_RBIP2_CNT21
VT_BIP2ERR_CNT(21)[11:0]
0x20375
VT_RBIP2_CNT22
VT_BIP2ERR_CNT(22)[11:0]
0x20376
VT_RBIP2_CNT23
VT_BIP2ERR_CNT(23)[11:0]
0x20377
VT_RBIP2_CNT24
VT_BIP2ERR_CNT(24)[11:0]
0x20378
VT_RBIP2_CNT25
VT_BIP2ERR_CNT(25)[11:0]
0x20379
VT_RBIP2_CNT26
VT_BIP2ERR_CNT(26)[11:0]
0x2037A
VT_RBIP2_CNT27
VT_BIP2ERR_CNT(27)[11:0]
0x2037B
VT_RBIP2_CNT28
VT_BIP2ERR_CNT(28)[11:0]
Agere Systems Inc.
189
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
10 VT/TU Mapper Registers (continued)
Table 211. VT/TU Mapper Register Map (continued)
Address
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Receive REI-V Count Values—RO
0x2037C
VT_RREIV_CNT1
VT_REI_CNT(1)[10:0]
0x2037D
VT_RREIV_CNT2
VT_REI_CNT(2)[10:0]
0x2037E
VT_RREIV_CNT3
VT_REI_CNT(3)[10:0]
0x2037F
VT_RREIV_CNT4
VT_REI_CNT(4)[10:0]
0x20380
VT_RREIV_CNT5
VT_REI_CNT(5)[10:0]
0x20381
VT_RREIV_CNT6
VT_REI_CNT(6)[10:0]
0x20382
VT_RREIV_CNT7
VT_REI_CNT(7)[10:0]
0x20383
VT_RREIV_CNT8
VT_REI_CNT(8)[10:0]
0x20384
VT_RREIV_CNT9
VT_REI_CNT(9)[10:0]
0x20385
VT_RREIV_CNT10
VT_REI_CNT(10)[10:0]
0x20386
VT_RREIV_CNT11
VT_REI_CNT(11)[10:0]
0x20387
VT_RREIV_CNT12
VT_REI_CNT(12)[10:0]
0x20388
VT_RREIV_CNT13
VT_REI_CNT(13)[10:0]
0x20389
VT_RREIV_CNT14
VT_REI_CNT(14)[10:0]
0x2038A
VT_RREIV_CNT15
VT_REI_CNT(15)[10:0]
0x2038B
VT_RREIV_CNT16
VT_REI_CNT(16)[10:0]
0x2038C
VT_RREIV_CNT17
VT_REI_CNT(17)[10:0]
0x2038D
VT_RREIV_CNT18
VT_REI_CNT(18)[10:0]
0x2038E
VT_RREIV_CNT19
VT_REI_CNT(19)[10:0]
0x2038F
VT_RREIV_CNT20
VT_REI_CNT(20)[10:0]
0x20390
VT_RREIV_CNT21
VT_REI_CNT(21)[10:0]
0x20391
VT_RREIV_CNT22
VT_REI_CNT(22)[10:0]
0x20392
VT_RREIV_CNT23
VT_REI_CNT(23)[10:0]
0x20393
VT_RREIV_CNT24
VT_REI_CNT(24)[10:0]
0x20394
VT_RREIV_CNT25
VT_REI_CNT(25)[10:0]
0x20395
VT_RREIV_CNT26
VT_REI_CNT(26)[10:0]
0x20396
VT_RREIV_CNT27
VT_REI_CNT(27)[10:0]
0x20397
VT_RREIV_CNT28
VT_REI_CNT(28)[10:0]
190
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
10 VT/TU Mapper Registers (continued)
Table 211. VT/TU Mapper Register Map (continued)
Address
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Receive VT Pointer and Count Values—RO
0x20398
VT_RPTR_CNT1
VT_STORED_VTPTR(1)[7:0]
VT_PTR_DEC(1)[3:0]
VT_PTR_INC(1)[3:0]
0x20399
VT_RPTR_CNT2
VT_STORED_VTPTR(2)[7:0]
VT_PTR_DEC(2)[3:0]
VT_PTR_INC(2)[3:0]
0x2039A
VT_RPTR_CNT3
VT_STORED_VTPTR(3)[7:0]
VT_PTR_DEC(3)[3:0]
VT_PTR_INC(3)[3:0]
0x2039B
VT_RPTR_CNT4
VT_STORED_VTPTR(4)[7:0]
VT_PTR_DEC(4)[3:0]
VT_PTR_INC(4)[3:0]
0x2039C
VT_RPTR_CNT5
VT_STORED_VTPTR(5)[7:0]
VT_PTR_DEC(5)[3:0]
VT_PTR_INC(5)[3:0]
0x2039D
VT_RPTR_CNT6
VT_STORED_VTPTR(6)[7:0]
VT_PTR_DEC(6)[3:0]
VT_PTR_INC(6)[3:0]
0x2039E
VT_RPTR_CNT7
VT_STORED_VTPTR(7)[7:0]
VT_PTR_DEC(7)[3:0]
VT_PTR_INC(7)[3:0]
0x2039F
VT_RPTR_CNT8
VT_STORED_VTPTR(8)[7:0]
VT_PTR_DEC(8)[3:0]
VT_PTR_INC(8)[3:0]
0x203A0
VT_RPTR_CNT9
VT_STORED_VTPTR(9)[7:0]
VT_PTR_DEC(9)[3:0]
VT_PTR_INC(9)[3:0]
0x203A1
VT_RPTR_CNT10
VT_STORED_VTPTR(10)[7:0]
VT_PTR_DEC(10)[3:0]
VT_PTR_INC(10)[3:0]
0x203A2
VT_RPTR_CNT11
VT_STORED_VTPTR(11)[7:0]
VT_PTR_DEC(11)[3:0]
VT_PTR_INC(11)[3:0]
0x203A3
VT_RPTR_CNT12
VT_STORED_VTPTR(12)[7:0]
VT_PTR_DEC(12)[3:0]
VT_PTR_INC(12)[3:0]
0x203A4
VT_RPTR_CNT13
VT_STORED_VTPTR(13)[7:0]
VT_PTR_DEC(13)[3:0]
VT_PTR_INC(13)[3:0]
0x203A5
VT_RPTR_CNT14
VT_STORED_VTPTR(14)[7:0]
VT_PTR_DEC(14)[3:0]
VT_PTR_INC(14)[3:0]
0x203A6
VT_RPTR_CNT15
VT_STORED_VTPTR(15)[7:0]
VT_PTR_DEC(15)[3:0]
VT_PTR_INC(15)[3:0]
0x203A7
VT_RPTR_CNT16
VT_STORED_VTPTR(16)[7:0]
VT_PTR_DEC(16)[3:0]
VT_PTR_INC(16)[3:0]
0x203A8
VT_RPTR_CNT17
VT_STORED_VTPTR(17)[7:0]
VT_PTR_DEC(17)[3:0]
VT_PTR_INC(17)[3:0]
0x203A9
VT_RPTR_CNT18
VT_STORED_VTPTR(18)[7:0]
VT_PTR_DEC(18)[3:0]
VT_PTR_INC(18)[3:0]
0x203AA
VT_RPTR_CNT19
VT_STORED_VTPTR(19)[7:0]
VT_PTR_DEC(19)[3:0]
VT_PTR_INC(19)[3:0]
0x203AB
VT_RPTR_CNT20
VT_STORED_VTPTR(20)[7:0]
VT_PTR_DEC(20)[3:0]
VT_PTR_INC(20)[3:0]
0x203AC
VT_RPTR_CNT21
VT_STORED_VTPTR(21)[7:0]
VT_PTR_DEC(21)[3:0]
VT_PTR_INC(21)[3:0]
0x203AD
VT_RPTR_CNT22
VT_STORED_VTPTR(22)[7:0]
VT_PTR_DEC(22)[3:0]
VT_PTR_INC(22)[3:0]
0x203AE
VT_RPTR_CNT23
VT_STORED_VTPTR(23)[7:0]
VT_PTR_DEC(23)[3:0]
VT_PTR_INC(23)[3:0]
0x203AF
VT_RPTR_CNT24
VT_STORED_VTPTR(24)[7:0]
VT_PTR_DEC(24)[3:0]
VT_PTR_INC(24)[3:0]
0x203B0
VT_RPTR_CNT25
VT_STORED_VTPTR(25)[7:0]
VT_PTR_DEC(25)[3:0]
VT_PTR_INC(25)[3:0]
0x203B1
VT_RPTR_CNT26
VT_STORED_VTPTR(26)[7:0]
VT_PTR_DEC(26)[3:0]
VT_PTR_INC(26)[3:0]
0x203B2
VT_RPTR_CNT27
VT_STORED_VTPTR(27)[7:0]
VT_PTR_DEC(27)[3:0]
VT_PTR_INC(27)[3:0]
0x203B3
VT_RPTR_CNT28
VT_STORED_VTPTR(28)[7:0]
VT_PTR_DEC(28)[3:0]
VT_PTR_INC(28)[3:0]
Agere Systems Inc.
191
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
10 VT/TU Mapper Registers (continued)
Table 211. VT/TU Mapper Register Map (continued)
Address
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Channel 1 Receive J2 Expected/Monitor Values—R/W, RO
0x203B4
—
0x203C3
VT_J2BYTE_EXP_R[1][1]
—
VT_J2BYTE_EXP_R[1][16]
VT_J2BYTE_EXP(1)(1)[7:0]
—
VT_J2BYTE_EXP(1)(16)[7:0]
0x203C4
—
0x203D3
VT_J2BYTE_EXP_R[2][1]
—
VT_J2BYTE_EXP_R[2][16]
VT_J2BYTE_EXP(2)(1)[7:0]
—
VT_J2BYTE_EXP(2)(16)[7:0]
0x203D4
—
0x203E3
VT_J2BYTE_EXP_R[3][1]
—
VT_J2BYTE_EXP_R[3][16]
VT_J2BYTE_EXP(3)(1)[7:0]
—
VT_J2BYTE_EXP(3)(16)[7:0]
0x203E4
—
0x203F3
VT_J2BYTE_EXP_R[4][1]
—
VT_J2BYTE_EXP_R[4][16]
VT_J2BYTE_EXP(4)(1)[7:0]
—
VT_J2BYTE_EXP(4)(16)[7:0]
0x203F4
—
0x20403
VT_J2BYTE_EXP_R[5][1]
—
VT_J2BYTE_EXP_R[5][16]
VT_J2BYTE_EXP(5)(1)[7:0]
—
VT_J2BYTE_EXP(5)(16)[7:0]
0x20404
—
0x20413
VT_J2BYTE_EXP_R[6][1]
—
VT_J2BYTE_EXP_R[6][16]
VT_J2BYTE_EXP(6)(1)[7:0]
—
VT_J2BYTE_EXP(6)(16)[7:0]
0x20414
—
0x20423
VT_J2BYTE_EXP_R[7][1]
—
VT_J2BYTE_EXP_R[7][16]
VT_J2BYTE_EXP(7)(1)[7:0]
—
VT_J2BYTE_EXP(7)(16)[7:0]
0x20424
—
0x20433
VT_J2BYTE_EXP_R[8][1]
—
VT_J2BYTE_EXP_R[8][16]
VT_J2BYTE_EXP(8)(1)[7:0]
—
VT_J2BYTE_EXP(8)(16)[7:0]
0x20434
—
0x20443
VT_J2BYTE_EXP_R[9][1]
—
VT_J2BYTE_EXP_R[9][16]
VT_J2BYTE_EXP(9)(1)[7:0]
—
VT_J2BYTE_EXP(9)(16)[7:0]
0x20444
—
0x20453
VT_J2BYTE_EXP_R[10][1]
—
VT_J2BYTE_EXP_R[10][16]
VT_J2BYTE_EXP(10)(1)[7:0]
—
VT_J2BYTE_EXP(10)(16)[7:0]
0x20454
—
0x20463
VT_J2BYTE_EXP_R[11][1]
—
VT_J2BYTE_EXP_R[11][16]
VT_J2BYTE_EXP(11)(1)[7:0]
—
VT_J2BYTE_EXP(11)(16)[7:0]
VT_J2BYTE_DET(1)(1)[7:0]
—
VT_J2BYTE_DET(1)(16)[7:0]
Channel 2 Receive J2 Expected/Monitor Values—R/W, RO
VT_J2BYTE_DET(2)(1)[7:0]
—
VT_J2BYTE_DET(2)(16)[7:0]
Channel 3 Receive J2 Expected/Monitor Values—R/W, RO
VT_J2BYTE_DET(3)(1)[7:0]
—
VT_J2BYTE_DET(3)(16)[7:0]
Channel 4 Receive J2 Expected/Monitor Values—R/W, RO
VT_J2BYTE_DET(4)(1)[7:0]
—
VT_J2BYTE_DET(4)(16)[7:0]
Channel 5 Receive J2 Expected/Monitor Values—R/W, RO
VT_J2BYTE_DET(5)(1)[7:0]
—
VT_J2BYTE_DET(5)(16)[7:0]
Channel 6 Receive J2 Expected/Monitor Values—R/W, RO
VT_J2BYTE_DET(6)(1)[7:0]
—
VT_J2BYTE_DET(6)(16)[7:0]
Channel 7 Receive J2 Expected/Monitor Values—R/W, RO
VT_J2BYTE_DET(7)(1)[7:0]
—
VT_J2BYTE_DET(7)(16)[7:0]
Channel 8 Receive J2 Expected/Monitor Values—R/W, RO
VT_J2BYTE_DET(8)(1)[7:0]
—
VT_J2BYTE_DET(8)(16)[7:0]
Channel 9 Receive J2 Expected/Monitor Values—R/W, RO
VT_J2BYTE_DET(9)(1)[7:0]
—
VT_J2BYTE_DET(9)(16)[7:0]
Channel 10 Receive J2 Expected/Monitor Values—R/W, RO
VT_J2BYTE_DET(10)(1)[7:0]
—
VT_J2BYTE_DET(10)(16)[7:0]
Channel 11 Receive J2 Expected/Monitor Values—R/W, RO
192
VT_J2BYTE_DET(11)(1)[7:0]
—
VT_J2BYTE_DET(11)(16)[7:0]
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
10 VT/TU Mapper Registers (continued)
Table 211. VT/TU Mapper Register Map (continued)
Address
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Channel 12 Receive J2 Expected/Monitor Values—R/W, RO
0x20464
—
0x20473
VT_J2BYTE_EXP_R[12][1]
—
VT_J2BYTE_EXP_R[12][16]
VT_J2BYTE_EXP(12)(1)[7:0]
—
VT_J2BYTE_EXP(12)(16)[7:0]
0x20474
—
0x20483
VT_J2BYTE_EXP_R[13][1]
—
VT_J2BYTE_EXP_R[13][16]
VT_J2BYTE_EXP(13)(1)[7:0]
—
VT_J2BYTE_EXP(13)(16)[7:0]
0x20484
—
0x20493
VT_J2BYTE_EXP_R[14][1]
—
VT_J2BYTE_EXP_R[14][16]
VT_J2BYTE_EXP(14)(1)[7:0]
—
VT_J2BYTE_EXP(14)(16)[7:0]
0x20494
—
0x204A3
VT_J2BYTE_EXP_R[15][1]
—
VT_J2BYTE_EXP_R[15][16]
VT_J2BYTE_EXP(15)(1)[7:0]
—
VT_J2BYTE_EXP(15)(16)[7:0]
0x204A4
—
0x204B3
VT_J2BYTE_EXP_R[16][1]
—
VT_J2BYTE_EXP_R[16][16]
VT_J2BYTE_EXP(16)(1)[7:0]
—
VT_J2BYTE_EXP(16)(16)[7:0]
0x204B4
—
0x204C3
VT_J2BYTE_EXP_R[17][1]
—
VT_J2BYTE_EXP_R[17][16]
VT_J2BYTE_EXP(17)(1)[7:0]
—
VT_J2BYTE_EXP(17)(16)[7:0]
0x204C4
—
0x204D3
VT_J2BYTE_EXP_R[18][1]
—
VT_J2BYTE_EXP_R[18][16]
VT_J2BYTE_EXP(18)(1)[7:0]
—
VT_J2BYTE_EXP(18)(16)[7:0]
0x204D4
—
0x204E3
VT_J2BYTE_EXP_R[19][1]
—
VT_J2BYTE_EXP_R[19][16]
VT_J2BYTE_EXP(19)(1)[7:0]
—
VT_J2BYTE_EXP(19)(16)[7:0]
0x204E4
—
0x204F3
VT_J2BYTE_EXP_R[20][1]
—
VT_J2BYTE_EXP_R[20][16]
VT_J2BYTE_EXP(20)(1)[7:0]
—
VT_J2BYTE_EXP(20)(16)[7:0]
0x204F4
—
0x20503
VT_J2BYTE_EXP_R[21][1]
—
VT_J2BYTE_EXP_R[21][16]
VT_J2BYTE_EXP(21)(1)[7:0]
—
VT_J2BYTE_EXP(21)(16)[7:0]
0x20504
—
0x20513
VT_J2BYTE_EXP_R[22][1]
—
VT_J2BYTE_EXP_R[22][16]
VT_J2BYTE_EXP(22)(1)[7:0]
—
VT_J2BYTE_EXP(22)(16)[7:0]
VT_J2BYTE_DET(12)(1)[7:0]
—
VT_J2BYTE_DET(12)(16)[7:0]
Channel 13 Receive J2 Expected/Monitor Values—R/W, RO
VT_J2BYTE_DET(13)(1)[7:0]
—
VT_J2BYTE_DET(13)(16)[7:0]
Channel 14 Receive J2 Expected/Monitor Values—R/W, RO
VT_J2BYTE_DET(14)(1)[7:0]
—
VT_J2BYTE_DET()14(16)[7:0]
Channel 15 Receive J2 Expected/Monitor Values—R/W, RO
VT_J2BYTE_DET(15)(1)[7:0]
—
VT_J2BYTE_DET(15)(16)[7:0]
Channel 16 Receive J2 Expected/Monitor Values—R/W, RO
VT_J2BYTE_DET(16)(1)[7:0]
—
VT_J2BYTE_DET(16)(16)[7:0]
Channel 17 Receive J2 Expected/Monitor Values—R/W, RO
VT_J2BYTE_DET(17)(1)[7:0]
—
VT_J2BYTE_DET(17)(16)[7:0]
Channel 18 Receive J2 Expected/Monitor Values—R/W, RO
VT_J2BYTE_DET(18)(1)[7:0]
—
VT_J2BYTE_DET(18)(16)[7:0]
Channel 19 Receive J2 Expected/Monitor Values—R/W, RO
VT_J2BYTE_DET(19)(1)[7:0]
—
VT_J2BYTE_DET(19)(16)[7:0]
Channel 20 Receive J2 Expected/Monitor Values—R/W, RO
VT_J2BYTE_DET(20)(1)[7:0]
—
VT_J2BYTE_DET(20)(16)[7:0]
Channel 21 Receive J2 Expected/Monitor Values—R/W, RO
VT_J2BYTE_DET(21)(1)[7:0]
—
VT_J2BYTE_DET(21)(16)[7:0]
Channel 22 Receive J2 Expected/Monitor Values—R/W, RO
Agere Systems Inc.
VT_J2BYTE_DET(22)(1)[7:0]
—
VT_J2BYTE_DET(22)(16)[7:0]
193
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
10 VT/TU Mapper Registers (continued)
Table 211. VT/TU Mapper Register Map (continued)
Address
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Channel 23 Receive J2 Expected/Monitor Values—R/W, RO
0x20514
—
0x20523
VT_J2BYTE_EXP_R[23][1]
—
VT_J2BYTE_EXP_R[23][16]
VT_J2BYTE_EXP(23)(1)[7:0]
—
VT_J2BYTE_EXP(23)(16)[7:0]
0x20524
—
0x20533
VT_J2BYTE_EXP_R[24][1]
—
VT_J2BYTE_EXP_R[24][16]
VT_J2BYTE_EXP(24)(1)[7:0]
—
VT_J2BYTE_EXP(24)(16)[7:0]
0x20534
—
0x20543
VT_J2BYTE_EXP_R[25][1]
—
VT_J2BYTE_EXP_R[25][16]
VT_J2BYTE_EXP(25)(1)[7:0]
—
VT_J2BYTE_EXP(25)(16)[7:0]
0x20544
—
0x20553
VT_J2BYTE_EXP_R[26][1]
—
VT_J2BYTE_EXP_R[26][16]
VT_J2BYTE_EXP(26)(1)[7:0]
—
VT_J2BYTE_EXP(26)(16)[7:0]
0x20554
—
0x20563
VT_J2BYTE_EXP_R[27][1]
—
VT_J2BYTE_EXP_R[27][16]
VT_J2BYTE_EXP(27)(1)[7:0]
—
VT_J2BYTE_EXP(27)(16)[7:0]
0x20564
—
0x20573
VT_J2BYTE_EXP_R[28][1]
—
VT_J2BYTE_EXP_R[28][16]
VT_J2BYTE_EXP(28)(1)[7:0]
—
VT_J2BYTE_EXP(28)(16)[7:0]
VT_J2BYTE_DET(23)(1)[7:0]
—
VT_J2BYTE_DET(23)(16)[7:0]
Channel 24 Receive J2 Expected/Monitor Values—R/W, RO
VT_J2BYTE_DET(24)(1)[7:0]
—
VT_J2BYTE_DET(24)(16)[7:0]
Channel 25 Receive J2 Expected/Monitor Values—R/W, RO
VT_J2BYTE_DET(25)(1)[7:0]
—
VT_J2BYTE_DET(25)(16)[7:0]
Channel 26 Receive J2 Expected/Monitor Values—R/W, RO
VT_J2BYTE_DET(26)(1)[7:0]
—
VT_J2BYTE_DET(26)(16)[7:0]
Channel 27 Receive J2 Expected/Monitor Values—R/W, RO
VT_J2BYTE_DET(27)(1)[7:0]
—
VT_J2BYTE_DET(27)(16)[7:0]
Channel 28 Receive J2 Expected/Monitor Values—R/W, RO
194
VT_J2BYTE_DET(28)(1)[7:0]
—
VT_J2BYTE_DET(28)(16)[7:0]
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
10 VT/TU Mapper Registers (continued)
Table 211. VT/TU Mapper Register Map (continued)
Address
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Transmit Elastic Store Threshold Control—R/W
0x20574
VT_THRES_CTL1
VT_HIGH_THRES(1)[6:0]
VT_LOW_THRES(1)[6:0]
0x20575
VT_THRES_CTL2
VT_HIGH_THRES(2)[6:0]
VT_LOW_THRES(2)[6:0]
0x20576
VT_THRES_CTL3
VT_HIGH_THRES(3)[6:0]
VT_LOW_THRES(3)[6:0]
0x20577
VT_THRES_CTL4
VT_HIGH_THRES(4)[6:0]
VT_LOW_THRES(4)[6:0]
0x20578
VT_THRES_CTL5
VT_HIGH_THRES(5)[6:0]
VT_LOW_THRES(5)[6:0]
0x20579
VT_THRES_CTL6
VT_HIGH_THRES(6)[6:0]
VT_LOW_THRES(6)[6:0]
0x2057A
VT_THRES_CTL7
VT_HIGH_THRES(7)[6:0]
VT_LOW_THRES(7)[6:0]
0x2057B
VT_THRES_CTL8
VT_HIGH_THRES(8)[6:0]
VT_LOW_THRES(8)[6:0]
0x2057C
VT_THRES_CTL9
VT_HIGH_THRES(9)[6:0]
VT_LOW_THRES(9)[6:0]
0x2057D
VT_THRES_CTL10
VT_HIGH_THRES(10)[6:0]
VT_LOW_THRES(10)[6:0]
0x2057E
VT_THRES_CTL11
VT_HIGH_THRES(11)[6:0]
VT_LOW_THRES(11)[6:0]
0x2057F
VT_THRES_CTL12
VT_HIGH_THRES(12)[6:0]
VT_LOW_THRES(12)[6:0]
0x20580
VT_THRES_CTL13
VT_HIGH_THRES(13)[6:0]
VT_LOW_THRES(13)[6:0]
0x20581
VT_THRES_CTL14
VT_HIGH_THRES(14)[6:0]
VT_LOW_THRES(14)[6:0]
0x20582
VT_THRES_CTL15
VT_HIGH_THRES(15)[6:0]
VT_LOW_THRES(15)[6:0]
0x20583
VT_THRES_CTL16
VT_HIGH_THRES(16)[6:0]
VT_LOW_THRES(16)[6:0]
0x20584
VT_THRES_CTL17
VT_HIGH_THRES(17)[6:0]
VT_LOW_THRES(17)[6:0]
0x20585
VT_THRES_CTL18
VT_HIGH_THRES(18)[6:0]
VT_LOW_THRES(18)[6:0]
0x20586
VT_THRES_CTL19
VT_HIGH_THRES(19)[6:0]
VT_LOW_THRES(19)[6:0]
0x20587
VT_THRES_CTL20
VT_HIGH_THRES(20)[6:0]
VT_LOW_THRES(20)[6:0]
0x20588
VT_THRES_CTL21
VT_HIGH_THRES(21)[6:0]
VT_LOW_THRES(21)[6:0]
0x20589
VT_THRES_CTL22
VT_HIGH_THRES(22)[6:0]
VT_LOW_THRES(22)[6:0]
0x2058A
VT_THRES_CTL23
VT_HIGH_THRES(23)[6:0]
VT_LOW_THRES(23)[6:0]
0x2058B
VT_THRES_CTL24
VT_HIGH_THRES(24)[6:0]
VT_LOW_THRES(24)[6:0]
0x2058C
VT_THRES_CTL25
VT_HIGH_THRES(25)[6:0]
VT_LOW_THRES(25)[6:0]
0x2058D
VT_THRES_CTL26
VT_HIGH_THRES(26)[6:0]
VT_LOW_THRES(26)[6:0]
0x2058E
VT_THRES_CTL27
VT_HIGH_THRES(27)[6:0]
VT_LOW_THRES(27)[6:0]
0x2058F
VT_THRES_CTL28
VT_HIGH_THRES(28)[6:0]
VT_LOW_THRES(28)[6:0]
Note: Registers from 0x20590 to 0x20969 are reserved and should not be read.
Agere Systems Inc.
195
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
11 M13/M23 MUX/DeMUX Registers
Table of Contents
Contents
Page
11 M13/M23 MUX/DeMUX Registers .................................................................................................................. 196
11.1 M13 Block Register Descriptions ............................................................................................................ 198
11.2 M13 Register Map .................................................................................................................................. 228
Tables
Page
Table 212.
Table 213.
Table 214.
Table 215.
Table 216.
Table 217.
Table 218.
Table 219.
Table 220.
Table 221.
Table 222.
Table 223.
Table 224.
Table 225.
Table 226.
Table 227.
Table 228.
Table 229.
Table 230.
Table 231.
Table 232.
Table 233.
Table 234.
Table 235.
Table 236.
Table 237.
Table 238.
Table 239.
Table 240.
Table 241.
Table 242.
Table 243.
Table 244.
Table 245.
Table 246.
Table 247.
Table 248.
Table 249.
Table 250.
M13_ID_R, M13 Block Identification (RO) ......................................................................................... 198
M13_VERSION_R, M13 Version (RO) .............................................................................................. 198
M13_DELTA1, Delta (RO) ................................................................................................................. 199
M13_DELTA2, Delta (RO)................................................................................................................. 200
M13_DELTA3, Delta (RO)................................................................................................................. 200
M13_DELTA4, Delta (RO) ................................................................................................................. 201
M13_DELTA5, Delta (RO) ................................................................................................................. 202
M13_MASK1, Mask (R/W) ................................................................................................................ 202
M13_MASK2, Mask (R/W) ................................................................................................................ 203
M13_MASK3, Mask (R/W) ................................................................................................................ 203
M13_MASK4, Mask (R/W) ................................................................................................................ 204
M13_MASK5, Mask (R/W) ................................................................................................................ 205
M13_DS3_STATUS1, Status (RO) ................................................................................................... 205
M13_DS3_STATUS2, Status (RO) ................................................................................................... 206
M13_XC_DS2_LOCD_R, DS2 Loss of Clock Delta (RO) ................................................................. 206
M13_XC_DS2_AIS_DETD_R, DS2 Alarm Indication Signal Detection Delta (RO) .......................... 206
M13_DS2_OOFD_R, DS2 Out of Frame Delta (RO) ........................................................................ 207
M13_DS2_LOFD_R, DS2 Loss of Frame Delta (RO) ....................................................................... 207
M13_DS2_AIS_DETD_R, DS2 Alarm Indication Signal Detect Delta (RO) ...................................... 207
M13_DS2_RAI_DETD_R, DS2 Remote Alarm Indication Detection Delta (RO) .............................. 207
M13_DS2_LB_DETD_R, DS2 Loopback Detect Delta (RO) ............................................................. 208
M13_DS2_RSV_RCVD_R, DS2 Receive Reserved Bit Delta (RO) .................................................. 208
M13_DS2DMX_LOCD_R, DS2 DeMUX Loss of Clock Delta (RO) ................................................... 208
M13_DS1_LOCD_R[1—4], DS1 Loss of Clock Delta Registers (RO) .............................................. 208
M13_DS1_AIS_DETD_R[1—4], DS1 Alarm Indication Signal Delta Registers (RO) ........................ 209
M13_DS1_LB_DETD_R[1—4], DS1 Loopback Detect Delta Registers (RO) ................................... 209
M13__XC_DS2_LOC_R, DS2 Loss of Clock Status (RO) ................................................................ 209
M13_XC_DS2_AIS_DET_R, DS2 Alarm Indication Signal Detect Status (RO) ................................ 209
M13_DS2_OOF_R, DS2 Out of Frame Status (RO) ......................................................................... 210
M13_DS2_LOF_R, DS2 Loss of Frame Status (RO) ........................................................................ 210
M13_DS2_AIS_DET_R, DS2 Alarm Indication Signal Detect Status (RO) ....................................... 210
M13_DS2_RAI_DET_R, DS2 Remote Alarm Indication Detect Status (RO) .................................... 210
M13_DS2_LB_DET_R, DS2 Loopback Detect Status (RO) ............................................................. 211
M13_DS2_RSV_RCV_R, DS2 Receive Reserved Bit Delta Status (RO) ......................................... 211
M13_DS2DMX_LOC_R, DS2 DeMUX Loss of Clock Status (RO) ................................................... 211
M13_DS1_LOC_R[1—4], DS1 Loss of Clock Status Registers (RO) ............................................... 211
M13_DS1_AIS_DET_R[1—4], DS1 Alarm Indication Signal Detect Status Registers (RO) ............. 212
M13_DS1_LB_DET_R[1—4], DS1 Loopback Detect Status Registers (RO) .................................... 212
M13_DS1_FEAC_LB_DETD_R[1—4], DS1 Far-End Alarm and Control Loopback Detect Delta
Registers (RO) ................................................................................................................................... 213
Table 251. M13_DS1_FEAC_LB_DET_R[1—4], DS1 Far-End Alarm and Control Loopback Detect
Status Registers (RO) ....................................................................................................................... 213
Table 252. M13_RFEAC_CODE_R, Receive Far-End Alarm and Control Code Status (RO) ............................ 214
196
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
11 M13/M23 MUX/DeMUX Registers (continued)
Table of Contents (continued)
Tables
Page
Table 253. M13_RDL_STATUS, Receive Data-Link Status (RO) ....................................................................... 214
Table 254. M13_RDL_DATA_R, Receive Data-Link Data (RO) ......................................................................... 214
Table 255. M13_RDL_FRAME_SIZE_R, Receive Data-Link Frame Size (RO) .................................................. 214
Table 256. M13_RHDLC_STATUS_R, Receive High-Level Data-Link Control Status (RO) .............................. 215
Table 257. M13_DS2_FORCE_OOF_R, DS2 Force Out of Frame (One Shot R/W) .......................................... 215
Table 258. M13_CONTROL1, Control 1 (One Shot R/W) ................................................................................... 215
Table 259. M13_CONTROL2, Control 2 (R/W) ................................................................................................... 215
Table 260. M13_CONTROL3, Control 3 (R/W) .................................................................................................. 216
Table 261. M13_SP_OFFSET_R, Sync Pulse Offset (R/W) ............................................................................... 216
Table 262. M13_SP_D_OFFSET_R, Sync Pulse D Offset (R/W) ....................................................................... 216
Table 263. M13_M12_MUX_CONTROL1_R[1—7], M12 MUX CONTROL 1 Registers [1—7] (R/W) ................ 217
Table 264. M13_M12_MUX_CONTROL2_R[1—7], M12 MUX CONTROL 2 Registers [1—7] (R/W) ................ 217
Table 265. M13_DS2_RAI_SEND_R, DS2 Remote Alarm Indication Send (R/W) ............................................. 217
Table 266. M13_DS2_RSV_SEND_R, DS2 Reserve Bit Send (R/W) ................................................................ 217
Table 267. M13_DS2_MPINV_R, DS2 M Frame Alignment or Parity Error (R/W) ............................................. 218
Table 268. M13_DS2_FINV_R, DS2 Frame Error (R/W) .................................................................................... 218
Table 269. M13_DS2_P_BER_R, Parity Bit Error Rate (R/W) ............................................................................ 218
Table 270. M13_DS2M12_EDGE_R, DS2 M12 Edge (R/W) .............................................................................. 218
Table 271. M13_DS2_FORCE_AIS_R, DS2 Force Alarm Indication Signal (R/W) ............................................ 218
Table 272. M13_M12_DEMUX_CONTROL1_R[1—7], M12 DeMUX Control 1 Registers [1—7] (R/W) ............ 219
Table 273. M13_M12_DEMUX_CONTROL2_R[1—7], M12 DeMUX Control 2 Registers [1—7] (R/W) ............ 219
Table 274. M13_M12_DEMUX_CONTROL3, DS2 M12 DeMUX Control 3 (R/W) ............................................. 219
Table 275. M13_DMDS2_EDGE_R, DS2 Edge for M12 DeMUX (R/W) ............................................................. 220
Table 276. M13_DS3_CONTROL1, DS3 Control 1 (R/W) .................................................................................. 220
Table 277. M13_DS3_CONTROL2, DS3 Control 2 (R/W) .................................................................................. 221
Table 278. M13_TFEAC_CONTROL, Tx FEAC Control (R/W) ........................................................................... 221
Table 279. M13_THDLC_CONTROL1, Tx HDLC Control 1 (R/W) ..................................................................... 222
Table 280. M13_THDLC_CONTROL2, Tx HDLC Control 2 (R/W) ..................................................................... 222
Table 281. M13_DS2_LB_REQ_R, DS2 Loopback Request (R/W) ................................................................... 222
Table 282. M13_SEL_DS2_LB_R, Select DS2 Loopback (R/W) ........................................................................ 223
Table 283. M13_RDS2_EDGE_R[1—2], Rx DS2 Edge Registers [1—2](R/W) .................................................. 223
Table 284. M13_DS2_OUT_IDLE_R, DS2 Output Idle (R/W) ............................................................................ 223
Table 285. M13_DS2_OUT_AIS_R, DS2 Output Alarm Indication Signal (R/W) ................................................ 223
Table 286. M13_TDS2_EDGE_R, Tx DS2 Edge (R/W) ...................................................................................... 224
Table 287. M13_RDL_CONTROL, RDL Control (R/W) ....................................................................................... 224
Table 288. M13_PM_CNT_ACT_R, Performance Counter (RO) ........................................................................ 224
Table 289. M13_DS3_FERR_CNT_R[1—2], DS3 F-Bit Error Registers (RO) .................................................... 224
Table 290. M13_DS3_FEBE_CNT_R[1—2], DS3 Far-End Block Error Registers (RO) ..................................... 225
Table 291. M13_DS3_CPERR_CNT_R[1—2], DS3 C-Bit Parity Error Registers (RO) ...................................... 225
Table 292. M13_DS3_PERR_CNT_R[1—2], DS3 P-Bit Error Registers (RO) ................................................... 225
Table 293. M13_DS2_PERR_CNT[7—1]_R[1—2], P-Bit Error Counter Status Registers (RO) ......................... 225
Table 294. M13_DS2_FERR_CNT[7—1]_R, F-Bit Error Counter Status Registers (RO) ................................... 226
Table 295. M13_BPV_CNT_R[1—3], Bipolar Violation Counter Status Registers (RO) ..................................... 226
Table 296. M13_EXZ_CNT_R[1—3], Bipolar Violation Counter Status Registers (RO) ..................................... 227
Table 297. M13_TDL_BUFFER_R, Tx Data-Link Buffer Control (R/W) .............................................................. 227
Table 298. M13_TDL_0DATA_R[0—63], Tx Data for Path Maintenence Data-Link Buffer 0 Registers
(64 Bytes x 8 Bits) (R/W) ................................................................................................................... 227
Table 299. M13_TDL_1DATA_R[0—63], Tx Data for Path Maintenence Data-Link Buffer 1 Registers
(64 Bytes x 8 Bits) (R/W) ................................................................................................................... 227
Table 300. Register Address Map ....................................................................................................................... 228
Agere Systems Inc.
197
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
11 M13/M23 MUX/DeMUX Registers (continued)
11.1 M13 Block Register Descriptions
The following tables describe the functions of all bits. For each address, the register bits are indicated as either
read/write (R/W) or read only (RO), and the value of the bits on reset is given.
Table 212. M13_ID_R, M13 Block Identification (RO)
Address
Bit
Name
0x10000
15:8
7:0
—
M13_ID[7:0]
Function
Reserved.
The M13_ID_R register returns a fixed value (0x01) when read.
Reset
Default
0x00
0x01
Table 213. M13_VERSION_R, M13 Version (RO)
Address
Bit
0x10001
15:3
2:0
198
Name
Function
—
Reserved.
M13_VERSION[2:0] These bits identify the version number of the M13.
Reset
Default
0x000
0x0
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
11 M13/M23 MUX/DeMUX Registers (continued)
Table 214. M13_DELTA1, Delta (RO)
Address
Bit
0x10004 15:8
7
6
5
4
3
2
1
0
Name
Reserved.
This delta bit is set if M13_RDL_IDLE (Table 224)
changes state. It can be programmed to be either clear
on read (COR) or clear on write (COW), and it is not set
to 1 again until another state transition occurs.
M13_DS3_LOFD
This delta bit is set if M13_DS3_LOF (Table 224)
changes state. It can be programmed to be either clear
on read (COR) or clear on write (COW), and it is not set
to 1 again until another state transition occurs.
M13_DS3_OOFD
This delta bit is set if M13_DS3_OOF (Table 224)
changes state. It can be programmed to be either clear
on read (COR) or clear on write (COW), and it is not set
to 1 again until another state transition occurs.
M13_DS3_C1_DETD
This delta bit is set if M13_DS3_C1_DET (Table 224)
changes state. It is cleared when read, and it is not set to
1 again until another state transition occurs.
M13_DS3_RAI_DETD
This delta bit is set if M13_DS3_RAI_DET (Table 224)
changes state. It can be programmed to be either clear
on read (COR) or clear on write (COW), and it is not set
to 1 again until another state transition occurs.
M13_DS3_AISPAT_DETD This delta bit is set if M13_DS3_AISPAT_DET
(Table 224) changes state. It can be programmed to be
either clear on read (COR) or clear on write (COW), and it
is not set to 1 again until another state transition occurs.
M13_DS3_IDLEPAT_DETD This delta bit is set if M13_DS3_IDLEPAT_DET
(Table 224) changes state. It can be programmed to be
either clear on read (COR) or clear on write (COW), and it
is not set to 1 again until another state transition occurs.
M13_DS3_CBZ_DETD
This delta bit is set if M13_DS3_CBZ_DET (Table 224)
changes state. It can be programmed to be either clear
on read (COR) or clear on write (COW), and it is not set
to 1 again until another state transition occurs.
Agere Systems Inc.
—
M13_RDL_IDLED
Function
Reset
Default
0x00
0
0
0
0
0
0
0
0
199
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
11 M13/M23 MUX/DeMUX Registers (continued)
Table 215. M13_DELTA2, Delta (RO)
Address
Bit
0x10005 15:8
7
6
5
4
3
2
1
0
Name
Function
—
M13_DS1_LB_SD
Reserved.
This delta bit summarizes the state of
M13_DS1_LB_DETD[28:1] (Table 237) bits.
M13_DS1_AIS_SD
This delta bit is set if any M13_DS1_AIS_DETD[28:1]
(Table 236) bit is high.
M13_DS1_LOC_SD
This delta bit is set if any M13_DS1_LOCD[28:1]
(Table 235) bit is high.
M13_RDS3_SEFD
This delta bit is set if M13_RDS3_SEF (Table 225)
changes state. It can be programmed to be either clear on
read (COR) or clear on write (COW), and it is not set to 1
again until another state transition occurs.
M13_RDS3_ALL1_DETD This delta bit is set if M13_RDS3_ALL1_DET (Table 225)
changes state. It can be programmed to be either clear on
read (COR) or clear on write (COW), and it is not set to 1
again until another state transition occurs.
M13_RDS3_LOSD
This delta bit is set if M13_RDS3_LOS (Table 225)
changes state. It can be programmed to be either clear on
read (COR) or clear on write (COW), and it is not set to 1
again until another state transition occurs.
M13_TDS3_LOCD
This delta bit is set if M13_TDS3_LOC (Table 225)
changes state. It can be programmed to be either clear on
read (COR) or clear on write (COW), and it is not set to 1
again until another state transition occurs.
M13_RDS3_LOCD
This delta bit is set if M13_RDS3_LOC (Table 225)
changes state. It can be programmed to be either clear on
read (COR) or clear on write (COW), and it is not set to 1
again until another state transition occurs.
Reset
Default
0x00
0
0
0
0
0
0
0
0
Table 216. M13_DELTA3, Delta (RO)
Address
Bit
0x10006 15:8
7
6
5
4
3
2
1
0
200
Name
—
M13_DS2_RSV_SD
Function
Reserved.
This delta bit is high if any M13_DS2_RSV_RCVD[7:1]
(Table 233) bit is high.
M13_DS2_LB_SD
This delta bit summarizes the state of
M13_DS2_LB_DETD[7:1] (Table 232).
M13_DS2_RAI_SD
This delta bit summarizes the state of
M13_DS2_RAI_DETD[7:1] (Table 231).
M13_DS2_AIS_SD
This delta bit summarizes the state of
M13_DS2_AIS_DETD[7:1] (Table 230).
M13_DS2_LOF_SD
This delta bit is high if any M13_DS2_LOFD[7:1] (Table 229)
bit is high.
M13_DS2_OOF_SD
This delta bit is high if any M13_DS2_OOFD[7:1]
(Table 228) bit is high.
M13_XC_DS2_AIS_SD This delta bit is set if any M13_XC_DS2_AIS_DETD[7:1]
(Table 227) bit is high.
M13_XC_DS2_LOC_SD This delta bit is set if any M13_XC_DS2_LOCD[7:1]
(Table 226) bit is high.
Reset
Default
0x00
0
0
0
0
0
0
0
0
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
11 M13/M23 MUX/DeMUX Registers (continued)
Table 217. M13_DELTA4, Delta (RO)
Address
Bit
0x10007 15:8
7
6
5
4
3
2
1
0
Name
Reserved.
This bit is set when the M13 completes transmission of a
sequence of FEAC control code. It can be programmed to
be either clear on read (COR) or clear on write (COW), and it
is not set to 1 again until the event reoccurs.
M13_TDL_DONE
This bit is set when the M13 completes transmission of a
data-link frame. It can be programmed to be either clear on
read (COR) or clear on write (COW), and it is not set to 1
again until the event reoccurs.
M13_TDL_BUF1_INT This bit is set when the device completes transmission of
M13_TDL_1DATA63[7:0] (Table 299) (the last byte of buffer
1). It can be programmed to be either clear on read (COR) or
clear on write (COW), and it is not set to 1 again until the
event reoccurs.
M13_TDL_BUF0_INT This bit is set when the device completes transmission of
M13_TDL_0DATA63[7:0] (Table 298) (the last byte of buffer
0). It can be programmed to be either clear on read (COR) or
clear on write (COW), and it is not set to 1 again until the
event reoccurs.
M13_RDL_FIFO_AFD This delta bit is set if M13_RDL_FIFO_AF (Table 225)
changes state. It can be programmed to be either clear on
read (COR) or clear on write (COW), and it is not set to 1
again until another state transition occurs.
M13_RDL_FRM_INT This bit indicates that a new data-link frame closing flag or
an abort byte has been received. It can be programmed to
be either clear on read (COR) or clear on write (COW), and it
is not set to 1 again until the event reoccurs.
M13_RFEAC_ALM_INT This bit indicates that a new DS3 FEAC alarm codeword has
been received. The new codeword is available in register
M13_RFEAC_CODE_R (Table 252). For loopback codewords, the appropriate M13_DS1_FEAC_LB_DETx
(Table 251) and M13_DS3_FLB_DET (Table 251) bits in registers 0x2F through 0x32 will be set or cleared. It can be programmed to be either clear on read (COR) or clear on write
(COW), and it is not set to 1 again until the event reoccurs.
M13_RFEAC_LB_INT This bit indicates that a new DS3 FEAC loopback codeword
has been received. The new codeword is available in register M13_RFEAC_CODE_R. For loopback codewords, the
appropriate M13_DS1_FEAC_LB_DETx and
M13_DS3_FLB_DET bits will be set or cleared. It can be
programmed to be either clear on read (COR) or clear on
write (COW), and it is not set to 1 again until the event reoccurs.
Agere Systems Inc.
—
M13_TFEAC_DONE
Function
Reset
Default
0x00
0
0
0
0
0
0
0
0
201
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
11 M13/M23 MUX/DeMUX Registers (continued)
Table 218. M13_DELTA5, Delta (RO)
Address
Bit
0x10008 15:2
1
0
Name
—
Function
Reset
Default
Reserved.
0x0000
M13_DS2DMX_LOC_SD This delta bit is set if any M13_DS2DMX_LOCD[7:0]
(Table 234) bit register is high.
M13_RDL_FIFO_UFD
This delta bit is set if bit M13_RDL_FIFO_UF (Table 225)
changes state. It can be programmed to be either clear on
read (COR) or clear on write (COW), and it is not set to 1
again until another state transition occurs.
0
0
Table 219. M13_MASK1, Mask (R/W)
Address
Bit
0x1000A 15:8
—
Function
Reset
Default
Reserved.
0x00
7
M13_RDL_IDLEM
Setting this mask bit high prevents the delta
M13_RDL_IDLED (Table 214) from causing the block
output interrupt (INT) to be active.
1
6
M13_DS3_LOFM
Setting this mask bit high prevents the delta
M13_DS3_LOFD (Table 214) from causing the block output INT to be active.
1
5
M13_DS3_OOFM
Setting this mask bit high prevents the delta
M13_DS3_OOFD (Table 214) from causing the block
output INT to be active.
1
4
M13_DS3_C1_DETM
Setting this mask bit high prevents the delta
M13_DS3_C1_DETD (Table 214) from causing the block
output INT to be active.
1
3
M13_DS3_RAI_DETM
Setting this mask bit high prevents the delta
M13_DS3_RAI_DETD (Table 214) from causing the
block output INT to be active.
1
2
M13_DS3_AISPAT_DETM
Setting this mask bit high prevents the delta
M13_DS3_AISPAT_DETD (Table 214) from causing the
block output INT to be Active.
1
1
0
202
Name
M13_DS3_IDLEPAT_DETM Setting this mask bit high prevents the delta
M13_DS3_IDLEPAT_DETD (Table 214) from causing the
block output INT to be active.
M13_DS3_CBZ_DETM
Setting this mask bit high prevents the delta
M13_DS3_CBZ_DETD (Table 214) from causing the
block output INT to be active.
1
1
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
11 M13/M23 MUX/DeMUX Registers (continued)
Table 220. M13_MASK2, Mask (R/W)
Address
Bit
Name
0x1000B 15:8
—
Function
Reserved.
Reset
Default
0x00
7
M13_DS1_LB_SM
Setting this mask bit high prevents the summary delta
M13_DS1_LB_SD (Table 215) from causing the block output interrupt (INT) to be active.
1
6
M13_DS1_AIS_SM
Setting this mask bit high prevents the summary delta
M13_DS1_AIS_SD (Table 215) from causing the block output INT to be active.
1
5
M13_DS1_LOC_SM
Setting this mask bit high prevents the summary delta
M13_DS1_LOC_SD (Table 215) from causing the block
output INT to be active.
1
4
M13_RDS3_SEFM
Setting this mask bit high prevents the delta
M13_RDS3_SEFD (Table 215) from causing the block output INT to be active.
1
3
M13_RDS3_ALL1_DETM Setting this mask bit high prevents the delta
M13_RDS3_ALL1_DETD (Table 215) from causing the
block output INT to be active.
1
2
M13_RDS3_LOSM
Setting this mask bit high prevents the delta
M13_RDS3_LOSD (Table 215) from causing the block output INT to be active.
1
1
M13_TDS3_LOCM
Setting this mask bit high prevents the delta
M13_TDS3_LOCD (Table 215) from causing the block output INT to be active.
1
0
M13_RDS3_LOCM
Setting this mask bit high prevents the delta
M13_RDS3_LOCD (Table 215) from causing the block output INT to be active.
1
Name
Function
—
M13_DS2_RSV_SM
Reserved.
Setting this mask bit high prevents the summary delta
M13_DS2_RSV_SD (Table 216) from causing the block output interrupt (INT) to be active.
Setting this mask bit high prevents the summary delta
M13_DS2_LB_SD (Table 216) from causing the block output INT to be active.
Setting this mask bit high prevents the summary delta
M13_DS2_RAI_SD (Table 216) from causing the block output INT to be active.
Setting this mask bit high prevents the summary delta
M13_DS2_AIS_SD (Table 216) from causing the block output INT to be active.
Setting this mask bit high prevents the summary delta
M13_DS2_LOF_SD (Table 216) from causing the block output INT to be active.
Reset
Default
0x00
1
Table 221. M13_MASK3, Mask (R/W)
Address
Bit
0x1000C 15:8
7
6
M13_DS2_LB_SM
5
M13_DS2_RAI_SM
4
M13_DS2_AIS_SM
3
M13_DS2_LOF_SM
Agere Systems Inc.
1
1
1
1
203
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
11 M13/M23 MUX/DeMUX Registers (continued)
Table 221. M13_MASK3, Mask (R/W) (continued)
Address
Bit
Name
0x1000C
2
M13_DS2_OOF_SM
1
0
Function
Setting this mask bit high prevents the summary delta
M13_DS2_OOF_SD (Table 216) from causing the block
output INT to be active.
M13_XC_DS2_AIS_SM Setting this mask bit high prevents the summary delta
M13_XC_DS2_AIS_SD (Table 216) from causing the block
output INT to be active.
M13_XC_DS2_LOC_SM Setting this mask bit high prevents the summary delta
M13_XC_DS2_LOC_SD (Table 216) from causing the block
output INT to be active.
Reset
Default
1
1
1
Table 222. M13_MASK4, Mask (R/W)
Address
Bit
0x1000D 15:8
7
6
5
4
3
2
1
0
204
Name
—
M13_TFEAC_DONEM
Function
Reserved.
Setting this mask bit high prevents M13_TFEAC_DONE
(Table 217) from causing the block output interrupt (INT) to
be active.
M13_TDL_DONEM
Setting this mask bit high prevents M13_TDL_DONE
(Table 217) from causing the block output INT to be active.
M13_TDL_BUF1_INTM Setting this mask bit high prevents M13_TDL_BUF1_INT
(Table 217) from causing the block output INT to be active.
M13_TDL_BUF0_INTM Setting this mask bit high prevents M13_TDL_BUF0_INT
(Table 217) from causing the block output INT to be active.
M13_RDL_FIFO_AFM Setting this mask bit high prevents M13_RDL_FIFO_AFD
(Table 217) from causing the block output INT to be active.
M13_RDL_FRM_INTM Setting this mask bit high prevents M13_RDL_FRM_INT
(Table 217) from causing the block output INT to be active.
M13_RFEAC_ALM_INTM Setting this mask bit high prevents
M13_RFEAC_ALM_INT (Table 217) from causing the block
output INT to be active.
M13_RFEAC_LB_INTM Setting this mask bit high prevents M13_RFEAC_LB_INT
(Table 217) from causing the block output INT to be active.
Reset
Default
0x00
1
1
1
1
1
1
1
1
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
11 M13/M23 MUX/DeMUX Registers (continued)
Table 223. M13_MASK5, Mask (R/W)
Address
Bit
Name
0x1000E 15:2
1
0
—
Function
Reserved.
M13_DS2DMX_LOC_SM Setting this mask bit high prevents the summary delta
M13_DS2DMX_LOC_SD (Table 218) from causing the
block output interrupt (INT) to be active.
M13_RDL_FIFO_UFM Setting this mask bit high prevents M13_RDL_FIFO_UFD
(Table 218) from causing the block output INT to be active.
Reset
Default
000000
000000
00
1
1
Table 224. M13_DS3_STATUS1, Status (RO)
Address
Bit
0x1000F 15:8
7
6
5
4
3
2
1
0
Name
Reserved.
This bit is set if 15 consecutive ones are received on the
path maintenance data link. it is cleared when a flag byte is
received.
M13_DS3_LOF
This bit is set if M13_DS3_OOF is high continuously for
28 frame periods (approximately 3 ms). Once set,
M13_DS3_LOF is not cleared until M13_DS3_OOF is continuously low for 28 frame periods.
M13_DS3_OOF
The DS3 framer out-of-frame state bit. (See DS3 Framer
on page 469) This bit is high while out-of-frame.
M13_DS3_C1_DET
This bit is set if the first C bit of each DS3 frame is received
high for 8 consecutive frames. Once M13_DS3_C1_DET is
set, 3 consecutive frames with C1 = 0 must be received
before it is cleared.
M13_DS3_RAI_DET
If both X bits in 2 consecutive frames are received as 0, the
M13 sets this bit to 1. Once it is set, it is not cleared until
both X bits in 2 consecutive frames are received as 1.
M13_DS3_AISPAT_DET The 4704 information bits in each M frame are checked for
the presence of the AIS (1010) pattern. A pattern detection
bit is set if fewer than 5 pattern errors are received in each
of 2 consecutive frames. Once a bit is set, it is not cleared
until at least 16 pattern errors are received in each of
2 consecutive frames.
M13_DS3_IDLEPAT_DET The 4704 information bits in each M frame are checked for
the presence of the idle (1100) pattern. A pattern detection
bit is set if fewer than 5 pattern errors are received in each
of 2 consecutive frames. Once a bit is set, it is not cleared
until at least 16 pattern errors are received in each of
2 consecutive frames.
M13_DS3_CBZ_DET
This bit is set if every C bit in 3 consecutive DS3 frames is
0. It is cleared if the three C bits in a single
M-subframe are all 1.
Agere Systems Inc.
—
M13_RDL_IDLE
Function
Reset
Default
0x00
1
0
1
0
0
0
0
0
205
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
11 M13/M23 MUX/DeMUX Registers (continued)
Table 225. M13_DS3_STATUS2, Status (RO)
Address
Bit
0x10010 15:7
6
5
4
3
2
1
0
Name
—
Function
Reserved.
M13_RDL_FIFO_UF
M13_RDL_FIFO_AF
This bit is 1 if the receive HDLC FIFO is underflow.
This bit is 1 if the number of unread bytes in the receive
HDLC FIFO is greater than the fill-up level set by bits
M13_RDL_FILL[1:0] (Table 287).
M13_RDS3_SEF
This bit is 1 if there are three or more F-bit errors in
16 consecutive F bits. It is not terminated until the signal is
in-frame and there are less than three F-bit errors in 16 consecutive F bits.
M13_RDS3_ALL1_DET This bit is 1 if the input data is 0 for fewer than 9 out of
8192 clock periods.
M13_RDS3_LOS
This bit is 1 if there are 175 ±75 contiguous pulse positions
with no pulses of either positive or negative polarity at the
DS3 Input. An LOS is cleared upon detecting an average
pulse density of at least 33% over a period of
175 ±75 contiguous pulse positions, starting with the receipt
of a pulse.
M13_TDS3_LOC
This bit is 1 if the SMPR_TDS3CLK signal fails to have transitions for at least 10 periods of SMPR_RDS3CLK. A single
transition on SMPR_TDS3CLK resets this bit.
M13_RDS3_LOC
This bit is 1 if the SMPR_RDS3CLK signal fails to have transitions for at least 10 periods of SMPR_TDS3CLK. A single
transition on SMPR_RDS3CLK resets this bit.
Reset
Default
000000
000
0
0
1
0
0
0
0
Table 226. M13_XC_DS2_LOCD_R, DS2 Loss of Clock Delta (RO)
Address
Bit
0x10011 15:7
6:0
Name
Function
—
M13_XC_DS2_
LOCD[7:1]
Reserved.
These individual delta bits are set as the result of the corresponding state bits M13_XC_DS2_LOC[7:1] (Table 238) transitioning either from 0 to 1 or from 1 to 0. They can be
programmed to be either clear on read (COR) or clear on write
(COW), and they are not set to 1 again until the event reoccurs.
Reset
Default
0x000
0x00
Table 227. M13_XC_DS2_AIS_DETD_R, DS2 Alarm Indication Signal Detection Delta (RO)
Address
Bit
0x10012 15:7
6:0
206
Name
Function
—
M13_XC_DS2_
AIS_DETD[7:1]
Reserved.
These individual delta bits are set as the result of the corresponding state bits M13_XC_DS2_AIS_DET[7:1]
(Table 239) transitioning either from 0 to 1 or from 1 to 0.
They can be programmed to be either clear on read (COR)
or clear on write (COW), and they are not set to 1 again until
the event reoccurs.
Reset
Default
0x000
0x00
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
11 M13/M23 MUX/DeMUX Registers (continued)
Table 228. M13_DS2_OOFD_R, DS2 Out of Frame Delta (RO)
Address
Bit
Name
Function
0x10013 15:7
—
Reserved.
6:0 M13_DS2_OOFD[7:1] These individual delta bits are set as the result of the corresponding state bits M13_DS2_OOF[7:1] (Table 240) transitioning either from 0 to 1 or from 1 to 0. Delta bits can be
programmed to be either clear on read (COR) or clear on write
(COW), and they are not set to 1 again until the event reoccurs.
Reset
Default
0x000
0x00
Table 229. M13_DS2_LOFD_R, DS2 Loss of Frame Delta (RO)
Address
Bit
Name
Function
0x10014 15:7
—
Reserved.
6:0 M13_DS2_LOFD[7:1] These individual delta bits are set as the result of the corresponding state bits M13_DS2_LOF[7:1] (Table 241) transitioning either from 0 to 1 or from 1 to 0. They can be programmed
to be either clear on read (COR) or clear on write (COW), and
they are not set to 1 again until the event reoccurs.
Reset
Default
0x000
0x00
Table 230. M13_DS2_AIS_DETD_R, DS2 Alarm Indication Signal Detect Delta (RO)
Address
Bit
0x10015 15:7
6:0
Name
Function
—
M13_DS2_AIS_
DETD[7:1]
Reserved.
These individual delta bits are set as the result of the corresponding state bits M13_DS2_AIS_DET[7:1] (Table 242) transitioning either from 0 to 1 or from 1 to 0. Delta bits can be
programmed to be either clear on read (COR) or clear on write
(COW), and they are not set to 1 again until the event reoccurs.
Reset
Default
0x000
0x00
Table 231. M13_DS2_RAI_DETD_R, DS2 Remote Alarm Indication Detection Delta (RO)
Address
Bit
0x10016 15:7
6:0
Agere Systems Inc.
Name
Function
—
M13_DS2_
RAI_DETD[7:1]
Reserved.
These individual delta bits are set as the result of the corresponding state bits M13_DS2_RAI_DET[7:1] (Table 243) transitioning either from 0 to 1 or from 1 to 0. Delta bits can be
programmed to be either clear on read (COR) or clear on write
(COW), and they are not set to 1 again until the event reoccurs.
Reset
Default
0x000
0x00
207
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
11 M13/M23 MUX/DeMUX Registers (continued)
Table 232. M13_DS2_LB_DETD_R, DS2 Loopback Detect Delta (RO)
Address
Bit
0x10017 15:7
6:0
Name
Function
—
M13_DS2_LB_
DETD[7:1]
Reserved.
These individual delta bits are set as the result of the corresponding state bits M13_DS2_LB_DET[7:1] (Table 244) transitioning either from 0 to 1 or from 1 to 0. Delta bits can be
programmed to be either clear on read (COR) or clear on write
(COW), and they are not set to 1 again until the event reoccurs.
Reset
Default
0x000
0x00
Table 233. M13_DS2_RSV_RCVD_R, DS2 Receive Reserved Bit Delta (RO)
Address
Bit
0x10018 15:7
6:0
Name
Function
—
M13_DS2_RSV_
RCVD[7:1]
Reserved.
These individual delta bits are set as the result of the corresponding state bits M13_DS2_RSV_RCV[7:1] (Table 245)
transitioning either from 0 to 1 or from 1 to 0. Delta bits can be
programmed to be either clear on read (COR) or clear on write
(COW), and they are not set to 1 again until the event reoccurs. (G.747).
Reset
Default
0x000
0x00
Table 234. M13_DS2DMX_LOCD_R, DS2 DeMUX Loss of Clock Delta (RO)
Address
Bit
0x10019 15:7
6:0
Name
Function
—
M13_DS2DMX_
LOCD[7:1]
Reserved.
These individual delta bits are set as the result of the corresponding state bits M13_DS2DMX_LOC[7:1] (Table 246) transitioning either from 0 to 1 or from 1 to 0. Delta bits can be
programmed to be either clear on read (COR) or clear on write
(COW), and they are not set to 1 again until the event reoccurs.
Reset
Default
0x000
0x00
Table 235. M13_DS1_LOCD_R[1—4], DS1 Loss of Clock Delta Registers (RO)
Address
Bit
Name
0x1001E
0x1001F—
0x10021
0x1001E
15:4
15:8
—
—
3:0
M13_DS1_LOCD[28:25]
0x1001F
7:0
M13_DS1_LOCD[24:17]
0x10020
7:0
M13_DS1_LOCD[16:9]
0x10021
7:0
M13_DS1_LOCD[8:1]
208
Function
Reset
Default
0x000
0x00
These individual delta bits are set as the result of the
corresponding state bits M13_DS1_LOC[28:1]
(Table 247) transitioning either from 0 to 1 or from 1 to
0. Delta bits can be programmed to be either clear on
read (COR) or clear on write (COW), and they are not
set to 1 again until the event reoccurs.
0x00
Reserved.
Reserved.
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
11 M13/M23 MUX/DeMUX Registers (continued)
Table 236. M13_DS1_AIS_DETD_R[1—4], DS1 Alarm Indication Signal Delta Registers (RO)
Address
Bit
0x10022 15:4
0x10023— 15:8
0x10025
0x10022
3:0
Name
—
—
Function
Reset
Default
0x000
0x00
These individual delta bits are set as the result of the
corresponding state bits M13_DS1_AIS_DET[28:1]
(Table 248) transitioning either from 0 to 1 or from 1
to 0. Delta bits can be programmed to be either clear
on read (COR) or clear on write (COW), and they are
not set to 1 again until the event reoccurs.
0x00
Reserved.
Reserved.
M13_DS1_AIS_DETD[28:25]
0x10023
7:0
M13_DS1_AIS_DETD[24:17]
0x10024
7:0
M13_DS1_AIS_DETD[16:9]
0x10025
7:0
M13_DS1_AIS_DETD[8:1]
Table 237. M13_DS1_LB_DETD_R[1—4], DS1 Loopback Detect Delta Registers (RO)
Address
Bit
0x10026 15:4
0x10027— 15:8
0x10029
3:0
0x10026
0x10027
7:0
0x10028
7:0
0x10029
7:0
Name
—
—
Function
Reserved.
Reserved.
M13_DS1_LB_DETD[28:25] These individual delta bits are set as the result of the
M13_DS1_LB_DETD[24:17] corresponding state bits M13_DS1_LB_DET[28:1]
(Table 249) transitioning either from 0 to 1 or From 1
M13_DS1_LB_DETD[16:9]
to 0. Delta bits can be programmed to be either clear
M13_DS1_LB_DETD[8:1]
on read (COR) or clear on write (COW), and they are
not set to 1 again until the event reoccurs.
Reset
Default
0x000
0x00
0x00
Table 238. M13__XC_DS2_LOC_R, DS2 Loss of Clock Status (RO)
Address
Bit
0x1002F 15:7
6:0
Name
—
M13_XC_DS2_
LOC[7:1]
Function
Reserved.
A logic 1 of M13_XC_DS2_LOCy bit indicates that loss of
clock is detected on the DS2 clock input.
Reset
Default
0x000
0x00
Table 239. M13_XC_DS2_AIS_DET_R, DS2 Alarm Indication Signal Detect Status (RO)
Address
Bit
0x10030 15:7
6:0
Agere Systems Inc.
Name
Function
—
M13_XC_DS2_
AIS_DET[7:1]
Reserved.
The M13_XC_DS2_AIS_DETy bit is set high if the input
XC_DS2M23DATAy is 0 for fewer than 5 clock cycles in each
of two consecutive 840 clock periods, And cleared if there are
more than four zeros in each of two consecutive 840-bit periods.
Reset
Default
0x000
0x00
209
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
11 M13/M23 MUX/DeMUX Registers (continued)
Table 240. M13_DS2_OOF_R, DS2 Out of Frame Status (RO)
Address
Bit
0x10031 15:7
6:0
Name
—
M13_DS2_OOF[7:1]
Function
Reserved.
This register contains the state bits for the DS2 framers. A 1
indicates out-of-frame.
Reset
Default
000000
000
0x7F
Table 241. M13_DS2_LOF_R, DS2 Loss of Frame Status (RO)
Address
Bit
0x10032 15:7
6:0
Name
—
M13_DS2_LOF[7:1]
Function
Reset
Default
Reserved.
—
0x00
The M13_DS2_LOFy bit is set if M13_DS2_OOFy (Table 240)
is high continuously for 28 DS3 frame periods (approximately
3 ms). Once set, M13_DS2_LOFy is not cleared until
M13_DS2_OOFy is continuously low for 28 DS3 frame periods. DS3 frame periods are not counted while M13_DS3_OOF
= 1 (Table 224).
Table 242. M13_DS2_AIS_DET_R, DS2 Alarm Indication Signal Detect Status (RO)
Address
Bit
0x10033 15:7
6:0
Name
Function
—
M13_DS2_AIS_
DET[7:1]
Reserved.
The M13_DS2_AIS_DETy bit is set high if the input to the yth
M12 demultiplexer is logic 0 for fewer than 5 clock cycles in
each of two consecutive 840 clock periods and cleared if there
are more than four zeros in each of two consecutive 840-bit
periods.
Reset
Default
0x000
0x00
Table 243. M13_DS2_RAI_DET_R, DS2 Remote Alarm Indication Detect Status (RO)
Address
Bit
0x10034 15:7
6:0
210
Name
—
M13_DS2_RAI_
DET[7:1]
Function
Reset
Default
Reserved.
0x000
The M13_DS2_RAI_DETy bit changes state only after the X bit 0x00
in the DS1 mode (M13_DS1_E1Ny = 1 (Table 263)), or the
RAI bit in the E1 mode is received as the same value for four
consecutive DS2 frames. DS2 frame periods are not counted
while M13_DS3_OOF = 1 (Table 224). In the DS1 mode,
M13_DS2_RAI_DETy is set to the inverse of the X bit. In the
E1 mode, it is set equal to the RAI bit.
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
11 M13/M23 MUX/DeMUX Registers (continued)
Table 244. M13_DS2_LB_DET_R, DS2 Loopback Detect Status (RO)
Address
Bit
0x10035 15:7
6:0
Name
—
M13_DS2_LB_
DET[7:1]
Function
Reset
Default
Reserved.
0x000
0x00
In the M23 mode (M13_M23_CBP = 1 (Table 260)), the C bits
in each received DS3 M-subframe are checked for loopback
requests. If the third C bit differs from the first and second C
bits in the yth M-subframe for 5 successive DS3 frames,
M13_DS2_LB_DETy is set to 1. M13_DS2_LB_DETy is
cleared when the third C bit does not differ from the first two C
bits in subframe y for 5 successive DS3 frames. In the C-bit
parity mode, M13_DS2_LB_DETy is fixed at 0.
Table 245. M13_DS2_RSV_RCV_R, DS2 Receive Reserved Bit Delta Status (RO)
Address
Bit
0x10036 15:7
6:0
Name
Function
—
M13_DS2_RSV_
RCV[7:1]
Reserved.
The M13_DS2_RSV_RCVy bit changes state only after the
reserved bit in the E1 mode (M13_DS1_E1Ny = 0) is received
as the same value for 4 consecutive DS2 frames. DS2 frame
periods are not counted while M13_DS3_OOF = 1. It is set
equal to the reserved bit.
Reset
Default
0x000
0x00
Table 246. M13_DS2DMX_LOC_R, DS2 DeMUX Loss of Clock Status (RO)
Address
Bit
0x10037 15:7
6:0
Name
—
M13_DS2DMX_
LOC[7:1]
Function
Reserved.
A logic 1 of M13_DS2DMX_LOCy bit indicates that loss of
clock is detected on the DS2 clock input, XC_DS2DMXCLKy.
Reset
Default
0x000
0x00
Table 247. M13_DS1_LOC_R[1—4], DS1 Loss of Clock Status Registers (RO)
Address
Bit
Name
Function
0x1003C 15:4
—
Reserved.
Reset
Default
0x000
0x1003D 15:8
—
Reserved.
0x00
0x1003E 15:8
—
Reserved.
0x00
0x1003F 15:8
—
Reserved.
0x00
The M13_DS1_LOCx bits indicate when loss of clock is
detected on a low-speed clock input, XC_DS1CLKx.
0x0
0x1003C
3:0
M13_DS1_LOC[28:25]
0x1003D
7:0
M13_DS1_LOC[24:17]
0x1003E
7:0
M13_DS1_LOC[16:9]
0x00
0x1003F
7:0
M13_DS1_LOC[8:1]
0x00
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0x00
211
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
11 M13/M23 MUX/DeMUX Registers (continued)
Table 248. M13_DS1_AIS_DET_R[1—4], DS1 Alarm Indication Signal Detect Status Registers (RO)
Address
Bit
0x10040 15:4
—
Reserved.
Reset
Default
0x000
0x10041 15:8
—
Reserved.
0x00
0x10042 15:8
—
Reserved.
0x00
0x10043 15:8
—
Reserved.
0x00
0x10040
3:0
0x10041
Name
Function
7:0
M13_DS1_AIS_DET[28:25] The M13_DS1_AIS_DETx bits indicate when AIS is
M13_DS1_AIS_DET[24:17] detected on a low-speed data input, XC_DS1DATAx.
0x00
0x10042
7:0
M13_DS1_AIS_DET[16:9]
0x00
0x10043
7:0
M13_DS1_AIS_DET[8:1]
0x00
0x0
Table 249. M13_DS1_LB_DET_R[1—4], DS1 Loopback Detect Status Registers (RO)
Address
Bit
Name
0x10044 15:4
—
Reserved.
Reset
Default
0x000
0x10045 15:8
—
Reserved.
0x00
0x10046 15:8
—
Reserved.
0x00
0x10047 15:8
—
Reserved.
0x00
The M13_DS1_LB_DETx bits indicate when a loopback
request has been received through inversion of the third
C bit in received DS2 frames.
0x0
0x10044
3:0
M13_DS1_LB_DET[28:25]
0x10045
7:0
M13_DS1_LB_DET[24:17]
0x10046
7:0
M13_DS1_LB_DET[16:9]
0x10047
7:0
M13_DS1_LB_DET[8:1]
212
Function
0x00
0x00
0x00
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Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
11 M13/M23 MUX/DeMUX Registers (continued)
Table 250. M13_DS1_FEAC_LB_DETD_R[1—4], DS1 Far-End Alarm and Control Loopback Detect Delta
Registers (RO)
Address
Bit
Name
Function
Reset
Default
0x00
0x0
—
This delta bit is set if M13_DS3_FLB_DET
(Table 251) changes state. It can be programmed to be either clear on read (COR) or
clear on write (COW), and it is not set to 1
again until another state transition occurs.
Reserved.
6:4
—
Reserved.
000
0x1004A 15:8
—
Reserved.
0x00
0x1004B 15:8
—
Reserved.
0x00
0x10049 15:8
0x10049
0x10049
—
7
M13_DS3_FLB_DETD
Reserved.
0x00
0x1004C 15:8
0x10049
3:0
0x1004A
7:0
0x1004B
7:0
0x1004C
7:0
These individual delta bits are set as the
M13_DS1_FEAC_LB_DETD[28:25] result of the corresponding state bits
M13_DS1_FEAC_LB_DETD[24:17] M13_DS1_FEAC_LB_DET[28:1] (Table 251)
transitioning either from 0 to 1 or from 1 to 0.
M13_DS1_FEAC_LB_DETD[16:9]
Delta bits can be programmed to be either
M13_DS1_FEAC_LB_DETD[8:1]
clear on read (COR) or clear on write
(COW), and they are not set to 1 again until
the event reoccurs.
0x0
0x00
0x00
0x00
Table 251. M13_DS1_FEAC_LB_DET_R[1—4], DS1 Far-End Alarm and Control Loopback Detect Status
Registers (RO)
Address
Bit
0x1004D 15:8
Name
Function
—
Reserved.
When an FEAC loopback activate codeword for
DS3 is received four consecutive times, the bit is
set high. The bit is cleared when a loopback deactivate codeword is received four consecutive times.
Reserved.
Reserved.
Reserved.
Reserved.
0x1004D
7
M13_DS3_FLB_DET
0x1004D
6:4
—
0x1004E 15:8
—
0x1004F 15:8
—
0x10050 15:8
—
0x1004D
3:0
0x1004E
7:0
0x1004F
7:0
0x10050
7:0
M13_DS1_FEAC_LB_DET[28:25] When an FEAC loopback activate codeword for
M13_DS1_FEAC_LB_DET[24:17] DS1 is received four consecutive times, the appropriate bit(s) is set high. The bit(s) is cleared when a
M13_DS1_FEAC_LB_DET[16:9]
loopback deactivate codeword for that channel(s) is
M13_DS1_FEAC_LB_DET[8:1] received four consecutive times.
Agere Systems Inc.
Reset
Default
0x00
0
000
0x00
0x00
0x00
0x0
0x00
0x00
0x00
213
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
11 M13/M23 MUX/DeMUX Registers (continued)
Table 252. M13_RFEAC_CODE_R, Receive Far-End Alarm and Control Code Status (RO)
Address
Bit
0x10051 15:6
5:0
Name
—
Function
Reserved.
M13_RFEAC_CODE[5:0] When the same codeword is received through the FEAC
channel four consecutive times, the M13 will set
M13_RFEAC_CODE[5:0] = x5x4x3x2x1x0, where the
received FEAC codeword is 0x5x4x3x2x1x0 0 11111111,
and it is received right to left.
Reset
Default
000000
0000
0x3F
Table 253. M13_RDL_STATUS, Receive Data-Link Status (RO)
Address
Bit
0x10052 15:5
4
3
2
1
0
Name
Function
—
M13_RDL_FLAG
Reserved.
This bit is high if the closing flag or an abort byte has been
received.
M13_RDL_ABORT
This bit is high if the frame was ended with an abort byte
rather than a closing flag.
M13_RDL_NOT_BYTE This bit is set if the number of bits in the frame (after removal
of stuffed zeros) is not a multiple of 8.
M13_RDL_OVFL
This bit is set if at least 1 byte of the frame was overwritten by
a byte from a succeeding frame before being read.
M13_RDL_FCS_ERR This bit is set if the CRC-16 check fails and M13_RDL_FCS =
1 (Table 287).
Reset
Default
0x000
0
0
0
0
0
Table 254. M13_RDL_DATA_R, Receive Data-Link Data (RO)
Address
Bit
0x10053 15:8
7:0
Name
Function
—
Reserved.
M13_RDL_DATA[7:0] Bytes received via the path maintenance data link are stored
in a 128-byte FIFO. They can be read out of the FIFO through
this register, M13_RDL_DATA_R. On reset, the FIFO is emptied, and reading from this register returns an undetermined
value.
Reset
Default
0x00
0xXX
Table 255. M13_RDL_FRAME_SIZE_R, Receive Data-Link Frame Size (RO)
Address
Bit
0x10054 15:7
6:0
214
Name
Function
—
M13_RDL_FRAME_
SIZE[6:0]
Reserved.
The number of bytes in the frame modulo-128 is indicated by
this register. This is the number of bytes from the frame that
have been written into the FIFO, not the number of bytes
remaining in the FIFO. All bytes between the opening flag and
the FCS bytes are included (unless M13_RDL_FCS
(Table 287) is low, in which case the FCS bytes are included in
the count).
Reset
Default
0x000
0x00
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
11 M13/M23 MUX/DeMUX Registers (continued)
Table 256. M13_RHDLC_STATUS_R, Receive High-Level Data-Link Control Status (RO)
Address
Bit
Name
0x10055 15:8
7:0
—
M13_RHDLC_
STATUS[7:0]
Function
Reset
Default
Reserved.
0x00
0x00
This register provides information on the earliest HDLC frame
still in the FIFO. A value of 1 in bit 7 indicates that the closing
flag or an abort byte for the current frame has been received; a
1 in bit 6 indicates the current frame is corrupted; bits 5 to 1
indicate the size of the current frame modulo-32; and bit 0 is
set to 1 if there are less than 32 bytes of the earliest frame left
in the FIFO.
Table 257. M13_DS2_FORCE_OOF_R, DS2 Force Out of Frame (One Shot R/W)
Address
Bit
0x10059 15:7
6:0
Name
—
M13_DS2_FORCE_
OOF[7:1]
Function
Reserved.
When M13_DS2_FORCE_OOFy transitions from 0 to 1, the
DS2 framer in M12 demultiplexer Y is forced out of frame.
Table 258. M13_CONTROL1, Control 1 (One Shot R/W)
Address Bit
Name
Reset
Default
0x000
0x00
Function
Reset
Default
0x1005A 15:3
—
Reserved.
0x000
0
2
M13_RDL_FRM_CLR If M13_RDL_FRM_CLR is set to 1, the portion of the earliest frame still in the receive HDLC FIFO will be deleted.
The user must reset M13_RDL_FRM_CLR before another
frame can be deleted. If M13_RDL_FRM_CLR is set before
the closing flag of the frame currently being read from the
FIFO has been received, all subsequent bytes of the frame
will be discarded without being written into the FIFO.
1
M13_DS3_FORCE_OOF When this bit transitions from 0 to 1, the DS3 framer is
0
forced out-of-frame.
0
M13_BIPOL_ERR
A single bipolar violation error is transmitted each time this
0
bit transitions from 0 to 1.
Table 259. M13_CONTROL2, Control 2 (R/W)
Address
Bit
0x1005C 15:8
7
6
5
4
Reset
Default
—
Reserved.
0x00
M13_BPV_IN
If this bit is 1, the SMPR_RDS3NEG_BPV input is used as an
0
external B3ZS bipolar violation indication instead of a negative
input pulse.
M13_LOOP_TIME
The M23 multiplexer uses the SMPR_TDS3CLK if this bit is 0,
0
otherwise, the SMPR_RDS3CLK is used.
M13_LOOP_T_TO_R Setting this bit to 1 causes the M23 MUX output to be looped
0
back to the M23 DEMUX input.
M13_LOOP_R_TO_T Setting this bit to 1 causes the received DS3 input to be
0
looped back to the transmit DS3 output.
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Name
Function
215
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
11 M13/M23 MUX/DeMUX Registers (continued)
Table 259. M13_CONTROL2, Control 2 (R/W) (continued)
Address
Bit
0x1005C
3
2
1
0
Name
Function
M13_AUTO_AIS_LOF If this bit is 1, the M13 will automatically insert AIS in all DS2
outputs of the M23 demultiplexer when M13_DS3_LOF = 1
(Table 224), and it will automatically insert AIS in all DS1 or E1
outputs of M12 demultiplexer Y when M13_DS2_LOFy = 1
(Table 241).
M13_AUTO_AIS_OOF If this bit is 1, the M13 will automatically insert AIS in all DS2
outputs of the M23 demultiplexer when M13_DS3_OOF = 1
(Table 224), and it will automatically insert AIS in all DS1 or E1
outputs of M12 demultiplexer Y when M13_DS2_OOFy = 1
(Table 240).
M13_AUTO_FLB
If this bit Is 1, the device will automatically loop the received
DS3 input to the transmit DS3 output when
M13_DS3_FLB_DET = 1 (Table 251), and it will automatically
select DS1/E1 output x from an M12 demultiplexer in place of
the DS1/E1 output from input selector x when
M13_DS1_FEAC_LB_DETx = 1 (Table 251).
M13_AUTO_LB
When M13_AUTO_LB = 1, loopback of DS1 channel x is activated if M13_DS1_LB_DETx = 1 (Table 249).
Reset
Default
1
1
0
0
Table 260. M13_CONTROL3, Control 3 (R/W)
Address
Bit
0x1005D 15:2
1
0
Name
—
M13_M23_CBP
M13_BIPOLAR
Function
Reserved.
If this Bit Is 1, the M13 Operates in the M23 mode. Otherwise, it is in the C-Bit Parity Mode.
The M13 Performs B3ZS Encoding And Decoding if this
Bit is High.
Reset
Default
0x0000
0
0
Table 261. M13_SP_OFFSET_R, Sync Pulse Offset (R/W)
Address
Bit
0x1005E 15:8
7:0
Name
Function
—
M13_NSMI_SP_
OFFSET[7:0]
Reserved.
The Register Determines the Offset Value (0—255) for the
Transmit NSMI sync Pulse ahead of the M1 Bit In a DS3
Frame.
Reset
Default
0x00
0x00
Table 262. M13_SP_D_OFFSET_R, Sync Pulse D Offset (R/W)
Address
Bit
0x1005F 15:8
7:0
216
Name
Function
—
M13_NSMI_SP_D_
OFFSET[7:0]
Reserved.
The Register Determines the Offset Value (0—255) for the
Receive NSMI Sync Pulse ahead of the M1 Bit In a DS3
Frame.
Reset
Default
0x00
0x00
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
11 M13/M23 MUX/DeMUX Registers (continued)
Table 263. M13_M12_MUX_CONTROL1_R[1—7], M12 MUX CONTROL 1 Registers [1—7] (R/W)
Address
Bit
0x10060 15:8
0x10062 7:6
0x10064
0x10066
0x10068
0x1006A
0x1006C
5
4
3:0
Name
Function
—
M13_M12_
MODE[1—7][1:0]
Reserved.
00 = The M12 MUX Operates as the First Stage Of M13
Multiplexing. The DS1/E1 clocks are inputs to the block.
01 = The M12 MUX operates as an independent multiplexer.
The DS1/E1 clocks are inputs to the block.
10 = The M12 MUX operates as an independent multiplexer.
The DS1/E1 clocks are outputs from the block.
11 = The M12 is idle.
M13_MUXCH2_4_ If these bits are 1, the second and fourth DS1 inputs to the
INV[1—7]
M12 multiplexers are inverted before they are MUXed into DS2
signals.
M13_DS1_E1N[1—7] If these bits are 1, the M12 multiplexers operate on DS1
inputs; otherwise, they operate on E1 inputs.
M13_DS1_LB_
If these bits are 1, the third C bit for DS1 or E1 channels is
REQ[1:28]
inverted in the generated DS2 frames to indicate loopback
requests.
Reset
Default
0x00
00
1
1
0x0
Table 264. M13_M12_MUX_CONTROL2_R[1—7], M12 MUX CONTROL 2 Registers [1—7] (R/W)
Address
Bit
0x10061 15:8
0x10063 7:4
0x10065
0x10067
3:0
0x10069
Name
—
M13_SEL_DS1_
LB[1:28]
M13_RDS1_
EDGE[1:28]
Function
Reserved.
A 1 in these bits will force DeMUXed DS1 or E1 signals to be
looped back.
A 1 in these bits means that the received DS1/E1 signals are
retimed by the rising edge of the associated clocks; a logic 0
means that the data is retimed by the falling edge.
Reset
Default
0x00
0x0
0x0
0x1006B
0x1006D
Table 265. M13_DS2_RAI_SEND_R, DS2 Remote Alarm Indication Send (R/W)
Address
Bit
0x1006E 15:7
6:0
Name
—
M13_DS2_RAI_
SEND[7:1]
Function
Reset
Default
Reserved.
0x000
The Remote Alarm Indication is Activated if These Bits are 0x00
Set to 1.
Table 266. M13_DS2_RSV_SEND_R, DS2 Reserve Bit Send (R/W)
Address
Bit
0x1006F 15:7
6:0
Agere Systems Inc.
Name
—
M13_DS2_RSV_
SEND[7:1]
Function
Reset
Default
Reserved.
0x000
In the E1 Mode, the Reserved Bit Of DS2 is set to the Value 0x00
of These Bits.
217
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
11 M13/M23 MUX/DeMUX Registers (continued)
Table 267. M13_DS2_MPINV_R, DS2 M Frame Alignment or Parity Error (R/W)
Address
Bit
0x10070 15:7
6:0
Name
—
M13_DS2_
MPINV[7:1]
Function
Reset
Default
Reserved.
0x000
These Bits Determine whether the DS2 M frame Alignment 0x00
Signals in the DS1 Mode, or the DS2 Parity Bits In the E1
Mode are Generated in Error.
Table 268. M13_DS2_FINV_R, DS2 Frame Error (R/W)
Address
Bit
0x10071 15:7
6:0
Name
Function
Reset
Default
—
Reserved.
0x000
M13_DS2_FINV[7:1] These Bits Determine whether the DS2 M-Subframe Align- 0x00
ment Signals in the DS1 Mode, or the Frame Alignment
Signal in the E1 Mode are Generated in Error.
Table 269. M13_DS2_P_BER_R, Parity Bit Error Rate (R/W)
Address
Bit
0x10072 15:7
6:0
Name
—
M13_DS2_P_
BER[7:1]
Function
Reset
Default
Reserved.
0x000
The DS2 Parity Bits in the E1 Mode Immediately Following 0x00
Each 0 to 1 Transition of the Input SMPR_BER_INSRT
(Table 65) are Inverted if these Register Bits are Set to 1.
Table 270. M13_DS2M12_EDGE_R, DS2 M12 Edge (R/W)
Address
Bit
0x10073 15:7
6:0
Name
—
M13_DS2M12_
EDGE[7:1]
Function
Reset
Default
Reserved.
0x000
A 1 in these Bits Means that the Output DS2 Signals From 0x00
M12 MUXs are Retimed by the Rising Edge of the Associated Clocks; A 0 Means that the Data is Retimed by the
Falling Edge.
Table 271. M13_DS2_FORCE_AIS_R, DS2 Force Alarm Indication Signal (R/W)
Address
Bit
0x10074 15:7
6:0
218
Name
—
M13_DS2_FORCE_
AIS[7:1]
Function
Reset
Default
Reserved.
0x000
A 1 in these Bits Means that the Output DS2 Signals From 0x00
M12 MUXs are Forced to be AIS (All Ones).
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
11 M13/M23 MUX/DeMUX Registers (continued)
Table 272. M13_M12_DEMUX_CONTROL1_R[1—7], M12 DeMUX Control 1 Registers [1—7] (R/W)
Address
Bit
0x1007B 15:8
7:6
0x1007D
0x1007F
Name
Function
—
M13_M12DMX_
MODE[1—7][1:0]
Reserved.
00 = The M12 DeMUX Receives DS2 Signal From the M23
DeMUX.
01 = The M12 deMUX operates as an independent demultiplexer.
10/11 = The M12 deMUX is idle and outputs are held low.
The Second and Fourth DS1 Outputs from the M12 Demultiplexers are Inverted if these Bits are 1.
Each DS1/E1 Output Selector Number, x, can be
Expressed as Either 4y – 3, 4y – 2, 4y – 1, or 4y, where y
Ranges From 1 to 7. For a given y, the 4 selectors in the
group output DS1 signals if M13_OUT_TYPEy = 1, or E1 signals if M13_OUT_TYPEy = 0.
The Transmit DS1/E1 Signals are Retimed by the Rising
Edge of the Associated Clocks if these Bits are Set High;
Otherwise, the Data is Retimed By the Falling Edge.
0x10081
0x10083
0x10085
5
0x10087
4
3:0
M13_DEMUXCH2_
4_INV[1—7]
M13_OUT_
TYPE[1—7]
M13_TDS1_
EDGE[28:1]
Reset
Default
0x00
00
1
1
0xF
Table 273. M13_M12_DEMUX_CONTROL2_R[1—7], M12 DeMUX Control 2 Registers [1—7] (R/W)
Address
Bit
0x1007C 15:4
0x1007E 3:0
0x10080
Name
—
M13_DS1_OUT_
AIS[28:1]
Function
Reset
Default
Reserved.
0x000
A logic 1 of these bits will cause the corresponding DS1 output
0x0
all ones AIS.
0x10082
0x10084
0x10086
0x10088
Table 274. M13_M12_DEMUX_CONTROL3, DS2 M12 DeMUX Control 3 (R/W)
Address
Bit
0x10089 15:2
1
0
Agere Systems Inc.
Name
Function
—
M13_DS2_MODE
Reserved.
This Bit Controls the DS2 Framing Algorithm In the DS1
Mode Only. Out of frame is declared if the F bits contain two
errors in 4 bits if M13_DS2_MODE = 0, or at least 1 F-bit error
in four consecutive M-subframe pairs if M13_DS2_MODE = 1.
This Bit Controls Frame Error Counting for the M12
Demultiplexers in the E1 Mode Only. If this bit is 0, the frame
error counters increment for each frame alignment signal bit
error. Otherwise, the counter increments once for each frame
alignment signal that contains at least 1 bit error.
M13_DS2_FERR_
MODE
Reset
Default
0x0000
0
0
219
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
11 M13/M23 MUX/DeMUX Registers (continued)
Table 275. M13_DMDS2_EDGE_R, DS2 Edge for M12 DeMUX (R/W)
Address
Bit
0x1008A 15:7
6:0
Name
—
M13_DMDS2_
EDGE[7:1]
Function
Reset
Default
Reserved.
0x000
A logic 1 of these bits means that the input DS2 signals to M12
0x00
demultiplexers are retimed by the rising edge of the associated
clocks; a logic 0 means that the data is retimed by the falling
edge.
Table 276. M13_DS3_CONTROL1, DS3 Control 1 (R/W)
Address
Reset
Default
0x10092 15:8
—
Reserved.
0x00
7
M13_DS3_FINV
For testing purposes, this bit is high to allow the F bit to be
0
generated with errors.
6
M13_DS3_MINV
For testing purposes, this bit is high to allow the M bit to
0
be generated with errors.
5
M13_DS3_PINV
For testing purposes, this bit is high to allow the P Bit to
0
be generated with errors.
4
M13_DS3_FORCE_AIS This bit causes the M13 to generate DS3 AIS in place of
0
the transmit DS3 signal from the M23 multiplexer.
3
M13_DS3_FORCE_IDLE This bit causes the M13 to generate DS3 idle (unless
0
M13_DS3_FORCE_AIS (Table 276) is also set) in place
of the transmit DS3 signal from the M23 multiplexer.
2
M13_TDS3_FORCE_ALL1 This bit causes the M13 to generate unframed all ones
0
DS3 output.
0
1
M13_M23CLK_MODE
If this bit is 1, DS2 clocks associated with DS2 signals
being MUXed into DS3 are outputs from the block; otherwise, they are inputs to the block.
0
—
Reserved.
0
220
Bit
Name
Function
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
11 M13/M23 MUX/DeMUX Registers (continued)
Table 277. M13_DS3_CONTROL2, DS3 Control 2 (R/W)
Address
Bit
0x10093 15:7
6
5
4
3
2
1
0
Name
Function
—
M23_STUFF_MODE
Reserved.
A Logic 0 on this Bit Will Cause the M23 Stuffing to be
Determined by the External Stuff Request; Otherwise,
Fixed Stuffing is Used.
M13_NSMI_MODE A Logic 1 of this Bit will Enable M13 to Receive and Output Ds3 Payload Through a Serial Link.
M13_DS3_P_BER
The P Bits and, in CBP Mode, the CP Bits in the DS3
Frame Immediately Following Each 0 to 1 Transition of the
Input SMPR_BER_INSERT (Table 65), are Inverted if this
Bit is Set to 1.
M13_CBIT2_ACT
This Bit is Used Only in the C-Bit Parity Mode. In this
mode, if it is 0, the second c-bit of each ds3 frame, c2, Is Set
To 1. Otherwise, the transmit value of C2 is input through pin
TCBDATA (E12).
M13_UNUSED_ACT This Bit is Used Only in the C-Bit Parity Mode. In this
mode, if it is 0, the unused C bits of each DS3 frame (the
fourth through sixth and the sixteenth through twenty-first) are
set to 1. Otherwise, the transmit values of these bits are input
through pin TCBDATA (E12).
M13_DS3_RAI_SEND The Transmitted DS3 X Bits are Set to the Inverse of this
Bit During Normal Transmission.
M13_FEBE_ERR
This Bit is Used to Force Errors in the Transmitted DS3
FEBE Indication. If the Bit is Set, all DS3 Frames are
Transmitted with the FEBE Bits Set to 000.
Reset
Default
0x000
0
0
0
0
0
0
0
Table 278. M13_TFEAC_CONTROL, Tx FEAC Control (R/W)
Address Bit
0x10094 15:8
7:6
Name
Function
—
Reserved.
M13_TFEAC_CTL[1:0] The User Can Provision the M13 to Transmit Continuous
Ones by Setting M13_TFEAC_CTL to 00.
5:0 M13_TFEAC_CODE[5:0] FEAC Signals. TFEAC signals are transmitted continuously
by setting M13_TFEAC_CTL to 01, and M13_TFEAC_CODE
= x5x4x3x2x1x0, where x5x4x3x2x1x0 Is the appropriate
value for the alarm or status codeword.
In order to activate a loopback, the user may set
M13_TFEAC_CTL = 11, And M13_TFEAC_CODE =
x5x4x3x2x1x0, where x5x4x3x2x1x0 Is the Appropriate value
for the loopback codeword. The M13 will then transmit 10 repetitions of the activate codeword, 0 000111 0 11111111, followed by 10 repetitions of 0 x5x4x3x2x1x0 0 11111111. After
transmitting this 40 octet sequence, it will set
M13_TFEAC_DONE (Table 217) to 1.
In order to deactivate a loopback, the user may set
M13_TFEAC_CTL = 10, and M13_TFEAC_CODE =
x5x4x3x2x1x0, where x5x4x3x2x1x0 is the appropriate value
for the loopback codeword. The M13 will then transmit 10 repetitions of the deactivate codeword, 0 011100 0 11111111, followed by 10 repetitions of 0 x5x4x3x2x1x0 0 11111111. After
transmitting this 40 octet sequence, it will set
M13_TFEAC_DONE to 1.
Agere Systems Inc.
Reset
Default
0x00
0x0
0x00
221
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
11 M13/M23 MUX/DeMUX Registers (continued)
Table 279. M13_THDLC_CONTROL1, Tx HDLC Control 1 (R/W)
Address
Bit
Name
Function
Reset
Default
0x10095 15:6
—
Reserved.
0x000
0
5
M13_TDL_BUF1_END If this Bit is 0, all Bytes from HDLC Buffer 1 and at Least
One Byte from HDLC Buffer 0 are Transmitted. If it is 1,
bytes from buffer 1 are transmitted sequentially up to and
including the byte set by M13_TDL_BYTE_END[5:0]
(Table 280).
4
M13_TDL_BUF0_END If this Bit is 0, all Bytes from HDLC Buffer 0 and at Least
0
One Byte from HDLC Buffer 1 are Transmitted. If it is 1,
bytes from buffer 0 are transmitted sequentially up to and
including the byte set by M13_TDL_BYTE_END[5:0].
3
M13_TDL_ACT
If the Data Link is not Used, the User Should set
0
M13_TDL_ACT to 0, Which Causes all Ones to be Transmitted. Otherwise, this bit should be set to 1.
2
M13_TDL_NTRNL
If M13_TDL_NTRNL = 0, the Data Transmitted on the
0
Data Link Comes Directly from the M13 Input Pin TDLDATA (E8); Otherwise (M13_TDL_NTRNL = 1), the Data
Link is Controlled by the Internal HDLC Transmitter. This
bit is valid only when M13_TDL_ACT = 1 (Table 279).
0
1
M13_TDL_NTRNL_ACT Once M13_TDL_NTRNL_ACT is Set to 1, the HDLC
Transmitter Begins Transmitting the First Byte of the
First Data Buffer Following the Completion of the Next
Flag Byte. The user may abort the transmission of an HDLC
frame by clearing M13_TDL_NTRNL_ACT to 0 prior to completing transmission of the last byte from the data buffers. If
so, the HDLC controller will stop transmission from the buffers and send an abort byte (01111111). The abort byte will
then be followed by flag bytes until M13_TDL_NTRNL_ACT
is again set to 1, starting transmission of a new frame.
1
0
M13_TDL_FCS
If M13_TDL_FCS = 1, the HDLC Controller Appends the
Two-Byte ITU-T FCS with the Necessary Zero Stuffing
Before Sending the Closing Flag; Otherwise, no FCS
Bytes will be Transmitted.
Table 280. M13_THDLC_CONTROL2, Tx HDLC Control 2 (R/W)
Address
Bit
0x10096 15:6
5:0
Name
—
M13_TDL_BYTE_
END[5:0]
Function
Reserved.
These Bits Define the Position of the Last Byte to be
Transmitted from the Buffer.
Reset
Default
0x000
0x00
Table 281. M13_DS2_LB_REQ_R, DS2 Loopback Request (R/W)
Address
Bit
0x10097 15:7
6:0
222
Name
Function
—
M13_DS2_LB_
REQ[7:1]
Reserved.
If M13_DS2_LB_REQy = 1, the Third C Bit in the yth DS3
M-Subframe is Transmitted as the Inverse of the First Two
C Bits (Which Indicates a Loopback Request for DS2
Channel y).
Reset
Default
0x000
0x00
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
11 M13/M23 MUX/DeMUX Registers (continued)
Table 282. M13_SEL_DS2_LB_R, Select DS2 Loopback (R/W)
Address
Bit
0x10098 15:7
6:0
Name
—
M13_SEL_DS2_
LB[7:1]
Function
Reset
Default
Reserved.
0x000
If M13_SEL_DS2_LBy = 1, the DS2 Signal from Time Slot y 0x00
in the Received DS3 Signal is Looped Back into Time
Slot y of the Transmitted DS3 Signal.
Table 283. M13_RDS2_EDGE_R[1—2], Rx DS2 Edge Registers [1—2](R/W)
Address
Bit
Name
Function
0x10099 15:7
6:0
—
M13_RDS2_
EDGE[7:1]
0x1009A 15:7
6:0
—
M13_DS2ALCO_
RTM_EDGE[7:1]
Reserved.
A logic 1 of these Bits Means that the Received DS2 Signals are Retimed by the Rising Edge of the Associated
Clocks. A logic 0 means that the data is retimed by the falling
edge. When used in the demand clocking mode of the M23
mapping, M13_RDS2_EDGE[7:1] = 1 should be set if the
delay from the output clock to the incoming data (the maximum
should be less than 8 STS-1 clock cycles) is less than 4 STS-1
clock cycles; otherwise, M13_RDS2_EDGE[7:1] = 0 should be
used.
Reserved.
In the Demand Clocking Mode of the M23 Mapping, this
Register Provides an Extra Clock Edge Selection Capability, in Addition to M13_RDS2_EDGE[7:1], for Retiming
Input DS2 Data. It should normally be set to logic 1 (default).
A logic 0 is suggested only to be used with
M13_RDS2_EDGE[7:1] = 0 when necessary.
Reset
Default
0x000
0x00
0x000
0x7F
Table 284. M13_DS2_OUT_IDLE_R, DS2 Output Idle (R/W)
Address
Bit
0x1009E 15:7
6:0
Name
—
M13_DS2_OUT_
IDLE[7:1]
Function
Reserved.
If M13_DS2_OUT_IDLEy = 1, the Output from DS2 Output
Selection Block y is Held Low.
Reset
Default
0x000
0x00
Table 285. M13_DS2_OUT_AIS_R, DS2 Output Alarm Indication Signal (R/W)
Address
Bit
0x1009F 15:7
6:0
Agere Systems Inc.
Name
Function
—
M13_DS2_OUT_
AIS[7:1]
Reserved.
If M13_DS2_OUT_IDLEy = 0 (Table 284), a Logic 1 of this
Bit Causes DS2 AIS to be Output From the DS2 Output
Selector y; Otherwise, the DS2 Signal From Time Slot y in
the Received DS3 Signal will be Output.
Reset
Default
0x000
0x00
223
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
11 M13/M23 MUX/DeMUX Registers (continued)
Table 286. M13_TDS2_EDGE_R, Tx DS2 Edge (R/W)
Address
Bit
0x100A0 15:7
6:0
Name
—
Function
Reserved.
M13_TDS2_EDGE[7:1] A logic 1 of these Bits Means that the Transmit DS2 Signals are Retimed by the Rising Edge of the Associated
Clocks. A logic 0 means that the data is retimed by the falling
edge.
Reset
Default
000000
000
0x7F
Table 287. M13_RDL_CONTROL, RDL Control (R/W)
Address
Bit
0x100A1 15:5
4:3
Name
—
M13_RDL_FILL[1:0]
2
M13_RDL_FCS
1
M13_DS3_MODE
0
M13_RDS3_EDGE
Function
Reserved.
00 = sets the receive HDLC FIFO fill level to 16 bytes.
01 = sets the receive HDLC FIFO fill level to 32 bytes.
10 = sets the receive HDLC FIFO fill level to 64 bytes.
11 = sets the receive HDLC FIFO fill level to 96 bytes.
The M13_RDL_FIFO_AF (Table 225) bit is set if the buffer
reaches the fill level.
If M13_RDL_FCS = 1, the FCS Bytes will be Checked at
HDLC Receiver. Otherwise, the FCS is not checked and the
last 2 bytes of the HDLC frame are written into the FIFO.
This Bit Controls the DS3 Framing Algorithm. Out-of-frame is
declared if the F bits contain 3 errors in 16 bits if
M13_DS3_MODE = 0, or at least 1 F-bit error in four consecutive M-subframes if M13_DS3_MODE = 1.
A logic 1 of this Bit Means that the Received DS3 Data is
Retimed by the Rising Edge of the Associated Clock. A
logic 0 means the data is retimed by the falling edge.
Reset
Default
0x000
00
1
0
0
Table 288. M13_PM_CNT_ACT_R, Performance Counter (RO)
Address
Bit
0x100A5 15:1
0
Name
—
M13_PM_CNT_ACT
Function
Reserved.
This Bit Returns a 0 When Read if all Performance
Counter Values are 0; Otherwise, it’s Set to 1.
Reset
Default
0x0000
0
Table 289. M13_DS3_FERR_CNT_R[1—2], DS3 F-Bit Error Registers (RO)
Address
Name
Function
0x100A6 15:4
0x100A7 15:8
0x100A6 3:0
—
—
M13_DS3_FERR_CNT[11:8]
0x100A7
M13_DS3_FERR_CNT[7:0]
Reserved.
Reserved.
This Register Holds the Results from a Counter
that Increments each Time an Error is Detected in
Either a DS3 F Bit, or M Bit.
224
Bit
7:0
Reset
Default
0x000
0x00
0x0
0x00
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
11 M13/M23 MUX/DeMUX Registers (continued)
Table 290. M13_DS3_FEBE_CNT_R[1—2], DS3 Far-End Block Error Registers (RO)
Address
Bit
Name
Function
0x100A8 15:6
0x100A9 15:8
0x100A8 5:0
—
—
M13_DS3_FEBE_CNT[13:8]
0x100A9
M13_DS3_FEBE_CNT[7:0]
Reserved.
Reserved.
This Register Holds the Results from a Counter
that Accumulates FEBE Error Indications (1 Error
Indication for each DS3 Frame with at Least One
FEBE Bit Equal to Zero).
7:0
Reset
Default
0x000
0x00
0x00
0x00
Table 291. M13_DS3_CPERR_CNT_R[1—2], DS3 C-Bit Parity Error Registers (RO)
Address
Bit
Name
Function
0x100AA 15:6
—
Reserved.
0x100AB 15:8
—
Reserved.
0x100AA 5:0 M13_DS3_CPERR_CNT[13:8] This Register is Used Only in the C-Bit Parity
0x100AB 7:0 M13_DS3_CPERR_CNT[7:0] Mode. It indicates the number of frames with two or
more C-bit parity errors.
Reset
Default
0x000
0x00
0x00
0x00
Table 292. M13_DS3_PERR_CNT_R[1—2], DS3 P-Bit Error Registers (RO)
Address
Bit
Name
0x100AC 15:6
0x100AD 15:8
0x100AC 5:0
—
—
M13_DS3_PERR_CNT[13:8]
0x100AD
M13_DS3_PERR_CNT[7:0]
7:0
Function
Reserved.
Reserved.
This Register Indicates the Number of Frames
with at Least One P Bit that Disagrees with the
Parity of the Previous Frame.
Reset
Default
0x000
0x00
0x00
0x00
Table 293. M13_DS2_PERR_CNT[7—1]_R[1—2], P-Bit Error Counter Status Registers (RO)
Address
Bit
0x100B2 15:5
Name
—
Function
Reserved.
Reset
Default
0x000
0x100B3 15:8
0x100B4 15:5
0x100B5 15:8
0x100B6 15:5
0x100B7 15:8
0x100B8 15:5
0x100B9 15:8
0x100BA 15:5
0x100BB 15:8
0x100BC 15:5
0x100BD 15:8
0x100BE 15:5
0x100BF 15:8
Agere Systems Inc.
225
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
11 M13/M23 MUX/DeMUX Registers (continued)
Table 293. M13_DS2_PERR_CNT[7—1]_R[1—2], P-Bit Error Counter Status Registers (RO) (continued)
Address
Bit
Name
Function
Reset
Default
0x00
0x100B2
4:0
M13_DS2_PERR_CNT7[12:8]
0x100B3
0x100B4
7:0
4:0
M13_DS2_PERR_CNT7[7:0]
M13_DS2_PERR_CNT6[12:8]
0x100B5
0x100B6
7:0
4:0
M13_DS2_PERR_CNT6[7:0]
M13_DS2_PERR_CNT5[12:8]
These Registers are Used by M12 Demultiplexers that Operate in the G.747 (E1)
mode. They indicate the number of received
DS2 frames with P-bit errors.
0x100B7
0x100B8
7:0
4:0
M13_DS2_PERR_CNT5[7:0]
M13_DS2_PERR_CNT4[12:8]
0x00
0x00
0x100B9
0x100BA
7:0
4:0
M13_DS2_PERR_CNT4[7:0]
M13_DS2_PERR_CNT3[12:8]
0x00
0x00
0x100BB
0x100BC
7:0
4:0
M13_DS2_PERR_CNT3[7:0]
M13_DS2_PERR_CNT2[12:8]
0x00
0x00
0x100BD
0x100BE
7:0
4:0
M13_DS2_PERR_CNT2[7:0]
M13_DS2_PERR_CNT1[12:8]
0x00
0x00
0x100BF
7:0
M13_DS2_PERR_CNT1[7:0]
0x00
0x00
0x00
0x00
0x00
Table 294. M13_DS2_FERR_CNT[7—1]_R, F-Bit Error Counter Status Registers (RO)
Address
Bit
0x100C6 15:8
—
0x100CC
0x100C6 7:0
—
0x100CC
Name
—
Function
Reset
Default
0x00
Reserved.
M13_DS2_FERR_CNT[7—1][7:0] These Registers Hold the Results From DS2
Frame Alignment Signal Error Counters. In the
DS1 mode, these counters increment each time
an error is detected in either an F bit or M bit. In
the E1 mode, the counters increment either for
each frame alignment signal bit error
(if M13_DS2_FERR_MODE (Table 274) is 0), or
once for each frame alignment signal that contains at least one bit error
(if M13_DS2_FERR_MODE = 1).
0x00
Table 295. M13_BPV_CNT_R[1—3], Bipolar Violation Counter Status Registers (RO)
Address
Bit
0x100CD 15:8
—
0x100CF
0x100CD 7:0
—
0x100CF
226
Name
—
M13_BPV_CNT[23:0]
Function
Reset
Default
0x00
This Register is Only Used In the DS3 Bipolar
Mode. It holds the results from a counter that increments each time a received B3ZS bipolar coding
violation is detected.
0x00
Reserved.
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
11 M13/M23 MUX/DeMUX Registers (continued)
Table 296. M13_EXZ_CNT_R[1—3], Bipolar Violation Counter Status Registers (RO)
Address
Bit
Name
Function
0x100D0 15:8
—
Reserved.
—
0x100D2
0x100D0 7:0 M13_EXZ_CNT[23:0] This Register is only Used in the DS3 Bipolar Mode. It
—
holds the results from a counter that increments each time an
0x100D2
excessive zeros string is detected.
Reset
Default
0x00
0x00
Table 297. M13_TDL_BUFFER_R, Tx Data-Link Buffer Control (R/W)
Address
Bit
0x100FF 15:1
0
Name
Function
—
Reserved.
M13_TDL_BUFFER If this Bit is 0, Data Written to Registers
M13_TDL_0DATA_R[0—63] Address 0x10100—0x1013F
(Table 297) is Stored in the Path Maintenance Data-Link
Buffer 0. Otherwise, the data is written to buffer 1.
Reset
Default
0x0000
0
Table 298. M13_TDL_0DATA_R[0—63], Tx Data for Path Maintenance Data-Link Buffer 0 Registers
(64 Bytes x 8 Bits) (R/W)
Address
Bit
0x10100 15:8
—
0x1013F
0x10100 7:0
—
0x1013F
Name
—
M13_TDL_
0DATA[0—63][7:0]
Function
Reset
Default
0x00
This 64-Byte Buffer for the Transmit Path Maintenance
Data Link is Accessible when M13_TDL_BUFFER = 0
(Table 297). On reset, reading from these registers returns an
undetermined value.
0xXX
Reserved.
Table 299. M13_TDL_1DATA_R[0—63], Tx Data for Path Maintenance Data-Link Buffer 1 Registers
(64 Bytes x 8 Bits) (R/W)
Address
Bit
0x10100 15:8
—
0x1013F
0x10100 7:0
—
0x1013F
Agere Systems Inc.
Name
—
M13_TDL_
1DATA[0—63][7:0]
Function
Reserved.
This 64-Byte Buffer for the Transmit Path Maintenance
Data Link is Accessible when M13_TDL_BUFFER = 1. On
reset, reading from these registers returns an undetermined
value.
Reset
Default
0x00
0xXX
227
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
11 M13/M23 MUX/DeMUX Registers (continued)
11.2 M13 Register Map
Table 300. Register Address Map
Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.
Addr
Symbol
Bits [15:8]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Block-level Status—RO
0x10000
M13_ID_R
0x10001
M13_VERSION_R
M13_ID[7:0]
0x10002
0x10003
—
0x10004
M13_DELTA1
M13_RDL_IDLED
M13_DS3_LOFD
M13_DS3_OOFD
M13_DS3_C1_DETD
M13_DS3_RAI_DETD
0x10005
M13_DELTA2
M13_DS1_LB_SD
M13_DS1_AIS_SD
M13_DS1_LOC_SD
M13_RDS3_SEFD
M13_RDS3_ALL1_DETD
M13_RDS3_LOSD
M13_TDS3_LOCD
M13_RDS3_LOCD
0x10006
M13_DELTA3
M13_DS2_RSV_SD
M13_DS2_LB_SD
M13_DS2_RAI_SD
M13_DS2_AIS_SD
M13_DS2_LOF_SD
M13_DS2_OOF_SD
M13_XC_DS2_AIS_SD
M13_XC_DS2_LOC_SD
0x10007
M13_DELTA4
M13_TFEAC_DONE
M13_TDL_DONE
M13_TDL_BUF1_INT
M13_TDL_BUF0_INT
M13_RDL_FIFO_AFD
M13_RDL_FRM_INT
0x10008
M13_DELTA5
0x10009
—
0x1000A
M13_MASK1
M13_RDL_IDLEM
M13_DS3_LOFM
M13_DS3_OOFM
M13_DS3_C1_DETM
M13_DS3_RAI_DETM
0x1000B
M13_MASK2
M13_DS1_LB_SM
M13_DS1_AIS_SM
M13_DS1_LOC_SM
M13_RDS3_SEFM
M13_RDS3_ALL1_DETM
M13_RDS3_LOSM
M13_TDS3_LOCM
M13_RDS3_LOCM
0x1000C
M13_MASK3
M13_DS2_RSV_SM
M13_DS2_LB_SM
M13_DS2_RAI_SM
M13_DS2_AIS_SM
M13_DS2_LOF_SM
M13_DS2_OOF_SM
M13_XC_DS2_AIS_SM
M13_XC_DS2_LOC_SM
0x1000D
M13_MASK4
M13_TFEAC_DONEM
M13_TDL_DONEM
M13_RDL_FIFO_AFM
M13_RDL_FRM_INTM
M13_RFEAC_ALM_INTM
M13_RFEAC_LB_INTM
0x1000E
M13_MASK5
M13_DS2DMX_LOC_SM
M13_RDL_FIFO_UFM
M13_VERSION[2:0]
DS3 Deltas, Summary Deltas, FEAC, and DL Interrupts—RO
M13_DS3_AISPAT_DETD M13_DS3_IDLEPAT_DETD M13_DS3_CBZ_DETD
M13_RFEAC_ALM_INT
M13_RFEAC_LB_INT
M13_DS2DMX_LOC_SD
M13_RDL_FIFO_UFD
Interrupt Masks—R/W
M13_TDL_BUF1_INTM M13_TDL_BUF0_INTM
M13_DS3_AISPAT_DETM M13_DS3_IDLEPAT_DETM M13_DS3_CBZ_DETM
DS3 Status—RO
0x1000F M13_DS3_STATUS1
0x10010 M13_DS3_STATUS2
Lucent Technologies Inc.
M13_RDL_IDLE
M13_DS3_LOF
M13_DS3_OOF
M13_DS3_C1_DET
M13_DS3_RAI_DET
M13_DS3_AISPAT_DET
M13_DS3_IDLEPAT_DET
M13_DS3_CBZ_DET
M13_RDL_FIFO_UF
M13_RDL_FIFO_AF
M13_RDS3_SEF
M13_RDS3_ALL1_DET
M13_RDS3_LOS
M13_TDS3_LOC
M13_RDS3_LOC
228
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
11 M13/M23 MUX/DeMUX Registers (continued)
Table 300. Register Address Map (continued)
Addr
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Individual DS2 and DS1 Deltas—RO
0x10011
M13_XC_DS2_LOCD_R
0x10012 M13_XC_DS2_AIS_DETD_R
M13_XC_DS2_LOCD[7:1]
M13_XC_DS2_AIS_DETD[7:1]
0x10013
M13_DS2_OOFD_R
0x10014
M13_DS2_LOFD_R
M13_DS2_OOFD[7:1]
M13_DS2_LOFD[7:1]
0x10015
M13_DS2_AIS_DETD_R
M13_DS2_AIS_DETD[7:1]
0x10016
M13_DS2_RAI_DETD_R
M13_DS2_RAI_DETD[7:1]
0x10017
M13_DS2_LB_DETD_R
M13_DS2_LB_DETD[7:1]
0x10018
M13_DS2_RSV_RCVD_R
M13_DS2_RSV_RCVD[7:1]
0x10019
M13_DS2DMX_LOCD_R
M13_DS2DMX_LOCD[7:1]
0x1001A
—
—
0x1001D
0x1001E
M13_DS1_LOCD_R1
0x1001F
M13_DS1_LOCD_R2
M13_DS1_LOCD[24:17]
M13_DS1_LOCD[28:25]
0x10020
M13_DS1_LOCD_R3
M13_DS1_LOCD[16:9]
0x10021
M13_DS1_LOCD_R4
M13_DS1_LOCD[8:1]
0x10022
M13_DS1_AIS_DETD_R1
0x10023
M13_DS1_AIS_DETD_R2
M13_DS1_AIS_DETD[24:17]
M13_DS1_AIS_DETD[28:25]
0x10024
M13_DS1_AIS_DETD_R3
M13_DS1_AIS_DETD[16:9]
0x10025
M13_DS1_AIS_DETD_R4
M13_DS1_AIS_DETD[8:1]
0x10026
M13_DS1_LB_DETD_R1
229
M13_DS1_LB_DETD[28:25]
Lucent Technologies Inc.
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
11 M13/M23 MUX/DeMUX Registers (continued)
Table 300. Register Address Map (continued)
Addr
Symbol
0x10027
M13_DS1_LB_DETD_R2
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
M13_DS1_LB_DETD[24:17]
Bit 4
Bit 3
0x10028
M13_DS1_LB_DETD_R3
M13_DS1_LB_DETD[16:9]
0x10029
M13_DS1_LB_DETD_R4
M13_DS1_LB_DETD[8:1]
0x1002A
—
—
Bit 2
Bit 1
Bit 0
0x1002E
DS2 and DS1 Status—RO
0x1002F
M13_XC_DS2_LOC_R
0x10030 M13_XC_DS2_AIS_DET_R
M13_XC_DS2_LOC[7:1]
M13_XC_DS2_AIS_DET[7:1]
0x10031
M13_DS2_OOF_R
0x10032
M13_DS2_LOF_R
M13_DS2_OOF[7:1]
M13_DS2_LOF[7:1]
0x10033
M13_DS2_AIS_DET_R
M13_DS2_AIS_DET[7:1]
0x10034
M13_DS2_RAI_DET_R
M13_DS2_RAI_DET[7:1]
0x10035
M13_DS2_LB_DET_R
M13_DS2_LB_DET[7:1]
0x10036
M13_DS2_RSV_RCV_R
M13_DS2_RSV_RCV[7:1]
0x10037
M13_DS2DMX_LOC_R
M13_DS2DMX_LOC[7:1]
0x10038
—
—
0x1003B
0x1003C
M13_DS1_LOC_R1
0x1003D
M13_DS1_LOC_R2
M13_DS1_LOC[24:17]
0x1003E
M13_DS1_LOC_R3
M13_DS1_LOC[16:9]
0x1003F
M13_DS1_LOC_R4
M13_DS1_LOC[8:1]
0x10040
M13_DS1_AIS_DET_R1
Lucent Technologies Inc.
M13_DS1_LOC[28:25]
M13_DS1_AIS_DET[28:25]
230
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
11 M13/M23 MUX/DeMUX Registers (continued)
Table 300. Register Address Map (continued)
Addr
Symbol
0x10041
M13_DS1_AIS_DET_R2
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
M13_DS1_AIS_DET[24:17]
Bit 4
Bit 3
0x10042
M13_DS1_AIS_DET_R3
M13_DS1_AIS_DET[16:9]
0x10043
M13_DS1_LB_DET_R4
M13_DS1_AIS_DET[8:1]
0x10044
M13_DS1_LB_DET_R1
0x10045
M13_DS1_LB_DET_R2
M13_DS1_LB_DET[24:17]
Bit 2
Bit 1
Bit 0
M13_DS1_LB_DET[28:25]
0x10046
M13_DS1_LB_DET_R3
M13_DS1_LB_DET[16:9]
0x10047
M13_DS1_LB_DET_R4
M13_DS1_LB_DET[8:1]
0x10048
—
FEAC Loopback Individual Deltas—RO
0x10049 M13_DS1_FEAC_LB_DETD_R1
M13_DS3_FLB_DETD
M13_DS1_FEAC_LB_DETD[28:25]
0x1004A M13_DS1_FEAC_LB_DETD_R2
M13_DS1_FEAC_LB_DETD[24:17]
0x1004B M13_DS1_FEAC_LB_DETD_R3
M13_DS1_FEAC_LB_DETD[16:9]
0x1004C M13_DS1_FEAC_LB_DETD_R4
M13_DS1_FEAC_LB_DETD[8:1]
FEAC
Status,
RDL Status, and
RDL
FIFO—
RO
0x1004D
M13_DS1_FEAC_LB_DET_R1
0x1004E
M13_DS1_FEAC_LB_DET_R2
M13_DS1_FEAC_LB_DET[24:17]
0x1004F
M13_DS1_FEAC_LB_DET_R3
M13_DS1_FEAC_LB_DET[16:9]
0x10050
M13_DS1_FEAC_LB_DET_R4
M13_DS1_FEAC_LB_DET[8:1]
0x10051
M13_RFEAC_CODE_R
231
M13_DS3_FLB_DET
M13_DS1_FEAC_LB_DET[28:25]
M13_RFEAC_CODE[5:0]
Lucent Technologies Inc.
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
11 M13/M23 MUX/DeMUX Registers (continued)
Table 300. Register Address Map (continued)
Addr
Symbol
0x10052
M13_RDL_STATUS
0x10053
M13_RDL_DATA_R
0x10054
M13_RDL_FRAME_SIZE_R
0x10055
M13_RHDLC_STATUS_R
0x10056
—
—
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
M13_RDL_FLAG M13_RDL_ABOR M13_RDL_NOT_ M13_RDL_OVFL M13_RDL_FCS_
T
BYTE
ERR
M13_RDL_DATA[7:0]
M13_RDL_FRAME_SIZE[6:0]
M13_RHDLC_STATUS[7:0]
0x10058
One Shot Signals—R/Wl
0x10059
M13_DS2_FORCE_OOF_R
0x1005A
M13_CONTROL1
0x1005B
—
0x1005C
M13_CONTROL2
M13_DS2_FORCE_OOF[7:1]
M13_RDL_FRM_ M13_DS3_FORC M13_BIPOL_ER
CLR
E_OOF
R
Block-level Controls—R/W
0x1005D
M13_CONTROL3
0x1005E
M13_SP_OFFSET_R
0x1005F
M13_SP_D_OFFSET_R
M13_BPV_IN M13_LOOP_TIME M13_LOOP_T_T M13_LOOP_R_T M13_AUTO_AIS_ M13_AUTO_AIS_ M13_AUTO_FLB
O_R
O_T
LOF
OOF
M13_AUTO_LB
M13_M23_CBP
M13_BIPOLAR
M13_SP__OFFSET[7:0]
M13_SP_D_OFFSET[7:0]
M12 MUX’s Control—R/W
0x10060 M13_M12_MUX_CONTROL1_R1
0x10061 M13_M12_MUX_CONTROL2_R1
0x10062 M13_M12_MUX_CONTROL1_R2
0x10063 M13_M12_MUX_CONTROL2_R2
0x10064 M13_M12_MUX_CONTROL1_R3
Lucent Technologies Inc.
M13_M12_MODE1[1:0]
M13_MUXCH2_4
_INV1
M13_DS1_E1N1
M13_DS1_LB_REQ[4:1]
M13_DS1_E1N2
M13_DS1_LB_REQ[8:5]
M13_DS1_E1N3
M13_DS1_LB_REQ[12:9]
M13_SEL_DS1_LB[4:1]
M13_M12_MODE2[1:0]
M13_MUXCH2_4
_INV2
M13_RDS1_EDGE[4:1]
M13_SEL_DS1_LB[8:5]
M13_M12_MODE3[1:0]
M13_MUXCH2_4
_INV3
M13_RDS1_EDGE[8:5]
232
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
11 M13/M23 MUX/DeMUX Registers (continued)
Table 300. Register Address Map (continued)
Addr
Symbol
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
0x10065 M13_M12_MUX_CONTROL2_R3
0x10066 M13_M12_MUX_CONTROL1_R4
0x10067 M13_M12_MUX_CONTROL2_R4
0x10068 M13_M12_MUX_CONTROL1_R5
0x10069 M13_M12_MUX_CONTROL2_R5
0x1006A M13_M12_MUX_CONTROL1_R6
0x1006B M13_M12_MUX_CONTROL2_R6
0x1006C M13_M12_MUX_CONTROL1_R7
0x1006D M13_M12_MUX_CONTROL2_R7
Bit 4
Bit 3
M13_SEL_DS1_LB[12:9]
M13_M12_MODE4[1:0]
M13_MUXCH2_4_INV4
M13_MUXCH2_4_INV5
M13_DS1_LB_REQ[16:13]
M13_DS1_E1N5
M13_DS1_LB_REQ[20:17]
M13_MUXCH2_4_INV6
M13_DS1_E1N6
M13_DS1_LB_REQ[24:21]
M13_DS1_E1N7
M13_DS1_LB_REQ[28:25]
M13_RDS1_EDGE[20:17]
M13_SEL_DS1_LB[24:21]
M13_M12_MODE7[1:0]
M13_MUXCH2_4_INV7
M13_RDS1_EDGE[24:21]
M13_SEL_DS1_LB[28:25]
M13_RDS1_EDGE[28:25]
0x1006E
M13_DS2_RAI_SEND_R
M13_DS2_RAI_SEND[7:1]
0x1006F
M13_DS2_RSV_SEND_R
M13_DS2_RSV_SEND[7:1]
0x10070
M13_DS2_MPINV_R
M13_DS2_MPINV[7:1]
0x10071
M13_DS2_FINV_R
M13_DS2_FINV[7:1]
0x10072
M13_DS2_P_BER_R
M13_DS2_P_BER[7:1]
0x10073
M13_DS2M12_EDGE_R
M13_DS2M12_EDGE[7:1]
0x10074
M13_DS2_FORCE_AIS_R
M13_DS2_FORCE_AIS[7:1]
0x10075
—
0x1007A
—
233
Bit 0
M13_RDS1_EDGE[16:13]
M13_SEL_DS1_LB[20:17]
M13_M12_MODE6[1:0]
Bit 1
M13_DS1_E1N4
M13_SEL_DS1_LB[16:13]
M13_M12_MODE5[1:0]
Bit 2
M13_RDS1_EDGE[12:9]
Lucent Technologies Inc.
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
11 M13/M23 MUX/DeMUX Registers (continued)
Table 300. Register Address Map (continued)
Addr
Symbol
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
M12 DeMUX’s Control—R/W
0x1007B M13_M12_DEMUX_CONTROL1_R1
M13_M12DMX_MODE1[1:0] M13_DEMUXCH2_4_ M13_OUT_TYPE1
INV1
M13_DS1_OUT_AIS[4:1]
0x1007C M13_M12_DEMUX_CONTROL2_R1
0x1007D M13_M12_DEMUX_CONTROL1_R2
M13_M12DMX_MODE2[1:0] M13_DEMUXCH2_4_ M13_OUT_TYPE2
INV2
0x1007E M13_M12_DEMUX_CONTROL2_R2
0x1007F M13_M12_DEMUX_CONTROL1_R3
0x10088 M13_M12_DEMUX_CONTROL2_R7
0x10089
M13_M12_DEMUX_CONTROL3
Lucent Technologies Inc.
M13_TDS1_EDGE[20:17]
M13_DS1_OUT_AIS[20:17]
M13_M12DMX_MODE6[1:0] M13_DEMUXCH2_4_ M13_OUT_TYPE6
INV6
0x10086 M13_M12_DEMUX_CONTROL2_R6
0x10087 M13_M12_DEMUX_CONTROL1_R7
M13_TDS1_EDGE[16:13]
M13_DS1_OUT_AIS[16:13]
M13_M12DMX_MODE5[1:0] M13_DEMUXCH2_4_ M13_OUT_TYPE5
INV5
0x10084 M13_M12_DEMUX_CONTROL2_R5
0x10085 M13_M12_DEMUX_CONTROL1_R6
M13_TDS1_EDGE[12:9]
M13_DS1_OUT_AIS[12:9]
M13_M12DMX_MODE4[1:0] M13_DEMUXCH2_4_ M13_OUT_TYPE4
INV4
0x10082 M13_M12_DEMUX_CONTROL2_R4
0x10083 M13_M12_DEMUX_CONTROL1_R5
M13_TDS1_EDGE[8:5]
M13_DS1_OUT_AIS[8:5]
M13_M12DMX_MODE3[1:0] M13_DEMUXCH2_4_ M13_OUT_TYPE3
INV3
0x10080 M13_M12_DEMUX_CONTROL2_R3
0x10081 M13_M12_DEMUX_CONTROL1_R4
M13_TDS1_EDGE[4:1]
M13_TDS1_EDGE[24:21]
M13_DS1_OUT_AIS[24:21]
M13_M12DMX_MODE7[1:0] M13_DEMUXCH2_4_ M13_OUT_TYPE7
INV7
M13_TDS1_EDGE[28:25]
M13_DS1_OUT_AIS[28:25]
M13_DS2_MODE M13_DS2_FERR_MODE
234
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
11 M13/M23 MUX/DeMUX Registers (continued)
Table 300. Register Address Map (continued)
Address
Symbol
0x1008A
M13_DMDS2_EDGE_R
0x1008B
—
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
M13_TDS3_
FORCE_ALL1
M13_M23CLK_
MODE
Bit 0
M13_DMDS2_EDGE[7:1]
—
0x10091
M23 MUX Controls—R/W
0x10092
M13_DS3_CONTROL1
0x10093
M13_DS3_CONTROL2
0x10094
M13_TFEAC_CONTROL
0x10095 M13_THDLC_CONTROL1
M13_DS3_FINV M13_DS3_MINV
M13_DS3_PINV
M13_NSMI_MODE M13_DS3_P_BER M13_CBIT2_ACT M13_UNUSED_AC
T
M13_TFEAC_CTL[1:0]
M13_DS3_RAI_
SEND
M13_FEBE_ERR
M13_TDL_
NTRNL_ACT
M13_TDL_FCS
M13_TFEAC_CODE[5:0]
M13_TDL_BUF1_ M13_TDL_BUF0_
END
END
0x10096 M13_THDLC_CONTROL2
0x10097
M13_DS3_FORCE M13_DS3_FORCE
_AIS
_IDLE
M13_TDL_ACT
M13_TDL_NTRNL
M13_TDL_BYTE_END[5:0]
M13_DS2_LB_REQ_R
M13_DS2_LB_REQ[7:1]
0x10098
M13_SEL_DS2_LB_R
M13_SEL_DS2_LB[7:1]
0x10099
M13_RDS2_EDGE_R1
M13_RDS2_EDGE[7:1]
0x1009A
M13_RDS2_EDGE_R2
M13_DS2ALCO_RTM_EDGE[7:1]
0x1009B
—
0x1009D
—
0x1009E
M13_DS2_OUT_IDLE_R
M13_DS2_OUT_IDLE[7:1]
0x1009F
M13_DS2_OUT_AIS_R
M13_DS2_OUT_AIS[7:1]
0x100A0
M13_TDS2_EDGE_R
0x100A1
M13_RDL_CONTROL
0x100A2
—
0x100A4
—
M23 DeMUX Controls—R/W
235
M13_TDS2_EDGE[7:1]
M13_RDL_FILL[1:0]
M13_RDL_FCS
M13_DS3_MODE M13_RDS3_EDGE
Lucent Technologies Inc.
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
11 M13/M23 MUX/DeMUX Registers (continued)
Table 300. Register Address Map (continued)
Address
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Performance Monitoring Counters—RO
0x100A5
M13_PM_CNT_ACT_R
0x100A6
M13_DS3_FERR_CNT_R1
0x100A7
M13_DS3_FERR_CNT_R2
0x100A8
M13_DS3_FEBE_CNT_R1
0x100A9
M13_DS3_FEBE_CNT_R2
0x100AA M13_DS3_CPERR_CNT_R1
0x100AB M13_DS3_CPERR_CNT_R2
0x100AC
M13_DS3_PERR_CNT_R1
0x100AD
M13_DS3_PERR_CNT_R2
0x100AE
—
0x100B1
—
0x100B2 M13_DS2_PERR_CNT7_R1
0x100B3 M13_DS2_PERR_CNT7_R2
0x100B4 M13_DS2_PERR_CNT6_R1
0x100B5 M13_DS2_PERR_CNT6_R2
0x100B6 M13_DS2_PERR_CNT5_R1
0x100B7 M13_DS2_PERR_CNT5_R2
0x100B8 M13_DS2_PERR_CNT4_R1
0x100B9 M13_DS2_PERR_CNT4_R2
0x100BA M13_DS2_PERR_CNT3_R1
0x100BB M13_DS2_PERR_CNT3_R2
Lucent Technologies Inc.
M13_PM_C
NT_ACT
M13_DS3_FERR_CNT[11:8]
M13_DS3_FERR_CNT[7:0]
M13_DS3_FEBE_CNT[13:8]
M13_DS3_FEBE_CNT[7:0]
M13_DS3_CPERR_CNT[13:8]
M13_DS3_CPERR_CNT[7:0]
M13_DS3_PERR_CNT[13:8]
M13_DS3_PERR_CNT[7:0]
M13_DS2_PERR_CNT7[12:8]
M13_DS2_PERR_CNT7[7:0]
M13_DS2_PERR_CNT6[12:8]
M13_DS2_PERR_CNT6[7:0]
M13_DS2_PERR_CNT5[12:8]
M13_DS2_PERR_CNT5[7:0]
M13_DS2_PERR_CNT4[12:8]
M13_DS2_PERR_CNT4[7:0]
vDS2_PERR_CNT3[12:8]
M13_DS2_PERR_CNT3[7:0]
236
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
11 M13/M23 MUX/DeMUX Registers (continued)
Table 300. Register Address Map (continued)
Address
Symbol
0x100BC M13_DS2_PERR_CNT2_R1
0x100BD M13_DS2_PERR_CNT2_R2
0x100BE M13_DS2_PERR_CNT1_R1
0x100BF M13_DS2_PERR_CNT1_R2
0x100C0
—
0x100C5
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 1
Bit 0
M13_DS2_PERR_CNT2[7:0]
M13_DS2_PERR_CNT1[12:8]
M13_DS2_PERR_CNT1[7:0]
—
0x100C6 M13_DS2_FERR_CNT7_R
M13_DS2_FERR_CNT7[7:0]
0x100C7 M13_DS2_FERR_CNT6_R
M13_DS2_FERR_CNT6[7:0]
0x100C8 M13_DS2_FERR_CNT5_R
M13_DS2_FERR_CNT5[7:0]
0x100C9 M13_DS2_FERR_CNT4_R
M13_DS2_FERR_CNT4[7:0]
0x100CA M13_DS2_FERR_CNT3_R
M13_DS2_FERR_CNT3[7:0]
0x100CB M13_DS2_FERR_CNT2_R
M13_DS2_FERR_CNT2[7:0]
0x100CC M13_DS2_FERR_CNT1_R
M13_DS2_FERR_CNT1[7:0]
0x100CD
M13_BPV_CNT_R1
M13_BPV_CNT[23:16]
0x100CE
M13_BPV_CNT_R2
M13_BPV_CNT[15:8]
0x100CF
M13_BPV_CNT_R3
M13_BPV_CNT[7:0]
0x100D0
M13_EXZ_CNT_R1
M13_EXZ_CNT[23:16]
0x100D1
M13_EXZ_CNT_R2
M13_EXZ_CNT[15:8]
0x100D2
M13_EXZ_CNT_R3
M13_EXZ_CNT[7:0]
0x100D3
—
0x100FE
—
237
Bit 2
M13_DS2_PERR_CNT2[12:8]
Lucent Technologies Inc.
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
11 M13/M23 MUX/DeMUX Registers (continued)
Table 300. Register Address Map (continued)
Address
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TDL Buffer Selection—R/W
0x100FF
M13_TDL_BUFFER_R
M13_TDL_B
UFFER
TDL Buffers—R/W
When M13_TDL_BUFFER = 0
M13_TDL_0DATA[0—63][7:0]
0x10100 M13_TDL_0DATA_R[0—63]
—
0x1013F
When M13_TDL_BUFFER = 1
0x10100 M13_TDL_1DATA_R[0—63]
—
0x1013F
0x10140
—
0x101FF
M13_TDL_1DATA[0—63][7:0]
—
Lucent Technologies Inc.
238
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers
Table of Contents
Contents
Page
12 28-Channel Framer Registers ........................................................................................................................ 239
12.1 Framer Global Register Descriptions ..................................................................................................... 243
12.2 Arbiter (Framer) Global Registers .......................................................................................................... 245
12.3 Performance Monitor Global Registers .................................................................................................. 247
12.4 HDLC Global Configuration and Status Registers .................................................................................. 253
12.5 System Interface Global Registers ......................................................................................................... 257
12.6 Signaling Global Registers ..................................................................................................................... 262
12.7 Frame Formatter (Transmit Framer) Global Register ............................................................................. 266
12.8 Facility Data Link Global Registers ......................................................................................................... 267
12.9 Super Mapper Framer Per Link Configuration and Status Registers ..................................................... 267
12.9.1 Signaling Per Link Registers ........................................................................................................ 267
12.10 Performance Monitor Per Link Registers .............................................................................................. 273
12.11 Receive Facility Data Link Configuration and Status Registers ........................................................... 288
12.12 Transmit Facility Data Link Configuration and Status Registers .......................................................... 290
12.13 System Interface, Arbiter, and Frame Formatter Mapping ................................................................... 292
12.14 System Interface Per Link Registers .................................................................................................... 293
12.15 Arbiter Framer Per Link Registers ........................................................................................................ 295
12.16 Frame Formatter Per Link Registers .................................................................................................... 300
12.17 Line Decoder/Encoder Per Link Registers ........................................................................................... 302
12.18 Line Encoder/Decoder Per Link Registers ........................................................................................... 303
12.19 HDLC Per Channel Configuration and Status Registers ...................................................................... 304
12.20 28-Channel Framer Block Register Map .............................................................................................. 311
Tables
Table 301.
Table 302.
Table 303.
Table 304.
Table 305.
Table 306.
Table 307.
Table 308.
Table 309.
Table 310.
Table 311.
Table 312.
Table 313.
Table 314.
Table 315.
Table 316.
Table 317.
Table 318.
Table 319.
Table 320.
Table 321.
Table 322.
Table 323.
Table 324.
Page
FRM_SFGR1, Superframer Global Register 1 (R/W) ........................................................................ 243
FRM_SFGR2, Superframer Global Register 2 (R/W) ........................................................................ 244
FRM_SFGR3, Superframer Global Register 3 (RO) ......................................................................... 245
FRM_SFGSR4, Superframer Global Register 4 (R/W) ..................................................................... 245
FRM_FGR1, Framer Global Register 1 (R/W) .................................................................................. 245
FRM_FGR2, Framer Global Register 2 (R/W) .................................................................................. 246
FRM_FGR3, Framer Global Register 3 (R/W) .................................................................................. 246
FRM_FGR4, Framer Global Register 4 (COR) ................................................................................. 246
FRM_FGR5, Framer Global Register 5 (COR) ................................................................................. 247
FRM_PMGR1_B, Performance Monitor Global Register 1_B (R/W) ................................................ 247
FRM_PMGR1, Performance Monitor Global Register 1 (COR) ........................................................ 247
FRM_PMGR2, Performance Monitor Global Register 2 (COR) ........................................................ 248
FRM_PMGR3, Performance Monitor Global Register 3 (R/W) ......................................................... 248
FRM_PMGR4, Performance Monitor Global Register 4 (R/W) ......................................................... 249
FRM_PMGR5, Performance Monitor Global Register 5—PMGR5 (R/W) ......................................... 249
FRM_PMGR6, Performance Monitor Global Register 6 (R/W) ......................................................... 249
FRM_PMGR7, Performance Monitor Global Register 7 (R/W) ......................................................... 249
FRM_PMGR8, Performance Monitor Global Register 8 (R/W) ......................................................... 250
FRM_PMGR9, Performance Monitor Global Register 9 (R/W) ......................................................... 250
FRM_PMGR10, Performance Monitor Global Register 10 (R/W) ..................................................... 250
FRM_PMGR11, Performance Monitor Global Register 11 (R/W) ..................................................... 250
FRM_PMGR12, Performance Monitor Global Register 12 (R/W) ..................................................... 251
FRM_PMGR13, Performance Monitor Global Register 13 (R/W) ..................................................... 251
FRM_PMGR14, Performance Monitor Global Register 14 (R/W) ..................................................... 252
Agere Systems Inc.
239
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
12 28-Channel Framer Registers (continued)
Table of Contents (continued)
Tables
Page
Table 325. FRM_PMGR15, Performance Monitor Global Register 15 (R/W) ..................................................... 252
Table 326. FRM_PMGR16, Performance Monitor Global Register 16 (R/W) ..................................................... 252
Table 327. FRM_HGR1, Transmit HDLC Global Register 1 (R/W) ..................................................................... 253
Table 328. FRM_HGR2, Transmit HDLC Global Register 2 (R/W) ..................................................................... 253
Table 329. FRM_HGR3, Transmit HDLC Global Register 3 (R/W) ..................................................................... 253
Table 330. FRM_HGR4, Transmit HDLC Global Register 4 (R/W) ..................................................................... 253
Table 331. FRM_HGR5, Transmit HDLC Global Register 5 (R/W) ..................................................................... 254
Table 332. FRM_HGR6, Transmit HDLC Global Register 6 (R/W) ..................................................................... 254
Table 333. FRM_HGR7, Transmit HDLC Global Register 7 (R/W) ..................................................................... 254
Table 334. FRM_HGR8, Transmit HDLC Global Register 8 (R/W) ..................................................................... 254
Table 335. FRM_HGR9, Transmit HDLC Global Register 9 (R/W) ..................................................................... 254
Table 336. FRM_HGR10, Transmit HDLC Global Register 10 (R/W) ................................................................. 255
Table 337. FRM_HGR11, Transmit HDLC Global Register 11 (RO) .................................................................. 255
Table 338. FRM_HGR12, Transmit HDLC Global Register 12 (R/W) ................................................................. 255
Table 339. FRM_HGR13, Transmit HDLC Global Register 13 (R/W) ................................................................. 255
Table 340. FRM_HGR14, Transmit HDLC Global Register 14 (R/W) ................................................................. 255
Table 341. FRM_HGR15, Receive HDLC Global Register 15 (R/W) .................................................................. 255
Table 342. FRM_HGR16, Receive HDLC Global Register 16 (R/W) .................................................................. 256
Table 343. FRM_HGR17, Receive HDLC Global Register 17 (R/W) .................................................................. 256
Table 344. FRM_HGR18, Receive HDLC Global Register 18 (R/W) .................................................................. 256
Table 345. FRM_HGR19, Receive HDLC Global Register 19 (R/W) .................................................................. 256
Table 346. FRM_HGR20, Receive HDLC Global Register 20 (R/W) .................................................................. 256
Table 347. FRM_SYSGR1, System Interface Global Register 1 (R/W) .............................................................. 257
Table 348. FRM_SYSGR2, System Interface Global Register 2 (R/W) .............................................................. 258
Table 349. FRM_SYSGR3, System Interface Global Register 3 (R/W) .............................................................. 259
Table 350. FRM_SYSGR4, System Interface Global Register 4 (R/W) .............................................................. 259
Table 351. FRM_SYSGR5, System Interface Global Register 5 (R/W) .............................................................. 259
Table 352. FRM_SYSGR6, System Interface Global Register 6 (COR) ............................................................. 259
Table 353. FRM_SYSGR7, System Interface Global Register 7 (COR) ............................................................. 260
Table 354. FRM_SYSGR8, System Interface Global Register 8 (R/W) .............................................................. 260
Table 355. FRM_SYSGR9, System Interface Global Register 9 (R/W) .............................................................. 260
Table 356. FRM_SYSGR10—FRM_SYSGR14, System Interface Global Register 10—14 (R/W) .................... 261
Table 357. FRM_SYSGR15, System Interface Global Register 15 (COR) ......................................................... 261
Table 358. FRM_SYSGR16, System Interface Global Register 16 (R/W) .......................................................... 261
Table 359. FRM_SGR1, Receive Signaling Global Register 1 (R/W) ................................................................. 262
Table 360. FRM_SGR2, Receive Signaling Global Register 2 (R/W) ................................................................. 262
Table 361. FRM_SGR3, Receive Signaling Global Register 3 (R/W) ................................................................. 263
Table 362. FRM_SGR4, Receive Signaling Global Register 4 (RO) ................................................................... 263
Table 363. FRM_SGR5, Receive Signaling Global Register 5 (RO) ................................................................... 263
Table 364. FRM_SGR6, Receive Signaling Global Register 6 .......................................................................... 264
Table 365. FRM_SGR7, Receive Signaling Global Register 7 (R/W) ................................................................. 264
Table 366. FRM_SGR8, Transmit Signaling Global Register 8 (R/W) ................................................................ 265
Table 367. FRM_FFGR1, Transmit Framer Global Register 1 (R/W) ................................................................. 266
Table 368. FRM_FDLGR1, Receive Facility Data Link Global Register 1 (R/W) ................................................ 267
Table 369. FRM_FDLGR2, Transmit Facility Data Link Global Register 2 (R/W) ............................................... 267
Table 370. Receive Path Signaling Register Addressing Map ............................................................................ 267
Table 371. Receive Path Signaling Registers Address Indexing ........................................................................ 267
Table 372. FRM_RSLR0—FRM_RSLR31, Receive Signaling Link Registers 0—31 (R/W) ............................... 268
Table 373. FRM_RSLR32, Receive Signaling Link Register 32 (COR) .............................................................. 269
240
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
Table of Contents (continued)
Tables
Page
Table 374. FRM_RSLR33, Receive Signaling Link Register 33 (R/W) ............................................................... 269
Table 375. Transmit Path Signaling Register Addressing Map ........................................................................... 270
Table 376. Transmit Path Signaling Registers Address Indexing ....................................................................... 270
Table 377. FRM_TSLR0—FRM_TSLR31, Transmit Signaling Link Registers 0—31 (R/W) .............................. 271
Table 378. FRM_TSLR32, Transmit Signaling Link Register 32 (R/W) .............................................................. 272
Table 379. FRM_TSLR33, Transmit Signaling Link Register 33 (COR) ............................................................. 273
Table 380. Performance Monitor Per Link Register Addressing Map ................................................................. 273
Table 381. Performance Monitor Per Link Register Address Indexing ................................................................ 274
Table 382. FRM_PMLR1, Performance Monitor Link Register 1 (R/W) .............................................................. 274
Table 383. FRM_PMLR2, Performance Monitor Link Register 2 (R/W) .............................................................. 274
Table 384. FRM_PMLR3, Performance Monitor Link Register 3 (R/W) .............................................................. 275
Table 385. FRM_PMLR4, Performance Monitor Link Register 4 (COR) ............................................................. 275
Table 386. FRM_PMLR5, Performance Monitor Link Register 5 (COR) ............................................................. 282
Table 387. FRM_PMLR6, Performance Monitor Link Register 6 (COR) ............................................................. 284
Table 388. FRM_PMLR7, Performance Monitor Link Register 7 (COR) ............................................................. 284
Table 389. FRM_PMLR8, Performance Monitor Link Register 8 (COR) ............................................................. 285
Table 390. FRM_PMLR9, Performance Monitor Link Register 9 (COR) ............................................................. 285
Table 391. FRM_PMLR10, Performance Monitor Link Register 10 (COR) ......................................................... 285
Table 392. FRM_PMLR11, Performance Monitor Link Register 11 (COR) ......................................................... 285
Table 393. FRM_PMLR12, Performance Monitor Link Register 12 (COR) ......................................................... 285
Table 394. FRM_PMLR13, Performance Monitor Link Register 13 (COR) ......................................................... 286
Table 395. FRM_PMLR14, Performance Monitor Link Register 14 (COR). ........................................................ 287
Table 396. FRM_PMLR15, Performance Monitor Link Register 15 (COR) ......................................................... 287
Table 397. FRM_PMLR16, Performance Monitor Link Register 16 (COR) ......................................................... 287
Table 398. FRM_PMLR17, Performance Monitor Link Register 17 (COR) ......................................................... 287
Table 399. FRM_PMLR18, Performance Monitor Link Register 18 (COR) ......................................................... 287
Table 400. FRM_PMLR19, Performance Monitor Link Register 19 (COR) ......................................................... 288
Table 401. FRM_PMLR20, Performance Monitor Link Register 20 (COR) ......................................................... 288
Table 402. Receive Facility Data Link Register Addressing Map ........................................................................ 288
Table 403. Receive Path Facility Data Link Registers Address Indexing ............................................................ 289
Table 404. FRM_RFDLLR1—FRM_RFDLLR5, Receive FDL Link Registers 1—5 (RO) ................................... 289
Table 405. FRM_RFDLLR6, Receive FDL Link Register 6 (R/W) ....................................................................... 289
Table 406. FRM_RFDLLR7, Receive FDL Link Register 7 (RO) ........................................................................ 289
Table 407. FRM_RFDLLR8, Receive FDL Link Register 8 (COR) ...................................................................... 290
Table 408. FRM_RFDLLR9, Receive FDL Link Register 9 (R/W) ....................................................................... 290
Table 409. Transmit Facility Data Link Register Addressing Map ....................................................................... 290
Table 410. Transmit Path Facility Data Link Registers Address Indexing ........................................................... 290
Table 411. FRM_TFDLLR1—FRM_TFDLR5, Transmit FDL Link Registers 1—5 (COR) ................................... 290
Table 412. FRM_TFDLLR6, Transmit FDL Link Register 6 (R/W) ...................................................................... 291
Table 413. FRM_TFDLLR7, Transmit FDL Link Register 7 (R/W) ...................................................................... 291
Table 414. FRM_TFDLLR8, Transmit FDL Link Register 8 (RO/COW) .............................................................. 292
Table 415. FRM_TFDLLR9, Transmit FDL Link Register 9 (R/W) ...................................................................... 292
Table 416. System Interface, Arbiter, and Frame Formatter Link Register Addressing Map .............................. 292
Table 417. System Interface, Arbiter, and Frame Formatter Link Register Address Indexing ............................ 293
Table 418. FRM_SYSLR1, System Interface Link Register 1 (R/W) ................................................................... 293
Table 419. FRM_SYSLR2, System Interface Link Register 2 (R/W) ................................................................... 294
Table 420. FRM_SYSLR3—FRM_SYSLR6, System Interface Link Registers 3—6 (R/W) ................................ 294
Table 421. FRM_ARLR1, Arbiter Link Register 1 (R/W) ..................................................................................... 295
Table 422. FRM_ARLR2, Arbiter Link Register 2 (R/W) ..................................................................................... 296
Agere Systems Inc.
241
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
12 28-Channel Framer Registers (continued)
Table of Contents (continued)
Tables
Page
Table 423. FRM_ARLR3, Arbiter Link Register 3 (R/W) ..................................................................................... 299
Table 424. FRM_FFLR1, Frame Formatter Link Register 1 (R/W) ..................................................................... 300
Table 425. FRM_FFLR2, Frame Formatter Link Register 2 (R/W) ..................................................................... 301
Table 426. Line Decoder Per LInk Register Addressing Map ............................................................................. 302
Table 427. Line Decoder Per Link Registers Address Indexing .......................................................................... 302
Table 428. Line Encoder Per Link Register Addressing Map .............................................................................. 302
Table 429. Line Encoder Per Link Registers Address Indexing .......................................................................... 302
Table 430. FRM_LDLR1, Line Decoder Link Register 1 (R/W) ........................................................................... 303
Table 431. FRM_LDLR2, Line Encoder Link Register 2 (R/W) ........................................................................... 303
Table 432. HDLC Per Channel Register Addressing Map .................................................................................. 304
Table 433. FRM_HCR1, Transmit HDLC Channel Register 1 (R/W) .................................................................. 304
Table 434. FRM_HCR2, Transmit HDLC Channel Register 2 (R/W) .................................................................. 304
Table 435. FRM_HCR3, Transmit HDLC Channel Register 3 (R/W) .................................................................. 305
Table 436. FRM_HCR4, Transmit HDLC Channel Register 4 (RO) .................................................................... 306
Table 437. FRM_HCR5, Transmit HDLC Channel Register 5 (R/W) .................................................................. 306
Table 438. FRM_HCR6, Transmit HDLC Channel Register 6 (WO) ................................................................... 307
Table 439. FRM_HCR7, Transmit HDLC Channel Register 7 (RO) .................................................................... 307
Table 440. FRM_HCR8, Receive HDLC Channel Register 8 (R/W) ................................................................... 307
Table 441. FRM_HCR9, Receive HDLC Channel Register 9 (R/W) ................................................................... 307
Table 442. FRM_HCR10, Receive HDLC Channel Register 10 (R/W) ............................................................... 308
Table 443. FRM_HCR11, Receive HDLC Channel Register 11 (RO) ................................................................. 308
Table 444. FRM_HCR12, Receive HDLC Channel Register 12 (R/W) ............................................................... 309
Table 445. FRM_HCR13, Receive HDLC Channel Register 13 (RO) ................................................................. 310
Table 446. FRM_HGR14, Receive HDLC Channel Register 14 (COR) .............................................................. 310
Table 447. Framer Register Map ......................................................................................................................... 311
242
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
12.1 Framer Global Register Descriptions
Table 301. FRM_SFGR1, Superframer Global Register 1 (R/W)
Address
0x80000
Bit
15
Name
Function
Reset Default
0
FRM_SW_TRN Superframer Configuration Modes.
0 = Transport mode.
1 = Switching mode.
14:13
FRM_LC_
Line Encoder/Decoder Control.
00
CNTRL[1:0]
00 = Line encoder and line decoder blocks are not used in
either the framer Tx or Rx paths. This setting is used in the
following switching modes:
■
STS-3/STS-1/DS3/DS2 to CHI/parallel system bus/SMI.
■
STS-3/STS-1/DS3 to line data rate mode.
01 = Line decoder is used in the Rx path and line encoder is
used in the Tx path. This setting is used in the framer-only
switching modes:
DS1 to CHI/parallel system bus/SMI channelized.
10 = Line decoder is used in the Tx path and line encoder is
used in the Rx path. This setting is used in the following
transport modes:
■
■
12
FRM_LOOP_
TIMING
11
FRM_DS1_
CEPTN
10
9:1
0
DS1 to DS2/DS3/STS-1/STS-3.
11 = Reserved.
Loop Timing.
0 = Superframer is programmed for normal mode.
1 = Superframer is programmed for loop timing; i.e., all received
line clocks are looped back to the corresponding transmit
line clocks.
DS1/CEPT Terminal Count.
0
1
0 = Superframer is programmed for CEPT mode, which has a
maximum of 21 operational links. Links 22 to 28 are
disabled.
1 = Superframer is programmed for DS1 mode, which has a
maximum of 28 operational links.
Note: For fewer links or DS1/CEPT mixed modes, use
FRM_TC_EN and FRM_TC[7:0] (Table 306) parameters to select an accurate link count.
FRM_PLL_
PLL Bypass.
BYPAS
0 = Internal PLL is used to generate the line clock in the
transmit path.
1 = The PLL is bypassed. External line clock is required in this
mode.
Reserved. Must write to 0.
—
FRM_LG_BUF_ HDLC Buffer Mode.
MODE
0 = HDLC channel buffers are configured for 128-byte storage.
Up to 64 (32) channels can be supported in the switching
(transport) mode.
0
0
0
1 = HDLC channel buffers are combined for 512-byte storage.
Up to 16 (8) channels can be supported in the switching
(transport) mode.
Agere Systems Inc.
243
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
12 28-Channel Framer Registers (continued)
Table 302. FRM_SFGR2, Superframer Global Register 2 (R/W)
Address
Bit
0x80001 15:14
244
Name
—
Function
Reset
Default
Reserved. Must write to 0.
0
13
FRM_TP_SIG_PWDN Transmit Path Receive Signaling Powerdown. When set
to 0, the transmit path receive signaling block for the transport mode is powered down.
1
12
FRM_RP_SIG_PWDN Receive Path Transmit Signaling Powerdown. When set
to 0, the receive path transmit signaling block for the transport mode is powered down.
1
11
FRM_TP_RDL_PWDN Transmit Path Receive Datalink Powerdown. When set to
0, the transmit path receive data link block for the transport
mode is powered down.
1
10
FRM_RP_TDL_PWDN Receive Path Transmit Datalink Powerdown. When set to
0, the receive path transmit data link block for the transport
mode is powered down.
1
9
FRM_TP_RH_PWDN
Transmit Path Receive HDLC Powerdown. When set to 0,
the transmit path receive HDLC block for the transport mode
is powered down.
1
8
FRM_RP_TH_PWDN
Receive Path Transmit HDLC Powerdown. When set to 0,
the receive path transmit HDLC block for the transport mode
is powered down.
1
7
FRM_TS_PWDN
Transmit Path System Block Powerdown. When set to 0,
the transmit path system block is powered down.
1
6
FRM_RS_PWDN
Receive Path System Block Powerdown. When set to 0,
the receive path system block is powered down.
1
5
FRM_TP_PM_PWDN
Transmit Path Performance Monitor Powerdown. When
set to 0, the transmit path performance monitor block is powered down.
1
4
FRM_RP_FF_PWDN
Receive Path Frame Formatter Powerdown. When set to
0, the receive path frame formatter block is powered down.
1
3
FRM_TP_RA_PWDN
Transmit Path Receive Aligner Powerdown. When set to
0, the transmit path receive aligner block is powered down.
1
2:0
—
Reserved. Must write to 0.
0
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
Table 303. FRM_SFGR3, Superframer Global Register 3 (RO)
Address
Bit
Name
Function
Reset
Default
0x80002
15
FRM_RP_SIG
A 1 indicates the change of signaling state FIFO contains
state change information.
0
14
FRM_AR_IS
A 1 indicates the FRM_AR_IS block has generated an
interrupt.
0
13
FRM_TP_RDL_IS
A 1 indicates the FRM_TP_RDL_IS block has generated
an interrupt.
0
12
FRM_TP_TDL_IS
A 1 indicates the FRM_TP_TDL_IS block has generated
an interrupt.
0
11
FRM_RH_IS
A 1 indicates the FRM_RH_IS block has generated an
interrupt.
0
10
FRM_TH_IS
A 1 indicates the FRM_TH_IS block has generated an
interrupt
0
9
FRM_TS_IS
A 1 indicates the FRM_TS_IS block has generated an
interrupt.
0
8
FRM_RS_IS
A 1 indicates the FRM_RS_IS block has generated an
interrupt.
0
7
FRM_TP_PM_IS
A 1 indicates the FRM_TP_PM_IS block has generated
an interrupt.
0
6
FRM_RP_PM_IS
A 1 indicates the FRM_RP_PM_IS block has generated
an interrupt.
0
5
FRM_RP_RDL_IS
A 1 indicates the FRM_RP_RDL_IS block has generated
an interrupt.
0
4
FRM_RP_TDL_IS
A 1 indicates the FRM_RP_TDL_IS block has generated
an interrupt.
0
3:0
—
Reserved. Reads 0.
0
Table 304. FRM_SFGSR4, Superframer Global Register 4 (R/W)
Address
Bit
Name
0x80003
15
—
14:12
11:0
Function
Reserved. Must write to 0.
FRM_VERSION[2:0] Superframer Version Number.
—
Reserved. Must write to 0.
Reset
Default
0
000
0x000
12.2 Arbiter (Framer) Global Registers
Table 305. FRM_FGR1, Framer Global Register 1 (R/W)
Address
Bit
0x80010
15:8
7:0
Agere Systems Inc.
Name
Function
Reserved. Must write to 0.
—
FRM_TO[7:0] Time-Out Count. The number of frames to wait before
declaring a time out. See FRM_OPT[1:0] (Table 422). The
default is 40 frames (5 ms).
Reset
Default
000000000
00101000
245
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
12 28-Channel Framer Registers (continued)
Table 306. FRM_FGR2, Framer Global Register 2 (R/W)
Address
Bit
0x80011
15
Name
Function
Reset
Default
0
FRM_TC_EN Terminal Count Enable.
0 = Terminal count disabled use defaults.
14:8
7:0
1 = Terminal count enabled.
Reserved. Must write to 0.
—
0000000
00000000
FRM_TC[7:0] Terminal Count. When enabled, the link counter will count
from 1 to the terminal count. The terminal count determines
the number of links available for use. The operational links are
link 1 to the link determined by the terminal count. By default,
the count is determined by the option bit, FRM_DS1_CEPTN
(Table 301). In an application, where there is a mix of DS1
and CEPT links or a small number of links, the terminal count
may be set by enabling FRM_TC_EN and setting the terminal
count, FRM_TC[7:0].
Table 307. FRM_FGR3, Framer Global Register 3 (R/W)
Address
Bit
0x80012
15
Name
Function
Reset
Default
FRM_TPSSE_IM Transmit Path System Synchronization Error Interrupt
Mask. A transmit path system synchronization error interrupt is generated when synchronization is lost between
the receive system interface and the transmit path line
clock. FRM_TPSSE_IM is a global mask for the interrupt
status from each link. The individual link transmit path
system error interrupt status bits, FRM_TPSSEI[28:1] are
summarized in FRM_AR_IS bit 14 of FRM_SFGR3
(Table 303).
1
0 = Allows any synchronization error, as reported in the
synchronization status registers, to generate an interrupt.
1 = Masks any synchronization error, as reported in the
synchronization status registers, from generating an interrupt.
14:0
—
Reserved. Must write to 0.
000000000
000000
Table 308. FRM_FGR4, Framer Global Register 4 (COR)
Address
Bit
0x80014
15:0
Name
Function
Reset
Default
FRM_TPSSEI[16:1] Transmit Path System Synchronization Error Interrupt.
00X0000
1 = Indicates a transmit path system synchronization
error on links 16 to 1.
246
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
Table 309. FRM_FGR5, Framer Global Register 5 (COR)
Address
Bit
Name
0x80015
15:12
—
11:0
Function
Reserved. Must write to 0.
Reset
Default
000
FRM_TPSSEI[28:17] Transmit Path System Synchronization Error Inter- 000000000
rupt.
000
1 = Indicates a transmit path system synchronization
error on links 28 to 17.
12.3 Performance Monitor Global Registers
Table 310. FRM_PMGR1_B, Performance Monitor Global Register 1_B (R/W)
Address*
Bit
Name
0x80P20
15
FRM_SEC_SEL
Function
Framer PMRESET Source. The source of the performance
monitoring interval (generally one second) may be selected to
be internal to the framer block or external to the framer block.
Reset
Default
0
0 = External.
1 = Internal.
14:13
—
Reserved. Must write to 0.
000
12:0 FRM_CT125[12:0] Framer Terminal Count. This is the terminal count for an inter- 0x1950
nal 125 µs timer that is multiplied by 8000 to determine the internal performance monitoring interval. This count is based on the
TDM clock speed. The default count is based on a 51.84 MHz
clock. This terminal count is calculated by the following equation.
Timer terminal count = (125 µs)(fTDM clock).
* P = 0x0 for the receive path, and P = 0x1 for the transmit path.
Table 311. FRM_PMGR1, Performance Monitor Global Register 1 (COR)
Address*
Bit
Name
0x80P30
15:2
1
—
FRM_DETECT
0
Function
Reserved. Must write to 0.
Test-Pattern Detect. A 1 indicates the pattern detector has
locked onto the pattern specified by the FRM_PTRN_SEL[3:0]
(Table 324) configuration bits. There is only one test-pattern
detector. See O.151 Section 2. Both framed and unframed testpattern generation/detection are supported.
FRM_PTRNBER Test-Pattern Bit Error. A 1 indicates the receive framer pattern
detector has found one or more single-bit errors in the pattern
that it is currently locked on to. There is only one test-pattern
BER counter for all links.
Reset
Default
0x0000
0
0
* P = 0x0 for the receive path, and P = 0x1 for the transmit path.
Agere Systems Inc.
247
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
12 28-Channel Framer Registers (continued)
Table 312. FRM_PMGR2, Performance Monitor Global Register 2 (COR)
Address*
Bit
0x80P31
15:0
Name
Function
Reset
Default
FRM_TPERR_CT[15:0] Test Pattern Error Count Register. This register contains the 16-bit count of test-pattern errors.
0
* P = 0x0 for the receive path, and P = 0x1 for the transmit path.
Table 313. FRM_PMGR3, Performance Monitor Global Register 3 (R/W)
Address*
Bit
Name
0x80P32
15:14
13:11
10:8
—
FRM_RAC[2:0]
FRM_RDC[2:0]
7
6
5
4:3
2
1
0
Function
Reserved. Must write to 0.
CEPT Mode RAI Activation Count†.
CEPT Mode RAI Deactivation Count†. RAC and RDC
can be set to meet various standards.
FRM_FSFBEEN
FS Frame Bit Error Enable. Allows a signaling frame (FS)
bit error to set the FBE status bit, FRM_FBE ( Table 386).
In DDS, a 0 means do not count TS24 framing and F S as
FBEs; a 1 means count TS24 framing and Fs as FBEs.
0 = F S bit errors disabled.
1 = F S bit errors enabled.
FRM_CMFRFEN
CEPT Multiframe Reframe Enable.
0 = CEPT CRC-4 multiframe reframe disabled.
1 = CEPT CRC-4 multiframe reframe enabled. A research
for multiframe alignment is initiated upon a loss of CEPT
CRC-4 multiframe alignment.
FRM_CRCRFEN
CRC Reframe Enable.
0 = CRC errors do not cause a reframe or LOF condition.
1 = The receive performance monitor will force a reframe
and LOF condition on excessive CRC errors.
FRM_CEPTAISM[1:0] CEPT AIS Mode.
00 = Option 0: G.775 section I.2; G.965 section 16.1.2.
01 = Option 1: G.775 section 5.2.
10 = Option 2: G.775 section I.2.
11 = Option 3: G.775 section I.2.
FRM_DS1AISM
DS1 AIS Mode.
0 = Option 0: T1.231 section 6.1.2.2.3, T1.403 section H,
G.775 section 5.4.
1 = Option 1: G.775 section I.2.
FRM_ESFRAIM
ESF RAI Mode.
0 = Alternating eight ones followed by eight zeros.
1 = All ones.
FRM_RAICLR
Clear RAI on Reception of DS1 Idle Signal.
0 = Ignore DS1 idle signal for RAI clearing.
1 = Clear failure on reception of DS1 idle signal: ANSI
T1.231 section 6.2.2.2.1.
Reset
Default
00
001
001
0
0
1
01
1
0
0
* P = 0x0 for the receive path, and P = 0x1 for the transmit path.
† FRM_RACFRM_RDC Standard.
248
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
Table 314. FRM_PMGR4, Performance Monitor Global Register 4 (R/W)
Address*
Bit
Name
0x80P33
15:0
Function
Reset
Default
FRM_SFSEST[15:0] SF Severely Errored Second Threshold for All SF Format- 0x0140
ted Channels.
Note: A bursty errored second will be recorded if the number
of events is greater than the errored second threshold
but less than the severely errored second threshold.
There is a separate threshold for ESF and SF because
of the bit error provisioning in ESF (F t or Fs).
* P = 0x0 for the receive path, and P = 0x1 for the transmit path.
Table 315. FRM_PMGR5, Performance Monitor Global Register 5—PMGR5 (R/W)
Address*
Bit
Name
0x80P34
15:0
Function
FRM_DCT[15:0] DS1 Excessive CRC Threshold—Default 320. This register
sets the one second CRC threshold at which an excessive CRC
error condition is reported and the one second CRC threshold at
which a reframe may be forced.
Reset
Default
0x0140
* P = 0x0 for the receive path, and P = 0x1 for the transmit path.
Table 316. FRM_PMGR6, Performance Monitor Global Register 6 (R/W)
Address*
Bit
Name
0x80P35
15:0
Function
FRM_ESFSEST[15:0] ESF Severely Errored Second Threshold for All ESF
Formatted Channels. A bursty errored second will be
recorded if the number of events is greater than the errored
second threshold but less than the severely errored second
threshold.
Reset
Default
0x0140
* P = 0x0 for the receive path, and P = 0x1 for the transmit path.
Table 317. FRM_PMGR7, Performance Monitor Global Register 7 (R/W)
These bits enable the errored events used to determine errored and severely errored seconds in the DS1 modes.
Address*
Bit
0x80P36 15:9
8
7
6
5
4
3
2
1
0
Name
—
FRM_DSEF
FRM_DLFA
FRM_DRFA
FRM_DSLIP
FRM_DLOS
FRM_DAIS
FRM_DCRC
FRM_DFS
FRM_DFT
Function
Reserved. Must write to 0.
DS1 Severely Errored Frame Enable. See FRM_SEFS (Table 400).
DS1 Loss of Frame Alignment Enable.
DS1 Remote Frame Alarm Enable.
DS1 Slip Enable.
DS1 Loss of Signal Enable.
DS1 Alarm Indication Signal Enable.
DS1 CRC-6 Error Enable.
DS1 Fs Framing Bit Error Enable (SF Only).
DS1 Ft Framing Bit Error Enable (SF and ESF).
Reset
Default
0x00
0
0
0
0
0
0
0
0
0
* P = 0x0 for the receive path, and P = 0x1 for the transmit path.
Agere Systems Inc.
249
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
12 28-Channel Framer Registers (continued)
Table 318. FRM_PMGR8, Performance Monitor Global Register 8 (R/W)
Address*
Bit
Name
Function
0x80P37
15:0
FRM_CCT[15:0]
CEPT Excessive CRC Threshold—Default 915. This register
sets the one second CRC threshold at which an excessive CRC
error condition is reported and the one second CRC threshold at
which a reframe may be forced.
Reset
Default
0x0393
* P = 0x0 for the receive path, and P = 0x1 for the transmit path.
Table 319. FRM_PMGR9, Performance Monitor Global Register 9 (R/W)
Address*
0x80P38
Bit
Name
Function
Reset
Default
15:0 FRM_CSEST[15:0] CEPT Severely Errored Second Threshold for All CEPT
Formatted Channels.
0x0000
* P = 0x0 for the receive path, and P = 0x1 for the transmit path.
Table 320. FRM_PMGR10, Performance Monitor Global Register 10 (R/W)
These bits enable the errored events used to determine errored and severely errored seconds in the CEPT modes.
Address*
Bit
Name
0x80P39
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FRM_CSA6_F
FRM_CSA6_E
FRM_CSA6_C
FRM_CSA6_8
FRM_CSA6_1X
FRM_CSA6_X1
FRM_CEBIT
FRM_CLMFA
FRM_CLFA
FRM_CRFA
FRM_CSLIP
FRM_CLOS
FRM_CAIS
FRM_CCRC
FRM_CNOTFAS
FRM_CFAS
Function
Reset
Default
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CEPT Sa6 = F Enable and Sa5 = 1. (Reception of AIS.)
CEPT Sa6 = E Enable and Sa5 = 1. (FC3 and FC4.)
CEPT Sa6 = C Enable and Sa5 = 1. (LOS/LFA.)
CEPT Sa6 = 8 Enable and Sa5 = 1. (Loss of power.)
CEPT Sa6 = 001x Event Enable.
CEPT Sa6 = 00x1 Event Enable.
CEPT E bit = 0 Event Enable.
CEPT Loss of Multiframe Alignment Enable.
CEPT Loss of Frame Alignment Enable.
CEPT Remote Frame Alarm Enable.
CEPT Slip Enable.
CEPT Loss of Signal Enable.
CEPT Alarm Indication Signal Enable.
CEPT CRC-4 Error Enable.
CEPT Non-FAS Bit Error Enable.
CEPT FAS Bit Error Enable.
* P = 0x0 for the receive path, and P = 0x1 for the transmit path.
Table 321. FRM_PMGR11, Performance Monitor Global Register 11 (R/W)
Address*
Bit
0x80P3A
15:0
Name
Function
FRM_CRET[15:0] Continuous Received E-Bit Threshold—Default 991. This
register sets the five second continuous E-bit threshold for setting the CRE bit status indication.
Reset
Default
0x03DF
* P = 0x0 for the receive path, and P = 0x1 for the transmit path.
250
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
Table 322. FRM_PMGR12, Performance Monitor Global Register 12 (R/W)
Address* Bit
0x80P3B
Name
Function
Reset
Default
15
FRM_CRAI_AIS
Send RAI Upon Detection of AIS Enable in CEPT Mode.
0
14
FRM_CRAI_OOF
Send RAI Upon Detection of OOF Enable in CEPT Mode.
0
13
FRM_CRAI_LOS
Send RAI Upon Detection of LOS Enable in CEPT Mode.
0
12
FRM_CRAI_SA6EQC Send RAI Upon Detection of Sa6 = (0xC) Enable in CEPT
0
Mode.
11
FRM_CRAI_SA6EQ8 Send RAI Upon Detection of Sa6 = (0x8) Enable in CEPT
0
Mode.
10
FRM_CRAI_CRCTX Send RAI Upon Detection of CRCTX Enable in CEPT
0
Mode.
0
9
FRM_CRAI_LTS0MFA Send RAI Upon Detection of LTS0MFA Enable in CEPT
Mode.
8 FRM_CRAI_LTS16MFA Send RAI Upon Detection of LTS16MFA Enable in CEPT
0
Mode.
7
FRM_CRAI_8MSEX
Send RAI Upon Detection of 8 ms Timer Expiration
0
Enable in CEPT Mode.
6:3
—
Reserved. Must write to 0.
0
2
FRM_DSRAI_LOS
Send RAI Upon Detection of LOS Enable in DS1 Mode.
0
1
FRM_DSRAI_OOF
Send RAI Upon Detection of OOF Enable in DS1 Mode.
0
0
FRM_DSRAI_AIS
Send RAI Upon Detection of AIS Enable in DS1 Mode.
0
* P = 0x0 for the receive path, and P = 0x1 for the transmit path.
Table 323. FRM_PMGR13, Performance Monitor Global Register 13 (R/W)
Address*
Bit
Name
0x80P3C
15:4
3
—
FRM_CFBE_MODE
2
1
0
Function
Reserved. Must write to 0.
CEPT FBE Mode.
0 = Count only FBEs received in FAS frame.
1 = Count FBEs received in both FAS and NOTFAS
frames.
FRM_CEBIT_LTS0MFA Set E Bits Upon Detection of LTS0MFA Enable (CEPT
Only).
FRM_CEBIT_ESMF
Set E Bits Upon Detection of an Errored CEPT_CRC4
SMF (Submultiframe) Enable.
FRM_CEBIT_CRCTX Set E Bits Upon Detection of CRCTX Enable (CEPT
Only).
Reset
Default
0x000
0
0
0
0
* P = 0x0 for the receive path, and P = 0x1 for the transmit path.
Agere Systems Inc.
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TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
12 28-Channel Framer Registers (continued)
Table 324. FRM_PMGR14, Performance Monitor Global Register 14 (R/W)
Address*
Bit
Name
0x80P3D
15:12
11
—
FRM_PTRN_EN
10
9
8:4
3:0
Function
Reserved. Must write to 0.
Enables the Detector Circuitry. FRM_PTRN_LNK[4:0]
should be set to 1 before enabling the detection circuitry.
FRM_PTRN_INV
Receive Pattern Normal/Invert Mode. Selects whether to
check for the selected pattern or its inverse.
0 = Selected pattern.
1 = Inverse.
FRM_PTRN_FRMT Receive Pattern Framed/Unframed Mode. Selects monitoring for either framed or unframed test pattern.
0 = Unframed.
1 = Framed.
FRM_PTRN_LNK[4:0] Pattern Detector Link Select. 5-bit link selection to indicate which link to monitor for test patterns.
FRM_PTRN_SEL[3:0] Receive Pattern Select.
0000 = Pattern detector deactivate.
0001 = MARK (all ones AIS).
0010 = QRSS (2 20 – 1 with zero suppression).
0011 = 25 – 1.
0100 = 63(2 6 – 1).
0101 = 511(2 9 – 1) (V.52).
0110 = 29 – 1.
0111 = 2047(2 11 – 1) (O.151).
1000 = 211 – 1 (reversed).
1001 = 215 – 1 (O.151).
1010 = 220 – 1 (V.57).
1011 = 220 – 1 (CB113/CB114).
1100 = 223 – 1 (O.151).
1101 = 1:1 (alternating).
Reset
Default
0x0
0
0
0
0
0x00
* P = 0x0 for the receive path, and P = 0x1 for the transmit path.
Table 325. FRM_PMGR15, Performance Monitor Global Register 15 (R/W)
Address*
Bit
0x80P3E
15:0
Name
Function
FRM_LN_IS[16:1] Per-Link PM Summary Interrupts for Links 16 Down to 1.
Reset
Default
0x0000
* P = 0x0 for the receive path, and P = 0x1 for the transmit path.
Table 326. FRM_PMGR16, Performance Monitor Global Register 16 (R/W)
Address*
Bit
Name
Function
0x80P3F 15:12
—
Reserved. Must write to 0.
11:0 FRM_LN_IS[28:17] Per-Link PM Summary Interrupts for Links 28 Down to 17.
Reset
Default
0x0
0x000
* P = 0x0 for the receive path, and P = 0x1 for the transmit path.
252
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
12.4 HDLC Global Configuration and Status Registers
Table 327. FRM_HGR1, Transmit HDLC Global Register 1 (R/W)
Address
0x80140
Bit
Name
Function
Reserved. Must write to 0.
15:10
—
9:0 FRM_HTTHRSH0[9:0] HDLC Transmit FIFO Threshold 0. These bits indicate
the threshold levels for the Tx FIFOs. When a channel is
enabled and the number of bytes in its FIFO decrements
to this value, its FRM_HTTHRSH (Table 436) bit is set
(optionally causes interrupt). FRM_HTTHRSH0[9:0] or
FRM_HTTHRSH1[9:0] is selected on a per-channel basis
with the FRM_HTTHRSEL (Table 436) parameter.
Reset
Default
0x00
0x000
Table 328. FRM_HGR2, Transmit HDLC Global Register 2 (R/W)
Address
0x80141
Bit
Name
Function
15:10
—
Reserved. Must write to 0.
9:0 FRM_HTTHRSH1[9:0] HDLC Transmit FIFO Threshold 1. These bits indicate
the threshold levels for the Tx FIFOs. When a channel is
enabled and the number of bytes in its FIFO decrements
to this value, its FRM_HTTHRSH bit is set (optionally
causes interrupt). FRM_HTTHRSH0[9:0] or
FRM_HTTHRSH1[9:0] is selected on a per-channel basis
with the FRM_HTTHRSEL (Table 436) parameter.
Reset
Default
0x00
0x000
Table 329. FRM_HGR3, Transmit HDLC Global Register 3 (R/W)
Address
Bit
0x80142
15:8
7:0
Name
Function
—
Reserved. Must write to 0.
FRM_TXICHAR0[7:0] Transparent Mode Transmit Idle Char 0. These bits are
used in transparent mode. They represent the first 8-bit pattern the transmitter should send when there is no data
available in the FIFO. One of the four patterns can be
selected on a per-channel basis with the
FRM_HXPIDLE[1:0] (Table 436) parameter.
Reset
Default
0x00
0x00
Table 330. FRM_HGR4, Transmit HDLC Global Register 4 (R/W)
Address
Bit
0x80143
15:8
7:0
Agere Systems Inc.
Name
Function
—
Reserved. Must write to 0.
FRM_TXICHAR1[7:0] Transparent Mode Transmit Idle Char 1. These bits are
used in transparent mode. They represent the second 8-bit
pattern the transmitter will send when there is no data available in the FIFO. One of the four patterns can be selected
on a per-channel basis with the FRM_HXPIDLE[1:0]
(Table 436) parameter.
Reset
Default
0x00
0x00
253
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
12 28-Channel Framer Registers (continued)
Table 331. FRM_HGR5, Transmit HDLC Global Register 5 (R/W)
Address
Bit
0x80144
15:8
7:0
Name
Function
—
Reserved. Must write to 0.
FRM_TXICHAR2[7:0] Transparent Mode Transmit Idle Char 2. These bits
are used in transparent mode. They represent the third
8-bit pattern the transmitter will send when there is no
data available in the FIFO. One of the four patterns can
be selected on a per-channel basis with the
FRM_HXPIDLE[1:0] (Table 435) parameter.
Reset
Default
0x00
0x00
Table 332. FRM_HGR6, Transmit HDLC Global Register 6 (R/W)
Address
Bit
0x80145
15:8
7:0
Name
Function
—
Reserved. Must write to 0.
FRM_TXICHAR3[7:0] Transparent Mode Transmit Idle Char 3. These bits
are used in transparent mode. They represent the fourth
8-bit pattern the transmitter will send when there is no
data available in the FIFO. One of the four patterns can
be selected on a per-channel basis with the
FRM_HXPIDLE[1:0] (Table 435) parameter.
Reset
Default
0x00
0x00
Table 333. FRM_HGR7, Transmit HDLC Global Register 7 (R/W)
Address
Bit
Name
0x80146
15:5
—
4:0
Function
Reset
Default
Reserved. Must write to 0.
0x000
FRM_FCNT0[4:0] HDLC Flag Count 0. These values are the number of additional idle flags to be sent between HDLC packets. One of
the four values can be selected on a per-channel basis with
the FRM_CFLAGS[1:0] (Table 435) parameter.
00000
Table 334. FRM_HGR8, Transmit HDLC Global Register 8 (R/W)
Address
Bit
Name
0x80147
15:5
—
4:0
Function
Reset
Default
Reserved. Must write to 0.
0x000
FRM_FCNT1[4:0] HDLC Flag Count 1. These values are the number of additional idle flags to be sent between HDLC packets. One of
the four values can be selected on a per-channel basis with
the FRM_CFLAGS[1:0] parameter.
00000
Table 335. FRM_HGR9, Transmit HDLC Global Register 9 (R/W)
Address
Bit
0x80148
15:5
4:0
254
Name
Function
—
Reserved. Must write to 0.
FRM_FCNT2[4:0] HDLC Flag Count 2. These values are the number of additional idle flags to be sent between HDLC packets. One of
the four values can be selected on a per-channel basis with
the FRM_CFLAGS[1:0] (Table 435) parameter.
Reset
Default
0x000
00000
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
Table 336. FRM_HGR10, Transmit HDLC Global Register 10 (R/W)
Address
Bit
0x80149
15:5
4:0
Name
Function
—
Reserved. Must write to 0.
FRM_FCNT3[4:0] HDLC Flag Count 3. These values are the number of
additional idle flags to be sent between HDLC packets.
One of the four values can be selected on a per-channel
basis with the FRM_CFLAGS[1:0] parameter.
Reset
Default
0x000
00000
Table 337. FRM_HGR11, Transmit HDLC Global Register 11 (RO)
Address
Bit
Name
0x8014A
15:0
FRM_TH_IS[15:0]
Function
Transmit HDLC Interrupt Summary. This bitmap
shows what channels have interrupts. This register
maps channels 15—0 to bits 15:0.
Reset
Default
0x0000
Table 338. FRM_HGR12, Transmit HDLC Global Register 12 (R/W)
Address
Bit
Name
0x8014B
15:0
FRM_TH_IS[31:16]
Function
Transmit HDLC Interrupt Summary. This bitmap
shows what channels have interrupts. This register
maps channels 31—16 to bits 15:0.
Reset
Default
0x0000
Table 339. FRM_HGR13, Transmit HDLC Global Register 13 (R/W)
Address
Bit
Name
0x8014C
15:0
FRM_TH_IS[47:32]
Function
Transmit HDLC Interrupt Summary. This bitmap
shows what channels have interrupts. This register
maps channels 47—32 to bits 15:0.
Reset
Default
0x0000
Table 340. FRM_HGR14, Transmit HDLC Global Register 14 (R/W)
Address
Bit
Name
0x8014D
15:0
FRM_TH_IS[63:48]
Function
Transmit HDLC Interrupt Summary. This bitmap
shows what channels have interrupts. This register
maps channels 63—48 to bits 15:0.
Reset
Default
0x0000
Table 341. FRM_HGR15, Receive HDLC Global Register 15 (R/W)
Address
Bit
0x80040
15:10
9:0
Agere Systems Inc.
Name
Function
—
Reserved. Must write to 0.
FRM_HRTHRSH0[9:0] Indicates the Threshold Levels for the Rx FIFOs.
When a channel is enabled and its FIFO count increments to this value, its FRM_HRTHRSH (Table 443)
status bit is set. FRM_HRTHRSH0 or
FRM_HRTHRSH1 is selected on a per-channel basis
with the FRM_RTHRSEL (Table 442) parameter.
Reset
Default
0x00
0x000
255
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
12 28-Channel Framer Registers (continued)
Table 342. FRM_HGR16, Receive HDLC Global Register 16 (R/W)
Address
Bit
0x80041
15:10
9:0
Name
Function
—
Reserved. Must write to 0.
FRM_HRTHRSH1[9:0] Indicates the Threshold Levels for the Rx FIFOs.
When a channel is enabled and its FIFO count increments to this value, its FRM_HRTHRSH status bit is
set. FRM_HRTHRSH0[9:0] or FRM_HRTHRSH1[9:0]
is selected on a per-channel basis with the
FRM_RTHRSEL (Table 442) parameter.
Reset
Default
0x00
0x000
Table 343. FRM_HGR17, Receive HDLC Global Register 17 (R/W)
Address
Bit
Name
0x80042
15:0
FRM_RH_IS[15:0]
Function
Receive HDLC Interrupt Summary. This bitmap
shows what channels have interrupts. This register
maps channels 15—0 to bits 15:0.
Reset
Default
0
Table 344. FRM_HGR18, Receive HDLC Global Register 18 (R/W)
Address
Bit
Name
Function
0x80043
15:0
FRM_RH_IS[31:16]
Receive HDLC Interrupt Summary. This bitmap
shows what channels have interrupts. This register
maps channels 31—16 to bits 15:0.
Reset
Default
0
Table 345. FRM_HGR19, Receive HDLC Global Register 19 (R/W)
Address
Bit
Name
Function
0x80044
15:0
FRM_RH_IS[47:32]
Receive HDLC Interrupt Summary. This bitmap
shows what channels have interrupts. This register
maps channels 47—32 to bits 15:0.
Reset
Default
0
Table 346. FRM_HGR20, Receive HDLC Global Register 20 (R/W)
Address
Bit
Name
Function
0x80045
15:0
FRM_RH_IS[63:48]
Receive HDLC Interrupt Summary. This bitmap
shows what channels have interrupts. This register
maps channels 63—48 to bits 15:0.
256
Reset
Default
0
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
12.5 System Interface Global Registers
Table 347. FRM_SYSGR1, System Interface Global Register 1 (R/W)
Address
0x80050
Bit
Name
Function
15:12 FRM_SYSMOD[3:0] System Interface Mode Associated Signaling Mode.
0000 = 2.048 Mbits/s CHI.
0001 = 4.096 Mbits/s CHI.
0010 = 8.192 Mbits/s CHI.
0100 = 19.44 Mbits/s PSB (device 0 mode).
0101 = 19.44 Mbits/s PSB (device 1 mode).
0110 = 19.44 Mbits/s PSB (device 2 mode).
1000 = SMI.
All others: Reserved.
11
FRM_ASM
System Interface Mode Associated Signaling Mode.
0 = CHI is configured to carry payload data only.
Reset
Default
0000
0
In PSB mode, transmit signaling is 3-stated, and receive signaling ignored.
1 = CHI is configured to carry both payload data and signaling
information. Each time slot consists of 16 bits where 8 bits are
data and the remaining 8 bits are signaling information. CHI
must be programmed for 4.096 Mbits/s or 8.192 Mbits/s
modes.
10
FRM_CMS
In PSB mode, transmit signaling is driven and receive signaling
is forwarded to the signaling block.
CHI Clock Mode. This bit is only applicable in the CHI mode.
Otherwise, it should be set to 0.
0
0 = CHI clock and CHI data have the same rate.
1 = CHI clock is twice the rate of CHI data.
9
FRM_CHIDTS
CHI Dual Time-Slot Mode. This bit is only applicable in the
CHI 4.096 Mbits/s (no ASM) and 8.192 Mbits/s (without ASM)
modes.
0
0 = Enables 32 contiguous time slots.
1 = Enables double time slot mode in which the transmit CHI
drives data for one time slot and 3-states for the subsequent
time slot.
8
FRM_STUFFL/
FRM_LNKSTART
Stuff Position/Link Start. CHI modes only: determines the
position of the stuffed time slots in conjunction with the byte offset.
0 = SDDDSDDDSDDDS.. . . . . . . (TS0—TS31).
1
1 = SDDDDDD. . . . . . . SSSSSSS (TS0—TS31).
NSMI modes only: this bit determines how links are numbered
on the NSMI. Internally, links are numbered starting at 1.
0 = NSMI link numbering starts at 0.
1 = NSMI link numbering starts at 1.
Agere Systems Inc.
257
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
12 28-Channel Framer Registers (continued)
Table 347. FRM_SYSGR1, System Interface Global Register 1 (R/W) (continued)
Address
Bit
Name
0x80050
7
FRM_AISLFA
6
5
Function
System AIS on Loss of Frame Alignment.
0 = No action.
1 = System AIS is transmitted when the receive framer or the mapper
loss of frame alignment (MFA for DS1, BFA for CEPT) is detected.
FRM_AISCRCT System AIS on CEPT Timer Expiration.
0 = No action.
1 = System AIS is transmitted when the receive framer loss of multiframe
alignment timer expiration is detected. (CEPT only.)
FRM_DNOTFAS CEPT Dual Not FAS. This bit is applicable in all system modes.
Reset
Default
0
0
0
0 = FAS and NOTFAS time slots are transmitted to the system. The
receive system interface expects both FAS and NOTFAS time slots.
4
FRM_TFSCKE
1 = NOTFAS is transmitted twice to the system (in the NOTFAS and FAS
time slots). The receive system expects time slots 0 to carry
NOTFAS that is repeated twice.
System Interface Transmit Frame Sync Clock Edge Select.
0
0 = Transmit frame sync is sampled on the falling edge of transmit clock.
1 = Transmit frame sync is sampled on the rising edge of transmit clock.
3
FRM_FSPOL
In PSB mode, this bit also determines the clock edge used to drive
data. The sampling point of transmit frame sync defines the zero offset for CHI mode.
Frame Sync Polarity.
0
0 = Transmit and receive frame sync is active low.
2:0
—
1 = Transmit and receive frame sync is active-high.
Reserved. Must write to 0.
0
Table 348. FRM_SYSGR2, System Interface Global Register 2 (R/W)
Address
Bit
0x80051
15
Name
Function
FRM_HWYENA Transmit System Interface Highway Enable.
0 = Transmit data is forced into a high-impedance state for all
transmitted time slots. Receive system ignores receive data and
inserts the idle code in all time slots transmitted to the line. This
allows the framer to be fully configured before transmission.
Reset
Default
0
1 = Transmit and receive data is enabled.
14
0
FRM_RSTDONE Framer Reset Status.
0 = Indicates internal reset is still in process.
(Read Only)
1 = Indicates internal reset is complete.
13:0
258
—
Generally, the FRM_HWYENA bit should not be set to1 until this bit
reads 1.
Reserved. Must write to 0.
0
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
Table 349. FRM_SYSGR3, System Interface Global Register 3 (R/W)
Address
Bit
0x80052
15:8
7:0
Name
Function
FRM_STUFF[7:0] Stuffed Time-Slot Code.
FRM_IDLE[7:0] CHI Time-Slot Loopback Idle Code.
Reset
Default
7F
7F
Table 350. FRM_SYSGR4, System Interface Global Register 4 (R/W)
Address
Bit
Name
0x80053
15
FRM_STSSLB
CHI Time Slot System Loopback
FRM_STSLLB
0 = No action.
1 = Receive CHI time slot is looped back to the system.
Idle code, FRM_IDLE[7:0] (Table 349), is inserted in place
of the looped back time slot to the line.
CHI Time-Slot Line Loop Back.
14
Function
Reset
Default
0
0
0 = No action.
13
12:8
7:5
4:0
1 = Transmit CHI time slot is looped back to the line. Idle
code, FRM_IDLE[7:0], is inserted in place of the looped
back time slot to the system.
Reserved. Must write to 0.
—
FRM_TSLBA[4:0] CHI Time-Slot Loopback Address.
Reserved. Must write to 0.
—
FRM_TSLBL[4:0] CHI Time-Slot Loopback Link Number.
0
00000
0
00000
Table 351. FRM_SYSGR5, System Interface Global Register 5 (R/W)
Address
Bit
0x80054
15
14
13:0
Name
Function
FRM_TS_DPAR Transmit PSB Data Parity. This bit is only applicable in the
parallel system bus mode. Otherwise, it should be set to
zero.
0 = Odd data parity is transmitted by the system.
1 = Even data parity is transmitted by the system.
FRM_TS_SPAR Transmit Signaling Parity. This bit applies to the signaling
information in the parallel system bus mode. It also determines the parity for CHI ASM mode. Otherwise, it should be
set to 0.
0 = Odd signaling parity is transmitted by the system.
1 = Even signaling parity is transmitted by the system.
Reserved. Must write to 0.
—
Reset
Default
0
0
0
Table 352. FRM_SYSGR6, System Interface Global Register 6 (COR)
Address
Bit
Name
0x80055
15:0
—
Agere Systems Inc.
Function
Reserved. Must write to 0.
Reset
Default
0x0000
259
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
12 28-Channel Framer Registers (continued)
Table 353. FRM_SYSGR7, System Interface Global Register 7 (COR)
Address
Bit
Name
Function
0x80056
15:1
0
—
FRM_TPSB_FS_IS
Reset
Default
Reserved. Must write to 0.
0x0
0
Transmit PSB Frame Sync Error Interrupt. A 1 indicates a frame sync error was detected in PSB mode.
The frame sync was either detected when it should
not have been (misplaced) or was not detected when
it should have (missing). This bit is cleared on read/
write unless the condition that set it still exists after
the read.
Table 354. FRM_SYSGR8, System Interface Global Register 8 (R/W)
Address
Bit
Name
0x80057
15:1
0
—
FRM_PSB_FS_IM
Function
Reserved. Must write to 0.
Transmit PSB Frame Sync Interrupt Mask. A 1 prevents the FRM_TPSB_FS_IS (Table 353) status from
causing an interrupt. A 0 allows the interrupt.
Reset
Default
0
1
Table 355. FRM_SYSGR9, System Interface Global Register 9 (R/W)
Address
Bit
0x80150
15
14
13
12:0
260
Name
Function
FRM_RS_DPAR Receive PSB Data Parity Select. This bit is only applicable in
the parallel system bus interface mode. Otherwise, it should
be set to 0.
0 = Odd data parity is expected by the receive system.
1 = Even data parity is expected by the receive system.
FRM_RS_SPAR Receive Signaling Parity Select. This bit applies to the signaling information in the parallel system bus mode. It also
determines the parity for CHI ASM mode. Otherwise, it should
be set to 0.
0 = Odd signaling parity is expected by the receive system.
1 = Even signaling parity is expected by the receive system.
FRM_RFSCKE System Interface Receive Frame Sync Clock Edge Select.
0 = Receive frame sync (and data) is sampled on the falling
edge of receive clock.
1 = Receive frame sync (and data) is sample on the rising
edge of receive clock.
In parallel system bus mode, this bit also determines the clock
edge used to sample data.
In CHI mode, the sample point of frame sync defines the zero
offset for the CHI.
—
Reserved. Must write to 0.
Reset
Default
0
0
0
0
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
Table 356. FRM_SYSGR10—FRM_SYSGR14, System Interface Global Register 10—14 (R/W)
Address
Bit
Name
0x80151
—
0x80155
15:0
—
Function
Reserved. Must write to 0.
Reset
Default
0x0000
Table 357. FRM_SYSGR15, System Interface Global Register 15 (COR)
Address
Bit
Name
0x80156
15
FRM_DPAR_IS
14
FRM_SPAR_IS
13:1
0
—
FRM_PSB_FS_IS
Function
Reset
Default
Data Parity Interrupt. In PSB mode, a 1 indicates a data parity
0
error was detected. This bit is cleared on read unless the condition that set it still exists after the read.
0
Signaling Parity Interrupt. In PSB mode, a 1 indicates a signaling parity error was detected. In CHI ASM mode, a 1 indicates a parity error was detected.
This bit is cleared on read unless the condition that set it still
exists after the read.
Reserved. Must write to 0.
0
0
Receive PSB frame Sync Interrupt. A 1 indicates a frame
sync error was detected in PSB mode. The frame sync was
either detected when it should not have been (misplaced) or
was not detected when it should have (missing). This bit is
cleared on read unless the condition that set it still exists after
the read.
Table 358. FRM_SYSGR16, System Interface Global Register 16 (R/W)
Address
Bit
Name
0x80157
15
FRM_DPAR_IM
14
13:1
0
Agere Systems Inc.
Function
Data Parity Interrupt Mask. A 1 prevents the FRM_DPAR_IS
status from causing an interrupt. A 0 allows the interrupt.
FRM_SPAR_IM
Signaling Parity Interrupt Mask. A 1 prevents the
FRM_SPAR_IS status from causing an interrupt. A 0 allows the
interrupt.
—
Reserved. Must write to 0.
FRM_PSB_FS_IM Receive PSB frame Sync Interrupt Mask. A 1 prevents the
FRM_PSB_FS_IS status from causing an interrupt. A 0 allows
the interrupt.
Reset
Default
1
1
0
1
261
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
12 28-Channel Framer Registers (continued)
12.6 Signaling Global Registers
Table 359. FRM_SGR1, Receive Signaling Global Register 1 (R/W)
Address
Bit
Name
0x80060
15
FRM_R_TSAISHG
14:10
9
8:6
5:2
1
0
Function
System AIS for Handling Groups. When set to 1, this
configuration bit forces AIS to the system interface for
those signaling bits which correspond to a handling group,
which is out of alignment. A 0 disables this feature. This
feature is only applied to those links which are enabled for
byte sync mapping and handling groups using the per-link
signaling configuration registers.
FRM_R_LINKCNT[4:0] Receive Link Count. Indicates the number of links serviced by the signaling block. This value should be set to 28
when the Super Mapper is interfacing with only DS1 links;
it should be set to the actual number of links active for
mixed mode applications.
—
Reserved. Must write to 0.
FRM_TEST_BIT[2:0] Test Bits.
—
Reserved. Must write to 0.
FRM_R_AFZFBE
Automatic Signaling Freeze on Framing Bit Errors. Set
to 1 in order to freeze signaling register updates based on
framing bit errors.
—
Reserved. Must write to 0.
Reset
Default
0
28
0
000
0
0
Table 360. FRM_SGR2, Receive Signaling Global Register 2 (R/W)
Address
Bit
0x80061
15
14:10
9:0
262
Name
Function
Reset
Default
0
FRM_R_SCOSEN Receive Signaling Change of State FIFO Enable. When set
to 1, this configuration bit enables the maintenance of the signaling change of state FIFO. When set to 0, no entries will be
made into the FIFO. This bit applies to all of the links. If an
individual time slot is programmed for no signaling, then no
entries will be made for that time slot. Also, if the signaling
source in the receive path is set to host, then no entries will be
made for that time slot.
—
Reserved. Must write to 0.
0
0
FRM_R_
Receive Signaling Change of State FIFO Depth Threshold.
SCOSDTH[9:0]
This number can be programmed from 0 to 672. If the number
of entries in the signaling change of state FIFO exceeds the
value programmed here, then the associated interrupt status
bit will be set.
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
Table 361. FRM_SGR3, Receive Signaling Global Register 3 (R/W)
Address
Bit
0x80062
15:0
Name
Function
Reset
Default
0x0000
FRM_
Receive Signaling Change of State FIFO Timer Threshold.
R_SCOSTTH[15:0] This number can be programmed from 0 to 0xFFFF. The value
indicates the number of 125 µs increments that the timer
counts before interrupting the processor. The associated interrupt status bit will be set only if there are valid entries in the
FIFO. When set to 0, the timer is disabled and no interrupt will
be generated. The maximum timer setting is 8 s.
Table 362. FRM_SGR4, Receive Signaling Global Register 4 (RO)
Address
Bit
Name
0x80063
15:14
FRM_
R_COSFIFOS[1:0]
13:9
8:4
3:0
Function
Receive Signaling Change of State FIFO Status. These
bits are located at the address for the signaling change of
state FIFO. These status bits have the following definitions:
01 = The entry being read is the last valid entry.
11 = The entry being read is not the last valid entry.
00 = The entry being read is not valid and should be ignored.
FRM_
COS Link Number. These bits are located at the address for
R_COSFIFOL[4:0] the signaling change of state FIFO. This number indicates
the particular link from which a signaling change of state has
been detected.
FRM_
COS Time-Slot Number. These bits are located at the
R_COSFIFOTS[4:0] address for the signaling change of state FIFO. This number
indicates the particular time slot in which a signaling change
of state has been detected.
FRM_
New Signaling Code. These bits are located at the address
R_COSFIFOSIG[3:0] for the signaling change of state FIFO. This value indicates
the new signaling state received.
Reset
Default
0
0
0
0
Table 363. FRM_SGR5, Receive Signaling Global Register 5 (RO)
Address
Bit
Name
Function
0x80064
15:1
0
—
FRM_
R_COSDTHS
Reserved.
Receive Signaling Change of State FIFO Depth Threshold
Overflow Status. This status bit reflects the actual depth of the
FIFO entries as compared to the threshold programmed by the
host. When set to 1, the threshold is currently exceeded. When
set to 0, the number of FIFO entries is less than the programmed
threshold.
Agere Systems Inc.
Reset
Default
0X0000
0
263
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
12 28-Channel Framer Registers (continued)
Table 364. FRM_SGR6, Receive Signaling Global Register 6
Address
Bit
0x80065
15:3
2
1
0
Name
Function
Reserved. Reads 0.
—
FRM_R_COSDTHI Receive Signaling Change of State FIFO Depth Threshold
Overflow Interrupt. This interrupt status bit will be set when
the programmed threshold for the FIFO capacity has been
exceeded. This interrupt bit can be reset based on a clear-onread protocol, which is provisioned in the Super Mapper global
registers.
FRM_R_COSTTHI Receive Signaling Change of State FIFO Timer Threshold
Interrupt. This interrupt status bit will be set when the programmed interrupt timer has expired and there are valid entries
in the FIFO to be processed. This interrupt bit can be reset
based on a clear-on-read protocol, which is provisioned in the
Super Mapper global registers.
FRM_R_COSOFI Receive Signaling Change of State FIFO Overflow Interrupt. This interrupt status bit will be set when the signaling
change of state FIFO overflows. The contents of the FIFO will
be lost and programmed threshold for the FIFO capacity has
been exceeded. This interrupt bit can be reset based on a
clear-on-read protocol, which is provisioned in the Super Mapper global registers.
Reset
Default
0
0
0
0
Table 365. FRM_SGR7, Receive Signaling Global Register 7 (R/W)
Address
Bit
0x80066
15:3
2
1
0
264
Name
Function
Reserved. Reads 0.
—
FRM_
Receive Signaling Change of State FIFO Depth Threshold
R_COSDTHM Overflow Interrupt Mask. The corresponding interrupt status bit
will cause a processor interrupt if this bit is set to 0. The corresponding interrupt status bit will be masked from causing a processor interrupt if this bit is set to 1.
FRM_
Receive Signaling Change of State FIFO Timer Threshold
R_COSTTHM Interrupt Mask. The corresponding interrupt status bit will cause
a processor interrupt if this bit is set to 0. The corresponding
interrupt status bit will be masked from causing a processor interrupt if this bit is set to 1.
FRM_
Receive Signaling Change of State FIFO Overflow Interrupt
R_COSOFM Mask. The corresponding interrupt status bit will cause a processor interrupt if this bit is set to 0. The corresponding interrupt status bit will be masked from causing a processor interrupt if this bit
is set to 1.
Reset
Default
0
1
1
1
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
Table 366. FRM_SGR8, Transmit Signaling Global Register 8 (R/W)
Address
Bit
Name
0x80160
15
—
Function
Reset
Default
Reserved. Must write to 0.
0
14:10 FRM_T_LINKCNT[4:0] Transmit Link Count. Indicates the number of links serviced by the signaling block. This value should be set to 28
when the Super Mapper is interfacing with only DS1 links; it
should be set to the actual number of links active for mixed
mode applications.
28
9:6
—
5
FRM_T_SUBZERO
4
Reserved. Must write to 0.
0000
Substitute Zero. A 1 forces signaling data to be 0000 for
those time slots which have a signaling state mode of no
signaling. This only applies to the signaling data transferred
to the VT mapper.
0
FRM_T_FAS_NOTFAS FAS/NOTFAS Transmission. Used to force alignment of
the CEPT TS16 multiframe to a FAS or NOTFAS frame. A 0
indicates alignment to a FAS frame. A 1 indicates alignment
to a NOTFAS frame.
0
3:2
—
1
FRM_T_AFZFBE
0
—
Agere Systems Inc.
Reserved. Must write to 0.
00
Automatic Signaling Freeze on Framing Bit Errors. Set
to 1 in order to freeze signaling register updates based on
framing bit errors.
0
Reserved. Must write to 0.
0
265
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
12 28-Channel Framer Registers (continued)
12.7 Frame Formatter (Transmit Framer) Global Register
Table 367. FRM_FFGR1, Transmit Framer Global Register 1 (R/W)
Address
Bit
Name
0x80170
15
FRM_TXFSOOF
14:12
11
10
9
8:4
3:0
266
Function
Transmit Frame Sync when Out-Of-Frame Valid in
Transport Modes Only.
0 = Do not transmit FS when out-of-frame. (FS is
present when in frame.)
1 = Transmit an arbitrary FS when out-of-frame.
—
Reserved. Must write to 0.
FRM_PTRN_EN
Transmit Pattern.
0 = Pattern generator off.
1 = Pattern generator on.
FRM_PTRN_INV
Transmit Pattern Normal/Invert Mode.
This bit inverts the pattern.
0 = Normal.
1 = Invert.
FRM_PTRN_FRMT Transmit Pattern Framed/Unframed Mode.
This bit selects either a framed (1) or unframed (0) pattern.
FRM_PTRN_LNK[4:0] Pattern Generator Link Select.
5-bit link selection to indicate link for pattern insertion.
FRM_PTRN_SEL[3:0] Transmit Pattern Select.
0000 = Pattern generator deactivated.
0001 = MARK (all ones AIS).
0010 = QRSS (2 20 – 1 with zero suppression).
0011 = 25 – 1.
0100 = 63 (2 65 – 1).
0101 = 511(2 9 – 1)(V.52).
0110 = 29 – 1.
0111 = 2047 (2 11 – 1) (O.151).
1000 = 211 – 1 (reversed).
1001 = 215 – 1 (O.151).
1010 = 220 – 1 (V.57).
1011 = 220 – 1 (CB113/CB114).
1100 = 223 – 1 (O.151).
1101 = 1:1 (alternating).
1110 = Reserved.
1111 = Reserved.
Reset
Default
0
0
0
0
0
00001
0000
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
12.8 Facility Data Link Global Registers
Table 368. FRM_FDLGR1, Receive Facility Data Link Global Register 1 (R/W)
Address
Bit
Name
0x80090
15:0
—
Function
Reset
Default
0x0000
Reserved. Must write to 0.
Table 369. FRM_FDLGR2, Transmit Facility Data Link Global Register 2 (R/W)
Address
Bit
Name
0x801A1
15:0
—
Function
Reset
Default
0x0000
Reserved. Must write to 0.
12.9 Super Mapper Framer Per Link Configuration and Status Registers
12.9.1 Signaling Per Link Registers
Table 370. Receive Path Signaling Register Addressing Map
Address Pins (ADDR15—ADDR0)
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0 LNK4 LNK3 LNK2 LNK1 LNK0 RXP = 0 0 SIG6 SIG5 SIG4 SIG3 SIG2 SIG1 SIG0
L*
R*
—
15
0
* L and R represent hexidecimal digits used for absolute addressing in Table 372, Table 373, and Table 374.
Table 371. Receive Path Signaling Registers Address Indexing
Read: for link 1, the hexidecimal digit L is 0x0 and the hexidecimal digit R is 0x2.
Link
L
R
Link
L
R
Link
L
R
Link
L
R
1
0x0
0x2
8
0x1
0x0
16
0x2
0x0
24
0x3
0x0
2
0x0
0x4
9
0x1
0x2
17
0x2
0x2
25
0x3
0x2
3
0x0
0x6
10
0x1
0x4
18
0x2
0x4
26
0x3
0x4
4
0x0
0x8
11
0x1
0x6
19
0x2
0x6
27
0x3
0x6
5
0x0
0xA
12
0x1
0x8
20
0x2
0x8
28
0x3
0x8
6
0x0
0xC
13
0x1
0xA
21
0x2
0xA
—
—
—
7
0x0
0xE
14
0x1
0xC
22
0x2
0xC
—
—
—
—
—
—
15
0x1
0xE
23
0x2
0xE
—
—
—
Agere Systems Inc.
267
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
12 28-Channel Framer Registers (continued)
Table 372. FRM_RSLR0—FRM_RSLR31, Receive Signaling Link Registers 0—31 (R/W)
Address*
Bit
Name
0x8LR00
0x8LR01
0x8LR02
0x8LR03
0x8LR04
0x8LR05
0x8LR06
0x8LR07
0x8LR08
0x8LR09
0x8LR0A
0x8LR0B
0x8LR0C
0x8LR0D
0x8LR0E
0x8LR0F
0x8LR10
0x8LR11
0x8LR12
0x8LR13
0x8LR14
0x8LR15
0x8LR16
0x8LR17
0x8LR18
0x8LR19
0x8LR1A
0x8LR1B
0x8LR1C
0x8LR1D
0x8LR1E
0x8LR1F
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
FRM_RPSR0[6:0]
FRM_RPSR1[6:0]
FRM_RPSR2[6:0]
FRM_RPSR3[6:0]
FRM_RPSR4[6:0]
FRM_RPSR5[6:0]
FRM_RPSR6[6:0]
FRM_RPSR7[6:0]
FRM_RPSR8[6:0]
FRM_RPSR9[6:0]
FRM_RPSR10[6:0]
FRM_RPSR11[6:0]
FRM_RPSR12[6:0]
FRM_RPSR13[6:0]
FRM_RPSR14[6:0]
FRM_RPSR15[6:0]
FRM_RPSR16[6:0]
FRM_RPSR17[6:0]
FRM_RPSR18[6:0]
FRM_RPSR19[6:0]
FRM_RPSR20[6:0]
FRM_RPSR21[6:0]
FRM_RPSR22[6:0]
FRM_RPSR23[6:0]
FRM_RPSR24[6:0]
FRM_RPSR25[6:0]
FRM_RPSR26[6:0]
FRM_RPSR27[6:0]
FRM_RPSR28[6:0]
FRM_RPSR29[6:0]
FRM_RPSR30[6:0]
FRM_RPSR31[6:0]
Function
Reset
Default
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
Time Slot 0 Receive Signaling Data.
Time Slot 1 Receive Signaling Data.
Time Slot 2 Receive Signaling Data.
Time Slot 3 Receive Signaling Data.
Time Slot 4 Receive Signaling Data.
Time Slot 5 Receive Signaling Data.
Time Slot 6 Receive Signaling Data.
Time Slot 7 Receive Signaling Data.
Time Slot 8 Receive Signaling Data.
Time Slot 9 Receive Signaling Data.
Time Slot 10 Receive Signaling Data.
Time Slot 11 Receive Signaling Data.
Time Slot 12 Receive Signaling Data.
Time Slot 13 Receive Signaling Data.
Time Slot 14 Receive Signaling Data.
Time Slot 15 Receive Signaling Data.
Time Slot 16 Receive Signaling Data.
Time Slot 17 Receive Signaling Data.
Time Slot 18 Receive Signaling Data.
Time Slot 19 Receive Signaling Data.
Time Slot 20 Receive Signaling Data.
Time Slot 21 Receive Signaling Data.
Time Slot 22 Receive Signaling Data.
Time Slot 23 Receive Signaling Data.
Time Slot 24 Receive Signaling Data.
Time Slot 25 Receive Signaling Data.
Time Slot 26 Receive Signaling Data.
Time Slot 27 Receive Signaling Data.
Time Slot 28 Receive Signaling Data.
Time Slot 29 Receive Signaling Data.
Time Slot 30 Receive Signaling Data.
Time Slot 31 Receive Signaling Data.
* See Table 371 for values of L and R.
Notes:Bit 0 = A, bit 1 = B, bit 2 = C, bit 3 = D, bit 5 = F, and bit 6 = G.
Register includes the following bits: F, G—selects 2, 4, 16 or no state signaling mode; A, B, C, D—signaling data.
For DS1 links, address locations 1 through 24 will contain valid data.
For CEPT links, locations 1 through 15 and 17 through 31 will contain valid data. Writes from the system interface to address 0 and 16 will
be accepted and stored in signaling registers.
268
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
Table 373. FRM_RSLR32, Receive Signaling Link Register 32 (COR)
Address*
Bit
Name
0x8LR20
15:12
11:8
7:4
3
2
1:0
Function
FRM_R_HGAIS[3:0] HG AIS Detection. Indicates the detection of AIS in the
corresponding HG.
FRM_R_HGA[3:0] HG Alignment. Indicates the alignment status for the corresponding HG. A 0 indicates no alignment. A 1 indicates
alignment for the corresponding group.
FRM_R_HGRDI[3:0] HG RDI. Indicates the detection of three consecutive
zeros in the Sp bit position of the corresponding HG.
FRM_R_TS16A
Time Slot 16 Multiframe Alignment Status. A 0 indicates that currently, time slot 16 multiframe alignment is
not established. A1 indicates that currently, time slot 16
multiframe alignment has been established.
FRM_R_TS16AIS Time Slot 16 AIS Detection Status. If time slot 16 multiframe alignment is lost, this bit will reflect the detection of
AIS in time slot 16.
—
Reserved. Must write to 0.
Reset
Default
0000
0000
0000
0
0
0
* See Table 371 for values of L and R.
Table 374. FRM_RSLR33, Receive Signaling Link Register 33 (R/W)
Address* Bit
0x8LR21
Name
Function
15
FRM_R_FZCON
14:9
8
—
FRM_R_SIGI
7
FRM_R_RXSTOMP
6
5
—
FRM_R_SIGDEB
4
FRM_R_HGEN
3
FRM_R_MSIGFZ
Freeze Conversion. When set to1, this enables the conversion of certain signaling codes when the signaling buffers
have been frozen. The code translation is 00 to 01 and 0000
to 0101 for 4-state and 16-state signaling, respectively.
Reserved. Must write to 0.
Signaling Insertion. A 1 enables the insertion of signaling
data into the Tx line. A 0 disables the insertion of signaling
data into the Tx line. This bit is valid in the Rx path only when
in transport mode; otherwise, it should be set to 0.
Rx Path Stomping. For DS1 links, this bit indicates to stomp
all robbed bit signaling on voice time slots on the corresponding link. Stomping of time slot 16 for CEPT links is performed
in the system interface block.
1 = Will enable stomping.
0 = Will disable stomping for the corresponding link.
Reserved. Must write to 0.
Signaling Debounce.This bit enables signal debounce on
signaling when extracted from the Rx line.
Handling Group Enable. When set to 1 in combination with
selecting the source of signaling data to be the VT mapper,
this indicates to the signaling block that the signaling for this
link is byte sync mapped and uses the handling group format.
Manual Signaling Freeze. Used to manually halt the signaling register updates when the source of signaling data is
either the VT mapper or when the signaling is extracted from
the Rx line. A 1 halts the updates.
Agere Systems Inc.
Reset
Default
0
0
0
0
0
0
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TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
June
May 2001
12 28-Channel Framer Registers (continued)
Table 374. FRM_RSLR33, Receive Signaling Link Register 33 (R/W) (continued)
Address* Bit
0x8LR21
2
1:0
Name
Function
FRM_R_FGSRC
F and G Source. Indicates which entity will be the source for
the F and G values used in handling the ABCD bits.
0 = Host programmed.
1 = Implied by the Tx path ASM.
The Tx path option can only be selected when the Tx path is
configured with an ASM CHI or parallel system bus interface.
Also, the Tx path option can only be selected when the Rx
path is extracting data from the receive line interface vs. byte
sync VT mapped mode.
FRM_R_SIGSRC[1:0] Signaling Data Source. Indicates which of the entities will be
the source for the ABCD bits.
00 = Signaling programmed by the host.
01 = Signaling extracted from the Rx line.
10 = Signaling read from VT mapper in byte sync mode (valid
only for DS1).
Reset
Default
0
00
* See Table 371 for values of L and R.
Table 375. Transmit Path Signaling Register Addressing Map
15
0
14
0
Address Pins (ADDR15—ADDR0)
13
12
11
10
9
8
7
6
5
4
3
LNK4 LNK3 LNK2 LNK1 LNK0 TXP=1 0 SIG6 SIG5 SIG4 SIG3
L*
T*
—
2
1
0
SIG2 SIG1 SIG0
* L and T represent hexidecimal digits used for absolute addressing in Table 377, Table 378, and Table 379.
Read: for link 1 (pertaining to Table 376), the hexidecimal digit L is 0x0 and the hexidecimal digit T is 0x3 .
Table 376. Transmit Path Signaling Registers Address Indexing
Link
L
T
Link
L
T
Link
L
T
Link
L
T
1
0x0
0x3
8
0x1
0x1
16
0x2
0x1
24
0x3
0x1
2
0x0
0x5
9
0x1
0x3
17
0x2
0x3
25
0x3
0x3
3
0x0
0x7
10
0x1
0x5
18
0x2
0x5
26
0x3
0x5
4
0x0
0x9
11
0x1
0x7
19
0x2
0x7
27
0x3
0x7
5
0x0
0xB
12
0x1
0x9
20
0x2
0x9
28
0x3
0x9
6
0x0
0xD
13
0x1
0xB
21
0x2
0xB
—
—
—
7
0x0
0xF
14
0x1
0xD
22
0x2
0xD
—
—
—
—
—
—
15
0x1
0xF
23
0x2
0xF
—
—
—
270
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
Table 377. FRM_TSLR0—FRM_TSLR31, Transmit Signaling Link Registers 0—31 (R/W)
Address*
Bit
Name
0x8LT00
0x8LT01
0x8LT02
0x8LT03
0x8LT04
0x8LT05
0x8LT06
0x8LT07
0x8LT08
0x8LT09
0x8LT0A
0x8LT0B
0x8LT0C
0x8LT0D
0x8LT0E
0x8LT0F
0x8LT10
0x8LT11
0x8LT12
0x8LT13
0x8LT14
0x8LT15
0x8LT16
0x8LT17
0x8LT18
0x8LT19
0x8LT1A
0x8LT1B
0x8LT1C
0x8LT1D
0x8LT1E
0x8LT1F
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
FRM_TPSR0[6:0]
FRM_TPSR1[6:0]
FRM_TPSR2[6:0]
FRM_TPSR3[6:0]
FRM_TPSR4[6:0]
FRM_TPSR5[6:0]
FRM_TPSR6[6:0]
FRM_TPSR7[6:0]
FRM_TPSR8[6:0]
FRM_TPSR9[6:0]
FRM_TPSR10[6:0]
FRM_TPSR11[6:0]
FRM_TPSR12[6:0]
FRM_TPSR13[6:0]
FRM_TPSR14[6:0]
FRM_TPSR15[6:0]
FRM_TPSR16[6:0]
FRM_TPSR17[6:0]
FRM_TPSR18[6:0]
FRM_TPSR19[6:0]
FRM_TPSR20[6:0]
FRM_TPSR21[6:0]
FRM_TPSR22[6:0]
FRM_TPSR23[6:0]
FRM_TPSR24[6:0]
FRM_TPSR25[6:0]
FRM_TPSR26[6:0]
FRM_TPSR27[6:0]
FRM_TPSR28[6:0]
FRM_TPSR29[6:0]
FRM_TPSR30[6:0]
FRM_TPSR31[6:0]
Function
Time Slot 0 Transmit Signaling Data.
Time Slot 1 Transmit Signaling Data.
Time Slot 2 Transmit Signaling Data.
Time Slot 3 Transmit Signaling Data.
Time Slot 4 Transmit Signaling Data.
Time Slot 5 Transmit Signaling Data.
Time Slot 6 Transmit Signaling Data.
Time Slot 7 Transmit Signaling Data.
Time Slot 8 Transmit Signaling Data.
Time Slot 9 Transmit Signaling Data.
Time Slot 10 Transmit Signaling Data.
Time Slot 11 Transmit Signaling Data.
Time Slot 12 Transmit Signaling Data.
Time Slot 13 Transmit Signaling Data.
Time Slot 14 Transmit Signaling Data.
Time Slot 15 Transmit Signaling Data.
Time Slot 16 Transmit Signaling Data.
Time Slot 17 Transmit Signaling Data.
Time Slot 18 Transmit Signaling Data.
Time Slot 19 Transmit Signaling Data.
Time Slot 20 Transmit Signaling Data.
Time Slot 21 Transmit Signaling Data.
Time Slot 22 Transmit Signaling Data.
Time Slot 23 Transmit Signaling Data.
Time Slot 24 Transmit Signaling Data.
Time Slot 25 Transmit Signaling Data.
Time Slot 26 Transmit Signaling Data.
Time Slot 27 Transmit Signaling Data.
Time Slot 28 Transmit Signaling Data.
Time Slot 29 Transmit Signaling Data.
Time Slot 30 Transmit Signaling Data.
Time Slot 31 Transmit Signaling Data.
Reset
Default
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
* See Table 376 for values of L and T.
Notes:Bit 0 = A, bit 1 = B, bit 2 = C, bit 3 = D, bit 5 = F, and bit 6 = G.
Register includes the following bits: F, G—selects 2, 4, 16 or no state signaling mode; A, B, C, D—signaling data.
For DS1 links, address locations 1 through 24 will contain valid data.
For CEPT links, locations 1 through 15 and 17 through 31 will contain valid data. Writes from the system interface to address 0 and 16 will
be accepted and stored in signaling registers. For CEPT links, inserted time slot 16 X bits are written to locates 0.
Agere Systems Inc.
271
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
12 28-Channel Framer Registers (continued)
Table 378. FRM_TSLR32, Transmit Signaling Link Register 32 (R/W)
Address*
Bit
Name
Function
0x8LT21
15
14
—
FRM_T_ATS16RFA
13
12
—
FRM_T_ASPLB
11
FRM_T_MSP
10
FRM_T_ZCSM
9
FRM_T_VTSIGE
8
FRM_T_SIGI
7
6
—
FRM_T_TXSTOMP
5
4
—
FRM_T_HGEN
3
FRM_T_MSIGFZ
Reserved. Must write to 0.
Automatic TS16 Remote Frame Alarm. Enables automatic
transmission of a 1 in theY-bit position in the transmit path
when the receive path has lost TS16 alignment.
Reserved. Must write to 0.
Automatic Sp Loopback. When set, the Sp bit transmitted
for each individual HG will be set to 0 when the HG alignment is lost in the Rx path. Each Sp in the Tx path corresponds to the same HG in the Rx path.
Manual Sp. Used to manually force the transmission of a 0
in each of the Sp bits of the HGs on each link.
Zero Code Suppression Mode. When set to 1, the signaling block will give an indication to the frame formatter for
each of the data channels. This indication should disable the
zero-code suppression for the associated time slot. Signaling insertion must be enabled for FRM_T_ZCSM to take
effect. FRM_T_ZCSM will not work when byte sync mapping
is enabled.
VT Signaling Enable. A 1 enables the transport of signaling
to the VT mapper from the programmed signaling source in
byte sync mode. Byte sync mode cannot be enabled in conjunction with signaling insertion (bit 8, FRM_T_SIGI). The
robbed-bit positions can be stomped while in byte sync
mode but no signaling data can be inserted.
Signaling Insertion. A 1 enables the insertion of signaling
data into the Tx line. A 0 disables the insertion of signaling
data into the Tx line.
Reserved. Must write to 0.
Tx Path Stomping. For DS1 links, this bit indicates to stomp
all robbed-bit signaling on voice time slots on the corresponding link to 0. Stomping time slot 16 for CEPT links is
done by inserting all ones using the signaling registers. A 1
will enable stomping. A 0 will disable stomping for the corresponding link.
Reserved. Must write to 0.
Handling Group Enable. When set to 1 in combination with
(bit 9, FRM_T_VTSIGE), this bit indicates to the signaling
block that the signaling for this link is byte sync mapped and
uses the handling group format.
Manual Signaling Freeze. Used to manually halt the signaling register updates when the source of signaling data is
either the Rx system or the Rx line. A 1 halts the updates.
Reset
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
* See Table 376 for values of L and T.
272
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
Table 378. FRM_TSLR32, Transmit Signaling Link Register 32 (R/W) (continued)
Address*
Bit
Name
0x8LT21
2
FRM_T_FGSRC
1:0
Function
F and G Source. Indicates which entity will be the source for
the F and G values used in handling the ABCD bits.
0 = Host programmed.
1 = Sourced from the Rx system interface.
The F and G programming can be implied by the system
interface only when using the ASM CHI or the parallel system interface.
FRM_T_SIGSRC[1:0] Signaling Data Source. Indicates which of the entities will
be the source for the ABCD bits.
00 = Signaling programmed by the host.
01 = Signaling extracted from the Rx line.
10 = Signaling received from the system interface.
Reset
Default
0
00
* See Table 376 for values of L and T.
Table 379. FRM_TSLR33, Transmit Signaling Link Register 33 (COR)
Address*
Bit
Name
0x8LT20
15:4
3
—
FRM_T_TS16A
2
1:0
Function
Reserved. Must write to 0.
Time Slot 16 Multiframe Alignment Status. A 0 indicates
that currently, time slot 16 multiframe alignment is not established. A1 indicates that currently, time slot 16 multiframe
alignment has been established.
FRM_T_TS16AIS Time Slot 16 AIS Detection Status. If time slot 16 multiframe alignment is lost, this bit will reflect the detection of AIS
in time slot 16.
—
Reserved. Must write to 0.
Reset
Default
0x000
0
0
00
* See Table 376 for values of L and T.
12.10 Performance Monitor Per Link Registers
The following tables describe the functions of all bits in the register map. Counters are programmable to either rollover or saturate, and may be programmed to clear on read.
Registers are only provisionable to clear-on-read (COR).
For each address, the register bits are identified as either read/write (R/W) or read only (RO), and the value of the
bits on reset are given.
Table 380. Performance Monitor Per Link Register Addressing Map
15
0
Address Pins (ADDR15—ADDR0)
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0 LNK4 LNK3 LNK2 LNK1 LNK0
RXP = 0
1
0 PM5 PM4 PM3 PM2 PM1 PM0
TXP = 1
L*
P*
—
* L and P represent hexidecimal digits used for absolute addressing in Table 382 through Table 401.
Agere Systems Inc.
273
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
12 28-Channel Framer Registers (continued)
Table 381. Performance Monitor Per Link Register Address Indexing
Read: for link 1 on the receive path, the hexidecimal digit L is 0x0 and the hexidecimal digit P is 0x2.
Link
L
P
Link
1
2
3
4
5
6
7
—
0x0
0x0
0x0
0x0
0x0
0x0
0x0
—
0x2
0x4
0x6
0x8
0xA
0xC
0xE
—
8
9
10
11
12
13
14
15
1
2
3
4
5
6
7
—
0x0
0x0
0x0
0x0
0x0
0x0
0x0
—
0x3
0x5
0x7
0x9
0xB
0xD
0xF
—
8
9
10
11
12
13
14
15
L
P
Link
L
Receive Path (P is even)
0x1
0x0
16
0x2
0x1
0x2
17
0x2
0x1
0x4
18
0x2
0x1
0x6
19
0x2
0x1
0x8
20
0x2
0x1
0xA
21
0x2
0x1
0xC
22
0x2
0x1
0xE
23
0x2
Transmit Path (P is odd))
0x1
0x1
16
0x2
0x1
0x3
17
0x2
0x1
0x5
18
0x2
0x1
0x7
19
0x2
0x1
0x9
20
0x2
0x1
0xB
21
0x2
0x1
0xD
22
0x2
0x1
0xF
23
0x2
P
Link
L
P
0x0
0x2
0x4
0x6
0x8
0xA
0xC
0xE
24
25
26
27
28
—
—
—
0x3
0x3
0x3
0x3
0x3
—
—
—
0x0
0x2
0x4
0x6
0x8
—
—
—
0x1
0x3
0x5
0x7
0x9
0xB
0xD
0xF
24
25
26
27
28
—
—
—
0x3
0x3
0x3
0x3
0x3
—
—
—
0x1
0x3
0x5
0x7
0x9
—
—
—
Table 382. FRM_PMLR1, Performance Monitor Link Register 1 (R/W)
Address*
Bit
Name
0x8LP80
15:0
FRM_PM_IM4[15:0]
Function
Performance Monitoring Register FRM_PMLR4 Interrupt Mask. A 1 masks the corresponding status bit in the
interrupt status registers (Table 386) from generating an
interrupt. A 0 allows an interrupt to be generated.
Reset
Default
0xFFFF
* See Table 381 for values of L and P.
Table 383. FRM_PMLR2, Performance Monitor Link Register 2 (R/W)
Address*
Bit
Name
Function
0x8LP81
15:0
FRM_PM_IM5[15:0]
Performance Monitor Register FRM_PMLR5 Interrupt
Mask. A 1 masks the corresponding status bit in interrupt
status registers (Table 386) from generating an interrupt. A
0 allows an interrupt to be generated.
Reset
Default
0xFFFF
* See Table 381 for values of L and P.
274
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
Table 384. FRM_PMLR3, Performance Monitor Link Register 3 (R/W)
Address*
0x8LP82
Bit
Name
Function
Reset
Default
00000
0xF
15:11
—
Reserved. Must write to 0.
10:7 FRM_MHGALIGN[3:0] Handling Group Alignment Interrupt Mask. A 1 masks
the corresponding status bit in the interrupt status register
(Table 400) from generating an interrupt. A 0 allows an
interrupt to be generated.
6
FRM_MSEFS
Severely Errored Frame Interrupt Mask. A 1 masks the
1
corresponding status bit in the interrupt status register
(Table 400) from generating an interrupt. A 0 allows an
interrupt to be generated.
5
FRM_MFE
CEPT Functional Element Status Interrupt Mask. A 1
1
masks any and all of the FE status bits in Table 394 and
Table 395 from generating an interrupt. A 0 allows an
interrupt to be generated.
4:0
FRM_PM_IM6[15:0] Performance Monitor Register FRM_PMLR6 Interrupt 0x001F
Mask. A 1 masks the corresponding status bit in the interrupt status register (Table 387) from generating an interrupt. A 0 allows an interrupt to be generated.
* See Table 381 for values of L and P.
Table 385. FRM_PMLR4, Performance Monitor Link Register 4 (COR)
Address*
Bit
Name
Function
0x8LP83
15
FRM_SLIPO
14
FRM_SLIPU
13
FRM_OOF
Receive Elastic Store Slip Overflow. A 1 indicates that the
receive elastic store performed a control slip due to an elastic
store overflow condition. This signal is set when the error occurs
and is cleared when it is read, if there is not another error during
the read.
Receive Elastic Store Slip Underflow. A 1 indicates that the
receive elastic store performed a control slip due to an elastic
store underflow condition. This signal is set when the error
occurs and is cleared when it is read, if there is not another
error during the read.
Out Of Frame. A 1 indicates that the receive framer has lost
frame alignment and is currently searching for a new frame
alignment. Section 21.6.1 Loss of Frame Alignment Criteria on
page 488 lists the loss of frame criteria for the framing bit.
(T1.231 section 6.1.2.2.1, G.706 section 4.1). Excessive
(exceeding the provisionable CRC error count) CRC errors may
optionally cause a reframe.
Reset
Default
0
0
0
In ESF or J-ESF, more than 320 CRC-6 errors in 1 second
result in loss of frame alignment. The CRC error count is provisionable.
In the CEPT CRC-4 multiframe formats, more than 915 CRC-4
errors in 1 second result in loss of frame alignment. (G.706 section 4.3.2). The CRC error count is provisionable.
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Preliminary Data Sheet
June
May 2001
12 28-Channel Framer Registers (continued)
Table 385. FRM_PMLR4, Performance Monitor Link Register 4 (COR) (continued)
Address*
Bit
Name
Function
0x8LP83
12
FRM_LSFA
Loss of Signaling Frame Alignment. DS1: A 1 indicates that
the receive framer is in a loss of signaling superframe alignment
in the SLC-96 framing format. This bit is a 0 in all other DS1
framing modes. SLC-96 signaling alignment is assumed to have
been lost when multiframe alignment is lost.
11
FRM_OAIS
CEPT: A 1 indicates that the loss of the CEPT time slot 16
channel associated signaling multiframe structure. CEPT time
slot 16 multiframe alignment is assumed lost when two consecutive time slot 16 multiframe alignment patterns (0000) are
received in error, or when time slot 16 is all zeros for one or two
multiframes. Time slot 16 multiframe alignment is assumed to
have occurred when the first time slot 16 multiframe alignment
pattern is found in time slot 16 and optionally, the preceding
time slot 16 contained at least one. (G.732 section 5.2; O.162
section 2.1.3.) This is the time slot 16 align input from the signaling block.
Other Alarm Indication Signals. DS1 AIS-CI: A 1 indicates the
receive framer detected alarm indication signal customer installation (AIS-CI). AIS-CI is a repetitive pattern with a 1.26 s
period. It consists of 1.11 s of unframed all ones interleaved
with 0.15 s of all ones modified by the AIS-CI signature pattern.
The AIS signature pattern is 01111100 11111111 (transmitted
right-to-left at 386-bit intervals). It takes 4 ms to detect AIS-CI.
(T1.231 section D.1.3.)
Reset
Default
0
0
CEPT RTS16AIS: A 1 indicates the receive framer detected
time slot 16 AIS. Time slot 16 AIS is defined to be fewer than
three zeros in each of two consecutive time slot 16 multiframe
periods, (G775 section 5.1.1). This is the time slot 16 AIS input
from the signaling block.
* See Table 381 for values of L and P.
276
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Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
Table 385. FRM_PMLR4, Performance Monitor Link Register 4 (COR) (continued)
Address*
Bit
Name
0x8LP83
10
FRM_AIS
Function
Alarm Indication Signal. A 1 indicates the framer is currently
receiving an AIS pattern or receiving an AIS indication on the
TDM bus from the mapper.
Reset
Default
0
DS1: Option 0: AIS occurs upon detection of an unframed signal with a ones density of at least 99.9% for a time between
3 ms and 75 ms. AIS is removed if the signal does not meet the
99.9% ones density or the unframed criteria for a period
between 3 ms and 75 ms. (ANSI T1.231 section 6.1.2.2.3,
T1.403 section H, G.775 section 5.4.)
Option 1: AIS is detected if the signal has one or less zeros in
24 frames (3 ms/4632 bits). AIS is removed if the signal has two
or more zeros in 24 frames. ( ANSI G.775 section I.2.)
CEPT: Option 0:AIS is detected when loss of frame alignment
occurs and there are two or less zeros in a double frame period
(512 bits per double frame period). AIS is cleared on receipt of a
signal not conforming to the AIS defect criteria. (ANSI G.775
section I.2; G.965 section 16.1.2.)
Option 1: AIS is detected when there are two or fewer zeros in
each of two consecutive double frame periods (512 bits per
double frame period). AIS is cleared when each of two consecutive double frame periods contain three or more zeros or the
frame alignment signal (FAS) is found. ( ANSI G.775 section
5.2.)
Option 2: AIS is detected when there are three or less zeros in a
four frame period (0.5 ms/1024 bits) and the signal is out of
frame. AIS is cleared if there are four or more zeros in a fourframe period or the signal is in frame alignment. ( ANSI G.775
section I.2.)
Option 3: AIS is detected when there are one or fewer zeros in
each of two consecutive double frame periods (512 bits per
double frame period) and the FAS is not detected. AIS is
cleared when each of two consecutive double frame periods
contain three or more zeros or the frame alignment signal (FAS)
is found. ( ANSI G.775 section I.2.)
* See Table 381 for values of L and P.
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May 2001
12 28-Channel Framer Registers (continued)
Table 385. FRM_PMLR4, Performance Monitor Link Register 4 (COR) (continued)
Address*
Bit
Name
Function
0x8LP83
9
FRM_ORAI
Other Remote Alarm Indication. A 1 indicates the receive
framer detected an other remote (yellow) alarm. This bit is a 0 in
the modes not indicated below. This bit is set when the alarm is
detected, and is cleared on a read of this register if the alarm is
not detected during the read.
Reset
Default
0
J-D4 RJYA: The frame bit in frame 12 is a 1 two out of three
consecutive times.
ESF, J-ESF RAI-CI:
Option 0: A 1 indicates the receive framer detected remote
alarm indication customer installation (RAI-CI) in the ESF data
link. RAI-CI is a repetitive pattern with a 1.08 second period. It
consists of 0.99 s of the unscheduled message 00000000
11111111 (RAI in the data link) interleaved with
0.09 s of the RAI-CI signature pattern. The RAI-CI signature
pattern is 00111110 11111111 (transmitted right-to-left). (ANSI
T1.231 section D.1.2.)
Option 1: A 1 indicates the receive framer detected RAI-CI in
the ESF data link. RAI-CI is a repetitive pattern with a 1.08 second period. It consists of 0.99 s of all ones (RAI in the data link)
interleaved with 0.09 s of the RAI-CI signature pattern. The RAICI signature pattern is 00111110 11111111 (transmitted rightto-left). (ANSI T1.231 section D.1.2.)
CEPT RTS16MFA: Bit 6 of time slot 16 of signaling frame 0 is a
1 for three consecutive occurrences. The alarm is considered
inactive when bit 6 of time slot 16 of signaling frame 0 is 1 in
less than two consecutive occasions. This is true if time slot 16
is not carrying a payload, e.g., common channel signaling. If
time slot 16 is used for common channel signaling, bit 6 will be
continuously 1. In this case, it will be possible to inhibit the
remote alarm to prevent false alarm conditions. (O.162 section
2.1.5.) This is the y-bit input from the signaling block.
* See Table 381 for values of L and P.
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Preliminary Data Sheet
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TMXF28155/51 Super Mapper
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12 28-Channel Framer Registers (continued)
Table 385. FRM_PMLR4, Performance Monitor Link Register 4 (COR) (continued)
Address*
Bit
Name
Function
0x8LP83
8
FRM_RAI
Remote Alarm Indication. A 1 indicates the receive framer
detected a remote (yellow) alarm or detected an RAI indication
on the TDM bus from the mapper.
Reset
Default
0
D4: Bit 2 of all time slots is a 0 for one frame. (ANSI T1.403 section 9.1.)
DDS: Bit 6 of time slot 24 is a 0 for 12 frames.
ESF: Option 0: An alternating pattern of eight ones followed by
eight zeros in the ESF data link for 10 consecutive times. (ANSI
T1.403 section 9.1.)
Option 1: A pattern of all ones in the ESF data link for 10 consecutive times.
CEPT Basic Frame: RAI is activated when bit 3 of the NOTFAS
frame is 1 RAC consecutive times. RAI is deactivated when bit 3
of the NOTFAS frame is a 0 RDC consecutive times. RAI activation count (RAC) and RAI deactivation count (RDC) are provisionable in Section Table 313. FRM_PMGR3, Performance
Monitor Global Register 3 (R/W) on page 248.
Option 0: Bit 3 of the NOTFAS frame is a 1 one consecutive
time. RAI is inactive when bit 3 is set to a 0.
Option 1: RAI is set on three consecutive ones and deactivated
on three consecutive zeros.
Option 2: Bit 3 of the NOTFAS frame is a 1 four consecutive
times. RAI is inactive when bit 3 is set to a 1 in less than two
consecutive occasions. (O.162 section 2.1.4.)
Option 3: RAI is set on five consecutive ones and deactivated
on five consecutive zeros. (ETS 300.417-1-1.)
7
6
CEPT CRC-4 Multiframe: Reception of 1 bit A with a content of
1. (G.965 section 16.1.2)
FRM_SA600X1E Sa6 = 00x1 Event. This bit indicates detection of an Sa6 = 00x1
event. The Sa6 code is detected synchronously to the CRC-4
multiframe and is not counted during loss of CRC-4 multiframe
alignment. This detection is not qualified by Sa5 = 1, unlike bits
6 and 8 of Section Table 394. FRM_PMLR13, Performance
Monitor Link Register 13 (COR) on page 286.
FRM_SA6001XE Sa6 = 001x Event. This bit indicates detection of an Sa6 = 001x
event. The Sa6 code is detected synchronously to the CRC-4
multiframe and is not counted during loss of CRC-4 multiframe
alignment. This detection is not qualified by Sa5 = 1, unlike bits
7 and 8 of Table 394.
0
0
* See Table 381 for values of L and P.
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Preliminary Data Sheet
May 2001
12 28-Channel Framer Registers (continued)
Table 385. FRM_PMLR4, Performance Monitor Link Register 4 (COR) (continued)
Address*
Bit
Name
Function
0x8LP83
5
FRM_CRCTX
4
FRM_LTS0MFA
CRC-4 Multiframe Alignment Timer Expired. A 1 indicates
that either the 100 ms or the 400 ms interworking timer expired.
It is only active immediately after basic frame alignment is found
in CEPT CRC-4 modes. This signal is set when the error
occurs, and is cleared when it is read if there is not another
error during the read.
Loss of Time Slot 0 CRC-4 Multiframe Alignment. A 1 indicates the absence of CRC-4 multiframe alignment. This bit is
set when basic frame alignment has been found and multiframe
alignment is being searched for, or when multiframe alignment
is lost but basic frame alignment remains good, or when multiframe alignment is lost.
Reset
Default
0
0
Note: This is a stored version of the status. It is cleared after
one good multiframe bit is seen.
CRC-4 multiframe alignment is assumed lost when there are
three consecutive errors in the CRC-4 multiframe alignment bits
(bit 0 of not-FAS frames 1, 3, 5, 7, 9, and 11). Loss of CRC-4
multiframe alignment may optionally cause a research for CRC4 multiframe alignment without affecting the current basic frame
alignment.
3
2
CEPT with CRC-4 only. In all other modes, this bit is a 0.
FRM_TS0MFABE Time Slot 0 Multiframe Alignment Signal Bit Error. A 1
indicates that the receive framer detected an error in the CRC-4
multiframe alignment signal. A 0 indicates no errors. Bit 0 of
NOTFAS frames (1, 3, 5, 7, 9, and 11).
FRM_SES
Severely Errored Second (G.826 Annex B). A 1 indicates the
receive framer detected a severely errored second. The events
that can cause an errored second are provisionable for DS1
links in Table 317 and for CEPT links in Table 320. The severely
errored second threshold is provisionable; DS1-SF links in
Table 314 on page249 , DS1-ESF links in Table 316 on
page 249 and CEPT links in Table 319.
0
0
* See Table 381 for values of L and P.
280
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Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
Table 385. FRM_PMLR4, Performance Monitor Link Register 4 (COR) (continued)
Address*
Bit
Name
Function
Reset
Default
0x8LP83
1
FRM_BES
Bursty Errored Second. A 1 indicates the receive framer
detected a bursty errored second. The events that can cause an
errored second are provisionable for DS1 links in Table 317 on
page 249 and for CEPT links in Table 320 on page 250. The
severely errored second threshold is provisionable; DS1-SF
links in Table 314 on page249 , DS1-ESF links in Table 316 on
page 249 and CEPT links in Table 319 on page250 .
0
BES is not valid in any CEPT mode.
Note: The SES threshold must always be greater than the ES
threshold because BES lies in between (i.e., ES < BES <
SES).
0
FRM_ES
Errored Second (G.826 Annex B). A 1 indicates the receive
framer detected an errored second. The events that can cause
an errored second are provisionable for DS1 links in Section
Table 317. FRM_PMGR7, Performance Monitor Global Register
7 (R/W) on page 249 and for CEPT links in Section Table 320.
FRM_PMGR10, Performance Monitor Global Register 10 (R/W)
on page 250.
0
* See Table 381 for values of L and P.
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Preliminary Data Sheet
May 2001
12 28-Channel Framer Registers (continued)
Table 386. FRM_PMLR5, Performance Monitor Link Register 5 (COR)
Address*
Bit
0x8LP84
15:14
13
12
11
10
9
8
7
6
Name
Function
Reset
Default
—
Reserved. Must write to 0.
0
0
FRM_LFV
Line Format Violation. A 1 indicates the receive framer detected
a bipolar line coding or excessive zeros violation. The performance monitor counts all pulses on the BPV signal from the frame
aligner block. This signal is set when the error occurs and is
cleared when it is read, if there is not another error during the
read. (G.703 Annex A and O.161 section 2.)
FRM_FBE
Frame-Bit Errored. A 1 indicates the receive framer detected a
0
frame bit or frame alignment pattern error. For SF formats, either
FT, or FT and FS bits are used and are programmable. This signal
is set when the error occurs and is cleared when it is read, if there
is not another error during the read. In DDS, FT and FS are always
counted as FBEs. The PMON is, however, configurable as to
whether TS24 is also counted as a FBE. In CEPT, FAS words can
only generate one FBE.
0
FRM_CRCE CRC Errored. A 1 indicates the receive framer detected a CRC
error. It is the occurrence of a received CRC code that is not identical to the locally calculated code. This signal is set when the error
occurs and is cleared when it is read, if there is not another error
during the read. This signal is only valid in ESF(G.704 section A.1)
and CEPT CRC-4 (G.704 section A.3) modes.
0
FRM_ECRCE Excessive CRC Errors. A 1 indicates the receive framer detected
an excessive CRC error condition. This signal is set when the
error occurs and is cleared when it is read, if there is not another
error during the read. This signal is only valid in ESF and CEPT
CRC-4 modes. The CRC error count is provisionable. In ESF, an
excessive CRC error is defined as ≥320 CRC errors in one second. In CEPT, an excessive CRC error is defined as ≥915 CRC
errors in one second.
FRM_REBIT Received E Bit = 0. A 1 indicates the receive framer detected an
0
E bit = 0 in the CEPT CRC-4 modes. This signal is set when the
error occurs and is cleared when it is read if there is not another
error during the read. This signal is only valid in CEPT CRC-4
modes.
FRM_CREBIT Continuous Received E Bits. A 1 indicates the detection of a five
0
second interval containing ≥991 E bit = 0 events in each second.
The E-bit error count is provisionable. The defaults of 991 are
shown.
0
FRM_LTFA
Loss of Transmit Frame Alignment. DS1: Always 0.
CEPT FRM_LTFA: A 1 indicates that the CEPT biframe alignment
pattern (alternating 0, 1 in bit 2 of time slot 0) received from the
system is in error. This alignment pattern is required when transmitting the Si or Sa bits transparently. Detection of this condition
may optionally be disabled.
FRM_NFA
New Frame Alignment. A 1 indicates the receive framer has
0
reframed.
* See Table 381 for values of L and P.
282
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
Table 386. FRM_PMLR5, Performance Monitor Link Register 5 (COR) (continued)
Address*
Bit
0x8LP84
5
4
3
2
0x8LP84
1
Name
Reset
Default
FRM_SA7LID Sa7 Link Identification. A 1 indicates that a sequence was found
0
such that two out of three Sa7 bits are 0. (G.965 section 16.1.2.)
FRM_LLBON Line Loopback On Code Detect. A 1 indicates the receive framer
0
detected the DS1 line loopback enable code. The activation signal
consists of repetitions on the pattern 00001 with the framing bits
replacing the pattern bits. (T1.403 section 9.3.1.1.) Only applicable in DS1 SF formats.
FRM_LLBOFF Line Loopback Off Code Detect. A 1 indicates the receive framer
0
detected the DS1 line loopback disable code. The deactivation signal consists of repetitions on the pattern 001 with the framing bits
replacing the pattern bits. (T1.403 section 9.3.1.2.) Only applicable in DS1 SF formats.
0
FRM_AUXP Auxiliary Pattern. DS1 IDLEID: Each of the 24 time slots in a
frame contain the DS1 idle signal, 00010111. (T1.231 section
6.4.8.)
FRM_LOS
Function
CEPT AUXP: A 1 indicates the detection of a valid auxiliary pattern (unframed 10 . . . pattern) in the CEPT mode. When in loss of
frame alignment state, an auxiliary pattern is detected when more
than 255 10 patterns are detected in a 512-bit interval. The alarm
is disabled when three or more non-10 patterns are detected in a
512-bit interval. The search for AUXP is synchronized to the first
alternating 10 pattern found. (ETS 300 233 section 8.2.2.2, O.151
section 2.4.)
Loss of Signal. A 1 indicates that the receive line decoder has
detected a loss of signal condition. This status is only valid in the
dual-rail mode of operation.
0
DS1: Loss of signal occurs when, for 100 contiguous pulse positions, there are no pulses of either the positive or negative polarity
at the line interface. The loss of signal defect is removed upon
detecting 13 pulses over 100 pulse positions following the receipt
of a pulse, and there is no 100 pulse position interval where there
were no pulses. (T1.231 section 6.1.2.1.1, G.775 section 4.3.)
0
FRM_BOMR
CEPT: Loss of signal occurs when, for 100 consecutive pulse
positions, there are no pulses of either the positive or negative
polarity at the line interface. The loss of signal defect is removed
when there are pulses in a 100 consecutive pulse position period
(G.775 section 4.2.). Note that the defect is set and cleared at the
end defined sample period.
Bit Oriented Message Received. A 1 indicates a BOM has been
received in the ESF data link bits and FRM_RBOM[7:0]
(Table 399) should be read. A BOM is defined in ANSI T1.403 as a
0xxxxxx0 11111111 pattern (received right-to-left) repeated
10 consecutive times. The 0xxxxxx0 pattern is saved in the
FRM_RBOM[7:0] register (Table 399 on page287 ) upon the
10th occurrence of the BOM message.
0
* See Table 381 for values of L and P.
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Preliminary Data Sheet
May 2001
12 28-Channel Framer Registers (continued)
Table 387. FRM_PMLR6, Performance Monitor Link Register 6 (COR)
Address*
Bit
Name
0x8LP85
15:5
4
—
FRM_FDL_RAI
3
2
1
0
Function
Reserved.
ESF_FDL_RAI/Yellow Alarm. A 1 indicates the receive
framer detected the ESF_FDL_RAI/yellow alarm code in the
payload. This code is defined in ANSI T1.403-1995 as a
00000000 11111111 pattern in the facility data link (received
right-to-left). This signal is set when the pattern is detected
(10 consecutive times) and is cleared when it is read if the pattern is no longer being detected.
FRM_FDL_PLBON ESF_FDL Payload Loopback Enable. A 1 indicates the
receive framer detected the ESF_FDL payload loopback
enable code in the payload. This code is defined in
ANSI T1.403-1995 as a 00010100 11111111 pattern in the
facility data link (received right-to-left). This signal is set when
the pattern is detected (10 consecutive times) and is cleared
when it is read if the pattern is no longer being detected. This
could also be set by FF_PLB (manual PLB indication) input.
FRM_FDL_PLBOFF ESF_FDL Payload Loopback Disable. A 1 indicates the
receive framer detected the ESF_FDL payload loopback disable code in the payload. This code is defined in
ANSI T1.403-1995 as a 00110010 11111111 pattern in the
facility data link (received right-to-left). This signal is set when
the pattern is detected (10 consecutive times) and is cleared
when it is read if the pattern is no longer being detected.
FRM_FDL_LLBON ESF_FDL Line Loopback Enable. A 1 indicates the receive
framer detected the ESF_FDL line loopback enable code in
the payload. This code is defined in ANSI T1.403-1995 as a
00001110 11111111 pattern in the facility data link (received
right-to-left). This signal is set when the pattern is detected
(10 consecutive times) and is cleared when it is read if the pattern is no longer being detected.
FRM_FDL_LLBOFF ESF_FDL Line Loopback Disable. A 1 indicates the receive
framer detected the ESF_FDL line loopback disable code in
the payload. This code is defined in ANSI T1.403-1995 as a
00111000 11111111 pattern in the facility data link (received
right-to-left). This signal is set when the pattern is detected
(10 consecutive times) and is cleared when it is read if the pattern is no longer being detected.
Reset
Default
0
0
0
0
0
0
* See Table 381 for values of L and P.
Table 388. FRM_PMLR7, Performance Monitor Link Register 7 (COR)
Address*
Bit
Name
0x8LP86
15:0
FRM_BPV[15:0]
Function
Reset
Default
Bipolar Violation Counter. This register contains the 16-bit
count of received bipolar violations, line code violations, and
excessive zeros.
0x0
* See Table 381 for values of L and P.
284
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
Table 389. FRM_PMLR8, Performance Monitor Link Register 8 (COR)
Address*
0x8LP87
Bit
Name
Function
15:0 FRM_FBEC[15:0] Frame Bit Error Counter.
Reset Default
0x0
DS1: This register contains the 16-bit count of received
framing bit errors. Framing bit errors are not counted during loss of frame alignment. (T1.231 section 6.1.1.2.2.)
CEPT: This register contains the 16-bit count of received
frame alignment signal errors. Optionally, bit 2 of non-FAS
frames can be counted.
Note: A FAS with errors in two or more bit positions is
only counted once.
* See Table 381 for values of L and P.
Table 390. FRM_PMLR9, Performance Monitor Link Register 9 (COR)
Address*
0x8LP88
Bit
Name
Function
15:0 FRM_CEC[15:0] CRC Error Counter. This register contains the 16-bit count
of received CRC errors. CRC errors are not counted during
loss of CRC multiframe alignment.
Reset Default
0x0
* See Table 381 for values of L and P.
Table 391. FRM_PMLR10, Performance Monitor Link Register 10 (COR)
Address*
0x8LP89
Bit
Name
Function
15:0 FRM_REC[15:0] Receive E-bit Counter. This register contains the 16-bit
count of received E bit = 0 events. E bit = 0 events are not
counted during loss of CEPT CRC-4 multiframe alignment.
Reset Default
0x0
* See Table 381 for values of L and P.
Table 392. FRM_PMLR11, Performance Monitor Link Register 11 (COR)
Address*
0x8LP8A
Bit
Name
Function
15:0 FRM_CETE[15:0] Sa6 = 00x1 Event Counter. This register contains the
16-bit count of received Sa6 = 00x1 events. The Sa6
code is detected synchronously to the CRC-4 multiframe
and is not counted during loss of CRC-4 multiframe alignment. This detection is not qualified by Sa5 = 1.
Reset Default
0x0000
* See Table 381 for values of L and P.
Table 393. FRM_PMLR12, Performance Monitor Link Register 12 (COR)
Address*
0x8LP8B
Bit
Name
Function
Reset Default
15:0 FRM_CENT[15:0] Sa6 = 001x Event Counter. This register contains the
0x0000
16-bit count of received Sa6 = 001x events. The Sa6 code
is detected synchronously to the CRC-4 multiframe and is
not counted during loss of CRC-4 multiframe alignment.
This detection is not qualified by Sa5 = 1.
* See Table 381 for values of L and P.
Agere Systems Inc.
285
TMXF28155/51 Super Mapper
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Preliminary Data Sheet
May 2001
12 28-Channel Framer Registers (continued)
The register in Table 394 provides a status indication of functional elements (FE) exchanged between the access
digital section and the exchange termination (ET) as defined in ETS 300 233 section 9.3 and Table 2. These are
decoded from the A, Sa5, and Sa6 bits. The Sa6 code words are synchronized to the CRC-4 multiframe.
Table 394. FRM_PMLR13, Performance Monitor Link Register 13 (COR)
Address*
0x8LP8C
Bit
Name
Function
(A, SA5, SA6[1:4])
15:14
—
Reserved. Must write to 0.
13 FRM_FE_OP Defect FCET in the ET or FCDLd in the Digital Link Between V3
and V3 or Defect FCDLu Between the V3 and V3. AIS.
12
FRM_FE_N Reception of AIS at V3 Reference Point of LT and FC4 Simultaneously. (0, 1, 1111.)
11
FRM_FE_M Reception of AIS at V3 Reference Point of LT (Reaction to FCDL
or FCET). (1, 1, 1111.)
10
FRM_FE_L LOS at Line Side of LT (FC1). AUXP.
9
FRM_FE_K Loss of Power at NT1 and LOS/LFA at TE Simultaneously. (1, 1,
1000.)
8
FRM_FE_I Loss of Power at NTT. (0, 1, 1000.)
7
FRM_FE_H Simultaneous FC3 and FC4. (0, 1, 1110.)
6
FRM_FE_G LOS/LFA at T Reference Point of NT1. (0, 1, 1100.)
5
FRM_FE_F LOS/LFA at V3 Reference Point of ET. (1, 0, 0000.)
4
FRM_FE_E LOS at Line Side of NT1 or at V3 Reference Point of LT Only. (1,
1, 1110.)
3
FRM_FE_D LOS/LFA at TE. (1, 1, 00xx.)
2
FRM_FE_C Unintentional Loopback. (x, 0, xxxx.)
1
FRM_FE_B Normal Operation of the ET. (x, 0, 0000.)
0
FRM_FE_A Normal Operation of the DS. (x, 1, 00xx.)
Reset
Default
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
* See Table 381 for values of L and P.
286
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
The register in Table 395 provides a status indication of functional elements (FE) exchanged between the access
digital section and the exchange termination (ET) as defined in ETS 300 233 section 9.3 and Tables 3 and 4 .
Table 395. FRM_PMLR14, Performance Monitor Link Register 14 (COR)
Address*
Bit
Name
0x8LP8D
15:9
8
7
6
5
4
3
2
1
0
—
FRM_FE_Y
FRM_FE_X
FRM_FE_W
FRM_FE_V
FRM_FE_U
FRM_FE_T
FRM_FE_S
FRM_FE_R
FRM_FE_Q
Function
(A, Sa5, Sa6[1:4], E)
Reserved. Must write to 0.
Simultaneous Occurrence of FE_W and FE_X. (x, 1, 0011, x.)
CRC Error Detected at T Reference Point of NT1. (x, 1, 0010, x.)
CRC Error Reported from TE. (x, 1, 0001, x.)
CRC Error Information from ET. (x, 0, 0000, 0.)
CRC Error Report from NT1 Line Side. (x, 1, xxxx, 0.)
Loopback Release Command. (x, 0, 0000, x.)
Loopback Acknowledge. (1, 0, xxxx, x.)
Loopback 2 Command. (1, 0, 1010, x.)
Loopback 1 Command. (1, 0, 1111, x.)
Reset
Default
0x000
0
0
0
0
0
0
0
0
0
* See Table 381 for values of L and P.
Table 396. FRM_PMLR15, Performance Monitor Link Register 15 (COR)
Address*
Bit
0x8LP8E
15:0
Name
Function
Reset
Default
FRM_ESC[15:0] Errored Second Counter. This register contains the 16-bit count 0x0000
of errored seconds.
* See Table 381 for values of L and P.
Table 397. FRM_PMLR16, Performance Monitor Link Register 16 (COR)
Address*
0x8LP8F
Bit
Name
Function
15:0 FRM_BESC[15:0] Bursts Errored Second Counter. This register contains the
16-bit count of bursty errored seconds.
Reset
Default
0x0000
* See Table 381 for values of L and P.
Table 398. FRM_PMLR17, Performance Monitor Link Register 17 (COR)
Address*
Bit
Name
Function
0x8LP90
15:0
FRM_SESC[15:0]
Severely Errored Second Counter. This register contains the
16-bit count of severely errored seconds.
Reset
Default
0x0000
* See Table 381 for values of L and P.
Table 399. FRM_PMLR18, Performance Monitor Link Register 18 (COR)
Address*
0x8LP91
Bit
Name
Function
15:8
—
Reserved. Must write to 0.
7:0 FRM_RBOM[7:0] Received Bit-Oriented Message (0xxxxxx0). Note that only
storing the 8 bits that contain actual data, the first eight ones are
not stored.
Reset
Default
0x00
0x00
* See Table 381 for values of L and P.
Agere Systems Inc.
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155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
12 28-Channel Framer Registers (continued)
Table 400. FRM_PMLR19, Performance Monitor Link Register 19 (COR)
This register applies to the receive path only.
Address*
Bit
0x8LP92
15:5
4:1
0
Name
Function
—
Reserved. Must write to 0.
FRM_HGALIGN[3:0] Indicates HG Alignment for the Associated HG on Each
Link. The status will be given for a particular link any time
that link appears on the TDM bus. A 1 in any bit position indicates that alignment has been achieved. 0 indicates alignment is lost or handling groups are disabled.
FRM_SEFS
Severely Errored Frame Status. (See ANSI T1.403
9.4.2.2.2 for ESF and T1.231 6.1.2.2.2 for SF.)
Reset
Default
0x000
0000
0
* See Table 381 for values of L and P.
Table 401. FRM_PMLR20, Performance Monitor Link Register 20 (COR)
Address*
Bit
Name
0x8LP93
15:13
12:7
6
5
4
3
2
1
0
—
FRM_G[6:1]
FRM_SE
FRM_FE
FRM_LV
FRM_SL
FRM_LB
FRM_N1
FRM_N0
Function
Reset
Default
000
0
0
0
0
0
0
0
0
Reserved. Must write to 0.
PRM Message Bit G6—G1.
PRM Message Bit SE.
PRM Message Bit FE.
PRM Message Bit LV.
PRM Message Bit SL.
PRM Message Bit LB.
PRM Message Bit N1.
PRM Message Bit N0.
* See Table 381 for values of L and P.
12.11 Receive Facility Data Link Configuration and Status Registers
Table 402. Receive Facility Data Link Register Addressing Map
15
0
14
0
Address Pins (ADDR15—ADDR0)
13
12
11
10
9
8
7
6
5
LNK4 LNK3 LNK2 LNK1 LNK0
RXP = 0
1
1
0
L*
R*
4
0
3
2
1
0
RDL3 RDL2 RDL1 RDL0
—
* L and R represent hexidecimal digits used for absolute addressing in Table 404 through Table 408.
288
Agere Systems Inc.
Preliminary Data Sheet
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TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
Table 403. Receive Path Facility Data Link Registers Address Indexing
Read: for link 1, the hexidecimal digit L is 0x0 and the hexidecimal digit R is 0x2.
Link
L
R
Link
L
R
Link
L
R
Link
L
R
1
0x0
0x2
8
0x1
0x0
16
0x2
0x0
24
0x3
0x0
2
0x0
0x4
9
0x1
0x2
17
0x2
0x2
25
0x3
0x2
3
0x0
0x6
10
0x1
0x4
18
0x2
0x4
26
0x3
0x4
4
0x0
0x8
11
0x1
0x6
19
0x2
0x6
27
0x3
0x6
5
0x0
0xA
12
0x1
0x8
20
0x2
0x8
28
0x3
0x8
6
0x0
0xC
13
0x1
0xA
21
0x2
0xA
—
—
—
7
0x0
0xE
14
0x1
0xC
22
0x2
0xC
—
—
—
—
—
—
15
0x1
0xE
23
0x2
0xE
—
—
—
Table 404. FRM_RFDLLR1—FRM_RFDLLR5, Receive FDL Link Registers 1—5 (RO)
Address*
Bit
Name
0x8LRC0
0x8LRC1
0x8LRC2
0x8LRC3
0x8LRC4
15:0
15:0
15:0
15:0
15:0
FRM_RXS0[15:0]
FRM_RXS1[15:0]
FRM_RXS2[15:0]
FRM_RXS3[15:0]
FRM_RXS4[15:0]
Function
Reset
Default
0x0
0x0
0x0
0x0
0x0
Reset
Default
0x0
0
Rx Stack Data 0.
Rx Stack Data 1.
Rx Stack Data 2.
Rx Stack Data 3.
Rx Stack Data 4.
* See Table 403 for values of L and R.
Table 405. FRM_RFDLLR6, Receive FDL Link Register 6 (R/W)
Address*
Bit
Name
Function
0x8LRC5
15:1
0
—
FRM_RXCRCSM
Reserved. Must write to 0.
CEPT CRC-4 Stack Mode. When set to 0, the Sa bits will
be stored based on multiframe alignment. If multiframe
alignment is lost, the stack will not be made available to the
host. When set to 1, the Sa bits will be stored based on an
arbitrary multiframe alignment when only basic frame
alignment can be established.
* See Table 403 for values of L and R.
Table 406. FRM_RFDLLR7, Receive FDL Link Register 7 (RO)
Address*
Bit
0x8LRC6
15:1
0
Name
Function
—
Reserved. Reads 0.
FRM_RXSA Rx Stack Available. A 1 indicates that the Rx stack is available
for reading. 0 indicates that the stack is being updated and
should not be read. In order to prevent a mix of old and new
data being read the host should verify that this bit is set to 1
before continuing to read the stack.
Reset
Default
0x0
0
* See Table 403 for values of L and R.
Agere Systems Inc.
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TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
12 28-Channel Framer Registers (continued)
Table 407. FRM_RFDLLR8, Receive FDL Link Register 8 (COR)
Address*
Bit
0x8LRC7
Name
Function
Reset
Default
0x0
0
15:1
—
Reserved. Reads 0.
0
FRM_RXSR_IS Rx Stack Ready Interrupt. A 1 indicates that the Rx stack has
been filled with data following the format of the associated link.
* See Table 403 for values of L and R.
Table 408. FRM_RFDLLR9, Receive FDL Link Register 9 (R/W)
Address*
Bit
0x8LRC8
15:1
0
Name
Function
Reset
Default
0x0
1
—
Reserved. Must write to 0.
FRM_MRXSR Mask Rx Stack Ready Interrupt. A 1 masks the Rx stack
ready interrupt.
* See Table 403 for values of L and R.
12.12 Transmit Facility Data Link Configuration and Status Registers
Table 409. Transmit Facility Data Link Register Addressing Map
Address Pins (ADDR15—ADDR0)
15
14
0
0
13
12
11
10
9
LNK4 LNK3 LNK2 LNK1 LNK0
L*
8
7
6
5
4
TXP = 1
1
1
0
1
T*
3
2
TDL3 TDL2
1
0
TDL1 TDL0
—
* L and R represent hexidecimal digits used for absolute addressing in Table 411 through Table 415.
Table 410. Transmit Path Facility Data Link Registers Address Indexing
Read: for link 1, the hexidecimal digit L is 0x0 and the hexidecimal digit T is 0x3.
Link
1
2
3
4
5
6
7
—
L
0x0
0x0
0x0
0x0
0x0
0x0
0x0
—
T
0x3
0x5
0x7
0x9
0xB
0xD
0xF
—
Link
8
9
10
11
12
13
14
15
L
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
T
0x1
0x3
0x5
0x7
0x9
0xB
0xD
0xF
Link
16
17
18
19
20
21
22
23
L
0x2
0x2
0x2
0x2
0x2
0x2
0x2
0x2
T
0x1
0x3
0x5
0x7
0x9
0xB
0xD
0xF
Link
24
25
26
27
28
—
—
—
L
0x3
0x3
0x3
0x3
0x3
—
—
—
T
0x1
0x3
0x5
0x7
0x9
—
—
—
Table 411. FRM_TFDLLR1—FRM_TFDLR5, Transmit FDL Link Registers 1—5 (COR)
Address*
0x8LTD0
0x8LTD1
0x8LTD2
0x8LTD3
0x8LTD4
Bit
15:0
15:0
15:0
15:0
15:0
Name
FRM_TXS0[15:0]
FRM_TXS1[15:0]
FRM_TXS2[15:0]
FRM_TXS3[15:0]
FRM_TXS4[15:0]
Function
Tx Stack Data 0.
Tx Stack Data 1.
Tx Stack Data 2.
Tx Stack Data 3.
Tx Stack Data 4.
Reset Default
0x0000
0x0000
0x0000
0x0000
0x0000
* See Table 410 for values of L and T.
290
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
Table 412. FRM_TFDLLR6, Transmit FDL Link Register 6 (R/W)
Address*
Bit
Name
0x8LTD5
15:8
—
7
FRM_SA8SC
Sa8 Source Control. A 1 indicates that Sa8 is sourced from this
block. 0 indicates that Sa8 is sourced from the framer Sa stack.
0
6
FRM_SA7SC
Sa7 Source Control. A 1 indicates that Sa7 is sourced from this
block. 0 indicates that Sa7 is sourced from the framer Sa stack.
0
5
FRM_SA6SC
Sa6 Source Control. A 1 indicates that Sa6 is sourced from this
block. 0 indicates that Sa6 is sourced from the framer Sa stack.
0
4
FRM_SA5SC
Sa5 Source Control. A 1 indicates that Sa5 is sourced from this
block. 0 indicates that Sa5 is sourced from the framer Sa stack.
0
3
FRM_SA4SC
Sa4 Source Control. A 1 indicates that Sa4 is sourced from this
block. 0 indicates that Sa4 is sourced from the framer Sa stack.
0
FRM_TXCRCSM CEPT CRC-4 Stack Mode. When set to 0, the Sa bits will be
transmitted based on being active. If MFA is lost, the stack will
not be transmitted. When set to 1, the Sa bits will be transmitted
based on BFA only.
0
2
Function
Reserved. Must write to 0.
Reset
Default
0x0
1
FRM_ASRC
Alignment Source. A 1 indicates that the MFA and BFA will be
used to determine if a BOM or stack is transmitted. A 0 indicates
that, when enabled for insertion, BOMs and stacks will be
inserted whenever the TDM data is requested.
0
0
FRM_DS1I
DS1 Insertion. A 1 enables this block to insert the contents of
the stack into the associated DS1 link. For SLC-96 links, D bits
will be inserted given the associated stack format. For DDS
links, data-link bits will be inserted given the associated stack
format. For other DS1 link types, this bit has no effect. A 0 disables this block from inserting D bits or data link bits into the
associated link.
0
* See Table 410 for values of L and T.
Table 413. FRM_TFDLLR7, Transmit FDL Link Register 7 (R/W)
Address*
Bit
0x8LTD6 15:7
6
Name
—
FRM_BOME
Function
Reserved. Must write to 0.
Transmit Bit Oriented Message Enable. A 1 indicates that the
BOM message register has been initialized and should be transmitted on the data link of the ESF frame. The pattern will continue to
be transmitted until the enable is removed. When set to 0, the BOM
transmission will stop immediately without completing the current
pattern transmission or without completing the series of 10 patterns.
5:0 FRM_TBOM[5:0] Transmit Bit Oriented Message. Indicates the contents of the
BOM to be transmitted when enabled with FRM_BOME. A pattern
of 111110 implies a BOM of 0111110011111111 with the right
most bit being transmitted first.
Reset
Default
0x000
0
0
* See Table 410 for values of L and T.
Agere Systems Inc.
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TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
12 28-Channel Framer Registers (continued)
Table 414. FRM_TFDLLR8, Transmit FDL Link Register 8 (RO/COW)
Address*
Bit
Name
0x8LTD7
15:2
—
1
0
Function
Reserved. Must write to 0.
FRM_BOMC_IS BOM Complete Interrupt. (Clear on write.) A 1 indicates that the
BOM register contents have been transmitted 10 times over the
data link of the ESF frame.
FRM_TXSE_IS Tx Stack Empty Interrupt. (Clear on write.) A 1 indicates that
the Tx stack is empty. 0 indicates that the host has finished
updating the stack. The Tx data link block sets this bit when the
stack is empty and needs to be filled if the D bits or Sa bits
require changing. If the stack is not refilled, the old data will be
retransmitted.The new data can be written anytime without interfering with the current transmission. The stack needs to be
updated within 9 ms for a SLC-96 link or 4 ms for a CEPT link in
order for the new information to be transmitted in the next double
multiframe.
Reset
Default
0000000
0000000
0
1
* See Table 410 for values of L and T.
Table 415. FRM_TFDLLR9, Transmit FDL Link Register 9 (R/W)
Address*
Bit
Name
0x8LTD8
15:2
—
1
0
Function
Reserved. Must write to 0.
FRM_BOMC_IM Mask BOM Complete Interrupt. A 1 masks the BOM complete
interrupt, FRM_BOMC.
FRM_TXSE_IM Mask Tx Stack Empty Interrupt. A 1 masks the Tx stack empty
interrupt, FRM_TXSE.
Reset
Default
0000000
0000000
1
1
* See Table 410 for values of L and T.
12.13 System Interface, Arbiter, and Frame Formatter Mapping
Table 416. System Interface, Arbiter, and Frame Formatter Link Register Addressing Map
15
0
14
0
Address Pins (ADDR15—ADDR0)
13
12
11
10
9
8
7
6
LNK4 LNK3 LNK2 LNK1 LNK0 RXP=0/TXP=1 1
1
L*
P*
5
1
4
0
3
0
2
1
0
SYS2 SYS1 SYS0
—
* L and P represent hexidecimal digits used for absolute addressing in Table 419 through Table 425.
292
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
Table 417. System Interface, Arbiter, and Frame Formatter Link Register Address Indexing
Read: for link 1 on the receive path, the hexidecimal digit L is 0x0 and the hexidecimal digit P is 0x2.
Link
L
P
Link
L
P
Link
L
P
Link
L
P
Receive Path (P is even)
1
0x0
0x2
8
0x1
0x0
16
0x2
0x0
24
0x3
0x0
2
0x0
0x4
9
0x1
0x2
17
0x2
0x2
25
0x3
0x2
3
0x0
0x6
10
0x1
0x4
18
0x2
0x4
26
0x3
0x4
4
0x0
0x8
11
0x1
0x6
19
0x2
0x6
27
0x3
0x6
5
0x0
0xA
12
0x1
0x8
20
0x2
0x8
28
0x3
0x8
6
0x0
0xC
13
0x1
0xA
21
0x2
0xA
—
—
—
7
0x0
0xE
14
0x1
0xC
22
0x2
0xC
—
—
—
—
—
—
15
0x1
0xE
23
0x2
0xE
—
—
—
Transmit Path (P is odd))
1
0x0
0x3
8
0x1
0x1
16
0x2
0x1
24
0x3
0x1
2
0x0
0x5
9
0x1
0x3
17
0x2
0x3
25
0x3
0x3
3
0x0
0x7
10
0x1
0x5
18
0x2
0x5
26
0x3
0x5
4
0x0
0x9
11
0x1
0x7
19
0x2
0x7
27
0x3
0x7
5
0x0
0xB
12
0x1
0x9
20
0x2
0x9
28
0x3
0x9
6
0x0
0xD
13
0x1
0xB
21
0x2
0xB
—
—
—
7
0x0
0xF
14
0x1
0xD
22
0x2
0xD
—
—
—
—
—
—
15
0x1
0xF
23
0x2
0xF
—
—
—
12.14 System Interface Per Link Registers
Table 418. FRM_SYSLR1, System Interface Link Register 1 (R/W)
Address*
Bit
Name
0x8LPE0
15
—
14:8
Function
Reserved. Must write to 0.
Reset
Default
0
FRM_BYOFF[6:0] CHI Byte Offset. This bit is only applicable in the CHI mode. 0000000
7
—
6:4
FRM_OFF[2:0]
3:2
—
1
0
Reserved. Must write to 0.
CHI Bit Offset.
0
000
Reserved. Must write to 0.
0
FRM_HALFOFF
Half Bit Offset. When set to 1, an offset of 1/2 bit is added to
offsets.
0
FRM_QUAROFF
Quarter Bit Offset. When set to 1, an offset of 1/4 bit is
added to the offsets. CHI CMS mode only.
0
* See Table 417 for values of L and P.
Agere Systems Inc.
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TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
12 28-Channel Framer Registers (continued)
Table 419. FRM_SYSLR2, System Interface Link Register 2 (R/W)
This register applies to the receive path only, inserted in the transmit system interface on demand.
Address*
Bit
Name
0x8LPE1
15
FRM_CEPTMAIS
14
13
12
11:0
Function
Transmit CEPT TS16 AIS.
0 = No action.
1 = Time slot 16 is forced to all ones.
FRM_CEPTAAIS Transmit CEPT TS16 AIS on Loss of MFA.
0 = No action.
1 = Time slot 16 is forced to all ones when time slot 16 multiframe alignment is lost.
FRM_MANAIS
Transmit System AIS.
0 = No action.
1 = Transmit system AIS to the system.
FRM_CEPTSTMP Transmit System CEPT TS16 Stomp.
0 = No action.
1 = If upper or lower nibble of time slot 16 is 0000 then it is
changed to 1111 toward the transmit system interface.
—
Reserved. Must write to 0.
Reset
Default
0
0
0
0
0x000
* See Table 417 for values of L and P.
Table 420. FRM_SYSLR3—FRM_SYSLR6, System Interface Link Registers 3—6 (R/W)
Address*
Bit
Name
0x8LPE2
0x8LPE3
0x8LPE4
0x8LPE5
15:0
15:0
15:0
15:0
—
—
—
—
Function
Reserved. Must write to 0.
Reserved. Must write to 0.
Reserved. Must write to 0.
Reserved. Must write to 0.
Reset
Default
0x0000
0x0000
0x0000
0x0000
* See Table 417 for values of L and P.
294
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
12.15 Arbiter Framer Per Link Registers
Table 421. FRM_ARLR1, Arbiter Link Register 1 (R/W)
Address*
Bit
Name
0x8LPF0
15
FRM_LNK_ENA
Function
Link Enable.
Reset
Default
1
0 = Link is disabled.
14
FRM_LNK_TRANSP
1 = Link is enabled.
Transparent Mode Selection.
0
Switching:
0 = The link is in a nontransparent mode. (Regenerate
framing bits and CRC bits.)
1 = The link is in transparent mode. (Flow through
framing bits and CRC bits.)
Transport:
0 = Nontransparent mode (regenerate CRC bits and
flow through framing bits).
13
1 = Transparent mode (flow through framing bits and
CRC bits).
FRM_LNK_RESTARTN Restart Link.
0
0 = Restart the link.
12
FRM_LNK_REFRAME
1 = Normal operational mode for the link.
Force Reframe.
0
0 = Normal operational mode for the link.
11:10
9
—
FRM_ICKEDGE
1 = Link is forced to reframe.
Reserved. Must write to 0.
Input Clock Edge Selection.
0
0
0 = Sample data on rising edge of input clock.
8:0
—
1 = Sample data on falling edge of input clock.
Reserved. Must write to 0.
000
* See Table 417 for values of L and P.
Agere Systems Inc.
295
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
12 28-Channel Framer Registers (continued)
Table 422. FRM_ARLR2, Arbiter Link Register 2 (R/W)
Address*
Bit
Name
0x8LPF1
15
FRM_ESF_CRC_EN
Function
Reset
Default
0
CRC Framing Enable.
DS1 Modes: ESF CRC framing algorithm enable:
0 = ESF CRC framing disabled.
1 = ESF CRC framing enabled. (Enables inclusion of CRC
in the frame search algorithm.)
CEPT Modes: CRC-4 Multiframe:
0 = Multiframe reframe disabled.
14
FRM_FAST
1 = Multiframe reframe enabled. (Enables the inclusion of
the following criteria to the CEPT loss of multiframe criteria. Three consecutive multiframe alignment pattern bit
errors will cause a search for a new multiframe alignment.
Basic frame alignment is not lost.)
Fast Frame Mode.
0
DS1 Modes:
0 = Disable quick frame recovery.
1 = Enable quick frame recovery as follows:
D4 and J-D4: 36 fewer frame bits are checked.
SLC-96: Eighteen fewer FT bits are checked during the
search for FT framing.
DDS: No change.
CEPT Modes:
0 = Disable quick frame recovery.
1 = This bit enables the (n + 2) framing research algorithm
as defined in the note in Recommendation G.706 section
4.1.2. When an FAS is found in frame n, frame (n + 1) is
checked to ensure that it is a non-FAS frame and frame
(n + 2) is checked for FAS. Failure to meet either of these
conditions results in a new search in frame (n + 2).
* See Table 417 for values of L and P.
296
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
Table 422. FRM_ARLR2, Arbiter Link Register 2 (R/W) (continued)
Address*
Bit
Name
0x8LPF1
13:12
FRM_OPT[1:0]
Function
Frame Options.
Reset
Default
0
DS1 Mode:
00 = The frame aligner will not frame up until all mimics
are gone.
01 = Time-out algorithm is enabled. A counter is started
when, for the first time, one of the 193-bit positions contains a sequence long enough to declare frame but is prevented from doing so by the presence of a mimic. The
provisionable counter sets a time limit for mimics to go
away. If there are still mimics, a candidate bit position that
has met the minimum framing requirements is chosen and
frame alignment is made to that position. See
FRM_TO[7:0] (Table 305).
Others reserved.
CEPT Mode:
00 = No change.
01 = Enables an extra NOTFAS frame check. This can
prevent frame alignment on PRBS patterns which contain
a pseudoframing pattern. The CEPT framing sequence
now becomes:
Find FAS (n).
Verify NOTFAS frame (n + 1).
Verify second FAS in frame (n + 2).
Verify second NOTFAS frame (n + 3).
11
FRM_FBE_MODE
Others reserved.
DDS FBE Mode.
0
0 = Allows two FBEs to be detected in a frame in DDS
mode. One FBE for the frame bit (FT and FS) and one
FBE for the time slot 24 frame alignment signal.
1 = Only 1 FBE is detected in a frame in DDS mode.
* See Table 417 for values of L and P.
Agere Systems Inc.
297
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
12 28-Channel Framer Registers (continued)
Table 422. FRM_ARLR2, Arbiter Link Register 2 (R/W) (continued)
Address*
Bit
Name
0x8LPF1
10:8
FRM_LF_CRT[2:0]
Function
Reset
Default
0
Loss of Frame Criteria.
DS1 Mode:
000 = 2 errored framing bits out of 4 FT and FS bits.
001 = 2 errored framing bits out of 5 FT and FS bits.
010 = 2 errored framing bits out of 6 FT and FS bits.
011 = 3 errored framing bits out of 12 FT, Fs, and channel
24 FAS bits (DDS only).
100 = 2 errored framing bits out of 4 FT bits only.
101 = 2 errored framing bits out of 5 FT bits only.
110 = 2 errored framing bits out of 6 FT bits only.
111 = 4 errored framing bits out of 12 FT, FS, and channel
24 FAS bits (DDS only).
CEPT Mode:
7
6
—
FRM_AUTO_AIS
000 = 3 consecutive errored FAS patterns.
x01 = 3 consecutive errored FAS patterns or 3 consecutive errored NOTFAS bits (bit 2).
x10 = 3 consecutive errored frames (FAS and NOTFAS).
Others reserved.
Reserved. Must write to 0.
Auto AIS.
0
0
0 = Auto AIS is disabled.
1 = Auto AIS is enabled.
5:4
When auto AIS is enabled, the receive arbiter data is
forced to 1 when out of frame.
FRM_RAIL3_DEC[1:0] Third Rail Option.
0
00 = Third input signal to the frame aligner is ignored.
01 = Third input is bipolar violations (in the CMI mode,
CRVs are also included on the RBPV input, but not
passed through the frame aligner).
10 = Third rail is frame sync used to indicate time slot
alignment. The multiframe alignment is determined by the
frame sync.
11 = Third rail is frame sync used to indicate framing bit
position. Multiframe alignment is searched for expedited
by the frame sync.
* See Table 417 for values of L and P.
298
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
Table 422. FRM_ARLR2, Arbiter Link Register 2 (R/W) (continued)
Address*
Bit
Name
Function
0x8LPF1
3:0
FRM_MODE[3:0]
Framing Mode.
0000 = Nonalign 256 bit.
0001 = CEPT basic frame.
0010 = CEPT with CRC-4 and 100 ms timer.
0011 = CMI.
0100 = CEPT with CRC-4 and 400 ms timer.
0101 = Reserved. (Future J2 - G.704.)
0110 = Reserved. (Future J2 - NTT Y.)
0111 = Reserved.
1000 = Nonalign 193 bits.
1001 = SF (FT bits only).
1010 = J-ESF.
1011 = ESF.
1100 = D4.
1101 = J-D4 (SF with Japanese Yellow Alarm).
1110 = DDS.
1111 = SLC-96.
Reset
Default
1011
* See Table 417 for values of L and P.
Table 423. FRM_ARLR3, Arbiter Link Register 3 (R/W)
This register applies to the transmit path only.
Address*
0x8LPF2
Bit
15
Name
FRM_TP_CK_
SRC_EN
14
FRM_TP_CK_
SRC
13
FRM_TP_DD_
SRC
12:1
0
—
FRM_SYSFSM
Function
Reset Default
Framer Transmit Path Clock Source Enable.
0
0 = FRM_TP_CK_SRC bit is disabled. FRM_SW_TRN
(Table 301) bit controls clock source.
1 = FRM_TP_CK_SRC bit is enabled. FRM_SW_TRN bit
is ignored.
Transmit path clock and data is selected with bits
FRM_TP_CK_SRC and FRM_TP_DD_SRC.
Transmit Path Clock Source.
1
0 = Transmit clock comes from the frame aligner (transport
applications).
1 = Transmit clock comes from the system interface
(switching applications).
Transmit Path Default Data Source.
1
0 = Transmit data comes from the frame aligner (transport
applications).
1 = Transmit data comes from the system interface (switching applications).
Reserved. Must write to 0.
0000
System Frame Sync Mask. A 1 masks the system frame
synchronization signal in the transmit framer formatter.
Note: For those applications that have jitter on the transmit
clock signal relative to the system clock signal,
enable this bit so that the jitter is isolated from the
transmit framer.
* See Table 417 for values of L and P.
Agere Systems Inc.
299
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
12 28-Channel Framer Registers (continued)
12.16 Frame Formatter Per Link Registers
Table 424. FRM_FFLR1, Frame Formatter Link Register 1 (R/W)
Address*
Bit
Name
0x8LPF4
15:12
11
—
FRM_ESFRAMD
Function
Reset
Default
0000
0
Reserved. Must write to 0.
ESF Remote Alarm Indicator Mode.
0 = Data link remote alarm sequence is 1111 1111 0000 0000.
10:8
1 = Data link remote alarm is all ones.
FRM_ZCSMD[2:0] Zero Code Suppression Modes.
000
000 = ZCS off.
001 = Set bit 6 (numbered 0—7) of all time slots.
011 = Set bit 6 of all 0-byte time slots.
101 = Set bit 6 of all voice time slots.
111 = Set bit 6 of all 0-byte voice time slots.
110 = Set 0-byte time slots to 1001 1000.
100, 010 = Reserved.
7
6
(Signaling F and G bits identify voice time slots.)
—
Reserved. Must write to 0.
FRM_OCKEDGE Output Clock Edge Selection.
0
0
0 = Data clocked out on rising clock edge.
5:4
3
—
FRM_AUTOPLB
1 = Data clocked out on falling clock edge.
Reserved. Must write to 0.
Automatic Payload Loopback (ESF Framing Only).
0
0
0 = Ignore received payload loopback requests.
2
FRM_AUTOLLB
1 = Automatically start payload loopback when payload loopback signal is received.
Automatic Line Loopback (SF and ESF Framing Only).
0
0 = Ignore received line loopback requests.
1
FRM_AUTOEBIT
1 = Automatically start line loopback when line loopback signal
is received.
Automatic E-Bit Insertion (CEPT Framing Only).
0
0 = Ignore E-bit insertion requests from PM.
0
FRM_AUTORAI
1 = Automatically insert E bits when indicated by PM.
Automatic RAI Insertion.
0
0 = Ignore RAI insertion requests from PM.
1 = Automatically insert RAI when indicated by PM.
* See Table 417 for values of L and P.
300
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
Table 425. FRM_FFLR2, Frame Formatter Link Register 2 (R/W)
Address*
0x8LPF5
Bit
Name
Function
15:14 FRM_TXLBMD[1:0] Transmit Loopback Modes.
Reset
Default
00
00 = Loopbacks off.
01 = Line loopback.
10 = Payload line loopback pass through. (The received payload data, the CRC bits, and the frame alignment bits are
loopback to the line. The data link bits are inserted.)
13:10
9
—
FRM_TXLLBOFF
11 = Payload line loopback regenerate. (The received payload data is looped back to the line. The CRC bits, the frame
alignment bits, and data link bits are regenerated and
inserted.)
Reserved. Must write to 0.
Transmit D4 SF Line Loopback Off Code.
0000
0
0 = Do not transmit the D4 SF line loopback off code.
8
FRM_TXLLBON
1 = Transmit the D4 SF line loopback off code. (Repeated 001
patterns with the framing bits overwriting the pattern T1.403
section 9.3.1.2.)
Transmit D4 SF Line Loopback On Code.
0
0 = Do not transmit the D4 SF line loopback on code.
7:6
5
4
3
2
1
0
—
FRM_TXIID
1 = Transmit the D4 SF line loopback on code. (Repeated
00001 patterns with the framing bits overwriting the pattern
T1.403 section 9.3.1.1.)
Reserved. Must write to 0.
Transmit DS1 Idle ID (Fixed pattern defined inT1.403 section D.2).
0
0
FRM_TXAUXP
0 = On demand idle ID off.
1 = On demand idle ID on (send idle ID).
Transmit AUXP.
0
FRM_TXRAICI
0 = On demand AUXP off.
1 = On demand AUXP on (send AUXP).
Transmit RAI-CI (ESF modes only).
0
0 = On demand RAI-CI off.
1 = On demand RAI-CI on (send RAI-CI).
Transmit RAI.
0
0 = On demand RAI off.
1 = On demand RAI on (send RAI).
Transmit AIS-CI (ESF modes only).
0
0 = On demand AIS-CI off.
1 = On demand AIS-CI on (send AIS-CI).
Transmit AIS.
0
FRM_TXRAI
FRM_TXAISCI
FRM_TXAIS
0 = On demand AIS off.
1 = On demand AIS on (send AIS).
* See Table 417 for values of L and P.
Agere Systems Inc.
301
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
12 28-Channel Framer Registers (continued)
12.17 Line Decoder/Encoder Per Link Registers
Table 426. Line Decoder Per LInk Register Addressing Map
15
0
14
0
Address Pins (ADDR15—ADDR0)
13
12
11
10
9
8
7
6
5
LNK4 LNK3 LNK2 LNK1 LNK0
TXP=1
1
1
1
L*
T*
4
1
3
1
—
2
1
1
0
0
0
* L and R represent hexadecimal digits used for absolute addressing in Table 411 through Table 415.
Table 427. Line Decoder Per Link Registers Address Indexing
Read: for link 1, the hexadecimal digit L is 0x0 and the hexadecimal digit T is 0x3.
Link
1
2
3
4
5
6
7
—
L
0x0
0x0
0x0
0x0
0x0
0x0
0x0
—
T
0x3
0x5
0x7
0x9
0xB
0xD
0xF
—
Link
8
9
10
11
12
13
14
15
L
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
T
0x1
0x3
0x5
0x7
0x9
0xB
0xD
0xF
Link
16
17
18
19
20
21
22
23
L
0x2
0x2
0x2
0x2
0x2
0x2
0x2
0x2
T
0x1
0x3
0x5
0x7
0x9
0xB
0xD
0xF
Link
24
25
26
27
28
—
—
—
L
0x3
0x3
0x3
0x3
0x3
—
—
—
T
0x1
0x3
0x5
0x7
0x9
—
—
—
Table 428. Line Encoder Per Link Register Addressing Map
15
0
14
0
Address Pins (ADDR15—ADDR0)
13
12
11
10
9
8
7
6
5
LNK4 LNK3 LNK2 LNK1 LNK0
RXP = 0
1
1
1
L*
R*
4
1
3
1
2
1
1
0
0
0
—
* L and R represent hexadecimal digits used for absolute addressing in Table 404 through Table 408.
Table 429. Line Encoder Per Link Registers Address Indexing
Read: for link 1, the hexadecimal digit L is 0x0 and the hexidecimal digit R is 0x2.
Link
1
2
3
4
5
6
7
—
302
L
0x0
0x0
0x0
0x0
0x0
0x0
0x0
—
R
0x2
0x4
0x6
0x8
0xA
0xC
0xE
—
Link
8
9
10
11
12
13
14
15
L
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
R
0x0
0x2
0x4
0x6
0x8
0xA
0xC
0xE
Link
16
17
18
19
20
21
22
23
L
0x2
0x2
0x2
0x2
0x2
0x2
0x2
0x2
R
0x0
0x2
0x4
0x6
0x8
0xA
0xC
0xE
Link
24
25
26
27
28
—
—
—
L
0x3
0x3
0x3
0x3
0x3
—
—
—
R
0x0
0x2
0x4
0x6
0x8
—
—
—
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
12.18 Line Encoder/Decoder Per Link Registers
Table 430. FRM_LDLR1, Line Decoder Link Register 1 (R/W)
Address*
Bit
Name
0x8LTFC
15:6
5
—
FRM_EXCZERO
Function
Reserved. Must write to 0.
Line Format Violation Option.
Reset
Default
0x000
0
0 = Excessive zeros are not included in bipolar violations.
4
1 = Excessive zeros are included in bipolar violations.
FRM_RLCLK_EDGE Receive Line Clock Edge Select.
0
0 = Data and bipolar violations are latched in on the positive edge of the receive line interface clock (RLCLK).
3
2:0
1 = Data and bipolar violations are latched in on the negative edge of the receive line interface clock (RLCLK0).
—
Reserved. Must write to 0.
FRM_LD_MODE[2:0] Line Decoder Mode.
0
000
000 = Single rail (CMI use single rail).
001 = HDB3.
010 = B8ZS.
011 = AMI.
100 = Reserved.
101 = Reserved.
110 = Reserved.
111 = Reserved.
* See Table 427 for values of L and T.
Table 431. FRM_LDLR2, Line Encoder Link Register 2 (R/W)
Address*
Bit
Name
0x8LRFC
15:5
4
—
FRM_TLCLK_EDGE
Function
Reserved. Must write to 0.
Transmit Line Clock Edge Select.
Reset
Default
0x000
0
0 = Data and frame sync are latched out on the positive
edge of the transmit line interface clock (TL_CLK).
3
2:0
1 = Data and frame sync are latched out on the negative
edge of the transmit line interface clock (TL_CLK).
—
Reserved. Must write to 0.
FRM_LE_MODE[2:0] Line Encoder Mode.
0
000
000 = Single rail (CMI use single rail).
001 = HDB3.
010 = B8ZS.
011 = AMI.
100 = Reserved.
101 = Reserved.
110 = Reserved.
111 = Reserved.
* See Table 429 for values of L and R.
Agere Systems Inc.
303
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
12 28-Channel Framer Registers (continued)
12.19 HDLC Per Channel Configuration and Status Registers
Table 432. HDLC Per Channel Register Addressing Map
Address Pins (ADDR15—ADDR0)
15 14
13
12
11
10
9
8
7
6
5
0 1
HDLC Channels 1—64 (000000—111111) RXP= 0/ 0
0
TXP
=
1
HDL9 HDL8 HDL7 HDL6 HDL5 HDL4
H*
P*
4
0
3
2
1
0
Per Channel Register
HDL3 HDL2 HDL1 HDL0
—
* H and P represent hexidecimal digits used for absolute addressing in Table 433 through Table 446.
Table 433. FRM_HCR1, Transmit HDLC Channel Register 1 (R/W)
Address*
Bit
0x8HP80
15:13
12:8
7:0
Name
Function
Reset
Default
000
0x0
Reserved. Must write to 0.
—
FRM_TTIMESLOT[4:0] Transmit HDLC Time-Slot.
FRM_TBIT_IM[7:0]
These bits indicate (in binary) the time slot number
assigned to this channel.
Transmit HDLC Bit Assignment.
0x00
These bits indicate which bits of a time slot are to be
assigned to this channel (1 = bit assigned).
In loopback mode, set as follows:
00000000 = slowest (~6 kbits/s at 52MHz)
10000000 = faster (~2x above)
11000000 = faster still (~4x slowest rate)
....
11111111 = fastest (~1.5 Mbits/s at 52MHz)
Note: If running a mix of loopback and nonloopback
channels, the loopback speed should not be set
faster than 11100000.
* See Table 432 for mapping of H andP.
Table 434. FRM_HCR2, Transmit HDLC Channel Register 2 (R/W)
Address*
Bit
0x8HP81 15:14
13:5
4:0
Name
FRM_TFRAME_
SEL[1:0]
—
FRM_TLINK[4:0]
Function
Reset
Default
00
Transmit HDLC Frame Select.
These bits are encoded to select odd and/or even numbered frames assigned to this channel.
00 = No data selected.
01 = Data to even frames selected (F S, FAS).
10 = Data to odd frames selected (F T, NOTFAS, ESF-DL).
11 = Data to all (even and odd) frames selected.
Reserved. Must write to 0.
Transmit HDLC Link Select.
0x000
00000
These bits indicate (in binary) the link number assigned to
this channel.
* See Table 432 for mapping of H andP .
304
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
Table 435. FRM_HCR3, Transmit HDLC Channel Register 3 (R/W )
Address*
Bit
Name
Function
0x8HP82
15
FRM_THC_RESET
Transmit HDLC Reset. When this bit is 1, the channel is
held in reset.
14
FRM_TENABL
This clears status for the channel, disables the channel,
and clears the FIFO for the channel.
Transmit HDLC Enable. When this bit is 0, and written to
1, the channel is reinitialized and enabled. When this bit is
1, and written to 0, no further data will be transmitted and
any partial data being serialized will be lost. The channel
is disabled.
The user should reset the FIFO to prevent partial packets
from being transmitted once re-enabled. Writing the same
value as currently programmed has no effect.
13:11
—
Reserved. Must write to 0.
Bits 10:0, 3, 1:0 can only be written as the channel is being enabled, (i.e., bit 14 held 0 and is now being
written to 1).
0x8HP82
10:9
FRM_CFLAGS[1:0] Closing Flags. Only valid in HDLC mode. These bits
select one of four values (00 = FRM_FCNT0[4:0],
01 = FRM_FCNT1[4:0], 10 = FRM_FCNT2[4:0],
11 = FRM_FCNT3[4:0] (Table 333—Table 336)). This
value indicates the number of additional closing flags
inserted after an HDLC packet (e.g., if FRM_FCNT2[4:0]
is selected and it is set to 00100, then five flags are
inserted).
8
FRM_PRMEN
PRM Enable. When 1, this channel is enabled to send
PRM packets automatically. When 0, this feature is disabled. (Bit only for channels 1—28, or else reserved.)
When enabled, PRMs will not be sent until all four seconds of PRM information are valid.
7
FRM_TLOOP
HDLC Controller Loopback. When this bit is set to 1, the
channel will operate in loopback mode. When 0, the channel operates normally.
6
FRM_C_R
5
FRM_HTTHRSEL
4
FRM_IFCS
Note: The corresponding Rx channel should be enabled
before enabling the Tx channel for loopback.
PRM C/R Bit. This bit is inserted as the C/R bit when
sending a PRM packet on this channel. (Bit only for channels 0—27, or else reserved.)
Transmit Threshold Select. This bit selects which of the
two programmable FIFO threshold values to use for this
channel (0 selects FRM_HTTHRSH0 (Table 327), 1
selects FRM_HTTHRSH1 (Table 328)).
FCS Insert. Only valid in HDLC mode. When 0, this bit
indicates the FCS at the end of an HDLC packet should
be inserted. A 1 indicates that the internally computed
FCS will not be inserted at the end of the packet.
Reset
Default
0
0
000
00
0
0
0
0
0
* See Table 432 for mapping of H andP .
Agere Systems Inc.
305
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
12 28-Channel Framer Registers (continued)
Table 435. FRM_HCR3, Transmit HDLC Channel Register 3 (R/W) (continued)
Address*
Bit
0x8HP82
3
2
1:0
Name
Function
Reset
Default
FRM_HTIDLE
HDLC Idle Select. Only valid in HDLC mode. This bit indicates
0
the idle fill character when the Tx FIFO is empty. A 0 means fill
with flags (01111110). A 1 means fill with idle (11111111).
FRM_HTMODE
Transmit Channel Mode Select. A 0 indicates the channel is
0
in HDLC mode. A 1 indicates the channel is in transparent
mode.
00
FRM_HXPIDLE[1:0] Transparent Idle Mode Character Select. Only valid in transparent mode. These bits indicate one of the four possible 8-bit
patterns to be sent when the Tx FIFO is empty.
(00 selects TXICHAR0 (Table 329), 01 selects TXICHAR1
(Table 330), etc.)
* See Table 432 for mapping of H andP.
Table 436. FRM_HCR4, Transmit HDLC Channel Register 4 (RO)
Address*
Bit
Name
0x8HP83
15:3
2
—
FRM_HTUND
1
0
Function
Reserved. Reads 0.
Transmit FIFO Underrun. A 1 indicates this channel has
run out of data in the middle of an HDLC packet. In transparent mode, it simply means the channel has run out of
data.
FRM_HTDONE Transmit Done. A 1 indicates a complete packet has been
sent on this channel.
FRM_HTTHRSH Transmit FIFO Threshold Interrupt. A 1 indicates this
channels FIFO level has dropped below the programmed
threshold value.
Reset
Default
0x000
0
0
0
* See Table 432 for mapping of H andP.
Table 437. FRM_HCR5, Transmit HDLC Channel Register 5 (R/W)
Address*
Bit
Name
0x8HP84
15:3
2
—
FRM_MHTUND
1
0
Function
Reserved. Must write to 0.
Transmit FIFO Underrun Interrupt Mask. A 1 masks the
corresponding channel’s FRM_HTUND status from causing an interrupt.
FRM_MHTDONE Transmit Done Interrupt Mask. A 1 masks the corresponding channel’s FRM_HTDONE status from causing
an interrupt.
FRM_MHTTHRSH Transmit FIFO Threshold Interrupt Mask. A 1 masks the
corresponding channel’s FRM_HTTHRSH status from
causing an interrupt.
Reset
Default
0x0
0
0
0
* See Table 432 for mapping of H andP .
306
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
Table 438. FRM_HCR6, Transmit HDLC Channel Register 6 (WO)
Address*
0x8HP85
Bit
Name
Function
Reserved. Must write to 0.
15:10
—
9:8
FRM_HTFUNC[1:0] Transmit Data Function. These two bits indicate the
action to be taken by writing this register:
00 = Add DATA to the Tx FIFO (non-EOP).
01 = Add DATA to the Tx FIFO as EOP data (i.e., last byte
of packet).
10 = Abort last incomplete data packet in FIFO. (If written
after an EOP byte, this may abort the previous packet.)
11 = Reserved.
7:0
FRM_HTDATA[7:0] Transmit Data Register. When FRM_HTFUNC[1:0] = 00
or 01, then these bits contain a byte of data to be written to
the FIFO.
Reset
Default
0x00
00
0x00
* See Table 432 for mapping of H andP.
Table 439. FRM_HCR7, Transmit HDLC Channel Register 7 (RO)
Address* Bit
Name
Function
Reserved. Must write to 0.
0x8HP86 15:10
—
9:0 FRM_HTCOUNT[9:0] Transmit FIFO Byte Count. These bits indicate
the number of bytes available to be filled in the Tx
FIFO for the specific channel.
Reset Default
0x0
x80 (x200 in large
buffer mode)
* See Table 432 for mapping of H andP.
Table 440. FRM_HCR8, Receive HDLC Channel Register 8 (R/W)
Address*
0x8HP00
Bit
Name
Function
Reserved. Must write to 0.
15:13
—
12:8 FRM_RTIMESLOT[4:0] Received HDLC Time Slot. These bits indicate (in
binary) the time slot number assigned to this channel.
7:0
FRM_RBIT_IM[7:0]
Received HDLC Bit Assignment. These bits indicate
which bits of a time slot are to be assigned to this
channel (1 = bit assigned).
Reset
Default
000
00000
0x00
* See Table 432 for mapping of H andP.
Table 441. FRM_HCR9, Receive HDLC Channel Register 9 (R/W)
Address*
Bit
Name
Function
0x8HP01 15:14
FRM_RFRAME_
SEL[1:0]
13:5
4:0
—
FRM_RLINK[4:0]
Receive HDLC Frame Select. These bits are encoded to
select odd and/or even numbered frames assigned to this
channel.
00 = No data selected. (Use for loopback mode.)
01 = Data from even frames selected (Fs, FAS).
10 = Data from odd frames selected (FT, NOTFAS, ESF-DL).
11 = Data from all (even and odd) frames selected.
Reserved. Must write to 0.
Receive HDLC Link Select. These bits indicate (in binary)
the link number assigned to this channel.
Reset
Default
000
0x0
00000
* See Table 432 for mapping of H andP .
Agere Systems Inc.
307
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
12 28-Channel Framer Registers (continued)
Table 442. FRM_HCR10, Receive HDLC Channel Register 10 (R/W)
Address*
Bit
0x8HP02
15
Name
Function
Reset
Default
0
FRM_RHC_RESET Receive HDLC Reset. When this bit is 1, the channel is
held in reset.
14
—
Reserved. Must write to 0.
0
0
13
FRM_RENABL
Receive HDLC Enable. When this bit is 0 and written to 1,
the channel is reinitialized (i.e., HDLC searching for opening flag, transparent searching for alignment character if so
programmed) and enabled. When this bit is 1 and written to
0, any current HDLC packet will be aborted and the channel disabled. Writing the same value as currently programmed has no effect.
Reserved. Must write to 0.
12
—
0
Bits 11:0 can only be written as the channel is being enabled, (i.e., bit 13 held 0 and is now being
written to 1).
11
FRM_RTHRSEL Receive FIFO Threshold Select. This bit selects which of
0
the two programmable FIFO threshold values to use for this
channel. (0 selects FRM_HRTHRSH0[9:0] (Table 341), 1
selects FRM_HRTHRSH1[9:0] (Table 342)).
10
FRM_RFCS
Receive FCS Option. Only valid in HDLC mode. When 1,
0
this bit indicates the FCS at the end of an HDLC packet
should be removed. A 0 indicates it should kept as part of
the packet.
9
FRM_HRMODE
Receive Channel Mode Select. A 0 indicates the channel
0
is in HDLC mode. A 1 indicates the channel is in transparent mode.
8
FRM_BYTAL
Byte Alignment. This bit is only used in transparent mode
0
(forced to 1 in HDLC mode). A 0 indicates no byte alignment is done by the receiver. A 1 indicates that byte alignment will be done by the receiver once the
FRM_MATCH[7:0] code is found.
7:0
FRM_MATCH[7:0] Transparent Mode Pattern Match. Only valid in transpar0x0
ent mode with byte alignment. These bits indicate the pattern to match to begin receiving transparent data (forced to
ones in HDLC mode).
* See Table 432 for mapping of H andP.
Table 443. FRM_HCR11, Receive HDLC Channel Register 11 (RO)
Address*
Bit
Name
0x8HP03
15:4
3
—
FRM_RIDLE
2
1
0
Function
Reserved. Reads 0.
Receive Channel Idle. A 1 indicates this channel has been
detected as idle.
FRM_OVR
Receive FIFO Overflow. A 1 indicates this channel’s FIFO
has overflowed.
FRM_EOP
End of Packet. A 1 indicates an end-of-packet has been
detected on this channel.
FRM_HRTHRSH Receive FIFO Threshold Interrupt. A 1 indicates this
channel’s FIFO has exceeded the programmed threshold
value.
Reset
Default
0x000
0
0
0
0
* See Table 432 for mapping of H andP .
308
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
Table 444. FRM_HCR12, Receive HDLC Channel Register 12 (R/W)
Address*
Bit
Name
0x8HP04
15:4
3
—
FRM_MIDLE
2
1
0
Function
Reserved. Must write to 0.
Receive Channel Idle Interrupt Mask. A 1 masks this
channel’s idle detection interrupt.
FRM_MOVR
Receive FIFO Overflow Interrupt Mask. A 1 masks this
channel’s FIFO overflow interrupt.
FRM_MEOP
End of Packet Interrupt Mask. A 1 masks this channel’s
end-of-packet interrupt.
FRM_MHRTHRSH Receive FIFO Threshold Interrupt Mask. A 1 masks this
channel’s exceeded FIFO threshold interrupt.
Reset
Default
0x000
1
1
1
1
* See Table 432 for mapping of H andP .
Agere Systems Inc.
309
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
12 28-Channel Framer Registers (continued)
Table 445. FRM_HCR13, Receive HDLC Channel Register 13 (RO)
Address*
Bit
Name
0x8HP05
15:11
10
—
FRM_HMDA
9
8
7:0
7
6
5
4
3
2:0
Function
Reserved. Reads 0.
More Data Available. A 1 indicates that if the FIFO is
read again, valid data will be returned. A 0 indicates no
more data is available.
FRM_HRVALID
Receive FIFO Valid Data. A 1 indicates the information
read from the FIFO is valid. A 0 indicates the FIFO was
empty and no information was available.
FRM_HRTYPE
Receive FIFO Data Type. A 0 indicates
FRM_HR_DATA[7:0] is data. A 1 indicates
FRM_HR_DATA[7:0] is status information.
FRM_HR_DATA[7:0] Receive FIFO Data. When FRM_HRTYPE = 0, these bits
contain a byte of data. When FRM_HRTYPE = 1, the bits
are defined below.
FRM_HOVR
FIFO Overflow. A 1 indicates the FIFO overflowed.
FRM_HEOP
End of Packet. A 1 indicates end of packet (normal
packet).
FRM_HCRCERR
HDLC CRC Error. A 1 indicates a CRC error was
detected.
FRM_HABRT
HDLC Abort. A 1 indicates an abort was received.
FRM_HIDL
HDLC Idle. A 1 indicates idle (as defined by HDLC protocol) condition detected.
FRM_HBIT[2:0]
Complete Byte Status. 111 indicates the last data
received was a complete byte.
These bits should be ignored if EOP is 0.
Reset
Default
00000
0
0
0
0
0
0
0
0
0
0
* See Table 432 for mapping of H andP.
Table 446. FRM_HGR14, Receive HDLC Channel Register 14 (COR)
Address*
Bit
0x8HP06
15:10
9:0
Name
Function
Reserved. Must write to 0.
—
FRM_HRCOUNT[9:0] Receive FIFO Byte Count. These bits indicate the
number of valid bytes contained in the Rx FIFO for the
specific channel.
Reset
Default
0x00
0x000
* See Table 432 for mapping of H andP .
310
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
12.20 28-Channel Framer Block Register Map
Table 447. Framer Register Map
Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.
Address
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Superframer Global Registers—R/W
0x80000
FRM_SFGR1
FRM_
SW_TRN
0x80001
FRM_SFGR2
0x80002
FRM_SFGR3
(RO)
0x80003
FRM_SFGR4
0x80004
—
0x80009
—
0x80010
FRM_FGR1
0x80011
FRM_FGR2
FRM_TC_
EN
0x80012
FRM_FGR3
FRM_
TPSSE_IM
0x80014
FRM_FGR4
(COR)
0x80015
FRM_FGR5
(COR)
0
FRM_LC_CNTRL[1:0]
FRM_AR_IS
FRM_LOOP_
TIMING
FRM_DS1_
CEPTN
FRM_PLL_
BYPAS
FRM_
LG_BUF_M
ODE
FRM_TP_
SIG_PWDN
FRM_RP_
SIG_PWDN
FRM_TP_
RDL_PWDN
FRM_RP_ FRM_TP_R FRM_RP_T
TDL_PWDN H_PWDN
H_PWDN
FRM_TS_
PWDN
FRM_RS_
PWDN
FRM_TP_P FRM_RP_F FRM_TP_
M_PWDN
F_PWDN RA_PWDN
FRM_TP_
RDL_IS
FRM_TP_
TDL_IS
FRM_RH_IS
FRM_TH_IS
FRM_TP_
PM_IS
FRM_RP_
PM_IS
FRM_RP_R FRM_RP_T
DL_IS
DL_IS
FRM_TS_
IS
FRM_RS_
IS
0
0
0
0
FRM_VERSION[2:0]
Arbiter (Framer) Global Registers—R/W
FRM_TO[7:0]
Agere Systems Inc.
FRM_TC[7:0]
FRM_TPSSEI[16:1]
FRM_TPSSEI[28:17]
311
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
12 28-Channel Framer Registers (continued)
Table 447. Framer Register Map (continued)
Address
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FRM_
DETECT
FRM_
PTRNBER
FRM_
DS1AISM
FRM_
ESFRAIM
FRM_
RAICLR
Performance Monitor Global Registers—R/W
0x80P20 FRM_PMGR1_
B
FRM_
SEC_SEL
FRM_CT125[11:0]
0x80P30
FRM_PMGR1
(COR)
0x80P31
FRM_PMGR2
0x80P32
FRM_PMGR3
0x80P33
FRM_PMGR4
0x80P34
FRM_PMGR5
FRM_DCT[15:0]
0x80P35
FRM_PMGR6
FRM_ESFSEST[15:0]
0x80P36
FRM_PMGR7
0x80P37
FRM_PMGR8
FRM_CCT[15:0]
0x80P38
FRM_PMGR9
FRM_CSEST[15:0]
0x80P39 FRM_PMGR10
FRM_TPERR_CT[15:0]
FRM_RAC[2:0]
FRM_RDC[2:0]
FRM_
CMFRFEN
FRM_
CRCRFEN
FRM_
DSEF
FRM_
CSA6_F
FRM_
CSA6_E
FRM_
CSA6_C
FRM_
CRAI_AIS
FRM_
CRAI_OOF
FRM_
CRAI_LOS
FRM_
CSA6_8
FRM_
CSA6_1X
FRM_
CSA6_X1
FRM_
CEBIT
FRM_
CLMFA
FRM_DLFA FRM_DRFA
FRM_CLFA FRM_CRFA
FRM_
DSLIP
FRM_
DLOS
FRM_DAIS
FRM_
DCRC
FRM_DFS
FRM_DFT
FRM_
CSLIP
FRM_
CLOS
FRM_CAIS
FRM_
CCRC
FRM_
CNOTFAS
FRM_
CFAS
FRM_DSR
AI_LOS
FRM_DSR
AI_OOF
FRM_DSR
AI_AIS
FRM_
CEBIT_
LTS0MFA
FRM_
CEBIT_
ESMF
FRM_
CEBIT_
CRCTX
FRM_CRET[15:0]
FRM_CRAI_S FRM_CRAI_ FRM_CRAI_C FRM_CRAI FRM_CRAI FRM_CRAI_
A6EQC
SA6EQ8
RCTX
_LTS0MFA _LTS16MFA
8MSEX
0x80P3C FRM_PMGR13
0x80P3D FRM_PMGR14
0x80P3E FRM_PMGR15
0x80P3F FRM_PMGR16
312
FRM_CEPTAISM[1:0]
FRM_SFSEST[15:0]
0x80P3A FRM_PMGR11
0x80P3B FRM_PMGR12
FRM_
FSFBEEN
FRM_CFBE
_MODE
FRM_PTRN_ FRM_PTRN_ FRM_PTRN
EN
INV
_FRMT
FRM_PTRN_LNK[4:0]
FRM_PTRN_SEL[3:0]
FRM_LN_IS[16:1]
FRM_LN_IS[28:17]
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
Table 447. Framer Register Map (continued)
Address
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
HDLC Global Configuration and Status Registers—R/W
Transmit HDLC Global Registers
0x80140
FRM_HGR1
FRM_HTTHRSH0[9:0]
0x80141
FRM_HGR2
FRM_HTTHRSH1[9:0]
0x80142
FRM_HGR3
FRM_TXICHAR0[7:0]
0x80143
FRM_HGR4
FRM_TXICHAR1[7:0]
0x80144
FRM_HGR5
FRM_TXICHAR2[7:0]
0x80145
FRM_HGR6
FRM_TXICHAR3[7:0]
0x80146
FRM_HGR7
FRM_FCNT0[4:0]
0x80147
FRM_HGR8
FRM_FCNT1[4:0]
0x80148
FRM_HGR9
FRM_FCNT2[4:0]
0x80149
FRM_HGR10
0x8014A
FRM_HGR11
FRM_TH_IS[15:0]
FRM_FCNT3[4:0]
0x8014B
FRM_HGR12
FRM_TH_IS[31:16]
0x8014C
FRM_HGR13
FRM_TH_IS[47:32]
0x8014D
FRM_HGR14
FRM_TH_IS[63:48]
Receive HDLC Global Registers
0x80040
FRM_HGR15
0x80041
FRM_HGR16
0x80042
FRM_HGR17
FRM_RH_IS[15:0]
0x80043
FRM_HGR18
FRM_RH_IS[31:16]
0x80044
FRM_HGR19
FRM_RH_IS[47:32]
0x80045
FRM_HGR20
FRM_RH_IS[63:48]
Agere Systems Inc.
FRM_HRTHRSH0[9:0]
FRM_HRTHRSH1[9:0]
313
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
12 28-Channel Framer Registers (continued)
Table 447. Framer Register Map (continued)
Address
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
FRM_
AISLFA
FRM_
AISCRCT
FRM_
DNOTFAS
FRM_
TFSCKE
FRM_
FSPOL
Bit 2
Bit 1
Bit 0
System Interface Global Registers—R/W
Receive System Interface Global Registers
0x80050
FRM_SYSGR1
FRM_SYSMOD[3:0]
FRM_ASM
FRM_CMS
FRM_
CHIDTS
FRM_
STUFFL or
FRM_
LNKSTART
0x80051
FRM_SYSGR2 FRM_HWYE FRM_RSTDO
NA
NE (read
only)
0x80052
FRM_SYSGR3
0x80053
FRM_SYSGR4
FRM_
STSSLB
FRM_
STSLLB
0x80054
FRM_SYSGR5
FRM_TS_
DPAR
FRM_TS_
SPAR
0x80055
FRM_SYSGR6
0x80056
FRM_SYSGR7
FRM_TPSB
_FS_IS
(COR)
0x80057
FRMSYSGR8
FRM_PSB_
FS_IM
0x80150
FRM_SYSGR9
0x80151
FRM_SYSGR1
0
0x80152
FRM_SYSGR1
1
0x80153
FRM_SYSGR1
2
0x80154
FRM_SYSGR1
3
0x80155
FRM_SYSGR1
4
0x80156
0x80157
FRM_STUFF[7:0]
FRM_IDLE[7:0]
FRM_TSLBA[4:0]
FRM_TLSBL[4:0]
Transmit System Interface Global Registers
314
FRM_RS_
DPAR
FRM_RS_
SPAR
FRM_
RFSCKE
FRM_SYSGR1
5
FRM_
DPAR_IS
FRM_
SPAR_IS
FRM_PSB_
FS_IS
FRM_SYSGR1
6
FRM_
DPAR_IM
FRM_
SPAR_IM
FRM_PSM
_FS_IM
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
Table 447. Framer Register Map (continued)
Address
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Signaling Global Registers—R/W
0x80060
FRM_SGR1
FRM_R_
TSAISHG
FRM_R_LINKCNT[4:0]
FRM_TEST_BIT[2:0]
FRM_R_
AFZFBE
0x80061
FRM_SGR2
FRM_R_
SCOSEN
0x80062
FRM_SGR3
0x80063
FRM_SGR4
(RO)
0x80064
FRM_SGR5
(RO)
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
FRM_R_
COSDTHS
0x80065
FRM_SGR6
(COR)
0
0
0
0
0
0
0
0
0
0
0
0
0
FRM_R_
COSDTHI
FRM_R_
COSTTHI
FRM_R_
COSOFI
0x80066
FRM_SGR7
0
0
0
0
0
0
0
0
0
0
0
0
0
FRM_R_C FRM_R_
OSDTHM COSTTHM
FRM_R_
COSOFM
0x80160
FRM_SGR8
0x80170
FRM_FFGR1
0x80090
FRM_FDLGR1
0x801A1
FRM_FDLGR2
FRM_R_SCOSDTH[9:0]
FRM_R_SCOSTTH[15:0]
FRM_R_COSFIFO[1:0]
FRM_R_COSFIFOL[4:0]
FRM_R_COSFIFOTS[4:0]
FRM_T_LINKCNT[4:0]
FRM_R_COSFIFOSIG[3:0]
FRM_T_ FRM_T_FA
SUBZERO S_NOTFAS
FRM_T_
AFZFBE
Frame Formatter Global Register—R/W
FRM_
TXSOOF
FRM_
PTRN_EN
FRM_
PTRN_INV
FRM_PTRN
_FRMT
FRM_PTRN_LNK[4:0]
FRM_PTRN_SEL[3:0]
Facility Data Link Global Registers—R/W
Agere Systems Inc.
315
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
12 28-Channel Framer Registers (continued)
Table 447. Framer Register Map (continued)
Address
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Receive Signaling Link Registers—R/W
See Table 370 for Values of L and R in the Register Address Field
0x8LR00
FRM_RSLR0
FRM_RPSR0[6:0]
0x8LR01
FRM_RSLR1
FRM_RPSR1[6:0]
0x8LR02
FRM_RSLR2
FRM_RPSR2[6:0]
0x8LR03
FRM_RSLR3
FRM_RPSR3[6:0]
0x8LR04
FRM_RSLR4
FRM_RPSR4[6:0]
0x8LR05
FRM_RSLR5
FRM_RPSR5[6:0]
0x8LR06
FRM_RSLR6
FRM_RPSR6[6:0]
0x8LR07
FRM_RSLR7
FRM_RPSR7[6:0]
0x8LR08
FRM_RSLR8
FRM_RPSR8[6:0]
0x8LR09
FRM_RSLR9
FRM_RPSR9[6:0]
0x8LR0A
FRM_RSLR10
FRM_RPSR10[6:0]
0x8LR0B
FRM_RSLR11
FRM_RPSR11[6:0]
0x8LR0C
FRM_RSLR12
FRM_RPSR12[6:0]
0x8LR0D
FRM_RSLR13
FRM_RPSR13[6:0]
0x8LR0E
FRM_RSLR14
FRM_RPSR14[6:0]
0x8LR0F
FRM_RSLR15
FRM_RPSR15[6:0]
0x8LR10
FRM_RSLR16
FRM_RPSR16[6:0]
0x8LR11
FRM_RSLR17
FRM_RPSR17[6:0]
0x8LR12
FRM_RSLR18
FRM_RPSR18[6:0]
0x8LR13
FRM_RSLR19
FRM_RPSR19[6:0]
0x8LR14
FRM_RSLR20
FRM_RPSR20[6:0]
0x8LR15
FRM_RSLR21
FRM_RPSR21[6:0]
0x8LR16
FRM_RSLR22
FRM_RPSR22[6:0]
0x8LR17
FRM_RSLR23
FRM_RPSR23[6:0]
0x8LR18
FRM_RSLR24
FRM_RPSR24[6:0]
0x8LR19
FRM_RSLR25
FRM_RPSR25[6:0]
0x8LR1A
FRM_RSLR26
FRM_RPSR26[6:0]
0x8LR1B
FRM_RSLR27
FRM_RPSR27[6:0]
0x8LR1C
FRM_RSLR28
FRM_RPSR28[6:0]
0x8LR1D
FRM_RSLR29
FRM_RPSR29[6:0]
0x8LR1E
FRM_RSLR30
FRM_RPSR30[6:0]
0x8LR1F
FRM_RSLR31
0x8LR21
FRM_RSLR32
0x8LR20
FRM_RSLR33
316
FRM_RPSR31[6:0]
FRM_R_
FZCON
FRM_R_
SIGI
FRM_R_HGAIS[3:0]
FRM_R_HGA[3:0]
FRM_R_
RXSTOMP
FRM_R_
SIGDEB
FRM_R_HGRDI[3:0]
FRM_R_
HGEN
FRM_R_
MSIGFZ
FRM_R_
FGSRC
FRM_R_
TS16A
FRM_R_
TS16AIS
FRM_R_SIGSRC[1:0]
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
Table 447. Framer Register Map (continued)
Address
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Transmit Signaling Link Registers—R/W
See Table 375 for Values of L and T in the Register Address Field
0x8LT00
FRM_TSLR0
FRM_TPSR0[6:0]
0x8LT01
FRM_TSLR1
FRM_TPSR1[6:0]
0x8LT02
FRM_TSLR2
FRM_TPSR2[6:0]
0x8LT03
FRM_TSLR3
FRM_TPSR3[6:0]
0x8LT04
FRM_TSLR4
FRM_TPSR4[6:0]
0x8LT05
FRM_TSLR5
FRM_TPSR5[6:0]
0x8LT06
FRM_TSLR6
FRM_TPSR6[6:0]
0x8LT07
FRM_TSLR7
FRM_TPSR7[6:0]
0x8LT08
FRM_TSLR8
FRM_TPSR8[6:0]
0x8LT09
FRM_TSLR9
FRM_TPSR9[6:0]
0x8LT0A
FRM_TSLR10
FRM_TPSR10[6:0]
0x8LT0B
FRM_TSLR11
FRM_TPSR11[6:0]
0x8LT0C
FRM_TSLR12
FRM_TPSR12[6:0]
0x8LT0D
FRM_TSLR13
FRM_TPSR13[6:0]
0x8LT0E
FRM_TSLR14
FRM_TPSR14[6:0]
0x8LT0F
FRM_TSLR15
FRM_TPSR15[6:0]
0x8LT10
FRM_TSLR16
FRM_TPSR16[6:0]
0x8LT11
FRM_TSLR17
FRM_TPSR17[6:0]
0x8LT12
FRM_TSLR18
FRM_TPSR18[6:0]
0x8LT13
FRM_TSLR19
FRM_TPSR19[6:0]
0x8LT14
FRM_TSLR20
FRM_TPSR20[6:0]
0x8LT15
FRM_TSLR21
FRM_TPSR21[6:0]
0x8LT16
FRM_TSLR22
FRM_TPSR22[6:0]
0x8LT17
FRM_TSLR23
FRM_TPSR23[6:0]
0x8LT18
FRM_TSLR24
FRM_TPSR24[6:0]
0x8LT19
FRM_TSLR25
FRM_TPSR25[6:0]
0x8LT1A
FRM_TSLR26
FRM_TPSR26[6:0]
0x8LT1B
FRM_TSLR27
FRM_TPSR27[6:0]
0x8LT1C
FRM_TSLR28
FRM_TPSR28[6:0]
0x8LT1D
FRM_TSLR29
FRM_TPSR29[6:0]
0x8LT1E
FRM_TSLR30
FRM_TPSR30[6:0]
0x8LT1F
FRM_TSLR31
0x8LT21
FRM_TSLR32
0x8LT20
FRM_TSLR33
Agere Systems Inc.
FRM_TPSR31[6:0]
FRM_T_
ATS16RFA
FRM_T_
ASPLB
FRM_T_MSP
FRM_T_
ZCSM
FRM_T_
VTSIGE
FRM_T_
SIGI
FRM_T_
TXSTOMP
FRM_T_
HGEN
FRM_T_
MSIGFZ
FRM_T_
FGSRC
FRM_T_
TS16A
FRM_T_
TS16AIS
FRM_T_SIGSRC[1:0]
317
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
12 28-Channel Framer Registers (continued)
Table 447. Framer Register Map (continued)
Address
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
FRM_
MSEFS
FRM_MFE
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FRM_BES
FRM_ES
FRM_LOS
FRM_
BOMR
Performance Monitor Link Registers—COR
See Table 381 for Values of L and P in the Register Address Field
0x8LP80
FRM_PMLR1
(R/W)
FRM_PM_IM4[15:0]
0x8LP81
FRM_PMLR2
(R/W)
FRM_PM_IM5[15:0]
0x8LP82
FRM_PMLR3
(R/W)
0x8LP83
FRM_PMLR4
0x8LP84
FRM_PMLR5
0x8LP85
FRM_PMLR6
0x8LP86
FRM_PMLR7
FRM_BPV[15:0]
0x8LP87
FRM_PMLR8
FRM_FBEC[15:0]
0x8LP88
FRM_PMLR9
FRM_CEC[15:0]
0x8LP89
FRM_PMLR10
FRM_REC[15:0]
0x8LP8A
FRM_PMLR11
FRM_CETE[15:0]
0x8LP8B
FRM_PMLR12
0x8LP8C FRM_PMLR13
FRM_MHGALIGN[3:0]
FRM_SLIPO FRM_SLIPU
FRM_OOF
FRM_LSFA
FRM_OAIS
FRM_AIS
FRM_LFV
FRM_FBE
FRM_CRCE FRM_ECRCE
FRM_PM_IM6[4:0]
FRM_ORAI
FRM_RAI
FRM_
SA600X1E
FRM_
SA6001XE
FRM_
CRCTX
FRM_
LTS0MFA
FRM_
REBIT
FRM_
CREBIT
FRM_LTFA
FRM_NFA
FRM_
SA7LID
FRM_
LLBON
FRM_
FDL_RAI
FRM_
FRM_SES
TS0MFABE
FRM_
LLBOFF
FRM_AUX
P
FRM_FDL_ FRM_FDL_ FRM_FDL_ FRM_FDL_
PLBON
PLBOFF
LLBON
LLBOFF
FRM_CENT[15:0]
FRM_FE_OP
FRM_FE_N
FRM_FE_M
FRM_FE_L
FRM_FE_K FRM_FE_I FRM_FE_H FRM_FE_G FRM_FE_F FRM_FE_E FRM_FE_D FRM_FE_C FRM_FE_B FRM_FE_A
0x8LP8D FRM_PMLR14
FRM_FE_Y FRM_FE_X FRM_FE_W FRM_FE_V FRM_FE_U FRM_FE_T FRM_FE_S FRM_FE_R FRM_FE_Q
0x8LP8E
FRM_PMLR15
FRM_ESC[15:0]
0x8LP8F
FRM_PMLR16
FRM_BESC[15:0]
0x8LP90
FRM_PMLR17
FRM_SESC[15:0]
0x8LP91
FRM_PMLR18
0x8LP92
FRM_PMLR19
0x8LP93
FRM_PMLR20
318
FRM_RBOM[7:0]
FRM_HGALIGN[3:0]
FRM_G6
FRM_G5
FRM_G4
FRM_G3
FRM_G2
FRM_G1
FRM_SE
FRM_FE
FRM_LV
FRM_SL
FRM_LB
FRM_SEFS
FRM_N1
FRM_N0
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
Table 447. Framer Register Map (continued)
Address
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Receive FDL Link Registers—R/W
See Table 403 for Values of L and R in the Register Address Field
0x8LRC0
FM_RFDLLR1
FRM_RXS0[15:0]
0x8LRC1
FM_RFDLLR2
FRM_RXS1[15:0]
0x8LRC2
FM_RFDLLR3
FRM_RXS2[15:0]
0x8LRC3
FM_RFDLLR4
FRM_RXS3[15:0]
0x8LRC4
FM_RFDLLR5
FRM_RXS4[15:0]
0x8LRC5
FM_RFDLLR6
0x8LRC6
FM_RFDLLR7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FRM_
RXSA
0x8LRC7
FM_RFDLLR8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FRM_
RXSR_IS
0x8LRC8
FM_RFDLLR9
FRM_RXC
RCSM
FRM_
RXSR_IM
Transmit FDL Link Registers—R/W
See Table 410 for Values of L and T in the Register Address Field
0x8LTD0
FM_TFDLLR1
FRM_TXS0[15:0]
0x8LTD1
FM_TFDLLR2
FRM_TXS1[15:0]
0x8LTD2
FM_TFDLLR3
FRM_TXS2[15:0]
0x8LTD3
FM_TFDLLR4
FRM_TXS3[15:0]
0x8LTD4
FM_TFDLLR5
0x8LTD5
FM_TFDLLR6
FRM_TXS4[15:0]
FRM_
ABITSRC
FRM_
MBITSRC
FRM_
SBITSRC
FRM_
CBITSRC
FRM_
SA8SC
FRM_
SA7SC
FRM_
SA6SC
FRM_BOME
FRM_
SA5SC
FRM_
SA4SC
FRM_
TXCRCSM
FRM_
ASRC
FRM_DS1I
0x8LTD6
FM_TFDLLR7
0x8LTD7
FM_TFDLLR8
(RO/COW)
FRM_TBOM[5:0]
FRM_
BOMC_IS
FRM_
TXSE_IS
0x8LTD8
FM_TFDLLR9
FRM_
BOMC_IM
FRM_
TXSE_IM
FRM_
HALFOFF
FRM_
QUAROFF
System Interface Link Registers—R/W
See Table 417 for Values of L and P in the Register Address Field
FRM_BYOFF[6:0]
0x8LPE0
FRM_SYSLR1
0x8LPE1
FRM_SYSLR2 FRM_CEPT FRM_CEPTA FRM_MANAI FRM_CEPTS
MAIS
AIS
S
TMP
0x8LPE2
FRM_SYSLR3
0x8LPE3
FRM_SYSLR4
0x8LPE4
FRM_SYSLR5
0x8LPE5
FRM_SYSLR6
Agere Systems Inc.
FRM_OFF[2:0]
319
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
12 28-Channel Framer Registers (continued)
Table 447. Framer Register Map (continued)
Address
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Arbiter Link Registers—R/W
See Table 417 for Values of L and T in the Register Address Field
0x8LPF0
FRM_ARLR1
FRM_
LNK_ENA
FRM_LNK_
TRANSP
0x8LPF1
FRM_ARLR2
FRM_ESF_
CRC_EN
FRM_FAST
0x8LPF2
FRM_ARLR3
FRM_TP_C
K_SRC_EN
FRM_TP_
CK_SRC
FRM_LNK_
RESTARTN
FRM_LNK_
REFRAME
FRM_OPT[1:0]
FRM_
ICKEDGE
FRM_FBE_
MODE
FRM_LF_CRT[2:0]
FRM_AUTO
_AIS
FRM_RAIL3_DEC[1:0]
FRM_MODE[3:0]
FRM_TP_
DD_SRC
Frame Formatter Link Registers—R/W
See Table 417 for Values of L and T in the Register Address Field
0x8LPF4
FRM_FFLR1
0x8LPF5
FRM_FFLR2
FRM_
ESFRAMD
FRM_ZCSMD[2:0]
FRM_TXLBMD[1:0]
FRM_
TXLLBOFF
FRM_
OCKEDGE
FRM_
TXLLBON
FRM_TXIID
FRM_
TXAUXP
FRM_
AUTOPLB
FRM_
AUTOLLB
FRM_
AUTOEBIT
FRM_
AUTORAI
FRM_
TXRAICI
FRM_
TXRAI
FRM_
TXAISCI
FRM_
TXAIS
Line Decoder/Encoder Link Registers—R/W
See Table 427 and Tabl e429 for Values of L and T in the Register Address Field
0x8TPFC
FRM_LDLR1
FRM_
FRM_RLCL
EXCZERO K_EDGE
FRM_LD_MODE[2:0]
0x8LPFD
FRM_LDLR2
FRM_TLCL
K_EDGE
FRM_LE_MODE[2:0]
HDLC Channel Registers—R/W
See Table 432 for Mapping of H and P in the Register Address Field
Transmit HDLC Channel Registers
0x8HP80
FRM_HCR1
FRM_TTIMESLOT[4:0]
0x8HP81
FRM_HCR2
0x8HP82
FRM_HCR3
FRM_THC_
RESET
FRM_
TENABL
0x8HP83
FRM_HCR4
(RO)
0
0
0x8HP84
FRM_HCR5
0x8HP85
FRM_HCR6
(WO)
0x8HP86
FRM_HCR7
FRM_TBIT_IM[7:0]
FRM_TFRAME_SEL[1:0]
FRM_TLINK[4:0]
FRM_CFLAGS[1:0]
0
0
0
0
0
FRM_
PRMEN
FRM_
TLOOP
FRM_C_R
0
0
0
FRM_
FRM_IFCS
HTTHRSEL
0
0
FRM_
HTIDLE
FRM_
HTMODE
0
FRM_
HTUND
FRM_
MHTUND
FRM_HTFUNC[1:0]
FRM_HXPIDLE[1:0]
FRM_
HTDONE
FRM_
HTTHRSH
FRM_
FRM_MHT
MHTDONE
THRSH
FRM_HTDATA[7:0]
FRM_HTCOUNT[9:0]
Receive HDLC Channel Registers
0x8HP00
FRM_HCR8
0x8HP01
FRM_HCR9
0x8HP02
FRM_HCR10
FRM_RHC_
RESET
0x8HP03
FRM_HCR11
(RO)
0
0x8HP04
FRM_HCR12
0x8HP05
FRM_HCR13
(RO)
0x8HP06
320
FRM_HCR14
(COR)
FRM_RTIMESLOT[4:0]
FRM_RBIT_IM[7:0]
FRM_RFRAME_SEL[1:0]
FRM_RLINK[4:0]
FRM_
RENABL
0
0
0
FRM_
RTHRSEL
FRM_RFCS
FRM_
HRMODE
FRM_
BYTAL
0
0
0
0
FRM_MATCH[7:0]
0
0
0
0
FRM_
RIDLE
FRM_
MIDLE
0
0
0
0
0
FRM_HMDA
FRM_
HRVALID
FRM_
HRTYPE
FRM_OVR FRM_EOP
FRM_
MOVR
FRM_
MEOP
FRM_
HRTHRSH
FRM_MHR
THRSH
FRM_HR_DATA[7:0]
FRM_HOVR FRM_HEOP
FRM_
HCRCERR
FRM_
HABRT
FRM_HIDL
FRM_HBIT[2:0]
FRM_HRCOUNT[9:0]
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
13 Cross Connect (XC) Registers
Table of Contents
Contents
Page
13 Cross Connect (XC) Registers ....................................................................................................................... 321
13.1 Cross Connect Register Descriptions ..................................................................................................... 322
13.2 Cross Connect Register Map ................................................................................................................. 328
Tables
Page
Table 448. XC_ID_R, XC Global Register 1 (RO) ............................................................................................... 322
Table 449. XC_CHI_MODE1_R, XC System Interface Global Register 1 (R/W) ................................................ 322
Table 450. XC_CHI_MODE2_R, XC System Interface Global Register 2 (R/W) ................................................ 322
Table 451. XC_PIND_SRC[1—15], XC1 External I/O TXDATA and TXCLK Source Configuration (R/W) ......... 323
Table 452. XC_FRP_SRC[1—14], XC1 Framer Receive Path Data Source Configuration (R/W) ..................... 323
Table 453. XC_M13_SRC[1—14], XC1 M13 Data Source Configuration (R/W) ................................................. 323
Table 454. XC_VT_SRC[1—14], XC1 VT Mapper Source Configuration (R/W) ................................................. 324
Table 455. XC_DJA_SRC[1—14], XC1 Digital Jitter Attenuator Source Configuration (R/W) ............................ 324
Table 456. XC_FTP_SRC[1—14], XC1 Framer Transmit Path Data Source Configuration (R/W) ..................... 324
Table 457. XC_FRS_SRC[1—14], XC1 Framer Receive System Interface Source Configuration (R/W) .......... 324
Table 458. XC_TPM_SRC[1—4], XC1 Test-Pattern Monitor Source Configuration (R/W) ................................. 325
Table 459. XC2_M12_SRC[1—7], XC2 M12 DS2 Clock and Data Source Configuration (R/W) ........................ 325
Table 460. XC2_M23_SRC[1—7], XC2 M23 DS2 Data Source Configuration (R/W) ......................................... 325
Table 461. XC2_TPM_SRC, XC2 Test-Pattern Monitor Source Configuration (R/W) ........................................ 326
Table 462. XC_MISC, XC Global Register 2 (R/W) ............................................................................................ 326
Table 463. XC3_TPM_SRC, XC3 Test-Pattern Monitor Source Configuration (R/W) ........................................ 326
Table 464. XC3_MDS3_SRC, XC3 DS3 Source Configuration (R/W) ................................................................ 327
Table 465. XC_PINS_SRC[1—15], XC1 External I/O TXSYNC Source Configuration (R/W) ............................ 327
Table 466. XC_ALCO_SRC[1—15], XC1 External I/O RXCLK Clock Out Source Configuration (R/W) ............. 327
Table 467. Register Address Map ....................................................................................................................... 328
Agere Systems Inc.
321
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
13 Cross Connect (XC) Registers (continued)
13.1 Cross Connect Register Descriptions
Table 448. XC_ID_R, XC Global Register 1 (RO)
Address
Bit
Name
Function
0x50000
15:11
10:8
7:0
—
XC_VERSION[2:0]
XC_ID[7:0]
Reserved.
Version. These bits identify the version number of the XC.
XC_ID. XC_ID register returns a fixed value (0x05) when
read.
Reset
Default
0x0005
Table 449. XC_CHI_MODE1_R, XC System Interface Global Register 1 (R/W)
Address
Bit
0x5000E
15:3
2
1
0
Name
Function
—
Reserved.
—
Reserved. Must write to 0.
XC_SYNC_FOR_DATA Sync For Data. This bit should set to 1 if the transmit system interface is in use (CHI, PSB, and NSMI). Setting this
bit allows the external I/O pins LINETXSYNC[29—1] to
output transmit system data. Otherwise, set to 0.
XC_SI_CHI
PSB/CHI. This bit should be set to 1 if the transmit system
interface is in PSB mode; otherwise, 0 in CHI mode.
Reset
Default
0x0000
Table 450. XC_CHI_MODE2_R, XC System Interface Global Register 2 (R/W)
Address
Bit
Name
Function
0x5000F
15:14
13:0
—
XC_CHI_MODE
[1—7][1:0]
Reserved.
CHI Mode. The 28 transmit system links are broken down
into seven groups of four. Each group is controlled by two
bits XC_CHI_MODE[1—7][1:0]. XC_CHI_MODE[1—7][1:0]
controls the group of links 4i – 3, 4i – 2, 4i – 1, and 4i, where
i = 1 to 7. The definition of CHI_MODE[1—7][1:0] is as follows:
Reset
Default
0x0000
00 = All four links within the group are normal outputs at
2 Mbits/s or 4 Mbits/s.
01 = Links 4i – 3 and 4i – 2 are normal outputs; links 4i – 1
and 4i are combined into a single output on 4i; and output 4i – 1 is used as T1/E1 line output.
10 = Links 4i – 1 and 4i are combined into a single output on
4i; links 4i – 3 and 4i – 2 are combined into a single output on 4i – 2; and outputs 4i – 1 and 4i – 3 are used as
T1/E1 line outputs.
11 = All four links are combined into a single output on 4i;
and the other three outputs are used as T1/E1 line outputs.
DS1/E1 crosspoint connectivity is determined by a set of source identifiers (SOURCE_IDs), one for each channel
leaving the crosspoint switch. A DS1/E1 SOURCE_ID is therefore defined as follows:
Bit
SOURCE_ID
322
7
6
SOURCE_BLOCK[2:0]
5
4
3
2
1
0
CHANNEL_ID[4:0]
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
13 Cross Connect (XC) Registers (continued)
The SOURCE_BLOCK is defined as:
Index
000
001
010
011
Block Identifier
TPG (Test-Pattern Generator)/Special
PIN (External I/O)
FRM TP (Superframer)
M13 (M13 MUX)
Index
100
101
110
111
Block Identifier
VTMPR (VT Mapper)
DJA (Jitter Attenuator)
FRM RP (Framer Line Interface)
FRM TS (Framer System Interface)
The CHANNEL_ID typically ranges from 1 to 28 (29 for external). Values 0, 30, and 31 (and usually 29 as well) are
unused. The above definition is valid for XC_PDATA[1—29], XC_RP_RDATA[1—28], XC_MDS1DATA[1—29]
(Table 453), XC_VDATA[1—28] (Table 454), XC_SYNC[1—29] (Table 465), and XC_ALCO[1—29] (Table 466).
Table 451. XC_PIND_SRC[1—15], XC1 External I/O TXDATA and TXCLK Source Configuration (R/W)
Address
Bit
Name
0x50010
—
0x5001D
15:8
XC_PDATA
[2, 4, . . . 28][7:0]
0x5001E
0x50010
—
0x5001E
15:8
7:0
(SOURCE_ID)
—
XC_PDATA
[1, 3, . . . 29][7:0]
(SOURCE_ID)
Function
Source Identifier for External I/O Pin LINETXDATA and
LINETXCLK Connection. External I/O DS1/E1 data and
clock (even channels).
Reserved.
Source Identifier for External I/O Pin LINETXDATA and
LINETXCLK Connection. External I/O DS1/E1 data and
clock (odd channels).
Reset
Default
0x1E
(invalid)
0x00
0x1E
(invalid)
Note: External I/O has 29 channels.
Table 452. XC_FRP_SRC[1—14], XC1 Framer Receive Path Data Source Configuration (R/W)
Address
Bit
Name
Function
0x50020
—
0x5002D
15:8
XC_RP_RDATA
[2, 4, . . . 28][7:0]
Source Identifier for Framer Receive Path Connection.
Framer receive path DS1/E1 input signals RP_RDATA,
RP_RCLK, RP_RFS, RP_AIS, and RP_RAI (even channels).
0x50020
—
0x5002D
7:0
(SOURCE_ID)
XC_RP_RDATA
[1, 3, . . . 27][7:0]
(SOURCE_ID)
Source Identifier for Framer Receive Path Connection.
Framer receive path DS1/E1 input signals RP_RDATA,
RP_RCLK, RP_RFS, RP_AIS, and RP_RAI (odd channels).
Reset
Default
0xFF
(invalid)
0xFF
(invalid)
Table 453. XC_M13_SRC[1—14], XC1 M13 Data Source Configuration (R/W)
Address
Bit
Name
0x50030
—
0x5003D
15:8
XC_MDS1DATA
[2, 4, . . . 28][7:0]
0x50030
—
0x5003D
7:0
Agere Systems Inc.
(SOURCE_ID)
XC_MDS1DATA
[1, 3, . . . 27][7:0]
(SOURCE_ID)
Function
Source Identifier for M13 MUX Connection. M13 DS1/E1
data and clock inputs (even channels). Also for stuff request
inputs if operating in LOW_CLOCK_OUT mode.
Source Identifier for M13 MUX Connection. M13 DS1/E1
data and clock inputs (odd channels). Also for stuff request
inputs if operating in LOW_CLOCK_OUT mode.
Reset
Default
0xFF
(invalid)
0xFF
(invalid)
323
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
13 Cross Connect (XC) Registers (continued)
Table 454. XC_VT_SRC[1—14], XC1 VT Mapper Source Configuration (R/W)
Address
Bit
Name
Function
0x50040
—
0x5004D
15:8
XC_VDATA
[2, 4, . . . 28][7:0]
Source Identifier for VT Mapper Connection. VT mapper
DS1/E1 data, clock, sync, and RAI inputs (even channels).
0x50040
—
0x5004D
7:0
(SOURCE_ID)
XC_VDATA
[1, 3, . . . 27][7:0]
Source Identifier for VT Mapper Connection. VT mapper
DS1/E1 data, clock, sync, and RAI inputs (odd channels).
Reset
Default
0xFF
(invalid)
0xFF
(invalid)
(SOURCE_ID)
Table 455. XC_DJA_SRC[1—14], XC1 Digital Jitter Attenuator Source Configuration (R/W)
Address
Bit
Name
0x50050
—
0x5005D
15:8
XC_JDATA
[2, 4, . . . 28][7:0]
0x50050
—
0x5005D
7:0
(SOURCE_ID)
XC_JDATA
[1, 3, . . . 27][7:0]
(SOURCE_ID)
Function
Source Identifier for Jitter Attenuator Connection. DJA
DS1/E1 data, clock, pointer adjustment, and autoAIS inputs
(even channels).
Source Identifier for Jitter Attenuator Connection. DJA
DS1/E1 data, clock, pointer adjustment, and autoAIS inputs
(odd channels).
Reset
Default
0xFF
(invalid)
0xFF
(invalid)
Table 456. XC_FTP_SRC[1—14], XC1 Framer Transmit Path Data Source Configuration (R/W)
Address
Bit
Name
Function
0x50060
—
0x5006D
15:8
XC_TP_RDATA
[2, 4, . . . 28][7:0]
Source Identifier for Framer Transmit Path Connection.
Framer transmit path DS1/E1 input signals (even channels).
Reset
Default
0xFF
(invalid)
0x50060
—
0x5006D
7:0
(SOURCE_ID)
XC_TP_RDATA
[1, 3, . . . 27][7:0]
Source Identifier for Framer Transmit Path Connection.
Framer transmit path DS1/E1 input signals (odd channels).
0xFF
(invalid)
(SOURCE_ID)
Table 457. XC_FRS_SRC[1—14], XC1 Framer Receive System Interface Source Configuration (R/W)
Address
Bit
Name
0x50070
—
0x5007D
15:8
XC_RS_D
[2, 4, . . . 28][7:0]
0x50070
—
0x5007D
7:0
324
(SOURCE_ID)
XC_RS_D
[1, 3, . . . 27][7:0]
(SOURCE_ID)
Function
Source Identifier for Framer Receive System Interface
Connection. Framer receive system (RS) data input (even
channels).
Source Identifier for Framer Receive System Interface
Connection. Framer receive system (RS) data input (odd
channels).
Reset
Default
0x00
(invalid)
0x00
(invalid)
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
13 Cross Connect (XC) Registers (continued)
Table 458. XC_TPM_SRC[1—4], XC1 Test-Pattern Monitor Source Configuration (R/W)
Address
Bit
0x50080
15:8
—
Reserved.
7:0 XC_TPM_DS1_DATA[7:0] Source Identifier for TPM DS1 Data Pattern. Source
identifier for test-pattern monitor (TPM) DS1 test channel
(SOURCE_ID)
inputs.
15:8
—
Reserved.
7:0 XC_TPM_DS1_IDLE[7:0] Source Identifier for TPM DS1 Idle Pattern. Source
identifier for TPM DS1 idle channel inputs.
(SOURCE_ID)
0x50081
Name
0x50082
15:8
7:0
—
XC_TPM_E1_DATA[7:0]
0x50083
15:0
(SOURCE_ID)
—
Function
Reset
Default
0x00
0xFF
(invalid)
0x00
0xFF
(invalid)
Reserved.
Source Identifier for TPM E1 Data Pattern. Source
identifier for TPM E1 test channel inputs.
0x00
0xFF
(invalid)
Reserved.
0x0000
The DS2 crosspoint’s connectivity is determined by a smaller set of source2 identifiers (SOURCE2_IDs), one for
each channel leaving the DS2 crosspoint switch XC2. A DS2 SOURCE2_ID is therefore defined as follows:
Bit
SOURCE2_ID
7
0
6
5
SOURCE2_BLOCK[1:0]
4
3
2
1
CHANNEL2_ID[4:0]
0
The SOURCE2_BLOCK is defined as follows:
Index
00
01
10
11
Block2 Identifier
TPG (DS2 Test-Pattern Generator)
M13:M12 MUX
M13:M23 DeMUX
External I/O
The CHANNEL2_ID typically ranges from 1 to 7. For test data (SOURCE2_BLOCK = 0), value 4 represents the
DS2 test pattern. For DS2 signals routed from external pins to the input of M23 MUX or TPM, the CHANNEL2_ID
can range from 1 to 29.
Table 459. XC2_M12_SRC[1—7], XC2 M12 DS2 Clock and Data Source Configuration (R/W)
Address
Bit
Name
0x50090
—
0x50096
15:8
XC2_DS2M12CLK
[1—7][7:0]
0x50090
—
0x50096
7:0
(SOURCE_ID)
XC2_M21[1—7][7:0]
(SOURCE_ID)
Function
Source Identifier for High-speed DS2 Clock Input to
M12 Multiplexers Connection. DS2 clock input to M12
multiplexers. Refer to M12 MUX section for more details.
Reset
Default
0x0040
(invalid)
Source Identifier for High-speed DS2 Data and Clock
Connection. DS2 data and clock inputs to M12 demultiplexers. Refer to M12 deMUX section for more details.
Table 460. XC2_M23_SRC[1—7], XC2 M23 DS2 Data Source Configuration (R/W)
Address
Bit
Name
0x500A0
—
0x500A6
15:8
7:0
—
XC2_MDS2M23DATA
[1—7][7:0]
(SOURCE2_ID)
Agere Systems Inc.
Function
Reserved.
Source Identifier for M23 Input DS2 Signals Connection. When SOURCE2_BLOCK = 11, CHANNEL2_ID
can range from 1 to 29.
Reset
Default
0x0040
(invalid)
325
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
13 Cross Connect (XC) Registers (continued)
Table 461. XC2_TPM_SRC, XC2 Test-Pattern Monitor Source Configuration (R/W)
Address
Bit
Name
Function
0x500A8
15:8
—
Reserved.
7:0 XC2_TSOURCE_ID[7:0] XC2 TPM Source Connection. Source2 identifier for TPM
DS2 test data. When external I/O is selected
(SOURCE2_BLOCK = 11), CHANNEL2_ID can range
from 1 to 29.
Reset
Default
0x0000
(invalid)
Table 462. XC_MISC, XC Global Register 2 (R/W)
Address
Bit
Name
Function
0x500C0
15:6
5
—
XC_DS2ALCOEN
4
XC_DS1ALCOEN
3
XC_RPOAC_EN
2
XC_TPOAC_EN
1
XC_RSTS1_TUG3
0
XC_TSTS1_TUG3
Reserved.
M23 DS2 Clock Out. Setting this bit to 1 enables DS2 low
clock-out mode from M23. Setting this bit to 0 selects the normal DS2 clock and data input mode.
M12/M13 DS1 Clock Out. Setting this bit to 1 enables DS1
low clock-out mode from M12/M13. Setting this bit to 0 selects
the normal DS1 clock and data input mode.
Receive POAC Enable. Setting this bit to 1 enables RPOAC
channel output and 0 to disable.
Transmit POAC Enable. Setting this bit to 1 enables TPOAC
channel output and 0 to disable.
Receive POAC Channel Select. Selector for TMUX (logic 1)/
SPEMPR (logic 0) receive POAC channel.
Transmit POAC Channel Select. Selector for TMUX (logic 1)/
SPEMPR (logic 0) transmit POAC channel.
Reset
Default
0
0
0
0
0
0
0
Table 463. XC3_TPM_SRC, XC3 Test-Pattern Monitor Source Configuration (R/W)
Address
Bit
Name
Function
0x500D3 15:8
—
Reserved.
7
—
Reserved. Must write to 0.
6:5 XC3_TSOURCE_ID[1:0] TPG/TPM DS3 Source. Source identifier for TPM DS3 test
data.
00 = TPM receives DS3 from external pins.
01 = TPG and TPM are connected to M13 through NSMI
interface.
10 = TPM receives DS3 from SPE.
11 = Reserved.
4:0
—
Reserved. Must write to 0.
326
Reset
Default
0x0000
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
13 Cross Connect (XC) Registers (continued)
Table 464. XC3_MDS3_SRC, XC3 DS3 Source Configuration (R/W)
Address
Bit
Name
Function
0x500D4 15:2
—
Reserved.
1:0 XC3_SOURCE_ID[1:0] DS3 Level Connections. This register defines the connectivity at DS3 level among external I/O, M13, and SPE.
00 = M13 inputs/outputs DS3 through external pins.
01 = M13 and SPE pass data to each other.
10 = SPE inputs/outputs DS3 through external pins and M13
is used as a monitor for the transmit DS3.
11 = SPE inputs/outputs DS3 through external pins and M13
is used as a monitor for the receive DS3.
Reset
Default
0x0000
Table 465. XC_PINS_SRC[1—15], XC1 External I/O TXSYNC Source Configuration (R/W)
Address
Bit
Name
Function
0x500E0 15:8
—
0x500ED
XC_SYNC
[2, 4, . . . 28][7:0]
0x500EE 15:8
0x500E0 7:0
—
0x500EE
—
XC_SYNC
[1, 3, . . . 29][7:0]
Source Identifier for External I/O Pin LINETXSYNC. (Even
channels.) In the LIU mode, these registers must be programmed the same as XC_PIND_SRC[1—15] (Table 451)
registers; in the system interface mode (CHI, PSB, and framer
only), these registers will be programmed separately to
ensure the system data output properly.
Reserved.
Source Identifier for External I/O Pin LINETXSYNC (Odd
channels).
Note: External I/O has 29 channels.
(SOURCE_ID)
(SOURCE_ID)
Reset
Default
0xFF
(invalid)
0x00
0xFF
(invalid)
Table 466. XC_ALCO_SRC[1—15], XC1 External I/O RXCLK Clock Out Source Configuration (R/W)
Address
Bit
Name
0x500F0 15:8
—
0x500FD
XC_ALCO
[2, 4, . . . 28][7:0]
0x500FE
0x500F0
—
0x500FE
—
XC_ALCO
[1, 3, . . . 29][7:0]
15:8
7:0
(SOURCE_ID)
(SOURCE_ID)
Function
Source Identifier for External I/O Pin LINERXCLK when
Operating in Low Clock Output Mode. (Either DS1/E1 or
DS2.) For DS1/E1 channels, the programmed value of these
registers should be consistent with those of registers
XC_PIND_SRC[1—15] (Table 451) to ensure that clock and
data for the same channel always will be routed together;
while for DS2 channels, the value of these registers should
match those of registers XC2_M23_SRC[1—7] (Table 460)
(even channels).
Reserved.
Source Identifier for External I/O Pin LINERXCLK when
Operating in Low Clock Output Mode. (Either DS1/E1 or
DS2.) For DS1/E1 channels, the programmed value of these
registers should be consistent with those of registers
XC_PIND_SRC[1—15] (Table 451) to ensure that clock and
data for the same channel will always be routed together;
while for DS2 channels, the value of these registers should
match those of registers XC2_M23_SRC[1—7] (odd channels).
Reset
Default
0xFF
(invalid)
0x00
0xFF
(invalid)
Note: External I/O has 29 channels.
Agere Systems Inc.
327
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
13 Cross Connect (XC) Registers (continued)
13.2 Cross Connect Register Map
Table 467. Register Address Map
Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.
Addr
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Cross Connect Global—RO
0x50000
XC_ID_R
0x50001
—
0x5000D
—
XC_VERSION[2:0]
XC_ID[7:0]
Framer System Interface Control—R/W
0x5000E XC_CHI_MODE1_
R
0x5000F XC_CHI_MODE2_
R
0
XC_CHI_MODE7[1:0]
XC_CHI_MODE6[1:0]
XC_CHI_MODE5[1:0]
XC_CHI_MODE4[1:0]
XC_CHI_MODE3[1:0]
XC_SYNC_ XC_SI_CHI
FOR_DATA
XC_CHI_MODE2[1:0]
XC_CHI_MODE1[1:0]
DS1/E1 Crosspoint Configuration—R/W
External I/O (LINETXDATA[1—29] and LINETXCLK[1—29] Pins) Data and Clock Output Selects
0x50010 XC_PIND_SRC[1—
—
14]
0x5001D
XC_PDATA[2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28][7:0] Source_ID
XC_PDATA29[7:0] Source_ID
0x5001E XC_PIND_SRC15
0x5001F
XC_PDATA[1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27][7:0] Source_ID
—
DS1/E1 Crosspoint Configuration—R/W
Framer Receive Path Selects
0x50020 XC_FRP_SRC[1—
—
14]
0x5002D
XC_RP_RDATA[2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28][7:0] Source_ID
XC_RP_RDATA[1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27][7:0] Source_ID
0x5002E
0x5002F
DS1/E1 Crosspoint Configuration—R/W
M13 MUX Selects
0x50030 XC_M13_SRC[1—
—
14]
0x5003D
XC_MDS1DATA[2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28][7:0] Source_ID
XC_MDS1DATA[1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27][7:0] Source_ID
0x5003E
0x5003F
DS1/E1 Crosspoint Configuration—R/W
VT Mapper Selects
0x50040
—
0x5004D
XC_VT_SRC[1—
14]
XC_VDATA[2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28][7:0] Source_ID
XC_VDATA[1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27][7:0] Source_ID
0x5004E
0x5004F
328
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
13 Cross Connect (XC) Registers (continued)
Table 467. Register Address Map (continued)
Addr
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DS1/E1 Crosspoint Configuration—R/W
Jitter Attenuation Selects
0x50050 XC_DJA_SRC[1—
—
14]
0x5005D
0x5005E
—
0x5005F
—
XC_JDATA[2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28][7:0] Source_ID
XC_JDATA[1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27][7:0] Source_ID
DS1/E1 Crosspoint Configuration—R/W
Framer Transmit Path Selects
0x50060 XC_FTP_SRC[1—
—
14]
0x5006D
0x5006E
—
0x5006F
XC_TP_RDATA[2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28][7:0] Source_ID
XC_TP_RDATA[1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27][7:0] Source_ID
—
DS1/E1 Crosspoint Configuration—R/W
Framer RS (System Interface) Selects
0x50070 XC_FRS_SRC[1—
—
14]
0x5007D
XC_RS_D[2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28][7:0] Source_ID
XC_RS_D[1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27][7:0] Source_ID
0x5007E
—
0x5007F
—
0x50080
XC_TPM_SRC1
XC_TPM_DS1_DATA[7:0] Source_ID
0x50081
XC_TPM_SRC2
XC_TPM_DS1_IDLE[7:0] Source_ID
0x50082
XC_TPM_SRC3
XC_TPM_E1_DATA[7:0] Source_ID
0x50083
XC_TPM_SRC4
0x50084
0x5008F
—
Test-Pattern Monitor (TPM) Inputs
DS2 Crosspoint Configuration—R/W
M12 MUX/DeMUX Selects
0x50090 XC2_M12_SRC[1—
—
7]
0x50096
0x50097
—
0x5009F
XC2_DS2M12CLK[1—7][7:0] Source_ID
XC2_M21_[1—7][7:0] Source_ID
—
Agere Systems Inc.
329
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
13 Cross Connect (XC) Registers (continued)
Table 467. Register Address Map (continued)
Addr
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DS2 Crosspoint Configuration—R/W
M23 MUX Selects
0x500A0 XC2_M23_SRC[1—
—
7]
0x500A6
0x500A7
XC2_MDS2M23DATA[1—7][7:0] Source2_ID
—
DS2 Crosspoint Configuration—R/W
Test-Pattern Monitor (TPM) Inputs
0x500A8
XC2_TPM_SRC
0x500A9
—
0x500BF
—
0x500C0
XC_MISC
0x500C1
—
0x500D2
—
0x500D3
XC3_TPM_SRC
XC2_TSOURCE_ID[7:0] Data Source2_ID
Miscellaneous
XC_DS2
ALCOEN
XC_DS1
ALCOEN
XC_RPOAC XC_TPOAC XC_RSTS1_ XC_TSTS1_
_EN
_EN
TUG3
TUG3
DS3 Crosspoint Configuration—R/W
0
XC3_TSOURCE_ID[1:0]
0
0
0x500D4 XC3_MDS3_SRC
0x500D5
—
0x500DF
0
0
0
XC3_SOURCE_ID[1:0]
—
DS1/E1 Crosspoint Configuration—R/W
External I/O (LINETXSYNC Pins) Sync Selects
0x500E0 XC_PINS_SRC[1—
—
14]
0x500ED
XC_SYNC[2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28][7:0] SOURCE ID
XC_SYNC29[7:0] SOURCE_ID
0x500EE XC_PINS_SRC15
0x500EF
XC_SYNC[1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27][7:0] SOURCE_ID
—
DS1/E1 Crosspoint Configuration—R/W
Low Clock Out Selects
0x500F0 XC_ALCO_SRC[1
—
—14]
0x500FD
0x500FE XC_ALCO_SRC15
0x500FF
330
XC_ALCO[2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28][7:0] Source_ID
XC_ALCO[1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27][7:0] Source_ID
XC_ALCO29 Source_ID
—
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
14 Digital Jitter Attenuation Controller Registers
Table of Contents
Contents
Page
14 Digital Jitter Attenuation Controller Registers ................................................................................................. 331
14.1 Digital Jitter Attenuation Controller Register Descriptions ....................................................................... 332
14.2 Digital Jitter Attenuation Controller Register Map ................................................................................... 335
Tables
Page
Table 468. DJA_VERSION, DJA Version and Identification (RO) .......................................................................332
Table 469. DJA_EVENT1—DJA_EVENT2, Loss of Clock and Overflow/Underflow Delta
(COR/COW) .......................................................................................................................................332
Table 470. DJA_MASK1—DJA_MASK2, Loss of Clock and Overflow/Underflow Masks (R/W) .........................332
Table 471. DJA_STATE1—DJA_STATE2, Loss of Clock and VT Pointer Adjustment Indicators
(R/W) ..................................................................................................................................................333
Table 472. DJA_E1GAINH—DJA_E1GAINL, E1 Accumulator Gain Threshold (R/W) ........................................333
Table 473. DJA_DS1GAINH—DJA_DS1GAINL, DS1 Accumulator Gain Threshold (R/W) ................................333
Table 474. DJA_E1SCALE, E1 Scale Factor (R/W) ............................................................................................333
Table 475. DJA_DS1SCALE, DS1 Scale Factor (R/W) .......................................................................................333
Table 476. DJA_E1PTRH—DJA_E1PTRL, E1 First-Order Loop Counter (R/W) ...............................................334
Table 477. DJA_DS1PTRH—DJA_DS1PTRL, DS1 First-Order Loop Counter (R/W) ........................................334
Table 478. DJA_DS1SELH—DJA_DS1SELL, DS1 E1 Mode Select (R/W) .......................................................334
Table 479. DJA_CLK_CTL1—DJA_CLK_CTL4, Reference Clock Rate and Edge Transitions (R/W) ...............334
Table 480. DJA Register Map ..............................................................................................................................335
Agere Systems Inc.
331
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
14 Digital Jitter Attenuation Controller Registers (continued)
14.1 Digital Jitter Attenuation Controller Register Descriptions
This section gives a brief description of each register bit and its functionality. The abbreviations after each register
indicate if the register is read only (RO), clear-on-read/clear-on-write (COR/COW), or read/write (R/W).
Table 468. DJA_VERSION, DJA Version and Identification (RO)
Address
Bit
Name
0x70000
15:11
10:8
—
DJA_VERSION[2:0]
7:0
DJA_ID[7:0]
Function
Reserved.
Block Version Number. Block version register
will change each time the device is changed.
Block ID Number.
Reset
Default
00000
0x0
0x7
Table 469. DJA_EVENT1—DJA_EVENT2, Loss of Clock and Overflow/Underflow Delta
(COR/COW)
Address
Bit
Name
0x70003
15
14
13
12
11:0
15:0
DJA_G_DS1_DLT
DJA_DS1_DLT
DJA_G_E1_DLT
DJA_E1_DLT
DJA_ESOVFL[28:17]
DJA_ESOVFL[16:1]
0x70003
0x70004
Function
Reset
Default
0
0
0
0
0x0
G_PIN_DS1XCLK Loss of Clock Delta.
PIN_DS1XCLK Loss of Clock Delta.
G_PIN_E1XCLK Loss of Clock Delta.
PIN_E1XCLK Loss of Clock Delta.
Elastic Store Overflow/Underflow Event.
Table 470. DJA_MASK1—DJA_MASK2, Loss of Clock and Overflow/Underflow Masks (R/W)
Address
Bit
Name
Function
0x70006
15
DJA_G_DS1_MSK
14
DJA_DS1_MSK
13
DJA_G_E1_MSK
12
11:0
15:0
DJA_E1_MSK
DJA_ESOVFL_MSK[28:17]
DJA_ESOVFL_MSK[16:1]
G_PIN_DS1XCLK Loss of Clock Indication
Mask.
PIN_DS1XCLK Loss of Clock Indication
Mask.
G_PIN_E1XCLK Loss of Clock Indication
Mask.
PIN_E1XCLK Loss of Clock Indication Mask.
Elastic Store Over/Underflow Indication
Mask.
0x70006
0x70007
332
Reset
Default
1
1
1
1
0xFFFFFFF
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
14 Digital Jitter Attenuation Controller Registers (continued)
Table 471. DJA_STATE1—DJA_STATE2, Loss of Clock and VT Pointer Adjustment Indicators
(R/W)
Address
Bit
Name
Function
0x70009
15
DJA_G_DS1LOC
G_PIN_DS1XCLK Loss of Clock Indication. (1 = LOC.)
14
DJA_DS1LOC
PIN_DS1XCLK Loss of Clock Indication. (1 = LOC.)
13
DJA_G_E1LOC
G_PIN_E1XCLK Loss of Clock Indication. (1 = LOC.)
12
DJA_E1LOC
PIN_E1XCLK Loss of Clock Indication. (1 = LOC.)
15:11
—
Reserved.
11:0 DJA_PTRADJS[28:17] VT Pointer Adjustment Indicator State. When this state
0x7000A 15:0
DJA_PTRADJS[16:1] is high, the associated PLL has experienced a VT pointer
adjustment within the last PTRADJCNT register specified
time interval.
Reset
Default
0
0
0
0
0
Table 472. DJA_E1GAINH—DJA_E1GAINL, E1 Accumulator Gain Threshold (R/W)
Address
Bit
0x7000B 15:11
10:0
0x7000C 15:0
Name
Function
—
DJA_E1GAIN[26:16]
DJA_E1GAIN[15:0]
Reserved.
E1 Gain. Accumulator gain threshold at which a
clock adjustment takes place for E1 signals (see
Table 622, PLL Bandwidth Control Parameters
on page573 ).
Reset
Default
0x7FFFFFF
Table 473. DJA_DS1GAINH—DJA_DS1GAINL, DS1 Accumulator Gain Threshold (R/W)
Address
Bit
0x7000D 15:11
10:0
0x7000E 15:0
Name
Function
—
DJA_DS1GAINTHR[26:16]
DJA_DS1GAINTHR[15:0]
Reserved.
DS1 Gain. Accumulator gain threshold at which
a clock adjustment takes place for DS1 signals
(see Table 622).
Reset
Default
0x7FFFFFF
Table 474. DJA_E1SCALE, E1 Scale Factor (R/W)
Address
Bit
Name
Function
0x7000F
15:0
DJA_E1SCALE[15:0]
E1 Scale. Scale factor that controls clock adjustment rates for E1 signals (see Table 622).
Reset
Default
0xFFFF
Table 475. DJA_DS1SCALE, DS1 Scale Factor (R/W)
Address
Bit
Name
0x70010
15:0
DJA_DS1SCALE[15:0]
Agere Systems Inc.
Function
DS1 Scale. Scale factor that controls clock
adjustment rates for DS1 signals (see
Table 622).
Reset
Default
0xFFFF
333
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
14 Digital Jitter Attenuation Controller Registers (continued)
Table 476. DJA_E1PTRH—DJA_E1PTRL, E1 First-Order Loop Counter (R/W)
Address
Bit
Name
Function
0x70011
15:5
4:0
15:0
—
DJA_E1PTRADJCNT[20:16]
DJA_E1PTRADJCNT[15:0]
Reserved.
E1 First-Order Loop Count. Count value that
determines the amount of time spent as a firstorder loop following a VT pointer adjustment in
E1 mode (see Table 623, First-Order Mode Duration Control on page573 ).
0x70012
Reset
Default
0x177000
Table 477. DJA_DS1PTRH—DJA_DS1PTRL, DS1 First-Order Loop Counter (R/W)
Address
0x70013
0x70014
Bit
Name
Function
15:5
—
Reserved.
4:0 DJA_DS1PTRADJCNT[20:16] DS1 First-Order Loop Count. Count value that
15:0 DJA_DS1PTRADJCNT[15:0] determines the amount of time spent as a firstorder loop following a VT pointer adjustment in
DS1 mode (see Table 623).
Reset
Default
0x11AB70
Table 478. DJA_DS1SELH—DJA_DS1SELL, DS1 E1 Mode Select (R/W)
Address
Bit
Name
Function
0x70015
15:12
11:0
15:0
—
DJA_DS1SEL[28:17]
DJA_DS1SEL[16:1]
Reserved.
DS1 E1 Mode Select. Control signal that determines the operating mode of each jitter attenuation block (1 = DS1, 0 = E1).
0x70016
Reset
Default
0xFFFFFFF
Table 479. DJA_CLK_CTL1—DJA_CLK_CTL4, Reference Clock Rate and Edge Transitions (R/W)
Address
Bit
Name
0x70017
15:14
13:12
—
DJA_BLUECLKD1[1:0]
0x70017
0x70018
11:0
15:0
DJA_TXEDGE[28:17]
DJA_TXEDGE[16:1]
15:12
11:0
0x7001A 15:0
—
DJA_RXEDGE[28:17]
DJA_RXEDGE[16:1]
0x70019
334
Function
Reset
Default
Reserved.
111
Reference Clock Rate. Control signal that indicates that the input XCLK runs at 32 X (11) or
16 X (01) the line rate or exactly the line rate
(00).
Transmit Edge Select. Control signal that deter- 0xFFFFFFF
mines on which edge of the clock the output
DS1/E1 data transitions (1 = rising edge).
0xFFFFFFF
Reserved.
Receive Edge Select. Control signal that determines on which edge of the clock the input
DS1/E1 data is retimed (1 = rising edge).
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
14 Digital Jitter Attenuation Controller Registers (continued)
14.2 Digital Jitter Attenuation Controller Register Map
The register bank architecture of the microprocessor interface is shown in Table 76 on page73 .
Table 480. DJA Register Map
Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.
Addr
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ID and Interrupt Registers (RO)
0x70000
DJA_VERSION
0x70001
0x70002
—
0x70003
DJA_EVENT1
0x70004
DJA_EVENT2
0x70005
—
0x70006
DJA_MASK1
0x70007
DJA_MASK2
0x70008
—
0x70009
DJA_STATE1
0x7000A
DJA_STATE2
DJA_VERSION[2:0]
DJA_ID[7:0]
Delta and Event Parameters (COR/COW)
DJA_G_DS1DLT
DJA_G_E1DLT
DJA_DS1DLT
DJA_E1DLT
DJA_ESOVFL[28:17]
ESOVFL[16:1]
Interrupt Mask Parameters for INT Pins (R/W)
DJA_G_DS1MSK
DJA_G_E1MS
K
DJA_DS1MS
K
DJA_E1MSK
DJA_ESOVFL[28:17]
ESOVFL[16:1]
State and Value Parameters (RO)
DJA_G_DS1LOC
DJA_G_E1LO
C
DJA_DS1LOC
DJA_E1LOC
DJA_PTRADJS[28:17]
DJA_PTRADJS[16:1]
Control Parameters for PLL Bandwidth and Mode (R/W)
0x7000B
DJA_E1GAINH
0x7000C
DJA_E1GAINL
0x7000D
DJA_DS1GAINH
0x7000E
DJA_DS1GAINH
DJA_E1GAIN[26:16]
DJA_E1GAIN[15:0]
DJA_DS1GAIN[26:16]
DJA_DS1GAIN[15:0]
0x7000F
DJA_E1SCALE
DJA_E1SCALE[15:0]
0x70010
DJA_DS1SCAL
E
DJA_DS1SCALE[15:0]
0x70011
DJA_E1PTRH
0x70012
DJA_E1PTRL
0x70013
DJA_DS1PTRH
0x70014
DJA_DS1PTRL
0x70015
DJA_DS1SELH
0x70016
DJA_DS1SELL
0x70017
DJA_TXEDGEH
0x70018
DJA_TXEDGEL
0x70019
DJA_RXEDGEH
0x7001A
DJA_RXEDGEL
0x7001B
—
0x700FF
—
Agere Systems Inc.
DJA_E1PTRADJCNT[20:16]
DJA_E1PTRADJCNT[15:0]
DJA_DS1PTRADJCNT[20:16]
DJA_DS1PTRADJCNT[15:0]
DJA_DS1SEL[28:17]
DJA_DS1SEL[16:1]
DJA_BLUECLKD[1:0]
DJA_TXEDGE[28:17]
DJA_TXEDGE[16:1]
DJA_RXEDGE[28:17]
DJA_RXEDGE[16:1]
335
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
15 Test-Pattern Generation/Detection Registers
Table of Contents
Contents
Page
15 Test-Pattern Generation/Detection Registers ................................................................................................. 336
15.1 Test-Pattern Generation/Detection Register Descriptions ...................................................................... 337
15.2 Test-Pattern Generation/Detection Register Map .................................................................................. 350
Tables
Page
Table 481. TPG_ID, Status Register (RO) .......................................................................................................... 337
Table 482. TPG_ISRC_OOFD, Delta Register (RO) ........................................................................................... 337
Table 483. TPG_ISRC_OOSD, Delta Register (RO) .......................................................................................... 337
Table 484. TPG_ISRC_BERE, Event Register (RO) .......................................................................................... 338
Table 485. TPG_ISRC_FERE, Event Register (RO) ........................................................................................... 338
Table 486. TPG_ISRC_BPVE, Event Register (RO) ........................................................................................... 338
Table 487. TPG_ISRC_AISD, Delta Register (RO) ............................................................................................. 339
Table 488. TPG_ISRC_CRCE, Event Register (RO) .......................................................................................... 339
Table 489. TPG_IMSK_OOFD, Register (R/W) .................................................................................................. 339
Table 490. TPG_IMSK_OOSD, Register (R/W) .................................................................................................. 339
Table 491. TPG_IMSK_BERE, Register (R/W) ................................................................................................... 340
Table 492. TPG_IMSK_FERE, Register (R/W) ................................................................................................... 340
Table 493. TPG_IMSK_BPV, Register (R/W) ..................................................................................................... 340
Table 494. TPG_IMSK_AISD, Register (R/W) .................................................................................................... 341
Table 495. TPG_IMSK_CRCE, Register (R/W) .................................................................................................. 341
Table 496. TPG_VAL_OOF, Register (RO) ........................................................................................................ 341
Table 497. TPG_VAL_OOS, Register (RO) ........................................................................................................ 342
Table 498. TPG_VAL_AIS, Register (RO) .......................................................................................................... 342
Table 499. TPG_VAL_FER, Register (RO) ......................................................................................................... 342
Table 500. TPG_VAL_CRCE, Register (RO) ...................................................................................................... 343
Table 501. TPG_BER_INSRT, Register (R/W) ................................................................................................... 343
Table 502. TPG_FER_INSRT, Register (R/W) ................................................................................................... 343
Table 503. TPG_CRCE_INSRT, Register (R/W) ................................................................................................ 343
Table 504. TPG_ESFDL_TX, Register (R/W) ..................................................................................................... 344
Table 505. TPG_E1SA_TX12, Register (R/W) .................................................................................................... 344
Table 506. TPG_E1SA_TX34, Register (R/W) .................................................................................................... 344
Table 507. TPG_CONFIG0, Register (R/W) ....................................................................................................... 345
Table 508. TPG_CONFIG2, Register (R/W) ....................................................................................................... 346
Table 509. TPG_CONFIG4, Register (R/W) ....................................................................................................... 347
Table 510. TPG_CONFIG5, Register (R/W) ....................................................................................................... 348
Table 511. TPG_USER, Register (R/W) ............................................................................................................. 348
Table 512. TPM_USER, Register (R/W) ............................................................................................................. 348
Table 513. TPG_BERCNT0, Register (RO) ........................................................................................................ 348
Table 514. TPG_BERCNT2, Register (RO) ........................................................................................................ 349
Table 515. TPG_BERCNT4, Register (RO) ........................................................................................................ 349
Table 516. TPG_BERCNT5, Register (RO) ........................................................................................................ 349
Table 517. TPM_ESFDL_RX, Register (RO) ...................................................................................................... 349
Table 518. TPM_E1SA_RX12, Register (RO) ..................................................................................................... 349
Table 519. TPM_E1SA_RX34, Register (RO) ..................................................................................................... 349
Table 520. Test-Pattern Generation/Detection Register Map ............................................................................. 350
336
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
15 Test-Pattern Generation/Detection Registers (continued)
15.1 Test-Pattern Generation/Detection Register Descriptions
The following tables describe the functions of all bits in the microprocessor register map. For each address, the
register bits are indicated as either read/write (R/W) or read only (RO), and the value of the bits on reset is given.
Table 481. TPG_ID, Status Register (RO)
Address
Bit
Name
0x60000
15
14:11
10:8
TPG_READY
—
TPG_
VERSION[2:0]
TPG_ID[7:0]
7:0
Function
This bit signifies that TPG reset/initialization is complete.
Reserved.
These bits identify the version number of the TPG.
TPG_ID returns a fixed value (0x06) when read.
Reset
Default
1
0x0
0x0
0x06
Table 482. TPG_ISRC_OOFD, Delta Register (RO)
Address
Bit
Name
Function
0x60004
15:3
2
—
TPM_OOF2D
1
0
—
TPM_OOF0D
Reserved.
This bit is set when the TPM monitor E1 test signal out-of-frame
detector changes state (transitions).
Reserved.
This bit is set when the TPM monitor DS1 test signal out-of-frame
detector changes state (transitions).
Reset
Default
0x0000
0
0
0
Table 483. TPG_ISRC_OOSD, Delta Register (RO)
Address
Bit
Name
Function
0x60005
15:6
5
—
TPM_OOS5D
4
TPM_OOS4D
3
2
—
TPM_OOS2D
1
0
—
TPM_OOS0D
Reserved.
This bit is set when the TPM monitor DS3 test signal out-of-sync
detector changes state (transitions).
This bit is set when the TPM monitor DS3 test signal out-of-sync
detector changes state (transitions).
Reserved.
This bit is set when the TPM monitor E1 test signal out-of-sync
detector changes state (transitions).
Reserved.
This bit is set when the TPM monitor DS1 test signal out-of-sync
detector changes state (transitions).
Agere Systems Inc.
Reset
Default
0x000
0
0
0
0
0
0
337
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
15 Test-Pattern Generation/Detection Registers (continued)
Table 484. TPG_ISRC_BERE, Event Register (RO)
Address
Bit
Name
0x60006
15:6
5
—
TPM_BERE5
4
TPM_BERE4
3
2
—
TPM_BERE2
1
0
—
TPM_BERE0
Function
Reserved.
This bit is set when the TPM monitor determines
ing DS3 test signal has a single bit error.
This bit is set when the TPM monitor determines
ing DS2 test signal has a single bit error.
Reserved.
This bit is set when the TPM monitor determines
ing E1 test signal has a single bit error.
Reserved.
This bit is set when the TPM monitor determines
ing DS1 test signal has a single bit error.
that the incom-
Reset
Default
0x000
0
that the incom-
0
that the incom-
0
0
that the incom-
0
0
Table 485. TPG_ISRC_FERE, Event Register (RO)
Address
Bit
Name
Function
0x60007
15:3
2
—
TPM_FERE2
1
0
—
TPM_FERE0
Reserved.
This bit is set when the TPM monitor determines that the incoming E1 test signal has a framing error.
Reserved.
This bit is set when the TPM monitor determines that the incoming DS1 test signal has a framing error.
Reset
Default
0x000
0
0
0
Table 486. TPG_ISRC_BPVE, Event Register (RO)
Address
Bit
Name
Function
0x60008
15:3
2
—
TPM_BPVE2
1
0
—
TPM_BPVE0
Reserved.
This bit is set when the TPM monitor determines that the incoming E1 test signal has a bipolar violation error.
Reserved.
This bit is set when the TPM monitor determines that the incoming DS1 test signal has a bipolar violation error.
338
Reset
Default
0x0000
0
0
0
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
15 Test-Pattern Generation/Detection Registers (continued)
Table 487. TPG_ISRC_AISD, Delta Register (RO)
Address
Bit
Name
0x60009
15:6
5
—
TPM_AIS5D
4
TPM_AIS4D
3
2
—
TPM_AIS2D
1
0
—
TPM_AIS0D
Function
Reset
Default
Reserved.
0x000
This bit is set when the TPM monitors DS3 test signal AIS detec0
tor changes state (transitions).
This bit is set when the TPM monitors DS2 test signal AIS detec0
tor changes state (transitions).
Reserved.
0
This bit is set when the TPM monitors E1 test signal AIS detector
0
changes state (transitions).
Reserved.
0
This bit is set when the TPM monitors DS1 test signal AIS detec0
tor changes state (transitions).
Table 488. TPG_ISRC_CRCE, Event Register (RO)
Address
Bit
Name
0x6000A
15:3
2
1
0
—
TPM_CRCE2
—
TPM_CRCE0
Function
Reserved.
This bit is set when the TPM monitors E1 CRC errors.
Reserved.
This bit is set when the TPM monitors DS1 CRC errors.
Reset
Default
0x000
0
0
0
Table 489. TPG_IMSK_OOFD, Register (R/W)
Address
Bit
Name
0x60010
15:3
2
—
TPM_OOF2DM
1
0
—
TPM_OOF0DM
Function
Reset
Default
Reserved.
0x000
This mask bit is set to suppress an interrupt when the TPM moni1
tor E1 test signal out-of-frame indicator changes.
Reserved.
0
This mask bit is set to suppress an interrupt when the TPM moni1
tor DS1 test signal out-of-frame indicator changes.
Table 490. TPG_IMSK_OOSD, Register (R/W)
Address
Bit
Name
0x60011
15:6
5
—
TPM_OOS5DM
4
TPM_OOS4DM
3
2
—
TPM_OOS2DM
1
0
—
TPM_OOS0DM
Agere Systems Inc.
Function
Reset
Default
Reserved.
0x000
This mask bit is set to suppress an interrupt when the TPM moni1
tor DS3 test signal out-of-sync indicator changes.
This mask bit is set to suppress an interrupt when the TPM moni1
tor DS2 test signal out-of-sync indicator changes.
Reserved.
0
This mask bit is set to suppress an interrupt when the TPM moni1
tor E1 test signal out-of-sync indicator changes.
Reserved.
0
This mask bit is set to suppress an interrupt when the TPM moni1
tor DS1 test signal out-of-sync indicator changes.
339
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
15 Test-Pattern Generation/Detection Registers (continued)
Table 491. TPG_IMSK_BERE, Register (R/W)
Address
Bit
Name
0x60012
15:6
5
—
TPM_BERE5M
4
TPM_BERE4M
3
2
—
TPM_BERE2M
1
0
—
TPM_BERE0M
Function
Reset
Default
Reserved.
0x000
This mask bit is set to suppress an interrupt when the TPM moni1
tor determines that the incoming DS3 test signal has a bit error.
This mask bit is set to suppress an interrupt when the TPM moni1
tor determines that the incoming DS2 test signal has a bit error.
Reserved.
0
This mask bit is set to suppress an interrupt when the TPM moni1
tor determines that the incoming E1 test signal has a bit error.
Reserved.
0
This mask bit is set to suppress an interrupt when the TPM moni1
tor determines that the incoming DS1 test signal has a bit error.
Table 492. TPG_IMSK_FERE, Register (R/W)
Address
Bit
Name
0x60013
15:3
2
—
TPM_FERE2M
1
0
—
TPM_FERE0M
Function
Reset
Default
Reserved.
0x0000
This mask bit is set to suppress an interrupt when the TPM moni1
tor determines that the E1 test signal has a framing error.
Reserved.
0
This mask bit is set to suppress an interrupt when the TPM moni1
tor determines that the DS1 test signal has a framing error.
Table 493. TPG_IMSK_BPV, Register (R/W)
Address
Bit
Name
0x60014
15:3
2
—
TPM_BPV2M
1
0
—
TPM_BPV0M
340
Function
Reset
Default
Reserved.
0x0000
This mask bit is set to suppress an interrupt when the TPM moni1
tor determines that the E1 test signal has a bipolar violation error.
Reserved.
0
1
This mask bit is set to suppress an interrupt when the TPM monitor determines that the DS1 test signal has a bipolar violation
error.
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
15 Test-Pattern Generation/Detection Registers (continued)
Table 494. TPG_IMSK_AISD, Register (R/W)
Address
Bit
Name
0x60015
15:6
5
—
TPM_AIS5DM
4
TPM_AIS4DM
3
2
—
TPM_AIS2DM
1
0
—
TPM_AIS0DM
Function
Reset
Default
Reserved.
0x000
This mask bit is set to suppress an interrupt when the TPM moni1
tor DS3 test signal AIS indicator changes.
This mask bit is set to suppress an interrupt when the TPM moni1
tor DS2 test signal AIS indicator changes.
Reserved.
0
This mask bit is set to suppress an interrupt when the TPM moni1
tor E1 test signal AIS indicator changes.
Reserved.
0
This mask bit is set to suppress an interrupt when the TPM moni1
tor DS1 test signal AIS indicator changes.
Table 495. TPG_IMSK_CRCE, Register (R/W)
Address
Bit
Name
0x60016
15:3
2
—
TPM_CRCE2M
1
0
—
TPM_CRCE0M
Function
Reset
Default
Reserved.
0x0000
This mask bit is set to suppress an interrupt when the TPM moni1
tor detects an E1 test signal CRC-4 error.
Reserved.
0
This mask bit is set to suppress an interrupt when the TPM moni1
tor detects a DS1 test signal CRC-6 error.
Table 496. TPG_VAL_OOF, Register (RO)
Address
Bit
Name
0x60020
15:3
2
—
TPM_OOF2
1
0
—
TPM_OOF0
Agere Systems Inc.
Function
Reserved.
This status bit is set whenever the TPM E1 test monitor has
encountered an out-of-frame condition.
Reserved.
This status bit is set whenever the TPM DS1 test monitor has
encountered an out-of-frame condition.
Reset
Default
0x0000
1
0
1
341
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
15 Test-Pattern Generation/Detection Registers (continued)
Table 497. TPG_VAL_OOS, Register (RO)
Address
Bit
Name
0x60021
15:6
5
—
TPM_OOS5
4
TPM_OOS4
3
2
—
TPM_OOS2
1
0
—
TPM_OOS0
Function
Reserved.
This status bit is set whenever the TPM DS3 test monitor has
encountered an out-of-sync condition.
This status bit is set whenever the TPM DS2 test monitor has
encountered an out-of-sync condition.
Reserved.
This status bit is set whenever the TPM E1 test monitor has
encountered an out-of-sync condition.
Reserved.
This status bit is set whenever the TPM DS1 test monitor has
encountered an out-of-sync condition.
Reset
Default
0x000
1
1
0
1
0
1
Table 498. TPG_VAL_AIS, Register (RO)
Address
Bit
Name
0x60022
15:6
5
—
TPM_AIS5
4
TPM_AIS4
3
2
—
TPM_AIS2
1
0
—
TPM_AIS0
Function
Reserved.
This status bit is set whenever the
encountered an AIS condition.
This status bit is set whenever the
encountered an AIS condition.
Reserved.
This status bit is set whenever the
encountered an AIS condition.
Reserved.
This status bit is set whenever the
encountered an AIS condition.
TPM DS3 test monitor has
Reset
Default
0x000
0
TPM DS2 test monitor has
0
TPM E1 test monitor has
0
0
TPM DS1 test monitor has
0
0
Table 499. TPG_VAL_FER, Register (RO)
Address
Bit
Name
0x60023
15:3
2
—
TPM_FER2
1
0
—
TPM_FER0
342
Function
Reserved.
This status bit is set whenever the TPM E1 test monitor has
encountered an FER condition.
Reserved.
This status bit is set whenever the TPM DS1 test monitor has
encountered an FER condition.
Reset
Default
0x0000
0
0
0
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
15 Test-Pattern Generation/Detection Registers (continued)
Table 500. TPG_VAL_CRCE, Register (RO)
Address
0x60024
Bit
Name
Function
15:3
—
Reserved.
2
TPG_CRCEINS2 This bit is set when the user desires to inject a single CRC error
into the E1 test signal (via 0 to 1 transition).
1
—
Reserved.
0
TPG_CRCEINS0 This bit is set when the user desires to inject a single CRC error
into the DS1 test signal (Via 0 to 1 transition).
Reset
Default
0x0000
0
0
0
Table 501. TPG_BER_INSRT, Register (R/W)
Address
Bit
Name
Function
0x60028
15
TPG_BER_EN
14:6
5
—
TPG_BERINS5
4
TPG_BERINS4
3
2
—
TPG_BERINS2
1
0
—
TPG_BERINS0
This bit, when set, allows automatic bit error insertion by the
microprocessor.
Reserved.
This bit is set when the user desires to inject a single bit error into
the DS3 test signal via SMPR_BER_INSRT (Table 65,
SMPR_GTR, Global Trigger Register (RW) on pag e66).
This bit is set when the user desires to inject a single bit error into
the DS2 test signal via SMPR_BER_INSRT.
Reserved.
This bit is set when the user desires to inject a single bit error into
the E1 test signal via SMPR_BER_INSRT.
Reserved.
This bit is set when the user desires to inject a single bit error into
the DS1 test signal via SMPR_BER_INSRT.
Reset
Default
0
0x000
0
0
0
0
0
0
Table 502. TPG_FER_INSRT, Register (R/W)
Address
Bit
Name
0x60029
15:3
2
—
TPG_FERINS2
1
0
—
TPG_FERINS0
Function
Reset
Default
Reserved.
0x0000
This bit injects a single framing error into the E1 test signal (via 0
0
to 1 transition).
Reserved.
0
This bit injects a single framing error into the DS1 test signal (via
0
0 to 1 transition).
Table 503. TPG_CRCE_INSRT, Register (R/W)
Address
Bit
Name
0x6002A
15:3
2
—
TPG_
CRC4EINS2
—
TPG_
CRC6EINS0
1
0
Agere Systems Inc.
Function
Reset
Default
Reserved.
0x0000
This bit is set when the user desires to inject a single CRC-4 error
0
into the E1 test signal (via 0 to 1 transition).
Reserved.
0
This bit is set when the user desires to inject a single
0
CRC-6 error Into the DS1 test signal (via 0 to 1 transition).
343
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
15 Test-Pattern Generation/Detection Registers (continued)
Table 504. TPG_ESFDL_TX, Register (R/W)
Address
0x6002C
Bit
Name
Function
15:0 TPG_ESFDL[15:0] Data-Link Field to be Sent with Each DS1 Idle Frame.
Reset
Default
0x7E7E
Table 505. TPG_E1SA_TX12, Register (R/W)
Address
Bit
Name
Function
0x6002E 15:13
—
Reserved.
12:8 TPG_E1SA2[4:0] Sa (spare bits [8:4]) to be Sent with E1 Idle Frame.
7:5
—
Reserved.
4:0 TPG_E1SA1[4:0] Sa (spare bits [8:4]) to be Sent with E1 Idle Frame.
Reset
Default
0x0
0x00
0x0
0x00
Table 506. TPG_E1SA_TX34, Register (R/W)
Address
0x6002F
344
Bit
Name
Function
15:13
—
Reserved.
12:8 TPG_E1SA4[4:0] Sa (spare bits [8:4]) to be Sent with E1 Test Frame.
7:5
—
Reserved.
4:0 TPG_E1SA3[4:0] Sa (spare bits [8:4]) to be Sent with E1 Test Frame.
Reset
Default
0x0
0x00
0x0
0x00
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
15 Test-Pattern Generation/Detection Registers (continued)
Table 507. TPG_CONFIG0, Register (R/W)
Address
Bit
Name
Function
0x60030
15:13
TPM_SEQ0[2:0]
12
11
10
TPM_TPINV0
TPG_TPINV0
TPM_EDGE0
9
TPG_EDGE0
8
TPG_TPM_
ESF_0
TPG_TPM_
CODE0[1:0]
These bits select the test pattern to be monitored by the TPG on
the DS1 test input.
This bit, if set, inverts the received data for DS1 test signals.
This bit, if set, inverts the transmitted data for DS1 test signals.
This bit, if set, selects the rising edge of XC_TCLK[0] for use as
the retiming clock edge; or else selects falling edge.
This bit, if set, selects the rising edge of TPG_CLK[0] for use as
the transmit clock edge; or else selects falling edge.
This bit selects extended superframe mode for DS1 Test signals.
7:6
Don’t Use Line Coding/decoding when 00.
Reset
Default
000
0
0
1
1
0
00
Use HDB3 coding/decoding when 01.
Use B8ZS coding/decoding when 10.
Use AMI coding/decoding when 11.
5
4
TPM_FRAME0
TPG_FINV0
3
TPG_FRAME0
2:0
TPG_SEQ0[2:0]
This code is common to the generator and monitor sides.
This bit is set to select a framed DS1 Test pattern in the monitor.
If this bit is set, the frame bit in the 12th frame of each superframe
is inverted in the DS1 test pattern.
This bit is set to select a framed DS1 test pattern in the generator.
These Bits Select the Test Pattern to be Generated and
Transmitted by the TPG on the DS1 Test Output.
0
0
0
000
000 = PRBS15
001 = PRBS20
010 = QRSS
011 = PRBS23
100 = Alternating 01
101 = All ones
110 = Unused
111 = User defined
Agere Systems Inc.
345
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
15 Test-Pattern Generation/Detection Registers (continued)
Table 508. TPG_CONFIG2, Register (R/W)
Address
Bit
Name
Function
0x60032
15:13
TPM_SEQ2[2:0]
12
11
TPM_TPINV2
TPG_TPINV2
10
TPM_EDGE2
9
TPG_EDGE2
8
TPG_TPM_
CRC4_EN2
These Bits Select the Test Pattern to be Monitored by the
TPG on the E1 Test Input.
This Bit, if Set, Inverts the Received Data for E1 Test Signals.
This Bit, if Set, Inverts the Transmitted Data for E1 Test Signals.
This Bit, if Set, Selects the Rising Edge of XC_TCLK[2] for
Use as the Retiming Clock Edge; or Else Selects Falling
Edge.
This Bit, if Set, Selects the Rising Edge of TPG_CLK[2] for
Use as the Transmit Clock Edge; or Else Selects Falling
Edge.
This Bit, if Set, Enables CRC-4 Insertion if E1 Framing is
Selected.
7:6
TPG_TPM_
CODE2[1:0]
This bit is common to the generator and monitor sides.
Don’t uSe Line Coding/decoding when 00.
Reset
Default
000
0
0
1
1
0
00
Use HDB3 coding/decoding when 01.
Use B8ZS coding/decoding when 10.
Use AMI coding/decoding when 11.
5
4
TPM_FRAME2
TPG_FINV2
3
2:0
TPG_FRAME2
TPG_SEQ2[2:0]
This code is common to the generator and monitor sides.
This Bit is Set to Select a Framed E1 Test Pattern.
If this Bit is Set, the Frame Alignment Sequence (Normally
0011011) is Transmitted with the Last Bit Inverted (0011010).
This Bit is Set to Select a Framed E1 Test Pattern.
These Bits Select the Test Pattern to Be Generated and
Transmitted by the TPG on the E1 Test Output
(TPG_DATA[2]).
0
0
0
000
000 = PRBS15
001 = PRBS20
010 = QRSS
011 = PRBS23
100 = Alternating 01
101 = All ones
110 = Unused
111 = User defined
346
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
15 Test-Pattern Generation/Detection Registers (continued)
Table 509. TPG_CONFIG4, Register (R/W)
Address
Bit
Name
Function
0x60034
15:13
TPM_SEQ4[2:0]
12
TPM_TPINV4
11
TPG_TPINV4
10
TPM_EDGE4
9
TPG_EDGE4
2:0
TPG_SEQ4[2:0]
These Bits Select the Test Pattern to be Monitored by the
TPG on the DS2 Test Input.
This Bit, if Set, Inverts the Received Data for DS2 Test Signals.
This Bit, if Set, Inverts the Transmitted Data for DS2 Test Signals.
This Bit, if Set, Selects the Rising Edge of XC_TCLK[4] for
Use as the Retiming Clock Edge; or Else Selects Falling
Edge.
This Bit, if Set, Selects the Rising Edge of TPG_CLK[4] for
Use as the Transmit Clock Edge; or Else Selects Falling
Edge.
These Bits Select the Test Pattern to be Generated and
Transmitted by the TPG on the DS2 Output (TPG_DATA[4]).
Reset
Default
000
0
0
1
1
0
000 = PRBS15
001 = PRBS20
010 = QRSS
011 = PRBS23
100 = Alternating 01
101 = All ones
110 = Unused
111 = User defined
Agere Systems Inc.
347
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
15 Test-Pattern Generation/Detection Registers (continued)
Table 510. TPG_CONFIG5, Register (R/W)
Address
Bit
Name
Function
0x60035
15:13
TPM_SEQ5[2:0]
12
TPM_TPINV5
11
TPG_TPINV5
10
TPM_EDGE5
9
TPG_EDGE5
8:3
2:0
—
TPG_SEQ5[2:0]
These Bits Select the Test Pattern to be Monitored by the
TPG on the DS3 Test Input.
This Bit, if Set, Inverts the Received Data for DS3 Test Signals.
This Bit, if Set, Inverts the Transmitted Data for DS3 Test Signals.
This Bit, if Set, Selects the Rising Edge of XC_TCLK[5] for
Use as the Retiming Clock Edge; or Else Selects Falling
Edge.
This Bit, if Set, Selects the Rising Edge of TPG_CLK[5] for
Use as the Transmit Clock Edge; or Else Selects Falling
Edge.
Reserved.
These Bits Select the Test Pattern to be Generated and
Transmitted by the TPG on the DS3 Output (TPG_DATA[5]).
Reset
Default
000
0
0
1
1
—
0
000 = PRBS15
001 = PRBS20
010 = QRSS
011 = PRBS23
100 = Alternating 01
101 = All ones
110 = Unused
111 = User defined
Table 511. TPG_USER, Register (R/W)
Address
Bit
0x60036
15:0
Name
Function
TPG_USER[15:0] User Programmed Test Pattern Generator Data.
Reset
Default
0xDEAD
Table 512. TPM_USER, Register (R/W)
Address
0x60037
Bit
Name
Function
15:0 TPM_USER[15:0] User Programmed Test Pattern Monitor Data.
Reset
Default
0xBEEF
Table 513. TPG_BERCNT0, Register (RO)
Address
Bit
0x60040
15:0
348
Name
Function
Reset
Default
TPM_CNT0[15:0] This Field Holds the Current Counter Value for DS1 Test Pat- 0x0000
tern Bit Errors as Detected by the TPM.
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
15 Test-Pattern Generation/Detection Registers (continued)
Table 514. TPG_BERCNT2, Register (RO)
Address
Bit
0x60042
15:0
Name
Function
TPM_CNT2[15:0] This Field Holds the Current Counter Value for E1 Test Pattern Bit Errors as Detected by the TPM.
Reset
Default
0x0000
Table 515. TPG_BERCNT4, Register (RO)
Address
Bit
0x60044
15:0
Name
Function
Reset
Default
TPM_CNT4[15:0] This Field Holds the Current Counter Value for DS2 Test Pat- 0x0000
tern Bit Errors as Detected by the TPM.
Table 516. TPG_BERCNT5, Register (RO)
Address
Bit
0x60045
15:0
Name
Function
Reset
Default
TPM_CNT5[15:0] This Field Holds the Current Counter Value for DS3 Test Pat- 0x0000
tern Bit Errors as Detected by the TPM.
Table 517. TPM_ESFDL_RX, Register (RO)
Address
Bit
Name
0x6004C
15:0
TPM_
ESFDL[15:0]
Function
Data-Link Field Received from Last DS1 Idle Frame.
Reset
Default
0x0000
Table 518. TPM_E1SA_RX12, Register (RO)
Address
Bit
Name
Function
0x6004E 15:13
—
Reserved.
12:8 TPM_E1SA2[4:0] Sa (spare bits [4:8]) Received from E1 Frame.
7:5
—
Reserved.
4:0 TPM_E1SA1[4:0] Sa (spare bits [4:8]) Received from E1 Frame.
Reset
Default
0x0
0x00
0x0
0x00
Table 519. TPM_E1SA_RX34, Register (RO)
Address
0x6004F
Bit
Name
Function
15:13
—
Reserved.
12:8 TPM_E1SA4[4:0] Sa (spare bits [4:8]) Received from E1 Frame.
7:5
—
Reserved.
4:0 TPM_E1SA3[4:0] Sa (spare bits [4:8]) Received from E1 Frame.
Agere Systems Inc.
Reset
Default
0x0
0x00
0x0
0x00
349
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
15 Test-Pattern Generation/Detection Registers (continued)
15.2 Test-Pattern Generation/Detection Register Map
Table 520. Test-Pattern Generation/Detection Register Map
Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.
Address
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
0x60000
TPG_ID
TPG_
READY
0
0
0
0
0x60001
—
0x60003
—
0x60004
TPG_ISRC_
OOFD
0x60005
TPG_ISRC_
OOSD
TPM_
OOS5D
0x60006
TPG_ISRC_
BERE
TPM_
BERE5
0x60007
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Block-Level Status—RO
TPG_VERSION[2:0]
TPG_ID[7:0]
TPM Interrupt Sources (Deltas and Events)—RO
TPM_
OOF2D
TPM_
OOF0D
TPM_
OOS4D
TPM_
OOS2D
TPM_
OOS0D
TPM_
BERE4
TPM_
BERE2
TPM_
BERE0
TPG_ISRC_
FERE
TPM_
FERE2
TPM_
FERE0
0x60008
TPG_ISRC_
BPVE
TPM_
BPV2
TPM_
BPV0
0x60009
TPG_ISRC_
AISDE
TPM_
AIS2D
TPM_
AIS0D
0x6000A
TPG_ISRC_
CRCE
TPM_
CRCE2
TPM_
CRCE0
0x6000B
—
0x6000F
—
0x60010
TPG_IMSK_
OOFD
TPM_
OOF2DM
TPM_
OOF0DM
0x60011
TPG_IMSK_
OOSD
TPM_
OOS5DM
TPM_
OOS4DM
TPM_
OOS2DM
TPM_
OOS0DM
0x60012
TPG_IMSK_
BERE
TPM_
BERE5M
TPM_
BERE4M
TPM_
BERE2M
TPM_
BERE0M
0x60013
TPG_IMSK_
FERE
TPM_
FERE2M
TPM_
FERE0M
0x60014
TPG_IMSK_
BPV
TPM_
BPV2M
TPM_
BPV0M
0x60015
TPG_IMSK_
AISD
TPM_
AIS2DM
TPM_
AIS0DM
TPM_
AIS5D
TPM_
AIS4D
TPM Interrupt Masks—R/W and Edge Controls
350
TPM_
AIS5DM
TPM_
AIS4DM
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
15 Test-Pattern Generation/Detection Registers (continued)
Table 520. Test-Pattern Generation/Detection Register Map (continued)
Address
Symbol
0x60016
TPG_IMSK_
CRCE
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
0x60017
—
0x6001F
—
0x60020
TPG_VAL_
OOF
0x60021
TPG_VAL_
OOS
TPM_
OOS5
0x60022
TPG_VAL_
AIS
TPM_
AIS5
0x60023
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TPM_
CRCE2M
TPM_
CRCE0M
TPM_
OOF2
TPM_
OOF0
TPM_
OOS4
TPM_
OOS2
TPM_
OOS0
TPM_
AIS4
TPM_
AIS2
TPM_
AIS0
TPG_VAL_
FER
TPM_
FER2
TPM_
FER0
0x60024
TPG_VAL_
CRCE
TPG_CR
CEINS2
TPG_CR
CEINS0
0x60025
—
0x60027
—
TPG_
BERINS2
TPG_
BERINS0
TPM State and Value Parameters—RO
TPG Error Insert Enables—R/W
(Error injection triggered by SMPR_BER_INSRT (Table 65, SMPR_GTR, Global Trigger Register (RW) on page 66))
0x60028
TPG_BER_
INSRT
TPG_
BERINS5
TPG_
BER_EN
TPG_
BERINS4
TPG Error Insert Triggers (rising edge)—R/W
0x60029
TPG_FER_
INSRT
TPG_
FERINS2
TPG_
FERINS0
0x6002A
TPG_CRCE_
INSRT
TPG_
CRC4EIN
S2
TPG_
CRC6EIN
S0
0x6002B
—
0x6002C
TPG_
ESFDL_TX
TPG (Transmit) ESF Data Link and E1 SA-Bits Contents—R/W
TPG_ESFDL[15:0]
0x6002D
—
0x6002E
TPG_E1SA_
TX12
TPG_E1SA2[4:8]
TPG_E1SA1[4:8]
0x6002F
TPG_E1SA_
TX34
TPG_E1SA4[4:8]
TPG_E1SA3[4:8]
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Preliminary Data Sheet
May 2001
15 Test-Pattern Generation/Detection Registers (continued)
Table 520. Test-Pattern Generation/Detection Register Map (continued)
Address
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TPG/TPM Configuration—R/W
(Test Channels Only)
0x60030
TPG_
CONFIG0
0x60031
—
0x60032
TPG_
CONFIG2
TPM_SEQ0[2:0]
TPM_
TPINV0
TPG_
TPINV0
TPM_
EDGE0
TPG_
EDGE0
TPG_
TPM_
ESF_0
TPG_TPM_
CODE0[1:0]
TPM_
FRAME0
TPG_
FINV0
TPG_
FRAME0
TPG_
SEQ0[2:0]
TPM_
SEQ2[2:0]
TPM_
TPINV2
TPG_
TPINV2
TPM_
EDGE2
TPG_
EDGE2
TPG_
TPM_
CRC4_
EN2
TPG_TPM_
CODE2[1:0]
TPM_
FRAME2
TPG_
FINV2
TPG_
FRAME2
TPG_SEQ2[2:0]
0x60033
—
0x60034
TPG_
CONFIG4
TPM_SEQ4[2:0]
TPM_
TPINV4
TPG_
TPINV4
TPM_
EDGE4
TPG_
EDGE4
TPG_SEQ4[2:0]
0x60035
TPG_
CONFIG5
TPM_SEQ5[2:0]
TPM_
TPINV5
TPG_
TPINV5
TPM_
EDGE5
TPG_
EDGE5
TPG_SEQ5[2:0]
0x60036
TPG_USER
TPG_USER[15:0]
0x60037
TPM_USER
TPM_USER[15:0]
0x60038
—
0x6003F
—
TPM Bit Error Counters—RO
(see also PMRST (Table 3, High-speed I/O Pin Descriptions on page 29), SMPR_SAT_ROLLOVER and SMPR_COR_COW (Table 67, SMPR_GCR, Global Control Register (RW) on page 68))
0x60040
TPG_
BERCNT0
0x60041
—
0x60042
TPG_
BERCNT2
TPM_CNT0[15:0]
TPM_CNT2[15:0]
0x60043
—
0x60044
TPG_
BERCNT4
TPM_CNT4[15:0]
0x60045
TPG_
BERCNT5
TPM_CNT5[15:0]
0x60046
—
0x6004B
—
352
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Preliminary Data Sheet
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TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
15 Test-Pattern Generation/Detection Registers (continued)
Table 520. Test-Pattern Generation/Detection Register Map (continued)
Address
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TPM Received DS1-ESF Data Link and E1 Sa-Bits Contents—RO
0x6004C
TPM_
ESFDL_RX
TPM_ESFDL0[15:0]
0x6004D
—
0x6004E
TPM_E1SA_
RX12
TPM_E1SA2[4:8]
TPM_E1SA1[4:8]
0x6004F
TPM_E1SA_
RX34
TPM_E1SA4[4:8]
TPM_E1SA3[4:8]
0x60050
—
0x600FF
—
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Preliminary Data Sheet
May 2001
Functional Descriptions
16 Microprocessor Interface Functional Description
Table of Contents
Contents
Page
16 Microprocessor Interface Functional Description ........................................................................................... 354
16.1 Introduction ............................................................................................................................................. 355
16.2 Features ................................................................................................................................................. 355
16.3 Microprocessor Interface ........................................................................................................................ 355
16.4 MPU Block Diagram ............................................................................................................................... 356
16.5 Super Mapper Register Address Mapping ............................................................................................. 356
16.6 Performance Monitoring (PM) Counters Operation ................................................................................ 356
16.7 Super Mapper Global Interrupt Status and Control ................................................................................ 358
16.8 Global Control ......................................................................................................................................... 358
Figures
Page
Figure 18. Microprocessor Interface..................................................................................................................... 356
Figure 19. PM Reset Counter ............................................................................................................................... 357
Figure 20. PM Reset Signal Generation ............................................................................................................... 357
Tables
Page
Table 521. Super Mapper Register Address Mapping ........................................................................................ 356
354
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TMXF28155 Super Mapper
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16 Microprocessor Interface Functional Description (continued)
16.1 Introduction
The Super Mapper microprocessor interface consists of a 20-bit address and a 16-bit data bus. In addition, this
block contains global control and status registers. These registers include the summary of interrupt status of major
functional blocks and the control to enable them or power them down.
16.2 Features
■
20-bit address/16-bit data bus microprocessor interface.
■
Synchronous (16 MHz to 66 MHz)/asynchronous microprocessor interface modes.
■
Microprocessor data bus parity monitoring.
■
Summary of interrupts from major functional blocks/maskable.
■
Separate device interrupt outputs for automatic protection switch and the Super Mapper global interrupt.
■
Global configuration of network performance monitoring counters operation.
■
Global software resets.
■
Global enabling and powering down of major functional blocks.
■
Miscellaneous global configuration and control.
16.3 Microprocessor Interface
This device is equipped with a generic 20-bit address/16-bit data microprocessor interface that allows operation
with most commercially available microprocessors. Device input pin MPMODE (pin AD17) is used to configure this
interface into one of two possible modes (synchronous or asynchronous). In synchronous mode (MPMODE = 1),
the microprocessor interface can operate at speeds from 16 MHz up to 66 MHz. In asynchronous mode
(MPMODE = 0), a 16 MHz to 66 MHz clock is required on the MPCLK (pin AE17) pin for proper operation.
Two parity detectors are provided for the microprocessor data bus, one for the higher-order byte and one for the
lower-order byte. The parity sense is programmed as even or odd with register bit SMPR_PARITY_EVEN_ODD
(Table 67 on page68 ). The composite status of both parity detectors is indicated in register bit SMPR_PARITY_IS
(Table 63 on page64 ). The interrupt from this status indicator may be masked with register bit SMPR_PARITY_IM
(Table 64 on page65 ). A bad parity event does not inhibit a data transfer. The microprocessor interface is fully
functional without parity supplied by the host processor.
The interrupt status from each of the major blocks, the automatic protection switch, and the microprocessor data
bus parity are summarized in Table 63 on page 64. Each interrupt is maskable with the complementary bit set in
the interrupt mask register, see Table 64 on page65 .
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Preliminary Data Sheet
May 2001
16 Microprocessor Interface Functional Description (continued)
16.4 MPU Block Diagram
MPCLK
ADDR[19:0]
INTERNAL
ADDRESS
CSN
ADSN
INTERNAL
DATA
DSN
INTERNAL
CONTROL
RWN
DATA[15:0]
DTN
PAR[1:0]
MPMODE
INTN
APS_INTN
5-9039(F)r.2
Figure 18. Microprocessor Interface
16.5 Super Mapper Register Address Mapping
Each of the Super Mapper’s major functional blocks is selected with an address mapping of the highest order nibble, device pins ADDR[19:16], and allocated a 16-bit address range, pins ADDR[15:0], as defined in Table 521.
Table 521. Super Mapper Register Address Mapping
ADDR[19:16]
0000
0001
0010
0011
0100
0101
0110
0111
1000
Block ID
0
1
2
3
4
5
6
7
8
Block Name
TOP
M13
VTMPR
SPEMPR
TMUX
XC
TPG
DJA
FRAMER
ADDR
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
16.6 Performance Monitoring (PM) Counters Operation
PM counters are error counters or other statistics counters. In general, two internal registers are needed to implement a PM counter: a running count register (1), maintained by the core logic, which is incremented by 1, every
time an error (or statistics event) happens. At a defined interval, one second for example, the content of the running
counter is transferred to a holding register (2), while the running count register is reset to 0 and starts to count
anew. The count holding register holds the data that microprocessor actually reads.
356
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TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
16 Microprocessor Interface Functional Description (continued)
PM COUNTER CONTROL
PM COUNTER
MPU READ HOLDING
REGISTER
RESET
PM COUNT EVENT
RUNNING
COUNTER
ENABLE
HOLDING
COUNTER
BUFFERED
MPUCLK
MPU READABLE
(ONE PER BLOCK)
PM COUNT EVENT CLOCK
5-9040(F)r.3
Figure 19. PM Reset Counter
The PM counter control signal controls the transfer and reset of all performance monitoring registers (collecting
events/statistics). The source of this signal is configurable and can come from external pin (PMRST pin T25), an
internal timer, or be controlled by software, depending on the SMPR_PMMODE[1:0] bits (Table 67, bits 9:8),
described as follows:
SMPR_PMMODE[1:0] = 00, 10: PM counter control is sourced from external pin PMRST.
SMPR_PMMODE[1:0] = 01: PM counter control is sourced from internal 1 second timer. Writing a logic one to the
SMPR_PMRESET bit (Table 65, bit 8) will reset the timer so that a transition occurs on the internal PM counter
control signal within 10 MPCLK clock cycles. The timer is based on the period of the MPCLK and the programmed
value of the registers in Table 72 and Table 73. Once initially reset and synchronized, the PM counter reset interval
is determined by the combined delay of the programmed registers. The device pin, PMRST, is enabled as an output.
SMPR_PMMODE[1:0] = 11: The PM counter control signal is software controlled. Writing a logic one to the
SMPR_PMRESET bit will cause a PM reset within 10 MPCLK cycle times after writing. This pulse will be
100 cycles high and 100 cycles low at the MPCLK frequency. During this 200 cycle time, writing to PM bit will have
no effect. The device pin, PMRST, is enabled as an output.
EXTERNAL
(SMPR_PMMODE[1:0] = 00, 10)
PMRSTI
PMRST (TO BLOCKS)
SMPR_PMRESET
(REGISTER SMPR_GTR bit 8)
SOFTWARE CONTROLLED
(SMPR_PMMODE[1:0] = 11)
PMRSTO
MPUCLK
DELAY
SMPR_PMRESET_HIGH_COUNT
SMPR_PMRESET_LOW_COUNT
MPUCLK
FREE RUNNING
(SMPR_PMMODE[1:0] = 01)
OUTPUT ENABLED
SMPR_PMMODE[1:0] = 01, 11
OUTPUT DISABLED
SMPR_PMMODE[1:0] = 00, 10
1/2 SECOND
COUNTERS
SMPR_PMMODE
(REGISTER SMPR_GCR bits[9:8])
MPU BLOCK
5-9931(F)
Figure 20. PM Reset Signal Generation
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TMXF28155 Super Mapper
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Preliminary Data Sheet
May 2001
16 Microprocessor Interface Functional Description (continued)
16.7 Super Mapper Global Interrupt Status and Control
The Super Mapper provides two hardware interrupt output pins: one global (INTN pin AB24) and one for the
SONET automatic protection switching (APS_INTN pin AC25). Both interrupt pins are active-low and are opendrain outputs to allow a wired OR with complementary devices.
Interrupt status for major functional blocks are summarized in Table 63 and maskable in Table 64.
16.8 Global Control
Several registers in this block provide global control of Super Mapper features. The register descriptions are selfexplanatory, but some highlights are listed as follows:
■
Global enabling and powering down of major functional blocks is shown in Table 71 SMPR_CPCR, Clock and
Power Control Register (RW) on page 71.
■
Software resets for major functional blocks are shown in Table 66 SMPR_MSRR, Block Software Reset Register
(RW) on page66 .
■
Global reset of the Super Mapper is controlled with SMPR_SWRS, bit 8 in Table 65 SMPR_GTR, Global Trigger
Register (RW) on page 66.
358
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Preliminary Data Sheet
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TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
17 TMUX Functional Description
Table of Contents
Contents
Page
17 TMUX Functional Description ......................................................................................................................... 359
17.1 TMUX Introduction .................................................................................................................................. 361
17.2 TMUX Features ...................................................................................................................................... 361
17.3 TMUX Receive Path Overview ............................................................................................................... 362
17.3.1 Receive Line Framer and Transport Overhead Termination ....................................................... 362
17.3.2 Receive Transport Overhead Monitor and RTOAC Drop ............................................................ 362
17.3.3 Receive MSP 1 + 1 Payload Switch ............................................................................................. 363
17.3.4 Receive Pointer Interpreter .......................................................................................................... 363
17.3.5 Receive High-Order Path Overhead Termination and RPOAC Drop .......................................... 363
17.3.6 Receive Byte Interleave Demultiplexer ........................................................................................ 363
17.3.7 Receive Telecom Bus .................................................................................................................. 363
17.4 TMUX Transmit Path Overview .............................................................................................................. 364
17.4.1 Transmit Telecom Bus ................................................................................................................. 364
17.5 Receive Direction (Receive Path from Sonet Global/SDH) .................................................................... 368
17.5.1 Input Clock and Loss-of-Signal Monitoring .................................................................................. 369
17.5.2 High-Speed Loopback Select Logic ............................................................................................. 369
17.5.3 Frame Alignment—STS-3/STM-1 (AU-4) Framing or STS-1 Framing ......................................... 369
17.5.4 B1 BIP-8 Check ........................................................................................................................... 369
17.5.5 J0 Monitor .................................................................................................................................... 370
17.5.6 Descrambler ................................................................................................................................. 370
17.5.7 F1 Monitor .................................................................................................................................... 371
17.5.8 B2 BIP-8 Check ........................................................................................................................... 371
17.5.9 Automatic Protection Switch (APS) Monitor ................................................................................. 371
17.5.10 K2 Monitor, AIS-L and RDI-L Detect .......................................................................................... 371
17.5.11 M1 REI-L Detect ........................................................................................................................ 372
17.5.12 Sync Status Monitor ................................................................................................................... 372
17.5.13 Receive Transport Overhead Access Channel (RTOAC) .......................................................... 372
17.5.14 MSP 1 + 1 Payload Switch ......................................................................................................... 374
17.5.15 Pointer Interpreter ...................................................................................................................... 374
17.5.16 Path Monitoring Functions ......................................................................................................... 377
17.6 Transmit Direction (Transmit Path to SONET/SDH Line) ....................................................................... 386
17.6.1 Transmit Side Telecom Bus Interface .......................................................................................... 386
17.6.2 Transmit Path and Transport Overhead Insertion Diagram ......................................................... 386
17.6.3 POAC Insert ................................................................................................................................. 388
17.6.4 AIS Path Generation .................................................................................................................... 389
17.6.5 J1 Insert Control ........................................................................................................................... 389
17.6.6 B3 BIP-8 Calculation and Insert ................................................................................................... 389
17.6.7 C2 Signal Label Byte Insert ......................................................................................................... 389
17.6.8 Path RDI (RDI-P) Insert ............................................................................................................... 390
17.6.9 REI-P: G1(7:4) Insert ................................................................................................................... 390
17.6.10 F2 Byte Insert ............................................................................................................................. 391
17.6.11 H4 Insert Control ........................................................................................................................ 391
17.6.12 F3 Byte Insert ............................................................................................................................. 391
17.6.13 K3 Byte Insert ............................................................................................................................ 391
17.6.14 N1 Byte Insert ............................................................................................................................ 391
17.6.15 MSP 1 + 1 Payload Switch ......................................................................................................... 391
17.6.16 Transmit Transport Overhead Access Channel (TTOAC) ......................................................... 391
17.6.17 Sync Status Byte (S1) Insert ...................................................................................................... 393
17.6.18 REI-L: M1 Insert ......................................................................................................................... 393
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17 TMUX Functional Description (continued)
Table of Contents (continued)
Contents
Page
17.6.19 APS Value and K2 Insert Control Parameters ........................................................................... 393
17.6.20 Criteria for Insert Line RDI ......................................................................................................... 394
17.6.21 Line AIS Generation ................................................................................................................... 394
17.6.22 B2 BIP-8 Calculation and Insert ................................................................................................. 394
17.6.23 F1 Byte Insert ............................................................................................................................. 394
17.6.24 B1 Generate and Error Insert ..................................................................................................... 395
17.6.25 Scrambler ................................................................................................................................... 395
17.6.26 J0 Insert Control ......................................................................................................................... 395
17.6.27 Z0-2, Z0-3 Insert Control ............................................................................................................ 395
17.6.28 A2 Error Insert ............................................................................................................................ 395
Figures
Page
Figure 21. TMUX RTOAC Timing Diagram .......................................................................................................... 362
Figure 22. TMUX TTOAC and RTOAC Timing Diagram ...................................................................................... 365
Figure 23. High-Level TMUX Interconnect ........................................................................................................... 365
Figure 24. Detailed Block Diagram of the TMUX .................................................................................................. 366
Figure 25. Receive Direction Functional Block Diagram ...................................................................................... 367
Figure 26. Pointer Interpretation State Diagram................................................................................................... 374
Figure 27. Receive Low-Speed Bus Interface Signals for STS-3/STM-1 Signals ................................................ 385
Figure 28. Transmit Low-Speed Bus Interface Signals for STS-3/STM-1 Signals ............................................... 386
Figure 29. Transmit Direction POH and TOH Insertion Diagram ......................................................................... 387
Tables
Page
Table 522. Receive TOAC Modes ....................................................................................................................... 373
Table 523. Transport Overhead Byte Access—Receive Direction ...................................................................... 373
Table 524. STS Signal Label Defect Conditions ................................................................................................. 379
Table 525. STS-1 P-REI Interpretation ................................................................................................................ 380
Table 526. Signal Degrade (SD) Parameters ...................................................................................................... 382
Table 527. Signal Fail Parameters ...................................................................................................................... 383
Table 528. Signal Fail or Signal Degrade Recommended Programming Values ................................................ 384
Table 529. Path Overhead Byte Access .............................................................................................................. 384
Table 530. Path Overhead Byte Access—Transmit Direction ............................................................................. 388
Table 531. TPOAC Control Bits ........................................................................................................................... 389
Table 532. RDI-P Defects for Enhanced RDI-P Mode ........................................................................................ 390
Table 533. Transmit TOAC Modes ...................................................................................................................... 392
Table 534. Transmit Transport Overhead Byte Full Access Mode ...................................................................... 392
Table 535. TTOAC Control Bits in Full Access Mode .......................................................................................... 393
360
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TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
17 TMUX Functional Description (continued)
17.1 TMUX Introduction
The TMUX multiplexer block implements SDH/SONET-compliant, byte-interleave multiplexing/demultiplexing, overhead insertion and termination, multiplex section protection (MSP) 1 + 1 switch capability, and serializer/deserializer for 155.52 Mbits/s and 51.84 Mbits/s traffic.
As shown in Figure 23 on page 365, the TMUX provides three modes of operation: STS-3 mode, STM-1 mode, and
STS-1 mode. In STS-3 mode, the TMUX implements the functions necessary to multiplex and demultiplex up to
three STS-1 signals to/from a SONET STS-3 signal. In STM-1 (VC-4) mode, the TMUX provides the functionality to
multiplex and demultiplex up to three TUG-3 signals to/from an STM-1(VC-4) signal. The device can also build/
extract up to three AU-3 signals to/from an STM-1(VC-3) stream. In STS-1 mode, the TMUX implements the functions necessary to interface a single STS-1 to/from an external serial link.
On the high-speed side or line side, the block can be configured for either a 155.52 Mbits/s (STS-3/STM-1) or
51.84 Mbits/s (STS-1) serial data interface. On the low-speed side or tributary side, the TMUX provides a byte-wide
bus that can communicate with up to three STS-1/TUG-3/AU-3 devices at a 19.44 MHz rate. If single STS-1 mode
is employed, the bus rate will be 6.48 MHz. The TMUX therefore provides complete multiplexing/demultiplexing
to/from an STS-3/STM-1 signal for up to 84 DS1, 84 JT1, or 63 E1 signals. In STS-1 mode, the TMUX provides
multiplexing/demultiplexing for up to 28 DS1, 28 JT1, or 21 E1 streams. In STS-3/STM-1 mode, the TMUX from
only one device is required. The TMUX in other connected devices may be powered down to reduce consumed
power. This architecture allows flexible and modular growth in equipment capacity for both 51.84 Mbits/s and
155.52 Mbits/s links.
17.2 TMUX Features
■
Multiplexes three STS-1 signals into a SONET STS-3 signal.
■
Multiplexes three VC-3 signals into an SDH STM-1 (AU-4) signal via a TUG-3 construction.
■
Multiplexes three VC-3 signals into an SDH STM-1 (AU-3) signal.
■
Demultiplexes three STS-1 signals from a SONET STS-3 signal.
■
Demultiplexes three VC-3 signals from an SDH STM-1 (AU-4) signal via a TUG-3 deconstruction.
■
Demultiplexes three VC-3 signals from an SDH STM-1 (AU-3) signal.
■
Provides STS-1-only mode for receive and transmit directions.
■
Provides complete functionality for SDH MSP 1 + 1 protection switching.
■
Detects STS-3/STM-1 loss-of-signal (LOS) conditions.
■
Detects STS-3/STM-1 out-of-frame and loss-of-frame (OOF/LOF) conditions.
■
Provides an 8-bit parallel bus interface that can accommodate up to three STS-1/AU-3s.
■
Provides STS-3/STM-1/STS-1 selectable scrambler/descrambler functions and B1/B2/B3 generation/detection.
■
Provides STS-3/STM-1/STS-1 pointer interpretation. Detects AIS-P and LOP.
■
Complies with GR-253-CORE, T1.105, G.707, G.783, G.806, G.821, and ETSI 417-1-1.
Agere Systems Inc.
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Preliminary Data Sheet
May 2001
17 TMUX Functional Description (continued)
17.3 TMUX Receive Path Overview
A detailed drawing of the TMUX receive path is provided in the bottom half of Figure 24 on page366 . For the
receive path, the TMUX implements two serial inputs for both the work and protect streams of an MSP 1 + 1 network interface. Synchronous data (SDH/SONET) framers are implemented to frame on the incoming receive data
streams. One or both may be employed depending on system architecture. The incoming traffic is converted from
serial to byte-wide parallel. The transport overhead bytes of the incoming traffic are monitored and dropped via the
receive path TOAC drop interface. A multiplexer implements the receive MSP 1 + 1 payload switch and only one of
the incoming streams is passed to the downstream processing blocks. The pointer interpreter passes pointer information to the 1:3 demultiplexer logic, and bus control circuitry provides functions necessary to manage traffic on
the telecom bus drop interface which drops traffic from up to three STS-1/TUG-3 paths on the TMUX receive path.
The path overhead bytes are monitored by the path overhead monitor and are dropped via the receive path POAC
drop interface.
17.3.1 Receive Line Framer and Transport Overhead Termination
Input receive data is received at the TMUX synchronous data framer from the high-speed line interface block. The
framer performs a multitude of functions including frame alignment (STS-3/STM-1 or STS-1), B1 BIP-8 check,
J0 byte monitoring, descrambling, F1 byte monitoring, B2 BIP-8 check, automatic protection switch (APS) and K2
byte monitoring, AIS-L and RDI-L detection, M1 byte REI-L detection, S1 byte sync status monitoring, and receive
transport overhead access channel (RTOAC) drop. The states of the framer as well as all state changes are
reported, and, if not masked, cause an interrupt. The B1 and B2 byte parity check supports bit and block modes.
The TMUX implements internal performance monitor counters. These counters can count up to one second worth
of BIP errors. The counters operate in either a saturation mode, such that the maximum value is retained once
reached, or in a rollover mode. These counters should be optimally read (and cleared) at least once per second.
The J0 monitor supports non-framed, SONET-framed, and SDH-framed 16-byte sequences as well as single
J0 byte monitoring mode. APS monitoring is performed on bytes K1[7:0] and K2[7:3]. The value of each is stored
and changes are reported. Bits [2:0] of the K2 byte are monitored independently. Line AIS (AIS-L/MS-AIS) and
RDI-L/MS-RDI are monitored separately and changes are reported. This AIS-L/MS-AIS and RDI-L/MS-RDI information is also sent to the protection device for add/drop multiplex (ADM) applications. The M1 byte monitor operates either in bit or block mode and allows access to the REI-L/MS-REI errored bit count. The S1 byte can be
monitored in two modes: as an entire 8-bit word or as one 4-bit nibble (bits 7 to 4). Continuous N-times detection
counters are implemented for these monitoring functions. All automatic receive monitoring functions can be configured to provide an interrupt to the control system, or the device can be operated in a polled mode.
17.3.2 Receive Transport Overhead Monitor and RTOAC Drop
The receive RTOAC provides access to all of the line section overhead bytes. Even or odd parity is calculated over
all bytes. It has a data rate of 5.184 Mbits/s and consists of a clock, data, and an 8 kHz sync pulse. In an alternate
operating mode, the data communication channel bytes D1—D3 or D4—D12 may transmit a serial 192 kbits/s or a
576 kbits/s data stream onto the RTOAC drop channel.
rtoac clk
rtoac sync
rtoac data
0783(F)
Figure 21. TMUX RTOAC Timing Diagram
362
Agere Systems Inc.
Preliminary Data Sheet
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TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
17 TMUX Functional Description (continued)
17.3.3 Receive MSP 1 + 1 Payload Switch
Output from both receive framer blocks provides the input to the MSP 1 + 1 payload switch.This portion of the
TMUX implements a payload 1 + 1 protection switch. In the receive direction, this occurs prior to pointer interpretation. If the protection switch is activated, then the data is selected from the receive protection interface rather than
from the high-speed input path. Only the selected input traffic is provided downstream to the pointer interpreter.
The interface consists of a 155.52 MHz or 51.84 MHz clock, data, and sync pulse.
17.3.4 Receive Pointer Interpreter
The pointer interpreter is implemented via a state machine which implements the pointer interpretation algorithm
described in ETS 300 417-1-1: January 1996 -Annex B. The pointer interpreter evaluates the current pointer state
for the normal state, path AIS state, or LOP conditions, as well as pointer increments and decrements. The current
pointer state and any changes in pointer condition are reported to the control system. The number of consecutive
frames for invalid pointer and invalid concatenation indication is fixed at nine.
17.3.5 Receive High-Order Path Overhead Termination and RPOAC Drop
Path overhead (POH) termination is performed in the receive path on either all three STS-1s or on the VC-4 POH
only. The receive POH circuitry includes: J1 byte monitoring, B3 byte BIP-8 checking, C2 byte signal label monitoring, REI-P and RDI-P detection, H4 byte multiframe monitoring; F2, F3, and K3 byte APS monitoring, N1 byte tandem connection monitoring (TCM), signal degrade BER and signal fail BER detection; receive path overhead
access channel (RPOAC) drop, and AIS-P/HO-AIS insertion and automatic AIS generation (with individual inhibit).
The J1 monitor provides five modes of operation for a programmable length (1 byte to 64 bytes) of the trace identifier. These five modes are comprised of: cyclic checking against the last received sequence, compare against a
programmed sequence, SONET framing mode, SDH framing mode, and consecutive consistent occurrences of a
new pattern. B3 is monitored either in bit or block mode. Provisionable N-times detection counters are implemented
for the C2, F2, F3, N1, and K3 bytes. The K3 APS byte and N1 TCM byte can be monitored as an entire 8-bit word
or two 4-bit nibbles.
The receive RPOAC provides access to all the path overhead bytes. Even or odd parity is calculated over all bytes.
The RPOAC has a data rate of 9 bytes per 8 kHz frame and consists of clock, data, and an 8 kHz sync pulse.
17.3.6 Receive Byte Interleave Demultiplexer
The byte interleave demultiplexer accepts serial traffic and demultiplexes that information into one (STS-1 mode) or
three (STS-3/STM-1 mode) traffic streams for input via the telecom bus to the VT/VC mapper. The demultiplexer
takes the bytes in the order they are presented and places that traffic onto the telecom bus.
17.3.7 Receive Telecom Bus
The TMUX can communicate with up to three SPE mappers via the telecom bus interface. In typical applications,
since one SPE mapper is included in the Super Mapper device, two external SPE mappers reside on the telecom
bus. The bus operates at 19.44 MHz for STS-3/STM-1 modes and at 6.48 MHz for STS-1 mode. In the receive
direction, the Super Mapper outputs one parallel clock at 19.44 MHz, three sync signals (SPE, J0J1V1, and V1), an
8-bit data bus, and an odd/even parity bit. The data bus carries either three STS-1/TUG-3 signals, each in their own
time slot, or it carries one STS-1 signal. A 51.84 MHz low-speed clock and sync signal is also output from this circuit.
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Preliminary Data Sheet
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17 TMUX Functional Description (continued)
17.4 TMUX Transmit Path Overview
The TMUX transmit path is depicted in the top half of Figure 24 on page366 . The transmit path of the TMUX implements the inverse function to the receive path. Transmit input traffic at the telecom bus interface from up to three
STS-1/TUG-3 paths is managed via the transmit path bus control circuitry. Transmit traffic, alarms, or unequipped
indication information is inserted as needed depending on the status and provisioning of the device. The 3:1 multiplexer provides byte interleave multiplexing of the incoming traffic and insertion of the path overhead bytes. A serial
path provides input for the transmit protection traffic and the framer and serial-to-parallel converter formats this traffic for input to the transmit MSP 1 + 1 payload switch. The selected output from the transmit MSP 1 + 1 switch is
input to the transport overhead insert block and the parallel to serial converter sends a serial stream to the device
output. The TMUX transmit path provides path overhead byte insertion and transport overhead byte insertion via
the respective POAC insert and TOAC insert interfaces.
Local clock and frame generation control circuitry is implemented in the TMUX for controlling the STS-1, STS-3,
and STM-1 termination and generation functions. Internal loopbacks in the TMUX provide near-end line loopback
and far-end line loopback capability.
17.4.1 Transmit Telecom Bus
The transmit side of Super Mapper drives a clock and three sync signals (SPE, J0J1V1, and V1) onto the telecom
bus. These signals control when the internal SPE mapper or one of the mate devices talks on the data bus.
Because it is on the receive side, the transmit telecom bus operates at 19.44 MHz for STS-3/STM-1 modes and at
6.48 MHz for STS-1 mode. The TMUX communicates with up to three VT/VC mappers, via an 8-bit data word and
an odd/even parity bit from the telecom bus. The data consists of the STS-1/TUG-3 from up to three mappers; each
in its own time slot, or it carries one single STS-1 signal. A 51.84 MHz low-speed clock and sync are also output.
Transmit High-Order Path Overhead Generation and TPOAC Insert. In the transmit direction, J1 path trace byte
insertion, B3 byte calculation and insertion, C2 signal label byte insertion, REI-P and RDI-P insertion; F2 byte
insertion, H4 multiframe byte insertion, F3 path user byte insertion, K3 byte insertion, N1 byte insertion, and AIS-P
insertion via POAC or software control is supported. The transmit TPOAC allows insertion of all overhead bytes
other than the B3 byte, which is automatically calculated. Even or odd parity is checked over all bytes. Bytes which
are not enabled for insertion are set to an all-ones or all-zeros stuff value. Transport path overhead bytes are added
to the payload stream during multiplexing in the byte interleave multiplexer.
Transmit Byte Interleave Multiplexer. In STS-3/STM-1 mode, the transmit byte interleave multiplexer block multiplexes up to three STS-1/TUG3 signals to form a SONET/SDH STS-3/STM-1 structured signal. The STS-3/STM-1
multiplexer function processes the input bytes in the order in which they are presented on the transmit telecom bus
and multiplexes these bytes into a single high-speed stream. Grooming of the VTs/VCs is performed in the SPE
mapper of each of the three devices. High-order path overhead bytes are interleaved with the data traffic during the
byte interleave multiplexing.
Transmit Payload Framer and MSP 1 + 1 Payload Switch. In the transmit direction, the MSP 1 + 1 switch function incorporates dual MSP 1 + 1 payload switch structures. In operation, the traffic from the transmit byte interleave multiplexer are presented to both MSP 1 + 1 payload switches. The output of the signal from the 3:1 multiplex
is broadcast to both switch paths, and the output of the receive payload framers is also input respectively to one of
the two switch paths. For normal operation, one of the two outputs from the two MSP 1 + 1 blocks is selected. The
path from the receive framer to the MSP switch structures provides a means to perform far-end loopback.
Transmit Transport Overhead Generation and TTOAC Insert. The transmit transport overhead generator performs TTOAC byte insertion, sync status byte (S1) insertion, M0/M1—REI-L insertion, K1 and K2 byte insertion,
AIS-L insertion, B2 byte calculation and insertion, F1 byte insertion, B1 byte generation and error insertion, scrambling, J0 byte insertion control, and A2 byte error insertion. All insert control functions that are inhibited will insert
optionally either an all-zeros or an all-ones word.
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17 TMUX Functional Description (continued)
The transmit TTOAC allows the users to insert the following overhead bytes: E1, F1, D1—D3, D4—D12, S1, and
E2. Even or odd parity is checked over all bytes. Bytes which are not enabled for insertion are set to an all-ones or
all-zeros stuff value.
The data communication channels D1—D3 or D4—D12 may also be received via the TTOAC interface. In this
mode, the TTOAC channel will comprise a serial 192 kbits/s or a 576 kbits/s data stream.
The insertion (overwrite by TOAC) of programmed S1, F1, J0, Z0-2, and Z0-3 bytes can be enabled via registers.
Automatic insertion of M0/M1 may also be inhibited via registers. A protection switch selects the REI-L value for
insertion to be taken from the protection board rather than from the receive side. The entire APS value or K2[2:0]
can be inserted via writable registers. Automatic RDI insertion is supported with individual inhibit for each contributor. A protection switch selects the RDI-L value for insertion to be taken from the protection board rather than from
the receive side. B1 and B2 BIP-8 values are calculated and inserted. Both values can be optionally inverted.
ttoac clk
ttoac sync
ttoac data
0784(F)
Figure 22. TMUX TTOAC and RTOAC Timing Diagram
HIGH-SPEED
S O N E T/SD H IN TE R FA C E
TMUX
TM U X R D I_ P , RE I_ P
T M U X R D I_ L , R EI_ L
S TS -3 /STM -1
O R STS -1
TELECOM BU S
S TS-1 /TU G -3
(TIM E S L O T # 1 )
S TS -1 /TU G -3
S TS -1 /TU G -3 (TIM E SL O T # 2 )
(TIM E SL O T # 3 )
SPE
MAPPER
DS3
M 13
TU G -2
V T/TU
M A PP E R
V T M PR R D I_ L , R E I_ L
V T M PR R D I_ P , R E I_ P
D EV IC E # 1
D E VIC E # 2
D E VIC E #3
5-9004(F)
Figure 23. High-Level TMUX Interconnect
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17 TMUX Functional Description (continued)
THSC
THSSYNC
RPSSYNC155 (FROM RECEIVE SIDE)
RPSC155
TPSMUXSEL2
TPSC155
LOCAL CLOCK
AND FRAME
GENERATION
MSP 1+1
PAYLOAD
SWITCH 3
TLSCLK52
TLSSYNC52
STS#1 PAIS, UEQ
INSERT
TLSPAR
BUS
CONTROL
TLSCLK
(19.44 MHz)
TLSDATA[7:0]
LOC, OOF,
LOF, B2E
STS#2 P AIS , UE Q
IN S ER T
3:1
MUX
LOGIC
AND
POH
INSERT
MSP 1+1
PAYLOAD
SWITCH 2
STS#3 P A IS , UE Q
INS ER T
TLSSPE
TPSD155
B2 ERR
INSERT,
L-REI INS
P/S
STM-1
TOH
INSERT
P/S
THSD
TOAC
INSERT
TLSJ0J1V1
TLSV1
TTOACCLKO,
TTOACSYNCO,
TTOACDATI
POAC
INSERT
TPOACCLK,
TPOACSYNC,
TPOACDATA
VTMPR RDI_L, REI_L
LINE RDI
LINE REI
TRANSMIT DIRECTION
VTMPR RDI_P,
REI_P
LOC, OOF,
LOF, B2E
RLSCLK52
STS#1
RLSSYNC52
RLSCLK
(19.44 MHz)
RLSPAR
STS#2
RLSV1
1:3
DEMUX
LOGIC
MSP 1+1
PAYLOAD
SWITCH 1
POH
MONITOR
RLSSPE
RLSJ0J1V1
FRAMER,
S/P, AND
B2 MON,
L-REI MON
POINTER
INTERPRETER
BUS
CONTROL
RLSDATA[7:0]
RPSSYNC155
PATH RDI
PATH REI
STS#3
FRAMER
AND S/P
AUTO_AISO[1—3]
POAC
DROP
RPSD155
RPSC155
RHSD
RHSC
TOH
MONITOR
TIMING SIGNALS TO T X SIDE
TOAC
DROP
RTPOACCLK,
RTPOACSYNC,
RTPOACDATA
RTOACCLK,
RTOACSYNC,
RTOACDATA
RECEIVE DIRECTION
5-9005(F)r.1
Figure 24. Detailed Block Diagram of the TMUX
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17 TMUX Functional Description (continued)
The following block diagram describes the receive side transport overhead functions. Data is received from the
high-speed interface at 155 Mbits/s (51.84 Mbits/s for STS-1 mode) and the output is driven onto the low-speed
telecom bus in a parallel format. The TOH receive side functional blocks are shown in Figure 25.
RECEIVE DATA
FRAME
ALIGN
DESCRAMBLER
J0
INPUT
MONITOR
OOF
LOF
MONITOR
LOS
DETECTOR
F1
J0
MONITOR
B1
BIP-8
CHECK
F1
MONITOR
K1
K2
B2
B2
BIP N
CHECK
B1
K2
K1/K2
APS
MONITOR
TOAC
DROP
BER
ALGORITHM
AIS-L
RDI-L
DETECT
H1, H2, H3
MONITOR
M1
S1
SYNC
STATUS
MONITOR
M1
REI-L
DETECT
M1
REI
COUNTER
POINTER
INTERPRETER
INSERT
AIS-P
F2
F2
MONITOR
F3
F3
MONITOR
C2
J1
C2
MONITOR
N1
J1
MONITOR
N1
MONITOR
BER
ALGORITHM
B3
B3
BIP N
CHECK
K3
K3
APS
MONITOR
G1
G1
RDI-P
DETECT
POAC
DROP
G1
G1
REI-L
DETECT
TELECOM BUS
G1
REI
COUNTER
5-9006(F)r.2
Figure 25. Receive Direction Functional Block Diagram
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Preliminary Data Sheet
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17 TMUX Functional Description (continued)
17.5 Receive Direction (Receive Path from Sonet Global/SDH)
All functions supported by the TMUX in the receive direction are summarized here:
■
Input clock monitoring and loss-of-signal monitoring
■
High-speed loopback
■
Frame alignment
■
Receive side frame sync output
■
B1 BIP-8 check
■
J0 monitor
■
Descrambler
■
F1 monitor
■
B2 BIP-8 check
■
APS (automatic protection switch) monitor
■
K2 monitor, AIS-L and RDI-L detect
■
M1 REI-L detect
■
Sync status monitor
■
Receive transport overhead access channel (RTOAC)
■
MSP 1 + 1 payload switch
■
Pointer interpreter
■
J1 monitor
■
B3 BIP-8 check
■
Signal label C2 byte monitor
■
RDI-P detect
■
REI-P detect
■
Path user byte F2 monitor
■
H4 multiframe indicator
■
Path user byte F3 monitor
■
K3 byte monitor
■
N1 tandem connection byte monitor
■
Signal degrade BER algorithm
■
Signal fail BER algorithm
■
Path overhead access channel (POAC) drop
■
AIS-P insertion and AUTO_AISO[1—3] generation
■
Receive side telecom bus interface
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TMXF28155/51 Super Mapper
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17 TMUX Functional Description (continued)
17.5.1 Input Clock and Loss-of-Signal Monitoring
The TMUX detects and reports the loss of the 155 MHz input clock for STS-3 mode and the loss of the
51.84 MHz clock for STS-1 mode with register bits TMUX_RHSILOC—state (Table 91, starting on page92 ),
TMUX_RHSILOCD—delta state (Table 91, starting on page 92), TMUX_RHSILOCM—interrupt mask (Table 91,
starting on page 92). LOC is determined by a stuck high or stuck low for a time greater than 10 µs and uses the
microprocessor clock as its reference.
The TMUX will detect and report a loss-of-signal condition with register bits TMUX_RHSLOS—state (Table 91 on
page 92), TMUX_RHSLOSD—delta state (Table 91, starting on pag e92), TMUX_RHSLOSM—interrupt mask
(Table 86 on page88 ), by monitoring the external input signal pin, LOSEXT (pin AE5), or detecting a continuous
all-zeros/ones pattern for 51.44 ns to 105 µs in 51.44 ns steps before data is descrambled. The detection time is
determined by the value programmed in register bits, TMUX_LOSDETCNT[10:0] (Table 97 on pag e97). The LOS
state will clear after reception of two consecutive receive frames with the correct framing pattern spaced 125 µs
apart without an incoming LOS all-zeros/ones pattern. This recovery applies to both internal and external LOS failure causes.
17.5.2 High-Speed Loopback Select Logic
The device can be configured to loopback the transmit STS-3/STM-1 (AU-4) TMUX_THS2RHSLB = 1 (Table 93 on
page 94) or accept the local STS-3/STM-1 (AU-4) signal TMUX_THS2RHSLB = 0.
17.5.3 Frame Alignment—STS-3/STM-1 (AU-4) Framing or STS-1 Framing
The device will frame on the incoming signal. The state of the framer, out of frame (OOF) (register bit
TMUX_RHSOOF, see Table 91 on page92 ) as well as any changes to this state (register bits TMUX_RHSOOFD—
delta state, see Table 91, starting on pag e92 and TMUX_RHSOOFM—interrupt mask; see Table 86 on page88 )
will be reported.
The 32-bit (A1-2, A1-3, A2-1, and A2-2) framing pattern will be used in the frame detection for the
STS-3/STM-1 case and a 16-bit pattern will be used for the STS-1 case. The device will be considered out of frame
until two successive framing patterns separated in time by 125 µs occur without framing byte errors.
The device will be considered in frame until five successive frames, separated in time by 125 µs, occur with errored
framing patterns. If the framer transitions to the out of frame state, the framer will remain synchronized to the last
known frame boundary or the latest detected unerrored framing pattern.
A loss of frame (LOF) (register bit TMUX_RHSLOF; see Table 91 on page 92) state bit as well as any changes to
this state (register bits TMUX_RHSLOFD—delta state, see Table 91, starting on page92 , TMUX_RHSLOFM—
interrupt mask; see Table 86 on page88 ) will be reported. These state and mask and delta bits are the same for
both types of input data, STS-3/STM-1 or STS-1.
The device will be considered in the LOF state when an OOF condition persists for 24 consecutive frames (3 ms).
The device will transition out of the LOF state after receiving 24 consecutive frames with the correct framing patterns spaced 125 µs apart and the OOF condition is clear.
17.5.4 B1 BIP-8 Check
A BIP-8 even parity will be computed over all the incoming bits of the STS-3/STM-1 frame (STS-1 frame in STS-1
mode), which are scrambled (except for the bits in the A1, A2, and J0/Z0 bytes) and compared to the B1 byte
received in the next frame.
The total number of B1 BIP-8 bit errors (raw count), or block errors (as determined by register bit
TMUX_BITBLKB1; see Table 95 on page 95), are counted. Upon the assertion of the performance monitor control
signal as configured in the microprocessor interface block, the raw count will be reset to zero and the value transferred to a 16-bit counter for B1 error counts B1ECNT[15:0] (Table 124 on pag e118).
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17 TMUX Functional Description (continued)
In case of overflow, depending on the value programmed in the microprocessor interface register bit
SMPR_SAT_ROLLOVER (Table 67 SMPR_GCR, Global Control Register (RW) on page 68), the B1 error counter
will either roll over or saturate at the maximum value until cleared.
17.5.5 J0 Monitor
J0 (section trace overhead) monitoring is done via register bits TMUX_J0MONMODE[2:0] (Table 95 on pag e95).
This J0 monitoring has six different monitoring modes, as follows:
■
TMUX_J0MONMODE[2:0] = 000: the TMUX latches the value of the J0 byte every frame for a total of
16 bytes into registers TMUX_J0DMON[16—1][7:0]; see Table 132 on page121 . The TMUX compares the
incoming J0 byte with the next expected value (the expected value is obtained by cycling through the previously
stored 16 received bytes in round-robin fashion) and, if different, setting the section trace identifier mismatch
state register bit, TMUX_RTIMS, see Table 91 on page92 . Any change to TMUX_RTIMS will be reported via
delta and interrupt register bits TMUX_RTIMSD; see Table 82, starting on pag e79 and TMUX_RTIMSM; see
Table 86 on page88 .
■
TMUX_J0MONMODE[2:0] = 001: this is the SONET framing mode. The hardware looks for a 0x0A character to
indicate that the next byte is the first byte of the path trace message. The J0 byte message is continuously written into TMUX_J0DMON[1—16][7:0] registers with the first byte residing at the first address. If any received byte
does not match the previously received byte for its location, then the state register bit, TMUX_RTIMS, is set. Any
change to RTIMS will be reported via delta and interrupt mask register bits TMUX_RTIMSD and
TMUX_RTIMSM.
■
TMUX_J0MONMODE[2:0] = 010: this is the SDH framing mode. The hardware looks for the byte with the most
significant bit (MSB) set to one, which indicates that the next byte is the second byte of the message. The rest of
operation is the same as in SONET framing mode.
■
TMUX_J0MONMODE[2:0] = 011: a new J0 byte (TMUX_J0DMON[1][7:0]) will be detected after the number of
consecutive consistent occurrences of a new pattern in the J0 overhead byte as determined by the values in registers TMUX_CNTDJ0[3:0]; see Table 98 on page98 . Any changes to this byte are reported via delta and interrupt mask registers TMUX_RTIMSD and TMUX_RTIMSM. The TMUX_RTIMSD delta bit in this mode indicates a
change in state for the TMUX_J0DMON[1][7:0] byte and the state register bit, TMUX_RTIMS, is not used.
■
TMUX_J0MONMODE[2:0] = 100: the user will program the 16 expected values of J0 in the SONET frame into
registers TMUX_EXPJ0DMON[1—16][7:0]; see Table 131 on page 121. The first expected byte, the byte following the 0x0A character, is written into the first location TMUX_J0DMON[1][7:0]. The TMUX compares the incoming J0 sequence with the stored expected value and sets the state register bit, TMUX_RTIMS ( Table 91 on
page 92), if they are different. Any change to TMUX_RTIMS is reported via register bits TMUX_RTIMSD (delta
state) and TMUX_RTIMSM (interrupt mask).
■
TMUX_J0MONMODE[1:0] = 101: the user will program the 16 expected values of J0 in the SDH frame in registers TMUX_EXPJ0DMON[1—16][7:0]. The first byte of the message has the MSB set to 1. The TMUX compares
the incoming J0 sequence with the stored expected value, setting the state register bit, TMUX_RTIMS, if they are
different. Any change to TMUX_RTIMS will be reported via register bits TMUX_RTIMSD (delta state) and
TMUX_RTIMSM (interrupt mask).
■
TMUX_J0MONMODE[1:0] = 110 and 111 are currently undefined.
17.5.6 Descrambler
A frame synchronous descrambler of length 127 and generating polynomial x7 + x6 + 1 will descramble the entire
STS-3/STM-1 (or STS-1) signal except for the first row of overhead. The scrambler will be set to 1111111 on the
first byte following the last section overhead byte in the first row (i.e., after byte J0 for STS-1). The descrambler
operates in a byte-wide mode.
The frame descrambler can be enabled or disabled using register bit TMUX_RHSDSCR (Table 93 on page94 ).
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17 TMUX Functional Description (continued)
17.5.7 F1 Monitor
The TMUX monitors the fault location byte TMUX_RF1MON0[7:0] (Table 101 on page 100). A new fault location
state will be detected after the number of consecutive consistent occurrences of a new pattern in the F1 overhead
byte as determined by the value programmed in TMUX_CNTDF1[3:0] ( Table 98 on pag e98).
The TMUX maintains a history of the previous, valid F1 byte in TMUX_RF1MON1[7:0] (Table 101 on pag e100),
and any changes will be reported via TMUX_RF1MOND (delta state) (Table 82, starting on pag e79) and
TMUX_RF1MONM— (interrupt mask) (Table 86 on page88 ).
This continuous N-times detection counter will be reset to 0 upon the transition of the framer into the out of frame
state.
17.5.8 B2 BIP-8 Check
A B2 BIP-8 even parity is computed over all the incoming bits (except for the nine section overhead bytes) of the
STS-1 frame after descrambling, and compared to the B2 byte received in the next frame. The total number of B2
BIP-8 bit errors (raw count), or block errors (as determined by TMUX_BITBLKB2; Table 94 on page 94), is counted.
Upon the assertion of the performance monitor control signal as configured in the microprocessor interface, the raw
count will be reset to zero and the value transferred to an 18-bit holding register for B2 error counts
(TMUX_B2ECNT[17:0]; see Table 125 on page119 ). In case of overflow, depending on the value programmed in
the microprocessor interface register bit SMPR_SAT_ROLLOVER (Table 67 on pag e68), the B2 error counter will
either roll over or saturate at the maximum value until cleared.
17.5.9 Automatic Protection Switch (APS) Monitor
The TMUX monitors the receive APS value (the K1 byte, and the five most significant bits of the K2 byte) and
stores this value in TMUX_RAPSMON[12:0] (Table 102 on page100 ). This register is updated after the reception
of a programmed number of identical consecutive frames as determined by the value in TMUX_CNTDK1K2[3:0]
(Table 98 on page98 ). Whenever the contents of TMUX_RAPSMON[12:0] changes, a delta bit,
TMUX_RAPSMOND will be set (Table 82, starting on page 79) and the interrupt can be masked using
TMUX_RAPSMONM (Table 86 on pag e88). This indication also contributes to a separate device interrupt indication specifically intended for automatic protection switching.
The TMUX monitors this same 13-bit APS value (K1[7:0], K2[7:3]) in the receive direction and reports when the
APS value is inconsistent, using TMUX_RAPSBABE—Receive APS Babble Event (Table 82 on pag e79) and
TMUX_RAPSBABM—Receive APS Babble Mask (Table 86 on page 88). Inconsistent APS bytes are defined as
the number of successive frames of ASP data where no frames satisfy the criteria for updating the
TMUX_RAPSMON register (Table 102 on page100 ). The number of inconsistent frames allowed before reporting
is programmed in TMUX_CNTDK1K2FRAME[3:0] (default = 12, see Table 98 on page98 ). This continuous Ntimes detection counter will be reset to 0 upon the transition of the framer into the out-of-frame state or upon the
detection of a B1 error.
17.5.10 K2 Monitor, AIS-L and RDI-L Detect
The three least significant bits of K2 are independently monitored and the current value is stored in
TMUX_K2MON[2:0] (Table 102 on page100 ). The register will be updated after the programmed number of consecutive identical K2[2:0] bits. This number is programmed by the value in TMUX_CNTDK2[3:0] (Table 98 on
page 98). Whenever the contents of TMUX_K2MON[2:0] changes, a delta bit, TMUX_RK2MOND will be set
(Table 82, starting on page79 ), and the interrupt can be masked using TMUX_RK2MONM (Table 86 on pag e88).
The TMUX monitors for line AIS (AIS-L/MS-AIS) in the K2[2:0] bits (K2[2:0] = 111). When line AIS is detected,
TMUX_RLAISMON (Table 91 on page92 ) will be set to 1 after a number of consecutive occurrences of line AIS as
determined by the value programmed in TMUX_CNTDK2[3:0]. Once set, AIS-L will be cleared after a number of
consecutive frames of no line AIS as determined by this same value in TMUX_CNTDK2[3:0].
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17 TMUX Functional Description (continued)
Any change to TMUX_RLAISMON will be reported in TMUX_RLAISMOND (Table 82, starting on page 79) and the
interrupt can be masked using TMUX_RLAISMONM (Table 86 on page 88).
The TMUX monitors for a remote defect indication (RDI-L/MS-RDI) condition in the K2[2:0] bits (K2[2:0] = 110) .A
line RDI condition will be detected and TMUX_RLRDIMON (Table 91 on page92 ) will be set to 1 after a number of
consecutive occurrences of RDI as determined by the value in TMUX_CNTDK2[3:0]. Once set, RDI-L will be
cleared after a number of consecutive frames of no RDI as determined by this same value programmed in
TMUX_CNTDK2[3:0]. Any change to TMUX_RLRDIMON, will be reported in TMUX_RLRDIMOND (Table 82, starting on page79 ) and the interrupt can be masked using TMUX_RLRDIMONM (Table 86 on page 88). This continuous N-times detection counter will be reset to 0 upon the transition of the framer into the out-of-frame state.
17.5.11 M1 REI-L Detect
One byte (M1) is allocated for use as a line remote error indication function (REI-L). For STS-3/STM-1 signals, all
eight bits of the M1 byte are allocated for REI-L information. The REI-L value reflects the error count detected by
the line terminating equipment (LTE) (using the line BIP-8 code) back to its peer LTE. For STS-3/STM-1 signals, the
value of the error count can be up to 24. A value of 25 and above will be interpreted as no errors. If
TMUX_R_M1_BIT7 (Table 96 on pag e96) is 1, then the most significant bit of the byte is ignored.
The TMUX allows access to the accumulated M1-REI errored bit count from the M1 byte via TMUX_M1ECNT[17:0]
(Table 126 on page 119). The counter will count in bit or block mode, depending upon the value of
TMUX_BITBLKM1 (Table 94 on page94 ). At the selected performance monitor (PM) interval, the value of the internal running raw counter is placed into a holding register, TMUX_M1ECNT[17:0], and then cleared. Depending on
the value of SMPR_SAT_ROLLOVER (Table 67 on pag e68) in the microprocessor interface, the internal counter
will either roll over or saturate at its maximum value until cleared.
17.5.12 Sync Status Monitor
The S1 byte is allocated for synchronization status. S1 bits [7:4] are used to convey a 4-bit code of which only six
patterns are defined with the remaining codes reserved for quality levels defined by individual administrations.
The S1 byte can be monitored in two modes: (1) as an entire 8-bit word or (2) as one 4-bit nibble (bits [7:4]), as programmed by TMUX_S1MODE4 (Table 95 on page 95).
■
TMUX_S1MODE4 = 0 the associated state, delta, and mask registers are TMUX_RS1MON[7:0] (Table 103 on
page 100), TMUX_RS1MOND (Table 82, starting on page79 ), and TMUX_RS1MONM (Table 86 on page 88),
respectively.
■
TMUX_S1MODE4 = 1 the associated state, delta, and mask registers are TMUX_RS1MON[7:4],
TMUX_RS1MOND, and TMUX_RS1MONM.
A new value will be detected after a programmed number of consecutive occurrences of a consistent new value in
the incoming S1 byte as determine by the value in TMUX_CNTDS1[3:0] (Table 98 on page98 ). A maskable event,
TMUX_RS1BABE (Table 82, starting on page79 ), is set if a programmed number of consecutive frames pass without a validated message occurring as determined by the value in TMUX_CNTDS1FRAME[3:0] ( Table 98).
In 8-bit mode, the entire value is monitored for an inconsistent value, while in 4-bit mode, only the most significant
nibble is monitored for an inconsistent value. This continuous N-times detection counter will be reset to 0 upon the
transition of the framer into the out-of-frame state.
17.5.13 Receive Transport Overhead Access Channel (RTOAC)
A transport overhead access channel (TOAC) is provided on-chip to drop the transport overhead (TOH) portion of
the incoming SDH or SONET frame. The TOAC channel supports three modes of operation based on the configuration of TMUX_RTOAC_D13MODE and TMUX_RTOAC_D412MODE (Table 117 on page113 ).
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The TOAC channel consists of the following signals:
■
A clock signal sourced by the device pin, RTOACCLK (external output pin AD1). The clock frequency depends on
the values of TMUX_RTOAC_D13MODE and TMUX_RTOAC_D412MODE. See Table 522 below.
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A data signal out of RTOACDATA (external output pin AD3). The data rate and the values transmitted depend on
the values of TMUX_RTOAC_D13MODE and TMUX_RTOAC_D412MODE. See Table 522 below.
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An 8 kHz synchronization signal, out to output pin, RTOACSYNC (external output pin AA5). The sync signal is
normally low. During the last clock period of each frame coincident with the least significant bit of the last byte
(the eighty-first byte for all TOH modes), the sync signal is driven high.
Table 522. Receive TOAC Modes
TOAC Mode
TMUX_RTOAC_D13MODE TMUX_RTOAC_D412MODE
Value
Value
DCC1—DCC3
1
X
DCC4—DCC12
0
1
Full TOH Mode
0
0
Number of Data
Bytes per Frame
3
9
81
Clock Rate
192 KHz
576 KHz
5.184 MHz
Receive TOAC DCC1—DCC3 Mode. In this mode, DCC bytes 1 to 3 are transmitted serially on the data pin. The
clock rate is 192 KHz. The data bytes are transmitted MSB first, and the data bytes are driven out in sequential
order: DCC1, DCC2, and DCC3. The data signal is partitioned into frames of 3 bytes with a repetition rate of 8 kHz.
Receive TOAC DCC4—DCC12 Mode. In this mode, DCC bytes 4 —12 are transmitted serially on the data output.
The clock rate is 576 KHz. The data bytes are transmitted MSB first, and the data bytes are driven out in sequential
order: DCC4, DCC5, DCC6, DCC7, DCC8, DCC9, DCC10, DCC11, and DCC12. The data signal is partitioned into
frames of 9 bytes. The frame repetition rate is 8 kHz.
Receive TOAC Full TOH Access Mode. In this mode, the data signal is partitioned into frames of 81 bytes. The
frame repetition rate is 8 kHz. Each byte consists of 8 bits that are transmitted/received most significant bit first.
The MSB of the first byte of each frame contains an odd/even parity bit over the 648 bits of the previous frame. The
remaining 7 bits of this byte are not specified.
Bytes shown in Table 523 below summarize the access capabilities of the receive TAOC in full access mode. The
transport overhead bytes shown in this table are always dropped by the receive side. There is programmability on
the transmit side regarding the insertion of these bytes. Bytes indicated in bold type are not specified in the standard, but are available on the receive TOAC data signal.
Table 523. Transport Overhead Byte Access—Receive Direction
OH Parity
B1
D1
H1-1
B2-1
D4
D7
D10
S1
A1-2
B1-2
D1-2
H1-2
B2-2
D4-2
D7-2
D10-2
Z1-2
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A1-3
B1-3
D1-3
H1-3
B2-3
D4-3
D7-3
D10-3
Z1-3
A2-1
E1
D2
H2
K1
D5
D8
D11
Z2-1
A2-2
E1-2
D2-2
H2-2
K1-2
D5-2
D8-2
D11-2
Z2-2
A2-3
E1-3
D2-3
H2-3
K1-3
D5-3
D8-3
D11-3
M1
J0
F1
D3
H3
K2
D6
D9
D12
E2
Z0-2
F1-2
D3-2
H3-2
K2-2
D6-2
D9-2
D12-2
E2-2
Z0-3
F1-3
D3-3
H3-3
K2-3
D6-3
D9-3
D12-3
E2-3
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17 TMUX Functional Description (continued)
Receive TOAC—OH Parity. Even or odd parity can be inserted into the first bit of the MSB byte of the TOAC outgoing frame by programming TMUX_RTOAC_OEPINS (Table 117 on pag e113).
17.5.14 MSP 1 + 1 Payload Switch
The TMUX supports a payload 1 + 1 protection switch. In the receive direction, this occurs prior to pointer interpretation. If TMUX_RPSMUXSEL1 = 1 ( Table 93), then the input receive data and clock are selected from the protection path: device pins RPSD155P/N (pins AD10/AE10) and RPSC155P/N (pins AC10/AD11), rather than from the
normal (working) path device pins, RHSDP/N (pins AF7/AE7) and RHSCP/N (pins AC7/AD8).
17.5.15 Pointer Interpreter
The STS-3/STM-1 pointer interpreter logic block performs all necessary functions to support STS-3/STM-1, as well
as STS-1, pointer interpretation. The pointer interpreter operates as one machine in STM-1 mode and as three
independent machines in STS-3 mode. The following features are implemented:
■
The pointer interpreter consists of the following states:
— LOP: loss of pointer
— AIS: alarm indiction signal (all ones in H1 and H2)
— NDF: new data flag enabled (1001,0001,1101,1011, and 1000)
— NORM: normal (disabled NDF, normal pointer)
— INC: increment (inverted I bits)
— DEC: decrement (inverted D bits)
NDF ENABLE
INC
DEC
3 NEW POINTERS
3 ANY
POINTERS
3 ANY
POINTERS
NDF
DECREMENT
INDICATION ENABLE
INCREMENT
INDICATION
3 NEW POINTERS
3 NEW POINTERS
NORM
3 ANY POINTERS
NDF
NDF ENABLE
NDF
ENABLE
8 INVALID
POINTERS
FROM ALL STATES
8 INVALID POINTERS*
FROM ALL STATES
3 AIS INDICATIONS
NDF
ENABLE
3 NEW POINTERS
LOP
8 INVALID POINTERS
AIS
8 NDF ENABLE
* This state diagram is based on the ETS-417-1-1 pointer interpretation state diagram (Figure B.1). Transitions of eight invalid pointers from the
INC, DEC, and NDF states into the LOP state have been added.
5-9007(F)
Figure 26. Pointer Interpretation State Diagram
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The pointer interpreter transitions into the LOP state based on the following conditions:
— Continuous NDF. If NDF (1001, 0001, 1101, 1011, and 1000) is received in 8, 9, or 10 consecutive frames, as
determined by the value in TMUX_CTDLOPCNT[1:0] (Table 98 on page98 ), then LOP will be declared.
— Invalid pointer values. If 8, 9, or 10 consecutive frames (determined by TMUX_CTDLOPCNT[1:0]) are received
with a pointer that is not a normal value, NDF, AIS, increment, or decrement, then LOP will be declared.
■
The pointer interpreter will transition out of the LOP state based on the following conditions:
— Following three consecutive frames with all ones in the H1 and H2 bytes, the pointer interpreter will transition
from the LOP state into the AIS state.
— Following three new consecutive, consistent, and valid pointers, the pointer interpreter will transition from the
LOP state into the NORM state.
— The pointer interpreter will not transition from the LOP state into the NDF state.
■
The pointer interpreter will transition into the AIS state based on the following conditions:
— Following three consecutive frames with all ones in the H1 and H2 bytes, AIS will be declared.
■
The pointer interpreter will transition out of the AIS state based on the following conditions:
— Following three new consecutive, consistent, and valid pointers, the pointer interpreter will transition from the
AIS state into the NORM state.
— Following eight consecutive invalid pointers, the pointer interpreter will transition from the AIS state into the
LOP state.
— If NDF is enabled on the incoming H1 and H2 bytes, the pointer interpreter will transition from the AIS state
into the NDF state.
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The pointer interpreter will transition into the NDF state based on the following condition:
— If NDF is enabled on the incoming H1 and H2 bytes, the pointer interpreter will transition from the NORM,
NDF, AIS, INC, and DEC states into the NDF state.
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The pointer interpreter will transition out of the NDF state based on the following conditions:
— Continuous NDF. If NDF (1001, 0001, 1101, 1011, and 1000) is received for eight consecutive frames, the
pointer interpreter will transition from the NDF state into the LOP state.
— Following any three consecutive, consistent, and valid pointers, the pointer interpreter will transition from the
NDF state into the NORM state.
— Following three consecutive frames with all ones in the H1 and H2 bytes, the pointer interpreter will transition
from the NDF state into the AIS state.
— Following three new, consecutive, consistent, and valid pointers, the pointer interpreter will transition from the
NDF state into the NORM state.
— Following eight consecutive invalid pointers, the pointer interpreter will transition from the NDF state into the
LOP state.
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The pointer interpreter will transition into the NORM state based on the following conditions:
— Following three new consecutive, consistent, and valid pointers, the pointer interpreter will transition into the
NORM state.
— Following any three consecutive, consistent, and valid pointers, the pointer interpreter will transition into the
NORM state, i.e., transitioning from the INC, DEC, and NDF states.
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The pointer interpreter will transition out of the NORM state based on the following conditions:
— Following eight consecutive invalid pointers, the pointer interpreter will transition from the NORM state into
the LOP state.
— If NDF is enabled on the incoming H1 and H2 bytes, the pointer interpreter will transition from the NORM
state into the NDF state.
— Following three consecutive frames with all ones in the H1 and H2 bytes, the pointer interpreter will transition
from the NORM state into the AIS state.
— When operating in the 8 of 10 mode, controlled by TMUX_8ORMAJORITY = 1 ( Table 95 on page95 ), if 8 of
the 10 I and D bits are correct for a pointer decrement on the incoming H1 and H2 bytes, the pointer interpreter will transition from the NORM state into the DEC state. Otherwise, if 3 of the 5 I bits and 3 of the 5 D
bits are correct for a pointer decrement on the incoming H1 and H2 bytes, the pointer interpreter will transition
from the NORM state into the DEC state.
— When operating in the 8 of 10 mode (TMUX_8ORMAJORITY = 1), if 8 of the 10 I and D bits are correct for a
pointer increment on the incoming H1 and H2 bytes, the pointer interpreter will transition from the NORM
state into the INC state. Otherwise, if 3 of the 5 I bits and 3 of the 5 D bits are correct for a pointer increment
on the incoming H1 and H2 bytes, the pointer interpreter will transition from the NORM state into the INC
state.The pointer interpreter will transition into the INC state based on the following conditions:
— When operating in the 8 of 10 mode (TMUX_8ORMAJORITY = 1), if 8 of the 10 I and D bits are correct for a
pointer increment on the incoming H1 and H2 bytes, the pointer interpreter will transition into the INC state.
Otherwise, if 3 of the 5 I bits and 3 of the 5 D bits are correct for a pointer increment on the incoming H1 and
H2 bytes, the pointer interpreter will transition into the INC state.
■
The pointer interpreter will transition out of the INC state based on the following conditions:
— If NDF is enabled on the incoming H1 and H2 bytes, the pointer interpreter will transition from the INC state
into the NDF state.
— Following three consecutive frames with all ones in the H1 and H2 bytes, the pointer interpreter will transition
from the INC state into the AIS state.
— Following three new consecutive, consistent, and valid pointers, the pointer interpreter will transition from the
INC state into the NORM state.
— Following any three consecutive, consistent, and valid pointers, the pointer interpreter will transition from the
INC state into the NORM state.
— Following eight consecutive invalid pointers, the pointer interpreter will transition from the INC state into the
LOP state.
■
The pointer interpreter will transition into the DEC state based on the following conditions:
— When operating in the 8 of 10 mode (TMUX_8ORMAJORITY = 1), if 8 of the 10 I and D bits are correct for a
pointer decrement on the incoming H1 and H2 bytes, the pointer interpreter will transition into the DEC state.
Otherwise, if 3 of the 5 I bits and 3 of the 5 D bits are correct for a pointer decrement on the incoming H1 and
H2 bytes, the pointer interpreter will transition into the DEC state.
■
The pointer interpreter will transition out of the DEC state based on the following conditions:
— If NDF is enabled on the incoming H1 and H2 bytes, the pointer interpreter will transition from the DEC state
into the NDF state.
— Following three consecutive frames with all ones in the H1 and H2 bytes, the pointer interpreter will transition
from the DEC state into the AIS state.
— Following three new consecutive, consistent, and valid pointers, the pointer interpreter will transition from the
DEC state into the NORM state.
— Following any three consecutive, consistent, and valid pointers, the pointer interpreter will transition from the
DEC state into the NORM state.
— Following eight consecutive invalid pointers, the pointer interpreter will transition from the DEC state into the
LOP state.
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17 TMUX Functional Description (continued)
■
Pointer increments and decrements will be counted and presented to the microprocessor as follows:
— Pointer increments and decrements will be monitored and counted internally.
— The internal and latched counts will be forced to clear (0x00) if TMUX_RLOP[3—1] = 1 (Table 92 on page 92)
or TMUX_RPAIS[3—1] = 1 (Table 92), where [3—1] designates the tributary number.
— Upon the configured performance monitoring interval, raw counts are transferred to holding registers for
pointer increments (TMUX_RPTR_INC[1—3][10:0] (Table 129 on page121 )) and decrements
TMUX_RPTR_DEC[1—3][10:0] (Table 130), allowing access by the microprocessor. The raw counters will
reset (to 0x00).
— Depending on the value of SMPR_SAT_ROLLOVER (Table 67 on page68 ) in the microprocessor interface
block, the internal running counts saturate at their maximum value or rollover.
— However, increment and decrement event indications should be ignored during LOP station.
■
The current pointer state is read from TMUX_RLOP[3—1] and TMUX_RPAIS[3—1]. Any changes in pointer condition are read from the delta state bits TMUX_RLOPD[3—1] and TMUX_RPAISD[3—1] (Table 83). The associated interrupt mask bits are TMUX_RLOPM[3—1] (Table 87 on page89 ) and TMUX_RPAISM[3—1] (Table 87).
When the device is receiving a concatenated signal (STM-1(AU-3)), the receive concatenation mode register bit,
TMUX_RCONCATMODE (Table 95 on page 95), must be set for the concatenation state machines (register bits
TMUX_CONCAT_STATE[3—2][1:0] (Table 92 on page92 )) on ports 2 and 3 to contribute to pointer evaluation.
This state machine implements the pointer interpretation algorithm described in ETS 300 417-1-1: January 1996
- Annex B.
17.5.16 Path Monitoring Functions
The following sections describe the path monitoring functions. For STM-1 signals, the values corresponding to
STS-1 #1 are the relevant signals. For STS-3 input data, there are three versions of each path monitor, one corresponding to each STS-1. The mode bits are applied to the monitors of all three STS-1s.
J1 Monitor. J1 (path trace) monitoring has six different monitoring modes controlled by TMUX_J1MONMODE[2:0]
(Table 95 on page95 ). The J1 monitoring mode for all three STS-1s within an STS-3 signal is the same.
■
TMUX_J1MONMODE[2:0] = 000: The TMUX latches the value of the J1 byte every frame for a total of 64 bytes
in TMUX_J1DMON[1—3][1—64][7:0] (Table 137 on page122 , Table 138, and Table 139). The TMUX compares
the incoming J1 byte with the next expected value (the expected value is obtained by cycling through the previous stored 64 received bytes in round-robin fashion) and setting the path trace identifier state register bit(s),
TMUX_RTIMP[1—3] (Table 92 on page92 ), if different. Any change to the path trace identifier is reported in
TMUX_RTIMPD[1—3] (Table 83), with interrupt mask bits, TMUX_RTIMPM[1—3] (Table 87 on page89 ).
■
TMUX_J1MONMODE[2:0] = 001: This is the SONET framing mode. The hardware looks for the 0x0A character
to indicate that the next byte is the first byte of the path trace message. The J1 byte message is continuously
written into registers, TMUX_J1DMON[1—3][1—64][7:0], with the first byte residing at the first address. If any
received byte does not match the previously received byte for its location, then the state bit(s),
TMUX_RTIMP[1—3], is set. Any change to the path trace identifier is reported in TMUX_RTIMPD[1—3], with
interrupt masks bits, TMUX_RTIMPM[1—3].
■
TMUX_J1MONMODE[2:0] = 010: This is the SDH framing mode. The hardware looks for the byte with the MSB
set to one, which indicates that the next byte is the second byte of the message. The rest of operation is the
same as in SONET framing mode, except that there are 16 bytes instead of 64.
■
TMUX_J1MONMODE[2:0] = 011: A new J1 byte (TMUX_J1DMON[1][7:0]) will be detected after a number of
consecutive consistent occurrences of a new pattern (determined by the value in TMUX_CNTDJ1[3:0] (Table 99
on pag e99)) in the J1 overhead byte. Any changes to this byte must be reported in TMUX_RTIMPD[1—3], with
the interrupt mask bits, TMUX_RTIMPM[1—3]. The delta bit(s) in this mode indicate a change in state for the
TMUX_J1DMON[1][7:0] byte, and the state bits, TMUX_RTIMP[1—3], are not used.
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17 TMUX Functional Description (continued)
■
TMUX_J1MONMODE[1:0] = 100: The user will program the 64 expected values of J1 in
TMUX_EXPJ1DMON[1—3][1—64][7:0] (Table 134 on page122 , Table 135, and Table 136), in SONET framing
mode, where the first expected byte, the byte following the 0x0A character, is written into the first location of
TMUX_EXPJ1DMON[1][7:0]. The TMUX will compare the incoming J1 sequence with the stored expected value,
setting the path trace identifier state bit(s), TMUX_RTIMP[1—3] if they are different. Any change to the path trace
identifier is reported in TMUX_RTIMPD[1—3], with interrupt mask bits, TMUX_RTIMPM[1—3].
■
TMUX_J1MONMODE[1:0] = 101: The user will program the 16 expected values of J1 in
EXPJ1DMON[1—16][7:0] in SDH framing mode, where the first byte of the message has the MSB set to 1. The
TMUX compares the incoming J1 sequence with the stored expected value, setting the state register bit(s),
TMUX_RTIMP[1—3], if they are different. Any change to path trace identifier is reported in register bits,
TMUX_RTIMPD[1—3], with interrupt mask bits, TMUX_RTIMPM[1—3].
■
TMUX_J1MONMODE[1:0] = 110 and 111 are currently undefined.
B3 BIP-8 Check. A B3 BIP-8 even parity is computed over all the incoming synchronous payload envelope bits of
the STS-3/STM-1/STS-1 signal after descrambling, and compared to the B3 byte received in the next frame. The
total number of B3 BIP-8 bit errors (raw count), or block errors (as determined by TMUX_BITBLKB3 (Table 95 on
page 95), is counted. Upon the configured performance monitor (PM) interval, the value of the internal running
counter is placed into holding registers TMUX_B3ECNT[1—3][15:0] (Table 126 on page119 ) and then cleared.
Depending on the value of SMPR_SAT_ROLLOVER (Table 67 on pa ge68) in the microprocessor interface block,
the internal counter will either roll over or stay at its maximum value until cleared.
Signal Label C2 Byte Monitor. The C2 byte per STS-1/STM-1 is stored in TMUX_C2MON[1—3][7:0] (Table 104
on page101 ). Each register will be updated after a number, determined by the value in TMUX_CNTDC2[3:0]
(Table 99 on pag e99), of consecutive frames of identical C2 bytes for a given STS-1/STM-1, i.e., the 8-bit pattern
must be identical for a programmed number frames prior to updating the C2 register. Any change to C2 byte monitor is reported via the corresponding delta and mask register bits, TMUX_RC2MOND[1—3] (Table 83) and
TMUX_RC2MONM[1—3] (Table 87 on pag e89).
In addition, there are programmable expected value(s) for the C2 bytes of each STS-1/STM-1 in
TMUX_C2EXP[1—3][7:0] (Table 100 on page100 ). If the current value of a C2 byte in TMUX_C2MON[1—3][7:0]
does not equal the expected C2 value in TMUX_C2EXP[1—3][7:0]), then a payload label mismatch defect may be
declared for that STS-1/STM-1 in TMUX_RPLMP[1—3] (Table 92 on page92 ). Also, if the current value of a
C2 byte is all 0s, then the corresponding unequipped defect is declared in TMUX_RUNEQP[1—3] ( Table 92).
Note: The payload label mismatch and unequipped defects are mutually exclusive and unequipped takes priority.
The following table describes the conditions for generating payload label mismatch (TMUX_RPLMP[1—3]) and
unequipped defects (TMUX_RUNEQP).
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17 TMUX Functional Description (continued)
Table 524. STS Signal Label Defect Conditions
Provisioned STS PTE
Functionality, Expected C2
Any Equipped Functionality
Any Equipped Functionality
Equipped—Nonspecific
Any Payload Specific Code
Any Payload Specific Code
Equipped—Nonspecific (01) or
VT-Structured STS-1 (02)
Any Payload Specific Code
Except VT-Structured
STS-1 (02)
Any Equipped Functionality
Any Equipped Functionality
Received Payload Label
(C2 in hex)
Unequipped (00)
Equipped—Nonspecific (01)
Any Value (02 to E0, FD to FE)
The Same Payload Specific
Code (02 to E0, FD to FE)
A Different Payload Specific
Code (02 to E0, FD to FE)
PDI, 1 to 27 VTx Defects
(E1 to FB)
PDI, 1 to 27 VTx Defects
(E1 to FB)
PDI, 28 VT1.5 Defects or 1
Non-VT Payload Defect (FC)
Reserved (FF)
Defect
TMUX_FORCEC2DEF = 1
(Table 97)
TMUX_RUNEQP
No Change
None
No Change
None
No Change
None
No Change
TMUX_RPLMP
No Change
None
TMUX_RPLMP
TMUX_RPLMP
No Change
None
TMUX_RPLMP
None
TMUX_RPLMP
TMUX_FORCEC2DEF[2:0] will force path payload label mismatch defects on those conditions that are shown on
in Table 524 above.
The continuous N-times detection counter(s) will be reset to 0 upon the transition of the framer into the out of frame
state.
RDI-P Detection. A remote defect indication-path (RDI-P) signal indicates to STS path terminating equipment
(PTE) that its peer STS PTE has detected a defect on the signal that it originated. The TMUX supports a 1-bit
RDI-P code as well as a 3-bit enhanced RDI-P code; the mode is selectable using the TMUX_REPRDI_MODE
(Table 95 on page95 ). If TMUX_REPRDI_MODE = 0, then the 1-bit code is supported, and if
TMUX_REPRDI_MODE = 1, then the 3-bit enhanced path RDI code is supported.
The TMUX monitors for a 1-bit RDI-P code in G1[3] or a 3-bit enhanced remote defect indication (RDI-P) condition
in G1[3:1]. The current value of the path RDI state will be detected after a number of consecutive occurrences
determined by the value in TMUX_CNTDRDIP[3:0] (Table 99 on page 99). The current value(s) will be stored in
TMUX_RDIPMON[1—3][2:0]] (Table 104 on page 101), for nonenhanced RDI-P mode, and the current value(s) will
be stored in TMUX_RDIPMON[1—3][2:0], for enhanced RDI-P mode. Any change to TMUX_RDIPMON[1—3][2:0]
will be reported in TMUX_RRDIPD[1—3] with interrupt mask bits,TMUX_RRDIPM[1—3] (Table 87 on page89 ).
The continuous N-times detection counter(s) will be reset to 0 upon the transition of the framer into the out of frame
state.
REI-P Detection. Bits [7:4] of the G1 byte are allocated for use as a path remote error indication function (REI-P).
■
For STS-1 and STM-1 signals, bits [7:4] of the G1 byte are allocated for REI-P which conveys the error count
detected by the PTE (using the path BIP-8 code B3) back to its peer PTE as shown in Table 525.
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17 TMUX Functional Description (continued)
Table 525. STS-1 P-REI Interpretation
G1[7:4] Code
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
...
1111
Code Interpretation
0 (no errors)
1
2
3
4
5
6
7
8
0 (no errors)
...
0 (no errors)
The TMUX allows access to the G1-REI errored bit count for each STS-1/STM-1 in TMUX_G1ECNT[1—3][15:0]
(Table 128 on page 120), which is the accumulated error count from G1[3:0] byte of the STS-1/STM-1 signal. The
counter(s) will count in bit or block mode, depending on the value of TMUX_BITBLKG1 (Table 95 on page95 ).
Upon the configured performance monitor (PM) interval, the value of the internal running counter is placed into the
holding registers TMUX_G1ECNT[1—3][15:0] and then cleared. Depending on the value of
SMPR_SAT_ROLLOVER (Table 67 on pag e68) in the microprocessor interface block, the internal counter will
either roll over or stay at its maximum value until cleared.
Path User Byte F2 Monitor. The TMUX monitors the path user channel in the F2 byte of each STS-1/STM-1. The
F2 byte(s) will be stored in TMUX_F2MON0[1—3][7:0] (Table 104, starting on page 101). Each register will be
updated after a number of consecutive frames of identical F2[7:0] as determined by the value in
TMUX_CNTDF2[3:0] (Table 99 on page 99). That is, the 8-bit pattern must be identical for the programmed number
of frames prior to updating the F2 register. Any change to F2 monitor registers will be reported in
TMUX_RF2MOND[1—3] (Table 83), with interrupt mask bits, TMUX_RF2MONM[1—3] (Table 87 on page89 ). The
TMUX also maintains a history of the previous valid F2 byte in TMUX_F2MON1[1—3][7:0] (Table 104). The continuous N-times detection counter(s) will be reset to 0 upon the transition of the framer into the out of frame state.
H4 Multiframe Indicator. The H4 byte is allocated for use as a mapping specific indicator byte. For VT-structured
SPEs, this byte is used as a multiframe indicator.
The TMUX passes the H4 byte of each STS-1 onto the low-speed telecom bus so that it can be monitored by the
VT mapper block. The TMUX also indicates when the H4 byte(s) has a value of 0x01 by asserting the RLSV1 output pin (pin number W4) on the telecom bus during that frame.
Note: The three H4 bytes of an STS-3 signal can occur at any time with respect to one another within a frame.
Path User Byte F3 Monitor. The TMUX monitors the second path user channel in the F3 byte for each
STS-1/STM-1. The F3 byte(s) for each STS-1/STM-1 is stored in TMUX_F3MON0[1—3][7:0] (Table 104 on
page 101). Each register will be updated after a number determined by the value in TMUX_CNTDF3[3:0] (Table 99
on pag e99) of consecutive frames of identical F3[7:0] monitor bytes on that particular STS-1. That is, the 8-bit pattern must be identical for the programmed number of frames prior to updating the F3 register.
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17 TMUX Functional Description (continued)
Any change to F3 byte monitor registers is reported in TMUX_RF3MOND[1—3] (Table 83), with interrupt mask bits,
TMUX_RF3MONM[1—3] (Table 87 on page89 ).
The TMUX also maintains a history of the previous valid F3 byte in TMUX_F3MON1[1—3][7:0] (Table 104 on
page 101). The continuous N-times detection counter(s) will be reset to 0 upon the transition of the framer into the
out of frame state.
K3 Byte Monitor. The TMUX monitors the K3 byte for each STS-1/STM-1. The K3 byte(s) are stored in
TMUX_K3MON[1—3][7:0] (Table 104). Each register will be updated after a number determined by the value in
TMUX_CNTDK3[3:0] (Table 99 on page99 ) of consecutive frames of identical K3[7:0] for that particular
STS-1/STM-1. That is, the 8-bit pattern must be identical for a number of frames prior to updating the K3 register.
Any change to K3 monitor registers is reported in TMUX_RK3MOND[1—3] (Table 83), with interrupt mask bits,
TMUX_RK3MONM[1—3] (Table 87 on page89 ). The continuous N-times detection counter(s) will be reset to 0
upon the transition of the framer into the out of frame state.
N1 Byte Monitor. The TMUX monitors the N1 byte for each STS-1/STM-1. The N1 byte(s) are stored in
TMUX_N1MON[1—3][7:0] (Table 104 on page101 ). Each register will be updated after a number determined by
the value in TMUX_CNTDN1[3:0] (Table 99 on page 99) of consecutive frames of identical N1[7:0] for that particular STS-1/STM-1. That is, the 8-bit pattern must be identical for a number of frames prior to updating the N1 register. Any change to N1 monitor registers will be reported in TMUX_RN1MOND[1—3] (Table 83), with interrupt mask
bits, TMUX_RN1MONM[1—3] (Table 87 on page89 ). The continuous N-times detection counter(s) will be reset to
0 upon the transition of the framer into the out of frame state.
Signal Degrade BER Algorithm. A signal degrade state in register bit TMUX_RHSSD (Table 91 on page 92) and
change of state indication is reported in register bit, TMUX_RHSSDD (Table 82, starting on page79 ), with the
interrupt mask bit, TMUX_RHSSDM (Table 87 on page 89). This bit error rate algorithm can operate on either B1 or
B2 errors, determined by the value of TMUX_SDB1B2SEL (Table 95 on page95 ). Each B3 monitor has an independent signal degrade function as well in TMUX_RSDB3[1—3] (Table 92 on page92 ).
Declaring the signal degrade state requires the definition of two measurement windows, a monitoring block consisting of a number of frames in TMUX_SDNSSET[18:0] (Table 120 on page116 ) and a measurement interval consisting of a number of monitoring blocks in TMUX_SDBSET[11:0] (Table 120). A block is determined bad when the
number of bit errors equals or exceeds a threshold set in TMUX_SDLSET[3:0] (Table 120). Signal degrade is
declared when a number of bad monitoring blocks equals or exceeds the threshold in TMUX_SDMSET[7:0]
(Table 526) for the measurement interval.
Clearing the signal degrade state requires the definition of two measurement windows, a monitoring block consisting of a number of frames in TMUX_SDNSCLEAR[18:0] (Table 120) and a measurement interval consisting of a
number of monitoring blocks in TMUX_SDBCLEAR[11:0] (Table 120). A block is determined good when the number of bit errors is less than a threshold set in TMUX_SDLCLEAR[3:0] (Table 120). Signal degrade is cleared when
a number of good monitoring blocks equals or exceeds the threshold in TMUX_SDMCLEAR[7:0] (Table 120) for the
measurement interval.
The set parameters are used when the signal degrade state is clear, and the clear parameters are used when the
signal degrade state is declared.
The signal degrade state may be forced to the declared state with TMUX_SDSET (Table 78 on page 77) and forced
to the cleared state with TMUX_SDCLEAR (Table 78). One shot signal must be provided to force the BER algorithm into the failed state or normal state, respectively.
The algorithm described above can detect bit error rates from 1 x 10–3 to 1 x 10–9.
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17 TMUX Functional Description (continued)
Table 526. Signal Degrade (SD) Parameters
Name
TMUX_SDNSSET[18:0] (Table 120)
TMUX_SDLSET[3:0] (Table 120)
Function
Signal Degrade Ns Set. Number of frames in a monitoring block for SD.
Signal Degrade L Set. Error threshold for determining if a monitoring
block is bad.
TMUX_SDMSET[7:0] (Table 120)
Signal Degrade M Set. Threshold of the number of bad monitoring blocks
in an observation interval. If the number of bad blocks is below this threshold, then SD is cleared.
TMUX_SDBSET[15:0] (Table 120) Signal Degrade B Set. Number of monitoring blocks in a measurement
interval.
TMUX_SDNSCLEAR[18:0]
Signal Degrade Ns Clear. Number of frames in a monitoring block for
(Table 120)
SD.
TMUX_SDLCLEAR[3:0] (Table 120) Signal Degrade L Clear. Error threshold for determining if a monitoring
block is bad.
TMUX_SDMCLEAR[7:0] (Table 120) Signal Degrade M Clear. Threshold of the number of bad monitoring
blocks in an observation interval. If the number of bad blocks is below this
threshold, then SD is cleared.
TMUX_SDBCLEAR[15:0] (Table 120) Signal Degrade B Clear. Number of monitoring blocks in a measurement
interval.
TMUX_SDSET (Table 78)
Signal Degrade Set. Allows the signal degrade algorithm to be forced
into the failed state (active 0 to 1).
TMUX_SDCLEAR (Table 78)
Signal Degrade Clear. Allows the signal degrade algorithm to be forced
into the normal state (active 0 to 1).
TMUX_SDB1B2SEL (Table 95)
Signal Degrade B1/B2 Error Count Select. Control bit, when set to a
logic 0, causes the signal fail bit error rate algorithm to use B1 errors; otherwise, B2 errors are used to calculate the error rate.
TMUX_RHSSD (Table 91)
Signal Degrade BER Algorithm State Bit.
TMUX_RHSSDD (Table 82)
Signal Degrade BER Algorithm Delta Bit.
TMUX_RHSSDM (Table 86)
Signal Degrade BER Algorithm Mask Bit.
Note: The thresholds written by the control system will be one less than the desired number, except for the TMUX_SDLSET[3:0] and
TMUX_SDLCLEAR[3:0] parameters.
Signal Fail BER Algorithm. A signal degrade state in register bit TMUX_RHSSF (Table 91) and change of state
indication is reported in register bit, TMUX_RHSSFD (Table 82, starting on page79 ), with the interrupt mask bit,
TMUX_RHSSFM (Table 86 on page88 ). This bit error rate algorithm can operate on either B1 or B2 errors
selected with register bit, TMUX_SDB1B2SEL (Table 95 on pag e95). Each B3 monitor has its own bit error rate
algorithm as well with the failure indicated in TMUX_RSFB3[1—3] (Table 92 on pag e92).
Declaring the signal degrade state requires the definition of two measurement windows, a monitoring block consisting of a number of frames in TMUX_SFNSSET[18:0] (Table 121 on page117 ) and a measurement interval consisting of a number of monitoring blocks in TMUX_SFBSET[11:0] (Table 121). A block is determined bad when the
number of bit errors equals or exceeds a threshold set in TMUX_SFLSET[3:0] (Table 121). Signal degrade is
declared when a number of bad monitoring blocks equals or exceeds the threshold in TMUX_SFMSET[7:0]
(Table 121) for the measurement interval.
Clearing the signal degrade state requires the definition of two measurement windows, a monitoring block consisting of a number of frames in TMUX_SFNSCLEAR[18:0] (Table 121) and a measurement interval consisting of a
number of monitoring blocks in TMUX_SFBCLEAR[11:0] (Table 121). A block is determined good when the number of bit errors is less than a threshold set in TMUX_SFLCLEAR[3:0] (Table 121).
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17 TMUX Functional Description (continued)
Signal degrade is cleared when a number of good monitoring blocks equals or exceeds the threshold in
TMUX_SFMCLEAR[7:0] (Table 121) for the measurement interval.
The set parameters are used when the signal fail state is clear, and the clear parameters are used when the signal
fail state is declared.
The signal degrade state may be forced to the declared state with TMUX_SFSET (Table 78) and forced to the
cleared state with TMUX_SFCLEAR (Table 78). One shot signal must be provided to force the BER algorithm into
the failed state or normal state, respectively.
The above algorithm can detect bit error rates from 1 x 10 –3 to 1 x 10 –9.
Table 527. Signal Fail Parameters
Name
TMUX_SFNSSET[18:0] (Table 121)
TMUX_SFLSET[3:0] (Table 121)
TMUX_SFMSET[7:0] (Table 121)
TMUX_SFBSET[15:0] (Table 121)
TMUX_SFNSCLEAR[18:0]
(Table 121)
TMUX_SFLCLEAR[3:0] (Table 121)
Function
Signal Fail Ns Set. Number of frames in a monitoring block for SF.
Signal Fail L Set. Error threshold for determining if a monitoring block is
bad.
Signal Fail M Set. Threshold of the number of bad monitoring blocks in
an observation interval. If the number of bad blocks is below this threshold, then SF is cleared.
Signal Fail B Set. Number of monitoring blocks.
Signal Fail Ns Clear. Number of frames in a monitoring block for SF.
Signal Fail L Clear. Error threshold for determining if a monitoring block
is bad.
TMUX_SFMCLEAR[7:0] (Table 121) Signal Fail M Clear. Threshold of the number of bad monitoring blocks in
an observation interval. If the number of bad blocks is below this threshold, then SF is cleared.
TMUX_SFBCLEAR[15:0] (Table 121) Signal Fail B Clear. Number of monitoring blocks.
TMUX_SFB1B2SEL (Table 95)
Signal Fail B1/B2 Error Count Select. Control bit, when set to a logic 0,
causes the signal fail bit error rate algorithm to use B1 errors; when set to
a logic 1, causes the signal fail bit error rate algorithm to use B2 errors.
TMUX_SFSET (Table 78)
Signal Fail Set. Allows the signal degrade algorithm to be forced into the
failed state (active 0 to 1).
TMUX_SFCLEAR (Table 78)
Signal Fail Clear. Allows the signal degrade algorithm to be forced into
the normal state. (active 0 to 1).
TMUX_RHSSF (Table 91)
Signal Fail BER Algorithm State Bit.
TMUX_RHSSFD (Table 82)
Signal Fail BER Algorithm Delta Bit.
TMUX_RHSSFM (Table 86)
Signal Fail BER Algorithm Mask Bit.
Note: The thresholds written by the control system will be one less than the desired number, except for the TMUX_SFLSET[3:0] and
TMUX_SFLCLEAR[3:0] parameters.
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17 TMUX Functional Description (continued)
Table 528. Signal Fail or Signal Degrade Recommended Programming Values
Set
Threshold
1x10–3
1x10–4
1x10–5
1x10–6
1x10–7
1x10–8
1x10–9
NsSet
LSet
MSet
BSet
0x00001
0x00006
0x00030
0x001E0
0x01275
0x0B5A4
0x3F7A0
0x5
0x8
0x6
0x6
0x6
0x6
0x4
0x3D
0x03
0x03
0x03
0x04
0x04
0x05
0x003D
0x0007
0x0007
0x0007
0x0009
0x0009
0x0013
Clear
Threshold
1x10–4
1x10–5
1x10–6
1x10–7
1x10–8
1x10–9
1x10–10
NsClear
LClear
MClear
BClear
0x00001
0x00006
0x00030
0x001E0
0x01275
0x0B5A4
0x3F7A0
0x6
0x2
0x2
0x2
0x2
0x2
0x2
0x03
0x03
0x03
0x03
0x04
0x03
0x02
0x0007
0x0007
0x0007
0x0007
0x0009
0x0009
0x000F
Path Overhead Access Channel (POAC) Drop. The TMUX provides one path overhead access channel (POAC
output channel). The TMUX can receive up to three STS-1 signals. There are two register bits,
TMUX_RPOAC_SEL[1:0] (Table 118 on page 115), to designate which STS-1s POH will be dropped onto the
POAC channel. TMUX_RPOAC_SEL[1:0] = 01 designates STS-1 #1, TMUX_RPOAC_SEL[1:0] = 10 designates
STS-1 #2, and TMUX_RPOAC_SEL[1:0] = 11 designates STS-1 #3. TMUX_RPOAC_SEL[1:0] = 00 designates
that the RPOAC channel is not driven by the TMUX.
The POAC channel consists of the following signals:
■
■
■
A 576 kHz inverted clock signal sourced by the TMUX (RPOACCLK, pin AE3).
A 576 kbits/s data signal sourced by the TMUX (RPOACDATA, pin AD4).
An 8 kHz synchronization signal, sourced by the TMUX (RPOACSYNC, pin AF4). The sync signal is normally
low. During the last clock period of each frame coincident with the least significant bit of the last byte, the sync
signal is high.
The data signal is partitioned into frames of 9 bytes. The frame repetition rate is 8 kHz. Each byte consists of 8 bits
that are transmitted/received most significant bit first. The MSB of the second byte of each frame contains an
odd/even parity bit over the 72 bits of the previous frame. The remaining 7 bits of this byte are not specified.
Bytes shown in Table 529 summarize the access capabilities of the receive POAC.
Table 529. Path Overhead Byte Access
J1
POH Parity
C2
G1
F2
H4
F3
K3
N1
Even or odd parity can be inserted into the first bit of the MSB byte of the POAC outgoing frame. Parity is selected
with TMUX_RPOAC_OEPINS (Table 118 on page115 ).
AIS-P Insertion and AUTO_AISO Generation. Upon detecting certain failure conditions, the TMUX asserts the
external output signals named AUTO_AIS[1—3] (pins AD6, AE6, and AC6). The AUTO_AIS[1—3] signals, one per
STS-1, also informs the other blocks within the Super Mapper to insert AIS downstream due to detected failures.
The following conditions can cause AUTO_AISO[1—3] signals to be asserted: line AIS, LOC (STS-1 mode only),
LOS, LOF, OOF, LOP-P, SF (B1, B2, or B3), SD (B1, B2, or B3), payload label mismatch, or payload unequipped.
Each condition can be individually inhibited from contributing to the internal AUTO_AISO[1—3] signals. For concatenated signals (STS-3c or STM-1), all AUTO_AISO[1—3] signals should be driven coincidentally. In STS-3 mode,
each STS-1 signal has a corresponding AUTO_AISO signal.
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17 TMUX Functional Description (continued)
The following boolean expression is the criteria for AUTO_AIS and send path AIS. The expressions represent combinations of signal status states register bits and inhibit state register bits that form the criteria.
Criteria for AUTO_AISO<n> =
((TMUX_RLAISMON AND TMUX_RLAISMON_AISINH AND TMUX_RPSMUXSEL) OR
(TMUX_RILOC AND TMUX_RILOC_AISINH AND TMUX_RPSMUXSEL) OR
(TMUX_RHSLOS AND TMUX_RHSLOS_AISINH AND TMUX_RPSMUXSEL) OR
(TMUX_RHSLOF AND TMUX_RHSLOF_AISINH) OR
(TMUX_RHSOOF AND TMUX_RHSOOF_AISINH) OR
(TMUX_RLOP<n> AND TMUX_RLOP_AISINH) OR
(TMUX_RHSSF AND TMUX_RHSSF_AISINH AND TMUX_RPSMUXSEL) OR
(TMUX_RHSSD AND TMUX_RHSSD_AISINH AND TMUX_RPSMUXSEL) OR
(TMUX_RSFB3<n> AND TMUX_RSFB3_AISINH) OR
(TMUX_RSDB3<n> AND TMUX_RSDB3_AISINH) OR
(TMUX_RPLMP<n> AND TMUX_RHPLMP_AISINH) OR
(TMUX_RUNEQP<n> AND TMUX_RUNEQP_AISINH) OR
(TMUX_RTIMP<n> AND TMUX_RTIMP_AISINH) OR
(TMUX_RPAIS_INS))
In addition to generating the external AUTO_AIS signal, the TMUX can insert path AIS into the received signal prior
to driving it onto the low-speed telecom bus. The conditions for sending path AIS include some of the above conditions. The same inhibit bits are used as above. Note that the above AUTO_AISO[1—3] signal generation is on a per
STS-1 basis, while sending path AIS occurs on the complete STS-3/STM-1 signal (or STS-1 for STS-1 only mode).
Criteria for Send Path AIS =
((TMUX_RLAISMON AND TMUX_RLAISMON_AISINH AND TMUX_RPSMUXSEL) OR
(TMUX_RHSLOS AND TMUX_RHSLOS_AISINH AND TMUX_RPSMUXSEL) OR
(TMUX_RHSLOF AND TMUX_RHSLOF_AISINH) OR
(TMUX_RHSOOF AND TMUX_RHSOOF_AISINH) OR
(TMUX_RLOP<n> AND TMUX_RLOP_AISINH) OR
(TMUX_RHSSF AND TMUX_RHSSF_AISINH AND TMUX_RPSMUXSEL) OR
(TMUX_RHSSD AND TMUX_RHSSD_AISINH AND TMUX_RPSMUXSEL) OR
(TMUX_RPAIS_INS))
Receive Side Telecom Bus Interface. The TMUX outputs one parallel clock (RLSCLK, pin V4), three sync signals
(RLSSPE, RLSJ0J1V1, and RLSV1; pin numbers V1, V3, and W4), an 8-bit data bus (RLSDATA[7:0], pins R1, R3,
T4, T2, T3, U4, U2, and U3), and an odd/even (RLSPAR, pin V2) parity signal. The data bus carries either three
STS-1/TUG-3 signals, each in their own time slot, or it carries one STS-1 signal where the parallel clock operates
at 6.48 MHz instead of 19.44 MHz.
RLSCLK
RLSSPE
RLSJ0J1V1
RLSV1
A1
RLSDATA[7:0]
A2
J0
J1
V1
A1-1 A1-2 A1-3 A2-1 A2-2 A2-3 J0-1 J0-2 J0-3 J1-1 J1-2 J1-3 V1-1 V1-2 V1-3
3 BYTES
3 BYTES
3 BYTES
3 BYTES
3 BYTES
5-9008(F)
Figure 27. Receive Low-Speed Bus Interface Signals for STS-3/STM-1 Signals
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17 TMUX Functional Description (continued)
17.6 Transmit Direction (Transmit Path to SONET/SDH Line)
All functions supported by TMUX in the transmit direction are summarized below:
■
Transmit side telecom bus interface
■
Path overhead access channel (POAC) insert
■
Path overhead insertion functions
■
MSP 1 + 1 payload switch
■
Transport overhead access channel (TOAC) insert
■
Section and line overhead insertion functions
17.6.1 Transmit Side Telecom Bus Interface
The TMUX transmit side drives a parallel clock (TLSCLK, pin AA2) and three sync signals (TLSSPE, TLSJ0J1V1,
and TLSV1; pins AB2, AB4, and AB3) onto the telecom bus. From these sync signals, the SPE mappers can determine when to drive data onto the bus. The TMUX receives an 8-bit data bus (TLSDATA[7:0], pins W2, W1, W3, Y4,
Y2, Y1, Y3, and AA4), and an odd/even (TLSPAR, pin AA3) parity signal from the telecom bus. The data consists of
the SPE for up to 3 STS-1s.
The parallel clock operates at 19.44 MHz for STS-3/STM-1 modes and at 6.48 MHz for STS-1 mode.
TLSCLK
TLSSPE
TLSJ0J1V1
TLSV1
A1
TLSDATA[7:0]
A2
J0
J1
V1
A1-1 A1-2 A1-3 A2-1 A2-2 A2-3 J0-1 J0-2 J0-3 J1-1 J1-2 J1-3 V1-1 V1-2 V1-3
3 BYTES
3 BYTES
3 BYTES
3 BYTES
3 BYTES
5-9009(F)
Figure 28. Transmit Low-Speed Bus Interface Signals for STS-3/STM-1 Signals
17.6.2 Transmit Path and Transport Overhead Insertion Diagram
The transmit block consists of two overhead insertion sections. The first section inserts the path overhead (POH)
bytes into the payload data to create an STS-3/STM-1/STS-1 SPE. After POH insertion, there is an MSP 1 + 1 protection switch on the payload. After the switch selection is made, the transport overhead bytes are added to the
SPE to generate a complete SONET/SDH frame.
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TMXF28155/51 Super Mapper
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17 TMUX Functional Description (continued)
TRANSMIT PATH TO SONET/SDH LINE (TRANSMIT DIRECTION)
TRANSMIT DATA
INSERT J0
SCRAM.
A1/A2
INSERT
SECTION/RSOH
B1
B1
GENERATE
INSERT
AIS
MSOH
INSERT LINE/MSOH
F1
B2
B2
GENERATE
F1
INSERT
B1, E1, F1, D1—3 INSERT
POAC INSERT
F2, F3, C2, N1, AND J1
K3
APS
INSERT
J1
K3
K2
[2:0]
K1/K2
APS
RDI-L
INSERT
M0
M0
REI-L
S1
SYNC
STATUS
TOAC INSERT
D4—D12 AND E2
MSP 1+1
SWITCH
INSERT
AIS-P
B3
INSERT
INSERT
J1
K1
K2
TRANSMIT PROTECTION
SWITCH BUS DATA
B3
GENERATE
G1
RDI-P
INSERT
G1
REI-P
INSERT
INSERT
N1
INSERT
C2
INSERT
F3
G1
G1
N1
C2
F3
INSERT
F2
F2
INSERT
H4
H4
TELECOM BUS
INSERT PATH OVERHEAD BYTES
5-9010(F)r.2
Figure 29. Transmit Direction POH and TOH Insertion Diagram
The first section, which is the path overhead section, is broken down into the following functional parts:
■
J1 path trace insert
■
B3 calculation and insert
■
C2 signal label insert
■
REI-P and RDI-P insert
■
Path user byte F2 insert
■
H4 multiframe insert
■
Path user byte F3 insert
■
■
■
K3 insert
Tandem connection byte N1 insert
AIS-P Insert
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Preliminary Data Sheet
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17 TMUX Functional Description (continued)
The second section after the switch, the transport overhead section, is broken down into the following functional
parts:
■
TOAC insert
■
Sync status byte (S1) insert
■
M0/M1—REI-L Insert
■
K1 and K2 insert
■
AIS-L insert
■
B2 calculation and insert
■
F1 byte insert
■
B1 generate and error insert
■
Scrambler
■
J0 insert control
■
A2 error insert
All insert control functions that are inhibited will insert all zeros or all ones, depending on the value of microprocessor register bit, SMPR_OH_DEFLT (Table 67 on pag e68).
17.6.3 POAC Insert
One path overhead access channel (POAC) is provided on-chip to provision the path overhead (POH) portion of
the outgoing frame. The TMUX transmits up to three STS-1s. The register bits TMUX_TPOAC_SEL[1:0] (Table 118
on page115 ) designate which STS-1s POH is inserted from the transmit POAC channel.
TMUX_TPOAC_SEL[1:0] = 00 designates no TMUX_TPOAC insertion, TMUX_TPOAC_SEL[1:0] = 01 designates
STS-1 #1, TMUX_TPOAC_SEL[1:0] = 10 designates STS-1 #2, and TMUX_TPOAC_SEL[1:0] = 11 designates
STS-1 #3.
A POAC channel consists of the following signals:
■
A 576 kHz inverted clock signal sourced by the TMUX (TPOACCLK, pin AE4).
■
A 576 kbits/s serial data signal received by the TMUX in the transmit direction (TPOACDATA, pin AD5).
An 8 kHz synchronization signal (TPOACSYNC, pin AC5), sourced by the TMUX. The sync signal is normally low.
During the last clock period of each frame, coincident with the least significant bit of the eighth byte, the sync signal
is high.
The data signal is partitioned into frames of 9 bytes. The frame repetition rate is 8 kHz. Each byte consists of 8 bits
that are transmitted/received most significant bit first. The MSB of the first byte of each frame contains an odd/even
parity bit over the 72 bits of the previous frame. The remaining 7 bits of this byte are not specified. The B3, G1, and
H4 transmit path overhead bytes are not provisionable via the POAC channel.
Bytes shown in Table 530 summarize the access capabilities of the transmit POAC channel. X indicates a don’t
care.
Table 530. Path Overhead Byte Access—Transmit Direction
388
J1
X
F3
POH Parity
F2
K3
C2
X
N1
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17 TMUX Functional Description (continued)
An event indication TMUX_TPOAC_PE (Table 80 on page78 ), interrupt mask bit TMUX_TPOAC_PM (Table 84 on
page 87), is provided to indicate parity errors for the POAC channel. Odd (logic 0)/even (logic 1) parity is checked
and is configured with TMUX_TPOAC_OEPMON (Table 117 on page113 ).
Table 531 summarizes the insertion options for the specified overhead bytes for POAC. The TMUX allows a fixed
default value (all zeros or all ones) to be inserted on the corresponding POAC value. All control signals are activehigh.
Table 531. TPOAC Control Bits
Overhead Bytes
Register Control Bits
J1
TMUX_TPOAC_J1 (Table 118)
C2
TMUX_TPOAC_C2 (Table 118)
F2
TMUX_TPOAC_F2 (Table 118)
F3
TMUX_TPOAC_F3 (Table 118)
K3
TMUX_TPOAC_K3 (Table 118)
N1
TMUX_TPOAC_N1 (Table 118)
Values
0 (Default Value)
1
SMPR_OH_DEFLT
(00000000/11111111)
TPOAC
Data
17.6.4 AIS Path Generation
Path AIS is specified as all ones in the entire STS-1 signal before scrambling, excluding the transport overhead
(section and line overhead).
Path AIS can be inserted for each STS-1 in the STS-3 using register bits, TMUX_TLS_PAISINS[3:1] (Table 105 on
page 102).
17.6.5 J1 Insert Control
A 64-byte sequence stored in TMUX_TJ1DINS[1—3][1—64][7:0] (Table 140 on page123 , Table 141, and
Table 142), will be inserted into the outgoing J1 byte if TMUX_THSJ1INS (Table 108 on page105 ) is set to 1. Otherwise, the associated POAC value is inserted when TMUX_TPOAC_J1 (Table 118 on page 115) is a logic 1, or
the default value is inserted when TMUX_TPOAC_J1 is logic 0.
17.6.6 B3 BIP-8 Calculation and Insert
The B3 bytes are allocated for a path overhead error monitoring function. This function will be a bit interleaved parity 8 code (BIP-8) using even parity. The BIP-8 is computed before scrambling over all bits of the previous STS-1
frame except for the first three columns consisting of the section and line overhead and is placed in byte B3 of the
current frame, also before scrambling.
A bit error rate can be inserted on any B3 byte with TMUX_THSB3ERRINS[1—3] ( Table 115 on page112 ) and
microprocessor interface block SMPR_BER_INSRT (Table 65 on page 66) bit. When TMUX_THSB3ERRINS[1—3]
is asserted, the corresponding B3 byte is inverted each time the SMPR_BER_INSRT bit is asserted.
17.6.7 C2 Signal Label Byte Insert
When TMUX_THSC2INS[1—3] = 1 (Table 108 on page 105), the value in TMUX_TC2INS[1—3][7:0] (Table 124 on
page 118) is inserted into the C2 byte of the outgoing signal. Otherwise, the associated POAC value is inserted
when TMUX_TPOAC_C2 = 1 (Table 118 on page115 ). If both TMUX_THSC2INS and TMUX_TPOAC_C2 = 0,
then the value inserted depends on the microprocessor interface block, SMPR_OH_DEFLT (Table 67 on page68 )
bit value. If SMPR_OH_DEFLT = 0, then all 0s are inserted. If SMPR_OH_DEFLT = 1, then all ones are inserted.
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17 TMUX Functional Description (continued)
17.6.8 Path RDI (RDI-P) Insert
When TMUX_THSRDIPINS = 1 (Table 108 on page 105), then data from TMUX_TRDIPINS[1—3][2:0] (Table 114
on page110 ) is written into the corresponding three STS-1 G1 byte output bits (G1[3:1]). For STS-3 mode, each
STS-1 signal carries its own G1 value. For STM-1 mode, only TMUX_TRDIPINS1[2:0] is written into the first
STS-1 location. When TMUX_THSRDIPINS = 0, hardware insert is enabled for RDI-P insertion. Each defect contribution to the RDI-P outgoing code can be inhibited. There are two modes supported for path RDI insertion. One
mode conforms to the earlier one-bit version of the standard. The other mode, enhanced RDI-P mode, uses a 3-bit
RDI-P code and conforms to the current version of the standard. When TMUX_TEPRDI_MODE = 0 (Table 110 on
page 109), the TMUX sends a 3-bit code that conforms to the earlier 1-bit version of the standards. If
TMUX_TEPRDI_MODE = 1, the TMUX will send a 3-bit code conforming to the current enhanced path RDI encoding. Note that for non-enhanced RDI-P mode, the relevant defects are AIS-P and LOP-P. For enhanced RDI-P
mode, the relevant defects are AIS-P, LOP-P, PLM-P, and UNEQ-P.
When a failure condition exists that will cause RDI-P to be generated via hardware, the generation of RDI-P must
last for at least 20 frames before clearing, even if the original failure cause has cleared in less than 20 frames.
Table 532 describes the encoding of the path RDI defects.
Table 532. RDI-P Defects for Enhanced RDI-P Mode
Bit 3
0
0
0
0
1
1
1
1
G1
Bit 2
0
0
1
1
0
0
1
1
Triggers
Bit 1
0
1
0
1
0
1
0
1
No defects (nonenhanced RDI-P mode).
No defects (enhanced RDI-P mode).
LCD-P, PLM-P (LCD-P not supported in Super Mapper).
No defects (nonenhanced RDI-P mode).
AIS-P, LOP-P (nonenhanced RDI-P mode).
AIS-P, LOP-P (enhanced RDI-P mode).
TIM-P, UNEQ-P (enhanced RDI-P mode).
AIS-P, LOP-P (nonenhanced RDI-P mode).
The TMUX provides a protection switch MUX for RDI-P insertion. The MUX is controlled by TMUX_TPREIRDISEL
(Table 107 on page 103). If TMUX_TPREIRDISEL = 1, then the RDI-P value for insertion is taken from the value on
the protection board rather than from the receive side of the same TMUX.
17.6.9 REI-P: G1(7:4) Insert
Four bits of the G1 byte G1(7:4) are allocated for use as path remote error indication (REI). For STS-1 signals and
for STM-1 signals, these bits convey the count (in the range of 0 to 8) of interleaved bit blocks that have been
detected in error by the BIP-8 (B3) detector on the received signal.
The automatic insertion of path REI can be inhibited on an STS-1 basis by programming the corresponding register
bits TMUX_TPREIINS[1:3] (Table 115) to 1. For STM-1 mode, only TMUX_TPREIINS[1] is relevant. If the register
bit(s) TMUX_TPREIINS[1:3] are programmed to 1, then one error is inserted into the G1 byte for that particular
STS-1(s) each time the microprocessor interface block SMPR_BER_INSRT (Table 65 on page66 ) bit is asserted.
The TMUX provides a protection switch MUX for REI-P insertion. The MUX is controlled by TMUX_TPREIRDISEL
(Table 107 on page 103). If TMUX_TPREIRDISEL = 1, then the REI-P value for insertion is taken from the value on
the protection board rather than from the receive side of the same TMUX.
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17 TMUX Functional Description (continued)
17.6.10 F2 Byte Insert
When TMUX_THSF2INS = 1 (Table 108 on page 105), the value in TMUX_TF2INS[1—3][7:0] ( Table 114 on
page 110) is inserted into the outgoing signal. Otherwise, the associated POAC value is inserted when
TMUX_TPOAC_F2 = 1 (Table 118 on page115 ). If both TMUX_THSF2INS and TMUX_TPOAC_F2 = 0, then the
value inserted depends on the value of microprocessor interface block SMPR_OH_DEFLT (Table 67 on pag e68)
bit. If SMPR_OH_DEFLT = 0, then all 0s are inserted. If SMPR_OH_DEFLT = 1, then all ones are inserted.
17.6.11 H4 Insert Control
A 4-byte sequence (0, 1, 2, and 3) will be inserted into the outgoing H4 bytes. Note that the assertion of pin TLSV1
(pin AB3) occurs after the J1 byte(s) during the frame where the H4 count equals one.
17.6.12 F3 Byte Insert
When TMUX_THSF3INS = 1 (Table 108), the value in TMUX_TF3INS[1—3][7:0] (Table 114 on page110 ) is
inserted into the outgoing signal. Otherwise, the associated POAC value is inserted when TMUX_TPOAC_F3 = 1
(Table 118 on page 115). If both TMUX_THSF3INS and TMUX_TPOAC_F3 = 0, then the value inserted depends
on the value of microprocessor interface block SMPR_OH_DEFLT (Table 67 on page68 ) bit. If SMPR_OH_DEFLT
= 0, then all 0s are inserted. If SMPR_OH_DEFLT = 1, then all ones are inserted.
17.6.13 K3 Byte Insert
When TMUX_THSK3INS = 1 (Table 108 on page105 ), the value in TMUX_TK3INS[1—3][7:0] (Table 114) is
inserted into the outgoing signal. Otherwise, the associated POAC value is inserted when TMUX_TPOAC_K3 = 1
(Table 118 on page 115). If both TMUX_THSK3INS and TMUX_TPOAC_K3 = 0, then the value inserted depends
on the value of microprocessor interface block SMPR_OH_DEFLT (Table 67) bit. If SMPR_OH_DEFLT = 0, then all
0s are inserted. If SMPR_OH_DEFLT = 1, then all ones are inserted.
17.6.14 N1 Byte Insert
When TMUX_THSN1INS = 1 (Table 108 on page 105), the value in TMUX_TN1INS[1—3][7:0] (Table 114 on
page 110) is inserted into the outgoing signal. Otherwise, the associated POAC value is inserted when
TMUX_TPOAC_N1 = 1 (Table 118). If both TMUX_THSN1INS and TMUX_TPOAC_N1 = 0, then the value inserted
depends on the value of microprocessor interface block SMPR_OH_DEFLT (Table 67 on page68 ) bit. If
SMPR_OH_DEFLT = 0, then all 0s are inserted. If SMPR_OH_DEFLT = 1, then all ones are inserted.
17.6.15 MSP 1 + 1 Payload Switch
For the working transmit high-speed data output (THSDP/N, pins AF9/AE9), it is possible to select the normal
transmit path low-speed data by setting TMUX_TPSMUXSEL2 = 0 (Table 106 on page 103) or the receive-side
protection input data by setting TMUX_TPSMUXSEL2 = 1. Note that if the receive-side protection input is selected,
then the local clock and frame sync are generated based on the receive-side protection inputs as well.
To create the transmit high-speed protection outputs (TPSD155P/N and TPSC155P/N; pins AF13/AE13 and
AC12/AD13), it is possible to select the normal transmit path low-speed input data with TMUX_TPSMUXSEL3 = 0
(Table 106 on page 103) or the receive-side working inputs with TMUX_TPSMUXSEL3 = 1.
Note: Clocks and timing signals are selected by TMUX_TPSMUXSEL3 as well as the parallel data.
17.6.16 Transmit Transport Overhead Access Channel (TTOAC)
The TMUX provides a transmit transport overhead access channel (TTOAC) to provision the TOH portion of the
outgoing frame. The TTOAC channel supports three modes of operation based on values in
TMUX_TTOAC_D13MODE and TMUX_TTOAC_D412MODE (Table 117 on page113 ).
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17 TMUX Functional Description (continued)
The TTOAC channel consists of the following signals:
■
A data signal received by the TMUX in the transmit direction (TTOACDATA, pin AE2). The data bytes per frame
received depend on the values of TMUX_TTOAC_D13MODE and TMUX_TTOAC_D412MODE. See Table 533
below.
■
A clock signal sourced by the TMUX (TTOACCLK, pin AB6). The clock frequency depends on the values of
TMUX_TTOAC_D13MODE and TMUX_TTOAC_D412MODE. See Table 533 below.
■
An 8 kHz synchronization signal (TTOACSYNC, pin AF3) is sourced by the TMUX. This sync signal is normally
low; during the last clock period of each frame, coincident with the least significant bit of the last byte, the sync
signal is high.
Table 533. Transmit TOAC Modes
TOAC Mode
DCC1—DCC3
DCC4—DCC12
Full TOH mode
TMUX_TTOAC_
D13MODE Value
1
0
0
TMUX_TTOAC_
D412MODE Value
X
1
0
Data Bytes per
Frame
3
9
81
Clock Rate
192 kHz
576 kHz
5.184 MHz
Transmit TOAC—DCC1 through DCC3 Mode. In this mode, DCC bytes 1 to 3 are received serially on the data
pin. The clock rate is 192 kHz. The data bytes are received MSB first, and the sequence of data bytes is DCC1,
DCC2, and DCC3. The data signal is partitioned into frames of 3 bytes. The frame repetition rate is 8 kHz.
Transmit TOAC—DCC4 through DCC12 Mode. In this mode, DCC bytes 4 to 12 are received serially on the data
output. The clock rate is 576 kHz. The data bytes are received MSB first, and the sequence of data bytes is DCC4,
DCC5, DCC6, DCC7, DCC8, DCC9, DCC10, DCC11, and DCC12. The data signal is partitioned into frames of
9 bytes. The frame repetition rate is 8 kHz.
Transmit TOAC—Full TOH Access Mode. In this mode, where TMUX_TTOAC_D13MODE = 0 and
TMUX_TTOAC_D412MODE = 0 (Table 117 on page113 ), the data signal (TTOACDATA, pin AE2) is partitioned
into frames of 81 bytes. The frame repetition rate is 8 kHz. Each byte consists of 8 bits that are transmitted/received
most significant bit first. The MSB of the first byte of each frame contains an odd/even parity bit over the 648 bits of
the previous frame. The remaining 7 bits of this byte are not specified.
Bytes shown in Table 534 summarize the access capabilities of the transmit TOAC. This table describes the possible bytes in the outgoing frame that can be provisioned from the values on the TOAC channel. There are additional
mode bits described in Table 535 that must be programmed to allow insertion from the TOAC channel. Bytes indicated in bold type below are not specified in the standard, but are available for insertion into the outgoing frame via
the register bit, TMUX_TTOAC_AVAIL (Table 117). An X in Table 534 indicates bytes that are don’t cares; the values of these bytes in the outgoing transmit frame are not related to the values on the TTOAC channel.
Table 534. Transmit Transport Overhead Byte Full Access Mode
OH Parity
X
D1
X
X
D4
D7
D10
S1
392
X
B1-2
D1-2
X
X
D4-2
D7-2
D10-2
Z1-2
X
B1-3
D1-3
X
X
D4-3
D7-3
D10-3
Z1-3
X
E1
D2
X
X
D5
D8
D11
Z2
X
E1-2
D2-2
X
K1-2
D5-2
D8-2
D11-2
Z2-2
X
E1-3
D2-3
X
K1-3
D5-3
D8-3
D11-3
X
X
F1
D3
X
X
D6
D9
D12
E2
X
F1-2
D3-2
X
K2-2
D6-2
D9-2
D12-2
E2-2
X
F1-3
D3-3
X
K2-3
D6-3
D9-3
D12-3
E2-3
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17 TMUX Functional Description (continued)
Table 535 summarizes the insertion options for the specified overhead bytes for TOAC in full TOH access mode.
The TMUX allows a default value (all zeros if microprocessor interface block SMPR_OH_DEFLT = 0 (Table 67 on
page 68), and all ones if SMPR_OH_DEFLT = 1) to be inserted on the corresponding TOAC value. All control signals are active-high.
Table 535. TTOAC Control Bits in Full Access Mode
Overhead Bytes
Register Control Bits
E1
TMUX_TTOAC_E1 (Table 117)
F1
TMUX_TTOAC_F1 (Table 117)
D1—D3
TMUX_TTOAC_D1TO3 (Table 117)
D4—D12
TMUX_TTOAC_D4TO12 (Table 117)
S1
TMUX_TTOAC_S1 (Table 117)
E2
TMUX_TTOAC_E2 (Table 117)
All remaining bytes
in Table 534
TMUX_TTOAC_AVAIL (Table 117)
Value of the Register Control Bits
0 (Default Value)
1
SMPR_OH_DEFLT
(00000000 or 11111111)
TOAC Data
An event indication must be provided to indicate parity errors for the TOAC channel. Odd or even parity is checked
depending on TMUX_TTOAC_OEPMON (Table 117 on page 113); 0 selects odd parity and 1 selects even parity. A
parity error is reported in status register bit TMUX_TTOAC_PE (Table 80 on pag e78), and the interrupt is
maskable with TMUX_TTOAC_PM (Table 84 on page87 ).
17.6.17 Sync Status Byte (S1) Insert
When TMUX_THSS1INS = 1 (Table 107 on page 103), the value in TMUX_TS1INS[7:0] (Table 112 on page 110) is
inserted into the S1 byte of the outgoing signal; otherwise, the associated TOAC value is inserted when
TMUX_TTOAC_S1 = 1 (Table 117 on pag e113). If both TMUX_THSS1INS and TMUX_TTOAC_S1 are a logic 0,
then the value inserted depends on the value of the microprocessor interface block SMPR_OH_DEFLT (Table 67
on page68 ) bit. If SMPR_OH_DEFLT = 0, then all zeros are inserted. If SMPR_OH_DEFLT = 1, then all ones are
inserted.
17.6.18 REI-L: M1 Insert
For STS-3/STM-1 modes, the M1 byte is allocated for use as a line remote error indication (REI). For STS-1, bits 0
to 3 of the M0 byte are used. The M0 or M1 bytes convey the count of interleaved bit blocks that have been
detected in error by the line BIP-8 (B2) detector on the received signal.
This function can be inhibited by asserting TMUX_THSLREIINH (Table 107 on page103 ). A bit error in the M0/M1
byte can be inserted under user control. When TMUX_TLREIINS (Table 115 on page112 ) is asserted the corresponding M0 or M1 byte will indicate one error each time the microprocessor interface block SMPR_BER_INSRT
(Table 65) bit is asserted.
The TMUX provides a protection switch MUX for REI-L insertion, controlled by TMUX_TLREIRDISEL (Table 107).
If TMUX_TLREIRDISEL = 1, then the REI-L value for insertion is taken from the value on the protection board
rather than from the receive side of the same TMUX.
17.6.19 APS Value and K2 Insert Control Parameters
When TMUX_THSAPSINS = 1 (Table 107), the K1 byte and the five most significant bits of the K2 byte are written
from TMUX_TAPSINS[12:0] (Table 113). When TMUX_THSAPSINS = 0, either all 0s or all ones will be written,
depending on the value of microprocessor interface block SMPR_OH_DEFLT (Table 67) bit.
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17 TMUX Functional Description (continued)
An APS babbling test is controlled with TMUX_TAPSBABINS (Table 116 on page113 ). Setting
TMUX_TAPSBABINS = 1 forces the K1[7:0], K2[7:3) to an inconsistent state; no three consecutive values are continuously the same.
When the transmit K2 software insert bit TMUX_THSK2INS = 1 (Table 107 on page103 ), data from bits
TMUX_TK2INS[2:0] (Table 113 on page110 ) is written into the K2[2:0] output bits. When TMUX_THSK2INS = 0,
hardware insertion of RDI-L is enabled.
17.6.20 Criteria for Insert Line RDI
Hardware insertion of line RDI is generated using the following equation. Each defect contribution to line RDI can
be individually inhibited.
(TMUX_RILOC AND TMUX_TRILOC_LRDIINH) OR
(TMUX_RHSLOS AND TMUX_TRLOS_LRDIINH) OR
(TMUX_RHSLOF AND TMUX_TRLOF_LRDIINH) OR
(TMUX_RHSOOF AND TMUX_TROOF_LRDIINH) OR
(TMUX_RLAISMON AND TMUX_TRLAISMON_LRDIINH) OR
(TMUX_RHSSF AND TMUX_TRSF_LRDIINH) OR
(TMUX_RHSSD AND TMUX_TRSD_LRDIINH)
When a failure condition exists that will cause RDI-L to be generated, the generation of RDI-L must last for at least
20 frames before clearing, even if the original failure cause has cleared in less than 20 frames.
The TMUX provides a protection switch MUX for RDI-L insertion. The MUX is controlled by TMUX_TLREIRDISEL
(Table 107). If TMUX_TLREIRDISEL = 1, then the RDI-L value for insertion is taken from the value on the protection board rather than from the receive side of the same TMUX.
17.6.21 Line AIS Generation
Line AIS is specified as all ones in the entire STS/STM signal before scrambling, excluding the section overhead.
Line AIS can be generated by setting TMUX_THSLAISINS = 1 (Table 107).
17.6.22 B2 BIP-8 Calculation and Insert
The B2 byte is allocated for a line overhead error monitoring function. This function will be a bit interleaved parity-8
code (BIP-8) using even parity. The BIP-8 is computed before scrambling, over all the bits of the previous STS-1
frame (except for the 9 bytes of section overhead) and is placed in byte B2 of the current frame also before scrambling.
A bit error rate can be inserted on any B2 byte. When bit(s) TMUX_THSB2ERRINS[1—3] (Table 115 on page112 )
is (are) asserted, the corresponding B2 byte is inverted each time the microprocessor interface block
SMPR_BER_INSRT (Table 65 on page66 ) bit is asserted.
17.6.23 F1 Byte Insert
When TMUX_THSF1INS = 1 (Table 107 on page 103), the value in TMUX_TF1INS[7:0] (Table 112 on page 110) is
inserted into the F1 byte of the outgoing signal. Otherwise, the associated TOAC value is inserted when
TMUX_TTOAC_F1 = 1 (Table 117 on page113 ). If both TMUX_THSF1INS and TMUX_TTOAC_F1 = 0, then the
value inserted depends on the value of microprocessor interface block SMPR_OH_DEFLT (Table 67 on page 68)
bit. If SMPR_OH_DEFLT = 0, then all 0s are inserted. If SMPR_OH_DEFLT = 1, then all ones are inserted.
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17 TMUX Functional Description (continued)
17.6.24 B1 Generate and Error Insert
The section bit interleaved parity code (BIP-8) byte (even parity) is used to check for transmission errors over a
section. Its value is calculated over all bits in the previous frame after scrambling and placed in the B1 byte of time
slot 1 before scrambling.
A bit error rate can be inserted on the B1 byte. When TMUX_THSB1ERRINS = 1 (Table 115 on page 112), the B1
byte is inverted each time the microprocessor interface block SMPR_BER_INSRT (Table 65 on page66 ) bit is
asserted.
17.6.25 Scrambler
The outgoing frame will be scrambled with the frame synchronous scrambler of length 127 and generating polynomial x7 + x6 + 1. The entire STS/STM signal will be scrambled except for the first row of overhead. The scrambler
will be set to 1111111 on the first byte following the last overhead byte in the first row.
For test purposes, the scrambler will be disabled when TMUX_THSSCR = 0 (Table 106 on page 103).
17.6.26 J0 Insert Control
A 16-byte sequence stored in TMUX_TJ0DINS[1—16][7:0] (Table 133 on page121 ) will be inserted into the outgoing J0 byte if TMUX_THSJ0INS = 1 (Table 107 on pag e103). If TMUX_THSJ0INS = 0, then the value inserted
depends on the value of microprocessor interface block SMPR_OH_DEFLT (Table 67) bit. If SMPR_OH_DEFLT =
0, then all 0s are inserted. If SMPR_OH_DEFLT = 1, then all ones are inserted.
17.6.27 Z0-2, Z0-3 Insert Control
The 2 bytes, Z0-2 and Z0-3, that follow J0 are not scrambled. If TMUX_THSZ0INS = 1 (Table 107), then the values
stored in TMUX_TZ02INS[7:0] (Table 111 on pag e110) and TMUX_TZ03INS[7:0] (Table 111) will be inserted. If
TMUX_THSZ0INS = 0, then the value inserted depends on the value of microprocessor interface block
SMPR_OH_DEFLT bit. If SMPR_OH_DEFLT = 0, then all zeros are inserted. If SMPR_OH_DEFLT = 1, then all
ones are inserted.
17.6.28 A2 Error Insert
The TMUX allows, under software control, from 1 to 32 continuous frames to have an inverted A2-1 (0x28 to 0xD7)
pattern in the outgoing frame. The value in TMUX_TA2ERRINS[4:0] (Table 106) specifies the number of frames to
insert errors into while assertion of microprocessor interface block, SMPR_BER_INSRT bit, starts the error insertion process.
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18 SPE Mapper Functional Description
Table of Contents
Contents
Page
18 SPE Mapper Functional Description ............................................................................................................... 396
18.1 Introduction ............................................................................................................................................. 398
18.2 Features ................................................................................................................................................. 398
18.3 SPE Mapper Functional Block Diagrams ............................................................................................... 399
18.4 TUG-2 to AU-3/STS-1 SPE Mapping (Used in North American Systems) ............................................. 402
18.5 TUG-2 to TUG-3 Mapping (Used in ITU/ETSI Standard Based Systems) ............................................. 402
18.6 DS3 to AU-3/STS-1 SPE Mapping (Used in Telcordia/ANSI Standards Based Systems) ..................... 403
18.7 DS3 to TUG-3 Mapping (Used in ITU/ETSI Standard Based Systems) ................................................. 403
18.8 SPE Mapper Basic Configuration ........................................................................................................... 403
18.9 DS3 Configuration .................................................................................................................................. 403
18.9.1 DS3 M13 ...................................................................................................................................... 404
18.9.2 DS3 Loopback Channel ............................................................................................................... 404
18.9.3 DS3 Clear Channel from External Pins ........................................................................................ 404
18.10 Phase Detector for External DS3 PLL .................................................................................................. 404
18.11 Serial STS-1 SPE Channel (NSMI) ...................................................................................................... 405
18.12 TMUX Interface to the SPE Mapper ..................................................................................................... 406
18.13 PATH Termination Block ...................................................................................................................... 406
18.13.1 Pointer Interpretation Block ....................................................................................................... 407
18.14 SPE Mapper Receive Direction Requirements ..................................................................................... 410
18.14.1 Loss of Clock and Loss of Sync Monitors ................................................................................. 411
18.14.2 J1 Monitor .................................................................................................................................. 411
18.14.3 B3 BIP-8 Check ......................................................................................................................... 412
18.14.4 Signal Label C2 Byte Monitor .................................................................................................... 412
18.14.5 Path User Byte F2 Monitor ........................................................................................................ 413
18.14.6 Path User Byte F3 Monitor ........................................................................................................ 414
18.14.7 N1 Monitor ................................................................................................................................. 414
18.14.8 K3 Byte Monitor ......................................................................................................................... 415
18.14.9 AIS-P and RDI-P Detect ............................................................................................................ 415
18.14.10 REI-P Detect ........................................................................................................................... 416
18.14.11 Signal Degrade BER Algorithm ............................................................................................... 416
18.14.12 Signal Fail BER Algorithm ....................................................................................................... 417
18.14.13 POAC Drop ............................................................................................................................. 418
18.14.14 Insertion of AIS-P .................................................................................................................... 419
18.15 Transmit Direction (to SONET/SDH Line) ............................................................................................ 420
18.15.1 PATH Insertion Block ................................................................................................................ 420
18.15.2 Loss of Clock and Loss of Sync Detectors ................................................................................ 421
18.15.3 J1 Byte Insert ............................................................................................................................ 421
18.15.4 B3 BIP-8 Calculation and Insert ................................................................................................ 421
18.15.5 C2 Signal Label Byte Insert ....................................................................................................... 421
18.15.6 REI-P G1(7:4) Insert .................................................................................................................. 421
18.15.7 Path RDI (RDI-P) Insert ............................................................................................................. 422
18.15.8 F2 Byte Insert ............................................................................................................................ 422
18.15.9 H4 Insert Control ....................................................................................................................... 422
18.15.10 F3 Byte Insert .......................................................................................................................... 422
18.15.11 K3 Insert Control Parameters .................................................................................................. 422
18.15.12 N1 Insert Control Parameters .................................................................................................. 423
18.16 POAC Insert ......................................................................................................................................... 423
18.17 AIS Path Generation ............................................................................................................................. 424
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18 SPE Mapper Functional Description (continued)
Table of Contents (continued)
Figures
Page
Figure 30. SPE Mapper Block with Connections to External Pins and Other Blocks in the Device ..................... 399
Figure 31. Basic Functional Flow of the SPE Mapper Transmit Section .............................................................. 400
Figure 32. Basic Functional Flow of the SPE Mapper Receive Section ............................................................... 401
Figure 33. STS-1 NSMI Receive Operation ......................................................................................................... 405
Figure 34. STS-1 NSMI Transmit Operation ........................................................................................................ 406
Figure 35. Receive Direction Path Termination Block .......................................................................................... 407
Figure 36. Pointer Interpretation State Diagram................................................................................................... 408
Figure 37. Transmit Direction Path Insertion Block .............................................................................................. 420
Tables
Table 536.
Table 537.
Table 538.
Table 539.
Table 540.
Table 541.
Table 542.
Table 543.
Table 544.
Table 545.
Table 546.
Table 547.
Table 548.
Table 549.
Table 550.
Page
J1 Monitor .......................................................................................................................................... 412
STS Signal Label Defect Conditions ................................................................................................. 412
C2MON Processing ........................................................................................................................... 413
F2 Monitor ......................................................................................................................................... 414
F3 Monitor ......................................................................................................................................... 414
N1 Monitor ......................................................................................................................................... 414
K3 Monitor ......................................................................................................................................... 415
AIS-P and RDI-P Detect .................................................................................................................... 415
STS-1 P-REI Interpretation ................................................................................................................ 416
Signal Degrade Parameters .............................................................................................................. 417
Signal Fail Parameters ...................................................................................................................... 418
Path Overhead Byte Access .............................................................................................................. 419
RDI-P Defects for Enhanced RDI-P Mode ........................................................................................ 422
Path Overhead Byte Access—Transmit Direction ............................................................................. 423
TPOAC Control Bits .......................................................................................................................... 424
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18 SPE Mapper Functional Description (continued)
18.1 Introduction
This section describes the functions of the SPE mapper block.
The SPE mapper is highly configurable; it can operate in two different modes, as an AU-3/STS-1 mapper or as a
TUG-3 mapper. In both modes, it can map/demap data from/to either the VT mapper block, the M13 MUX/deMUX
block, the DS3 clear channel, or the DS3 loopback channel.
The SPE mapper supports numerous automatic monitoring functions. It can provide interrupts to the control system, or it can be operated in a polled mode.
Additionally, this block has a built-in auxiliary channel known as the path overhead access channel (POAC). This
channel is mainly used for path overhead insertion and drop functions.
18.2 Features
■
The SPE mapper accepts/delivers TUG-2 data from/to the VT mapper. The TUG-2 data is mapped/demapped
either to/from an AU-3/STS-1 signal for the North American digital systems or to/from a TUG-3 signal for the
European digital systems.
■
Flexibility down to TUG-2 level is provided for choosing which TUG-2s (between 1 and 7) are mapped into which
TUG-3s (between 1 and 3) for generating STM-1 signals. Similarly, any TUG-2s (up to 7) may be dropped/terminated from the 21 TUG-2s of an STM-1 signal.
■
The SPE mapper accepts/delivers DS3 data from/to the M13 MUX/deMUX. The DS3 data is mapped/demapped
either to/from an AU-3/STS-1 signal for the North American digital systems or to/from a TUG-3 signal for the
European digital systems.
■
The SPE mapper accepts/delivers a clear DS3 signal at 44.736 Mbits/s rate. The clear DS3 signal is mapped/
demapped essentially the same way as M13 signal described above.
■
The SPE mapper has a DS3 loopback circuit placed for the functions of demapping and remapping a DS3 signal.
It is particularly useful in cases where a DS3 signal mapped as an AU-3/STS-1 signal is needed to be remapped
as a TUG-3 signal or vice versa.
■
The SPE mapper supports a path overhead access channel more commonly known as the POAC channel.
Seven path overhead bytes namely J1, C2, F2, H4, F3, K3, and N1 may be inserted/dropped through this channel. This channel works as the master which means that this channel provides a clock in both transmit and
receive directions and POH data may be inserted by the user on the transmit side or dropped by the block in the
receive side.
■
Path overhead byte B3 (BIP error) generation/detection and programmable BIP-2 bit error rate insertion.
■
Programmable clear on read/clear on write registers.
■
Signal fail and signal degrade indicators available to report bit error rates above a certain programmable threshold.
■
Capable of detecting/inserting alarm indication signals (AIS), remote defect indication signals (RDI) and remote
error indication signals (REI).
■
Numerous monitoring functions provided on all the TUG-3 path overhead bytes.
■
Supports unidirectional path switch ring (UPSR) applications.
■
N1 tandem connection support is provided.
■
Complies with GR-253-CORE, T1.105, ITU-T G.707, ITU-T G.831, G.783, ETS 300 417-1-1.
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18 SPE Mapper Functional Description (continued)
18.3 SPE Mapper Functional Block Diagrams
MICRO INTERFACE
MISC SIGNALS
RPOAC
DATA, CLK, SYNC
TRANSMIT
PATH OVERHEAD
INSERT
POAC CHANNEL
TPOAC
DATA, CLK, SYNC
SPE MAPPER
TRANSMIT
SECTION
TRANSMIT
TELECOM
BUS
TMUX
TRANSMIT
SECTION
REI
RDI
RECEIVE
PATH OVERHEAD
EXTRACT
POAC CHANNEL
TRANSMIT
DATA, CLK,
CONTROL
M13
MAPPER
TRANSMIT
SECTION
RECEIVE
DATA, CLK,
CONTROL
M13
MAPPER
RECEIVE
SECTION
DS3
LOOPBACK
DS3DATAINCLK
DS3POSDATAIN
TMUX
RECEIVE
SECTION
SPE MAPPER
RECEIVE
SECTION
RECEIVE
TELECOM
BUS
DS3NEGDATAIN
PHASEDETUP
DS3
CLEAR INPUT
TRANSMIT
PINS
PHASEDETDOWN
AUTO_AIS
DS3NEGDATAOUT
DS3POSDATAOUT
DS3DATAOUTCLK
TRANSMIT
CLK, DATA
RECEIVE
CLK, DATA
VT
MAPPER
TRANSMIT
SECTION
DS3
CLEAR INPUT
RECEIVE
PINS
AUTO_AIS,
RDI, REI
VT
MAPPER
RECEIVE
SECTION
5-9065(F)
Figure 30. SPE Mapper Block with Connections to External Pins and Other Blocks in the Devic e
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18 SPE Mapper Functional Description (continued)
TO/FROM TMUX TRANSMIT SIDE
TELECOM BUS DATA[7:0], CLOCK, PARITY, SYNC (19.44 MHz OR 6.48 MHz)
51.84 MHz CLOCK FROM TMUX
51.84 MHz CLOCK, CONTROL FROM TMUX
STS3_TIMESLOT
TU11_TU12
TUG-3 OR AU-3
OUTPUT (87 x 9 bytes)
CONTROL CIRCUITRY
TUG2_NO[2:0]
TUG3_NO[1:0]
AU3_TUG3
VT_DS3
MPUCLK
87 x 9 bytes
MICROINTERFACE
AU3_TUG3
MUX
87 x 9 bytes
AU3_TUG3
AU-3 MAPPER
ADD 2 COLUMNS
OF FIXED STUFFING
VT_DS3
TUG-2
FIFO
MUX
C-3
84 x 9 bytes
VT_DS3
DS3_SRC_TYPE
TUG-3 MAPPER
ADD 1 COLUMN
OF FIXED STUFFING &
TU-3 PTR BYTES
AU3_TUG3
85 x 9 bytes
DS3
MAPPED AS
CONTAINER C-3
VT_DS3
87 x 9 bytes
84 x 9
bytes
PATH
OVERHEAD
INSERTION
AU3_TUG3
VT_DS3
84 x 9 bytes
VT_DS3
DS3 INPUT CONTROL &
SERIAL-TO-PARALLEL
CONVERSION
TUG-2
INPUT
CONTROL
VT_DS3
TELECOM BUS
CLOCK
TDS3_BIPOLAR
M13
MAPPER
TX_POACINH
TX_POACDATA
TX_POACSYNC
SYNC_V1
TUG-2_DATA
CLK_6MHz
VT/TU
MAPPER
TX_POACCLKO
LOOPBACK_DATA
DS3 POS_DATA
DS3 NEG_DATA
DS3 _EXT_CLK
LOOPBACK_CLK
LOOPBACK_CLK_EN
B3ZS
DECODE
DS3 CLK
MUX
DS3 CLK_EN
MUX
DS3 DATA
DS3CLK
DS3_SRC_TYPE
PATH OVERHEAD
INSERT
POAC CHANNEL
VT_DS3
5-9066(F)
Figure 31. Basic Functional Flow of the SPE Mapper Transmit Section
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18 SPE Mapper Functional Description (continued)
FROM TMUX RECEIVE SIDE
TELECOM BUS DATA[7:0], CLOCK, PARITY, SYNC (19.44 MHz OR 6.48 MHz)
51.84 MHz CLOCK, CONTROL FROM TMUX
AUTO AIS SIGNAL FROM TMUX
STS3_TIMESLOT
TU11_TU12
TUG-3 OR AU-3
INPUT (87 x 9 BYTES)
CONTROL CIRCUITRY
TUG2_NO[2:0]
87 x 9 bytes
87 x 9 bytes
TUG-3 DEMAPPER
REMOVE 1 COLUMN
OF FIXED STUFFING &
TU-3 PTR BYTES
AU-3 DEMAPPER
REMOVE 2 COLUMNS
OF FIXED STUFFING
C-3
DE MAPPED AS
AS DS3
POINTER
INTERPRETER
C-3
TELECOM BUS
CLOCK
DS3
84 x 9
bytes
M13
DEMAPPER
RX_POACSINH
RX_POACDINH
RX_POACCINH
RX_POACSYNCO
RX_POACCLKO
PATH OVERHEAD
EXTRACT
POAC CHANNEL
TUG-2
VT_DS3
VT_DS3
RX_POACDATAO
DS3 _LOOPBACK_CLK
LOOPBACK_CLK_EN
DS3 _LOOPBACK_DATA
PHASE_DET_DOWN
DS3 _EXT_CLK
DS3 POS_DATA
PHASE_DET_UP
DS3_BIPOLAR
TUG3MPR_DS3_AIS
DS3 DATA
DS3 CLK
DS3 CLK_EN
VT_DS3
DS3 NEG_DATA
84 x 9 bytes
PATH
OVERHEAD
EXTRACTION/
TERMINATION
DS3 OUTPUT CONTROL &
PARALLEL-TO-SERIAL
CONVERSION
DS3_OUT_TYPE
B3ZS
ENCODER
85 x 9 bytes
VC-3
FIFO
DS3CLK
VT_DS3
AU3_TUG3
MUX
VT_DS3
VT_DS3
85 x 9 bytes
85 x 9 bytes
VT_DS3
AU3_TUG3
TUG-2
OUTPUT
CONTROL
VT_DS3
SYNC_V1
AU3_TUG3
VT_DS3
TUG-2_DATA
MICRO
INTERFACE
AU3_TUG3
CLK_6MHz
MPUCLK
TUG3_NO[1:0]
VT/TU
DEMAPPER
5-9067(F)r.1
Figure 32. Basic Functional Flow of the SPE Mapper Receive Section
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18 SPE Mapper Functional Description (continued)
The SPE mapper basically interfaces to three other blocks within the Super Mapper device:
■
The VT mapper.
■
The M13 MUX/deMUX.
■
The TMUX.
The interface between the SPE mapper and the VT mapper consists of clock, parallel data, sync, and control type
interfaces and is completely internal to the Super Mapper device.
The interface between the SPE mapper and the M13 MUX/deMUX consists of a serial clock, serial data, and clock
enable type interface and is also completely internal to the Super Mapper device.
The interface between the SPE mapper and the TMUX consists of the telecom bus and every signal that flows
between these two blocks is also brought in/out through external device pins connected to the telecom bus.
As outlined in the features, the SPE mapper can map/demap seven TUG-2 or a DS3 to/from AU3/STS-1 or TUG-3.
Each TUG-2 assembled/disassembled by the VT mapper consist of three TU-12 (E1) or four TU-11 (DS1) virtual
tributaries.
The following is a brief description of the supported standards based mappings. For greater details, please refer to
the appropriate standard.
18.4 TUG-2 to AU-3/STS-1 SPE Mapping (Used in North American Systems)
A TUG-2 payload capacity, which is 9 rows by 12 columns or 108 bytes, may contain four TU-11s or three TU-12s
byte interleavingly multiplexed.
The 27-byte capacity of a TU-11 is equivalent to three-column capacity in an STS-1 frame of 125 µs. Four TU-11s
are byte interleavingly multiplexed into a TUG-2 payload capacity which has a capacity of 12 columns. Seven
TUG-2s can then be byte interleavingly multiplexed into the payload capacity of a VC-3. The VC-3 has a structure
of 9 rows by 85 columns: one column is VC-3 path overhead and the other 84 columns are seven TUG-2s evenly
distributed within the payload. Two columns of fixed stuffing are then added to the payload to build the complete
STS-1 SPE frame of 9 rows by 87 columns.
The 36-byte capacity of a TU-12 is equivalent to four-column capacity in an STS-1 frame of 125 µs. Three TU-12s
are byte interleavingly multiplexed into a TUG-2 payload capacity which has a capacity of 12 columns. Seven
TUG-2s can then be byte interleavingly multiplexed into the payload capacity of a VC-3. The VC-3 has a structure
of 9 rows by 85 columns: one column is VC-3 path overhead and the other 84 columns are seven TUG-2s evenly
distributed within the payload. Two columns of fixed stuffing are then added to the payload to build the complete
STS-1 SPE frame of nine rows by 87 columns.
18.5 TUG-2 to TUG-3 Mapping (Used in ITU/ETSI Standard Based Systems)
A TUG-2 payload capacity, which is nine rows by 12 columns or 108 bytes, may contain four TU-11s or three
TU-12s byte interleavingly multiplexed.
The 27-byte capacity of a TU-11 is equivalent to three-column capacity in an STM-1 frame of 125 µs. Four TU-11s
are byte interleavingly multiplexed into a TUG-2 payload capacity which has a capacity of 12 columns. Seven
TUG-2s can then be byte interleavingly multiplexed into the payload capacity of a TUG-3. The TUG-3 has a structure of nine rows by 86 columns: one column of NPI (null pointer indication) plus fixed stuffing bytes, one column of
fixed stuffing and the other 84 columns are seven TUG-2s evenly distributed within the TUG-3 payload.
The 36-byte capacity of a TU-12 is equivalent to four-column capacity in an STM-1 frame of 125 µs. Three TU-12s
are byte interleaving multiplexed into a TUG-2 payload capacity which has a capacity of 12 columns. Seven
TUG-2s can then be byte interleavingly multiplexed into the payload capacity of a TUG-3.
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18 SPE Mapper Functional Description (continued)
The TUG-3 has a structure of 9 rows by 86 columns: one column of null pointer indication (NPI) plus fixed stuffing
bytes, one column of fixed stuffing, and the other 84 columns are seven TUG-2s evenly distributed within the
TUG-3 payload.
18.6 DS3 to AU-3/STS-1 SPE Mapping (Used in Telcordia/ANSI Standards Based Systems)
DS3 is an asynchronous signal with a rate of 44.736 Mbits/s. This payload with other information bits (total
3.648 Mbits/s) is used to form the container C-3 (48.384 Mbits/s) which occupies 84 columns of an STS-1 frame.
One column of path overhead bytes is added to the C-3 container to make a VC-3. Finally, two columns of fixed
stuffing (column numbers 30 and 59) are added to VC-3 to form an STS-1 SPE (87 columns).
Stuffing (S bits) is used to rate adapt the DS3 payload to the SPE. Nine stuffing S bits are included in the C-3 container. When no stuffing is used, the STS-1 SPE can accommodate a rate of 44.712 Mbits/s. When all nine stuffing
S bits are used, the STS-1 SPE can accommodate 44.784 Mbits/s. Since the DS3 coming from the M13 has a
nominal rate of 44.736 Mbits/s, stuffing is used for every third row of an STS-1 frame; or in other words, three S bits
per 125 µs are used for stuffing to achieve the DS3 rate.
18.7 DS3 to TUG-3 Mapping (Used in ITU/ETSI Standard Based Systems)
DS3 is an asynchronous signal with a rate of 44.736 Mbits/s. This payload with other information bits (total
3.648 Mbits/s) is used to form the container C-3 (48.384 Mbits/s) which occupies 84 columns of an STM-1 frame.
One column of path overhead bytes are added to the C-3 container to make a VC-3 (85 columns). Now a TUG-3
signal consists of 86 columns by 9 rows, therefore 3 bytes of TU-3 pointer (H1, H2, and H3 bytes) are placed on
rows 1 through 3 of the newly added column and fixed stuffing bits are placed on the remaining rows. Thus, a
TUG-3 frame of 9 rows by 86 columns is formed. Three TUG-3s are byte interleavingly multiplexed by the TMUX to
form an STM-1 signal.
Stuffing (S bits) is used to rate adapt the DS3 payload to the TUG-3. Nine stuffing Sbits are included in the C-3
container. When no stuffing is used, the TUG-3 payload can accommodate a rate of 44.712 Mbits/s. When all nine
stuffing S bits are used, the TUG-3 payload can accommodate 44.784 Mbits/s. Since the DS3 coming from the
M13 has a nominal rate of 44.736 Mbits/s, stuffing is used for every third row of a TUG-3 frame; or in other words,
three S bits per 125 µs are used for stuffing to achieve the DS3 rate.
18.8 SPE Mapper Basic Configuration
SPE mapper configuration programming is provided through registers SPE_MAP_CTL1—SPE_MAP_CTL3
(Table 153 on page 140).
When mapping to a STS-3/STM-1 rate, the SPE mapper requires configuration to select one of the three time slots
on the telecom bus that interfaces the TMUX. The register bits for selection are SPE_TSTS3TMSLOT[1:0] and
SPE_RSTS3TMSLOT[1:0] (Table 153).
Selection of AU-3/STS-1 or TUG-3 mapping is provided through bits SPE_T_AU3_TUG3 and SPE_R_AU3_TUG3
(Table 153).
TUG-2 (virtual tributary) or DS3 data is selected with bits, SPE_T_AU3_TUG3 and SPE_R_AU3_TUG3.
18.9 DS3 Configuration
The SPE mapper is configured to select the source and destination of the DS3 signals. The configuration is determined with register bits, SPE_TDS3SRCTYP[1:0] and SPE_RDS3OUTTYP[1:0] (Table 153). DS3 source/destination may be selected as loopback, external device pins, or M13.
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18 SPE Mapper Functional Description (continued)
18.9.1 DS3 M13
The SPE mapper is configured to/from the M13 MUX/deMUX as the source/destination of data by setting bits,
SPE_TDS3SRCTYP[1:0] = SPE_RDS3OUTTYP[1:0] = 00 or 01.
18.9.2 DS3 Loopback Channel
The DS3 loopback circuit is placed in the SPE mapper to allow demapping and remapping of a DS3 signal.
When SPE_TDS3SRCTYP[1:0] = SPE_RDS3OUTTYP[1:0] = 10, the SPE mapper extracts the asynchronous DS3
data and clock from the received payload. The recovered DS3 is looped back to the transmit path and either
mapped as AU-3/STS-1 SPE signal for the North American digital systems or mapped as TUG-3 for the European
digital systems. It is particularly useful in cases where a DS3 signal mapped as an AU-3/STS-1 signal is needed to
be remapped as a TUG-3 signal or vice versa.
18.9.3 DS3 Clear Channel from External Pins
The SPE mapper is configured for a DS3 signal at 44.736 MHz rate from external device pins by setting
SPE_TDS3SRCTYP[1:0] = SPE_RDS3OUTTYP[1:0] = 11.
The DS3 data can either be unipolar or bipolar. Unipolar data and clock is selected (device pins DS3POSDATAIN,
DS3DATAINCLK, DS3POSDATAOUT, and DS3DATAOUTCLK (pins M22, J22, R22, and N22, respectively)) when
bits SPE_TDS3_BIPOLAR and SPE_RDS3_BIPOLAR = 0 (Table 153). Bipolar data and clock is selected (device
pins DS3POSDATAIN, DS3NEGDATAIN, DS3DATAINCLK, DS3POSDATAOUT, DS3NEGDATAOUT, and
DS3DATAOUTCLK (pins M22, K22, J22, R22, P22, and N22, respectively)) when bits SPE_TDS3_BIPOLAR and
SPE_RDS3_BIPOLAR = 1.
When bipolar data is selected for the transmit path (SPE_TDS3_BIPOLAR = 1), the data received from the external
pins is expected to be B3ZS encoded. A B3ZS decoder is used to recover the DS3 data prior to being mapped into
a container.
The B3ZS decoder also checks for bipolar coding violations. The SPE mapper contains a counter that increments
on each occurrence of a received bipolar coding violation (BPV). It also monitors the occurrence of excessive zeros
(EXZ), which is defined as any zero string length equal to or greater than three. These are part of the performance
monitoring counters that can be sampled and simultaneously reset. Their last sampled values are available through
SPE_BIPOL_CNT[23:0] and SPE_EXZ_CNT[23:0] (Table 160).
When bipolar data is selected for the receive path (SPE_RDS3_BIPOLAR = 1), the data out from the external pins
will be B3ZS encoded. A single bipolar violation may be inserted in the data when SPE_BIPOL_ERR is asserted
(Table 145).
The clock edge for sampling the transmit path data (device pin DS3DATAINCLK (pin J22)) is selected with
SPE_TDS3CLK_EDGE (Table 153).
18.10 Phase Detector for External DS3 PLL
The receive section of the SPE mapper has a phase detector circuit built inside the device. This phase detector circuit generates the necessary up and down signals (device pins PHASEDETUP and PHASEDETDOWN (pins V22
and U22, respectively)) for an external phase-lock loop (PLL) circuit to generate a smooth DS3 clock at
44.736 MHz rate.
The logic sense of the phase detector up and down outputs may be inverted with bits SPE_PHDETUP_INV
(Table 153) and SPE_PHDETDN_INV, respectively.
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18 SPE Mapper Functional Description (continued)
18.11 Serial STS-1 SPE Channel (NSMI)
The SPE mapper has the capability of accepting a clear serial STS-1 SPE signal at 51.84 MHz rate. The intent is to
map/demap the network serial multiplexed interface (NSMI) interface data.
The receive section of the SPE mapper outputs a serial data at 51.84 MHz rate, a clock enable signal inhibited during overhead insertion times, and a sync signal whose position within the STS-1 frame is programmable to a certain extent (is programmable to occupy any STS-1 column position (numbers 0—89) within a fixed row (# 8)),
through bits SPE_R_NSMI_BIT[2:0] (Table 153) and SPE_R_NSMI_COL[6:0] (Table 153).
The transmit section of the SPE mapper inputs serial data at 51.84 MHz rate, outputs a clock enable signal inhibited during overhead insertion times and a sync signal whose position within the STS-1 frame is programmable to a
certain extent (is programmable to occupy any STS-1 column position (numbers 0—89) within a fixed row (#8)),
through bits, SPE_T_NSMI_BIT[2:0] and SPE_T_NSMI_COL[6:0] (Table 153).
The STS-1 SPE data is then mapped as AU-3 signal for the North American digital systems.
LINE_RXCLK29
RXDATAEN
VARIABLE
RXSYNC (OPTIONAL)
LINE_RXDATA29
UNUSED
0786(F)(F)
Figure 33. STS-1 NSMI Receive Operation
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18 SPE Mapper Functional Description (continued)
LINE_TXCLK29
TXDATAEN
VARIABLE
TXSYNC (OPTIONAL)
UNUSED
LINE_TXDATA29
0785(F)(F)
Figure 34. STS-1 NSMI Transmit Operation
18.12 TMUX Interface to the SPE Mapper
The SPE mapper sends/receives data mapped as an AU-3/STS-1 SPE signal or as a TUG-3 signal to/from the
TMUX. The interface required for this exchange of data, clock, and control signals is called the high-speed telecom
bus. The high-speed telecom bus is accessible from external pins so that the TMUX can send/receive data to/from
other external Super Mapper devices in the system. The TMUX can byte interleavingly multiplex three STS-1s or
three TUG-3 signals, receiving through the telecom bus, to form one STS-3 or STM-1 signal, respectively.
The high-speed telecom bus consists of a byte-wide data bus running at 19.44 Mbits/s for STS-3/STM-1 mode, or
6.48 Mbits/s for STS-1 stand-alone mode. It also consists of a parity bit line, a clock line which is 19.44 MHz or
6.48 MHz depending on STS-3/STM-1 or STS-1 mode, respectively; one sync line and two sync control lines. The
sync line outputs the J0, J1, and V1 time slot signals of the STS-3/STM-1 frame and the two sync control signals
distinguishes between the three sync bytes. The sync signals are used to synchronize the byte counters in the SPE
mapper, and the information is also passed along to the VT mapper for synchronizing the V1 counters.
The TMUX also provides through the external pins one 51.84 MHz serial clock and one clock control signal which
synchronizes the 51.84 MHz to the J0 byte of the STS-3/STM-1 frame. This serial clock is required for the M13
MUX/deMUX because of its serial mode of working.
In the case where the SPE mapper has to drive the telecom bus in the transmit side, there is a 3-state control signal (active-high) which is an output from the SPE mapper. This signal enables the 3-state drivers on the high-speed
telecom bus at the time period when the clock is low.
18.13 PATH Termination Block
The path termination block of the SPE mapper is shown below. The block consists of a pointer interpreter which
monitors the TU-3 pointer bytes H1, H2, and H3, and interprets the beginning of the path overhead bytes for the
TUG-3 frames. After monitoring and terminating the path overhead bytes, the TUG-3 payload is passed on to the
output blocks.
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18 SPE Mapper Functional Description (continued)
TUG-2 DATA
TUG-3 DATA
H1, H2, H3
MONITOR
POINTER
INTERPRETER
VC-3 DATA
INSERT
AIS-P
F2
F2
MONITOR
F3
F3
MONITOR
C2
C2
MONITOR
J1
N1
J1
MONITOR
N1
MONITOR
B3
K3
B3
BIP N
CHECK
POAC DATA
K3
APS
MONITOR
POAC
DROP
G1
AIS-P
RDI-P
DETECT
G1
G1
REI-L
DETECT
G1
REI
COUNTER
PATH
TERMINATE
MUX
PAYLOAD DATA TO OUTPUT BLOCKS
5-9068(F)
Figure 35. Receive Direction Path Termination Block
18.13.1 Pointer Interpretation Block
The TUG-3 pointer interpreter logic block performs all necessary functions to support TU-3 pointer interpretation.
The following features are implemented:
■
The pointer interpreter consists of the following states:
— LOP-TU3—loss of pointer
— AIS-TU3—TUG-3-AIS (all ones in H1 and H2)
— NDF—NDF enabled (1001, 0001, 1101, 1011, 1000)
— NORM—normal (disabled NDF, normal pointer)
— INC—increment (inverted I bits)
— DEC—decrement (inverted D bits)
The SPE mapper includes event or change of state indicators for pointer interpreter states except the NORM state.
States NDF, DEC, and INC are reported with event status bits SPE_RNDFE ( Table 146 on page134 ),
SPE_RDECE (Table 146), and SPE_RINCE (Table 146), respectively. States AIS and LOP are reported with
change of state (delta) status bits SPE_RAISD (Table 146) and SPE_RLOPD (Table 146), respectively. Interrupts
for each event or delta state may be masked with bits SPE_RNDFM, SPE_RDECM, SPE_RINCM, SPE_RAISM,
and SPE_RLOPM (all in Table 147 on page136 ).
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18 SPE Mapper Functional Description (continued)
NDF ENABLE
INC
DEC
3 NEW POINTERS
3 ANY
POINTERS
3 ANY
POINTERS
NDF
DECREMENT
INDICATION ENABLE
INCREMENT
INDICATION
3 NEW POINTERS
3 NEW POINTERS
NORM
3 ANY POINTERS
NDF
NDF ENABLE
NDF
ENABLE
8 INVALID
POINTERS
FROM ALL STATES
8 INVALID POINTERS*
FROM ALL STATES
3 AIS INDICATIONS
NDF
ENABLE
3 NEW POINTERS
LOP
8 INVALID POINTERS
AIS
8 NDF ENABLE
5-9007(F)
* This state diagram is based on the ETS 417-1-1 pointer interpretation state diagram (Figure B.1). Transitions of eight invalid pointers from the
INC, DEC, and NDF states into the LOP state have been added.
Figure 36. Pointer Interpretation State Diagram
■
The pointer interpreter transitions into the LOP-TU3 state based on the following conditions:
— Continuous NDF. If NDF (1001, 0001, 1101, 1011, 1000) is received for the number of consecutive frames
(determined by the value programmed in bits SPE_CNTDLOPCNT[1:0] ( Table 149)), then LOP-TU3 is declared.
— Invalid pointer values. If the number of consecutive frames (determined by the value programmed in
SPE_CNTDLOPCNT[1:0]) are received with a pointer that is not a normal value, NDF, AIS-TU3, increment, or
decrement, then LOP-TU3 is declared.
■
The pointer interpreter transitions out of the LOP-TU3 state based on the following conditions:
— Following three consecutive frames with all ones in the H1 and H2 bytes the pointer interpreter transitions from
the LOP-TU3 state into the AIS-TU3 state.
— Following three new consecutive, consistent, valid pointers the pointer interpreter transitions from the
LOP-TU3 state into the NORM state.
— The pointer interpreter will not transition from the LOP-TU3 state into the NDF state.
■
The pointer interpreter transitions into the AIS-TU3 state based on the following conditions:
— Following three consecutive frames with all ones in the H1 and H2 bytes AIS-TU3 is declared.
■
The pointer interpreter transitions out of the AIS-TU3 state based on the following conditions:
— Following three new consecutive, consistent, valid pointers the pointer interpreter transitions from the AIS-TU3
state into the NORM state.
— Following the number of consecutive invalid pointers (determined by the value programmed in
SPE_CNTDLOPCNT[1:0]) the pointer interpreter transitions from the AIS-TU3 state into the LOP-TU3 state.
— If NDF is enabled on the incoming H1 and H2 bytes, the pointer interpreter transitions from the AIS-TU3 state
into the NDF state.
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18 SPE Mapper Functional Description (continued)
■
The pointer interpreter transitions into the NDF state based on the following conditions:
— If NDF is enabled on the incoming H1 and H2 bytes, the pointer interpreter transitions from the NORM, NDF,
AIS, INC, and DEC states into the NDF state.
■
The pointer interpreter transitions out of the NDF state based on the following conditions:
— Continuous NDF. If NDF (1001, 0001, 1101, 1011, 1000) is received for the number of consecutive frames
(determined by the value programmed in SPE_CNTDLOPCNT[1:0] (Table 149)), the pointer interpreter transitions from the NDF state into the LOP-TU3 state.
— Following any three consecutive, consistent, and valid pointers, the pointer interpreter transitions from the NDF
state into the NORM state.
— Following three consecutive frames with all ones in the H1 and H2 bytes, the pointer interpreter transitions from
the NDF state into the AIS-TU3 state.
— Following three new, consecutive, consistent, and valid pointers, the pointer interpreter transitions from the
NDF state into the NORM state.
— Following the number of consecutive invalid pointers (determined by the value programmed in
SPE_CNTDLOPCNT[1:0]), the pointer interpreter transitions from the NDF state into the LOP-TU3 state.
■
The pointer interpreter transitions into the NORM state based on the following conditions:
— Following three new consecutive, consistent, and valid pointers, the pointer interpreter transitions into the
NORM state.
— Following any three consecutive, consistent, and valid pointers, the pointer interpreter transitions into the
NORM state. i.e., transitioning from the INC, DEC, and NDF states.
■
The pointer interpreter transitions out of the NORM state based on the following conditions:
— Following the number of consecutive invalid pointers (determined by the value programmed in
SPE_CNTDLOPCNT[1:0]), the pointer interpreter transitions from the NORM state into the LOP-TU3 state.
— If NDF is enabled on the incoming H1 and H2 bytes, the pointer interpreter transitions from the NORM state
into the NDF state.
— Following three consecutive frames with all ones in the H1 and H2 bytes, the pointer interpreter transitions from
the NORM state into the AIS-TU3 state.
— When operating in the 8 of 10 mode (SPE_8ORMAJORITY = 1 ( Table 149)), if 8 of the 10 I and D bits are
correct for a pointer decrement on the incoming H1 and H2 bytes the pointer interpreter transitions from the
NORM state into the DEC state. Otherwise, if 3 of the 5 I bits and 3 of the 5 D bits are correct for a pointer
decrement on the incoming H1 and H2 bytes, the pointer interpreter transitions from the NORM state into the
DEC state.
— When operating in the 8 of 10 mode (SPE_8ORMAJORITY = 1), if 8 of the 10 I and D bits are correct for a
pointer increment on the incoming H1 and H2 bytes, the pointer interpreter transitions from the NORM state
into the INC state. Otherwise, if 3 of the 5 I bits and 3 of the 5 D bits are correct for a pointer increment on the
incoming H1 and H2 bytes, the pointer interpreter transitions from the NORM state into the INC state.
■
The pointer interpreter transitions into the INC state based on the following conditions:
— When operating in the 8 of 10 mode (SPE_8ORMAJORITY = 1), if 8 of the 10 I and D bits are correct for a
pointer increment on the incoming H1 and H2 bytes the pointer interpreter transitions into the INC state. Otherwise, if 3 of the 5 I bits and 3 of the 5 D bits are correct for a pointer increment on the incoming H1 and H2
bytes, the pointer interpreter transitions into the INC state.
■
The pointer interpreter transitions out of the INC state based on the following conditions:
— If NDF is enabled on the incoming H1 and H2 bytes, the pointer interpreter transitions from the INC state into
the NDF state.
— Following three consecutive frames with all ones in the H1 and H2 bytes, the pointer interpreter transitions from
the INC state into the AIS-TU3 state.
— Following three new consecutive, consistent, and valid pointers, the pointer interpreter transitions from the INC
state into the NORM state.
— Following any three consecutive, consistent, and valid pointers, the pointer interpreter transitions from the INC
state into the NORM state.
— Following the number of consecutive invalid pointers (determined by the value programmed in
SPE_CNTDLOPCNT[1:0] (Table 149)), the pointer interpreter transitions from the INC state into the LOP-TU3
state.
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Preliminary Data Sheet
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18 SPE Mapper Functional Description (continued)
■
■
The pointer interpreter transitions into the DEC state based on the following conditions:
— When operating in the 8 of 10 mode (SPE_8ORMAJORITY = 1 ( Table 149)), if 8 of the 10 I and D bits are
correct for a pointer decrement on the incoming H1 and H2 bytes, the pointer interpreter transitions into the
DEC state. Otherwise, if 3 of the 5 I bits and 3 of the 5 D bits are correct for a pointer decrement on the incoming
H1 and H2 bytes the pointer interpreter transitions into the DEC state.
The pointer interpreter transitions out of the DEC state based on the following conditions:
— If NDF is enabled on the incoming H1 and H2 bytes, the pointer interpreter transitions from the DEC state into
the NDF state.
— Following three consecutive frames with all ones in the H1 and H2 bytes, the pointer interpreter transitions from
the DEC state into the AIS-TU3 state.
— Following three new consecutive, consistent, and valid pointers, the pointer interpreter transitions from the
DEC state into the NORM state.
— Following any three consecutive, consistent, and valid pointers, the pointer interpreter transitions from the DEC
state into the NORM state.
— Following the number of consecutive invalid pointers (determined by the value programmed in
SPE_CNTDLOPCNT[1:0]), the pointer interpreter transitions from the DEC state into the LOP-TU3 state.
■
Pointer increments and decrements will be counted and presented to the microprocessor as follows:
— Pointer increments and decrements will be monitored and counted internally.
— The internal and latched counts will be forced to 0x00 if device pin AUTO_AIS (AC6, AE6, and AD6) = 1 (from
TMUX), bit SPE_RLOP = 1 (Table 148), or bit SPE_RAIS = 1 (Table 148).
— Latched counts, SPE_RPTR_INC[10:0] (Table 161) and SPE_RPTR_DEC[10:0] (Table 161), will be updated
coincident with the end of a performance monitor interval.
— The internal counters will reset to 0x00 coincident with the end of a performance monitor interval.
— If SMPR_SAT_ROLLOVER = 1 (Table 67), the internal running counts will hold at their maximum value. Otherwise, the counts will roll over.
— However, increment and decrement event indications should be ignored during LOP state.
■
LOP-TU3 (TU-3 path LOP) and AIS-TU3 (TU-3 path AIS) will be detected and reported to the microprocessor.
Both the LOP-TU3 and AIS-TU3 conditions will contribute to the AUTO AIS control signal from the SPE mapper
to the VT mapper. Any change in state of SPE_RLOP ( Table 148) or SPE_RAIS (Table 148) will be reported to
the microprocessor via SPE_RLOPD (Table 146) and SPE_RAISD (Table 146). Unless the appropriate mask bit
is set (SPE_RLOPM/SPE_RAISM (Table 147)), SPE_RLOPD = 1 or SPE_RAISD = 1 will generate an interrupt.
■
The current TU-3 pointer value is stored in SPE_STORED_PTR[9:0] ( Table 161).
18.14 SPE Mapper Receive Direction Requirements
All monitoring functions supported by the SPE mapper in the receive direction are summarized here:
■
Loss of CLOCK and loss of sync monitors
■
J1 monitor
■
B3 BIP-8 check
■
C2 signal label monitor
■
F2 monitor
■
F3 monitor
■
N1 monitor
■
K3 monitor
■
AIS-P and RDI-P detect
■
REI-P detect
■
Signal degrade BER algorithm
■
Signal fail BER algorithm
■
Path overhead access channel (POAC) drop
■
Insertion of AIS-P
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TMXF28155/51 Super Mapper
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18 SPE Mapper Functional Description (continued)
Whenever the continuous N-times detect signals are defined, they require not only that the monitored signal be
consistent for N consecutive frames, but also that the frame bytes be error free for all N frames before the status
can be updated. If there are any errors in the framing pattern, then the consecutive N-times detection counters
must be reset to 0. N can range from 1 to 15. Programming a CNTD block with any value less than 1 will set the
CNTD to 1 time detect.
18.14.1 Loss of Clock and Loss of Sync Monitors
The SPE mapper detects and reports loss of the input clocks state for RLSCLK (pin V4) (19 MHz clock) in bit
SPE_RLSLOC (Table 148 on page 137), RLSC52 (pin AC2) (52 MHz clock) in bit SPE_RC52LOC (Table 148), and
DS3DATAINCLK (pin J22) (DS3 external clock) in bit SPE_RDS3LOC (Table 148), as determined by stuck high or
stuck low for time T. The detection time T will be greater than 10 µs but less than 125 µs. The function uses the
microprocessor clock as its reference. The device will report changes in the states using bits, SPE_RLSLOCD
(Table 146 on page 134), SPE_RC52LOCD (Table 146), and SPE_RDS3LOCD (Table 146); interrupt mask bits
SPE_RLSLOCM (Table 147), SPE_RC52LOCM (Table 147), and SPE_RDS3LOCM (Table 147 on page136 ),
respectively.
The SPE mapper will detect loss-of-sync conditions for the telecom bus sync signals. The states are reported in the
bits, SPE_RSY52LOS (Table 148), SPE_RJ0J1V1LOS (Table 148), SPE_RSPELOS (Table 148), and
SPE_RV1LOS (Table 148). The device will report changes in the states in bits SPE_RSY52LOSD (Table 146),
SPE_RJ0J1V1LOSD (Table 146), SPE_RSPELOSD (Table 146), SPE_RV1LOSD (Table 146); interrupt mask bits
SPE_RSY52LOSM (Table 147), SPE_RJ0J1V1LOSM (Table 147), SPE_RSPELOSM (Table 147), and
SPE_RV1LOSM (Table 147), respectively.
18.14.2 J1 Monitor
J1 (path trace) monitoring has six different monitoring modes controlled by bits SPE_J1MONMODE[2:0]
(Table 149):
■
SPE_J1MONMODE[2:0] = 000: the SPE mapper will latch the value of the J1 byte every frame for a total
64 bytes in SPE_RJ1DMON[1—64][7:0] (Table 162). The SPE mapper compares the incoming J1 byte with the
next expected value (the expected value is obtained by cycling through the previous stored 64 received bytes in
round-robin fashion) and setting the path trace identifier state bit, SPE_RTIM (Table 148), if different. Any change
in state is reported in bit, SPE_RTIMD (Table 146), using interrupt mask bit SPE_RTIMM (Table 147). CRC is not
checked by the hardware.
■
SPE_J1MONMODE[2:0] = 001: this is the SONET framing mode. The hardware looks for 0x0D and then the
0x0DA characters to indicate that the next byte is the first byte of the path trace message. The J1 byte message
is continuously written into SPE_RJ1DMON[1—64][7:0] with the first byte residing at the first address. If any
received byte does not match the previously received byte for its location, then the state bit SPE_RTIM is set.
Any change in state is reported in bit SPE_RTIMD, using interrupt mask bit SPE_RTIMM.
■
SPE_J1MONMODE[2:0] = 010: this is the SDH framing mode. The hardware looks for the byte with the most significant bit (MSB) set to one, which indicates that the next byte is the second byte of the message. The rest of
operation is the same as in SONET framing mode.
■
SPE_J1MONMODE[2:0] = 011: a new J1 byte (SPE_RJ1DMON[1][7:0]) will be detected after a number of consecutive consistent occurrences (SPE_CNTDJ1[3:0] (Table 150)) of a new pattern in the J1 overhead byte. Any
changes to this byte is reported in bit SPE_RTIMD, using interrupt mask bit SPE_RTIMM. The delta bit in this
mode indicates a change in state for the J1 byte, and the bit SPE_RTIM is not used.
■
SPE_J1MONMODE[2:0] = 100: the user will program the 64 expected values of J1 in registers,
SPE_RJ1DEXP[1—64][7:0] (Table 164), in SONET framing mode, where the first expected byte, the byte following the 0x0A character, is written into the first register location, SPE_RJ1DEXP[1][7:0]. The SPE mapper compares the incoming J1 sequence with the stored expected value, setting the SPE_RTIM state bit if they are
different. Any changes in the state is reported in bit SPE_RTIMD, using interrupt mask bit SPE_RTIMM.
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18 SPE Mapper Functional Description (continued)
■
SPE_J1MONMODE[2:0] = 101: the user will program the 16 expected values of J1 in
SPE_RJ1DEXP[1—16][7:0] in SDH framing mode, where the first byte of the message has the MSB set to 1.
The SPE mapper compares the incoming J1 sequence with the stored expected value, setting the state bit,
SPE_RTIM if they’re different. Any change in state is reported in bit SPE_RTIMD, using interrupt mask bit
SPE_RTIMM.
■
SPE_J1MONMODE[1:0] = 110 and 111 are currently undefined.
■
Unless bit PAIS_TIMINH (Table 149) is set, bit SPE_RTIMD contributes to the AUTO AIS control signal from the
SPE mapper to the VT mapper).
■
Unless mask bit SPE_RTIMM is set, bit SPE_RTIMD can generate an interrupt.
Table 536. J1 Monitor
Name
SPE_J1MONMODE[2:0] (Table 149)
SPE_RJ1DEXP[1—64][7:0] (Table 164)
SPE_RJ1DMON[1—64][7:0] (Table 162)
SPE_CNTDJ1[3:0] (Table 150)
SPE_RTIM (Table 148)
SPE_RTIMD (Table 146)
SPE_RTIMM (Table 147)
Function
J1 Monitoring Type.
J1 Expected Data Storage (64/1 Byte).
J1 Received Data Storage (64/1 Byte).
Continuous Times Detect Value.
J1 Mismatch State Bit.
J1 Mismatch Delta Bit, Active-High.
J1 Mismatch Mask Bit, Active-High.
18.14.3 B3 BIP-8 Check
A B3 BIP-8 even parity is computed over all the incoming bits of the TUG-3 frame, after descrambling, and compared to the B3 byte received in the next frame. The total number of B3 BIP-8 bit errors (raw count) or block errors
is counted (selected through SPE_B3BITBLKCNT (Table 149)). Upon a performance monitor (PM) interval, the
internal running counter is placed into SPE_B3ECNT[15:0] (Table 160) and then cleared. Depending on the value
of microprocessor bit SMPR_SAT_ROLLOVER (Table 67), the internal counter will roll over or stay at its maximum
value until cleared.
18.14.4 Signal Label C2 Byte Monitor
Table 537. STS Signal Label Defect Conditions
Provisioned STS PTE
Functionality, Expected C2
Any Equipped Functionality
Any Equipped Functionality
Equipped—Nonspecific
Any Payload Specific Code
Any Payload Specific Code
Equipped—Nonspecific (01) or
VT-Structured STS-1 (02)
Any Payload Specific Code
Except VT-Structured
STS-1 (02)
Any Equipped Functionality
Any Equipped Functionality
412
Received Payload Label
(C2 in hex)
Unequipped (00)
Equipped—Nonspecific (01)
Any Value (02 to E0, FD to FE)
The Same Payload Specific
Code (02 to E0, FD to FE)
A Different Payload Specific
Code (02 to E0, FD to FE)
PDI, 1 to 27 VTx Defects
(E1 to FB)
PDI, 1 to 27 VTx Defects
(E1 to FB)
PDI, 28 VT1.5 Defects or 1
Non-VT Payload Defect (FC)
Reserved (FF)
Defect
TMUX_FORCEC2DEF = 1
(Table 97)
TMUX_RUNEQP
No Change
None
No Change
None
No Change
None
No Change
TMUX_RPLMP
No Change
None
TMUX_RPLMP
TMUX_RPLMP
No Change
None
TMUX_RPLMP
None
TMUX_RPLMP
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18 SPE Mapper Functional Description (continued)
The C2 byte is stored in SPE_C2DMON[7:0] (Table 152 on page140 ). This is updated after a number of consecutive frames (determined by the value programmed in SPE_CNTDC2[3:0] (Table 150 on page139 )) of identical C2
bytes, i.e., the 8-bit pattern must be identical for the number of frames in the programmed SPE_CNTDC2[3:0] prior
to updating SPE_C2DMON[7:0].
Whenever the contents of the C2 byte monitor SPE_C2DMON[7:0] changes, a delta bit SPE_C2DMOND
(Table 146 on page 134) is set and bit SPE_C2DMONM (Table 147 on page136 ) is the interrupt mask bit.
The SPE mapper maintains a programmable expected value of the C2 byte in SPE_C2DEXP[7:0] ( Table 151 on
page 140). If the current value of the C2 byte (SPE_C2DMON[7:0]) does not equal the expected C2 value
(C2DEXP[7:0]), then a payload label mismatch (PLM-P) defect is declared and reported in SPE_RPLM
(Table 148). The change in PLM-P state is reported in SPE_RPLMD (Table 146) with an interrupt mask bit
SPE_RPLMM (Table 147).
Also if the current value of the C2 byte (SPE_C2DMON[7:0]) is all 0s, then an unequipped (UNEQ-P) defect is
declared and reported in SPE_RUNEQ (Table 148). The change in UNEQ-P state is reported in SPE_RUNEQD
(Table 146) with an interrupt mask SPE_RUNEQM (Table 147).
Table 538. C2MON Processing
Name
Function
SPE_C2DMON[7:0] (Table 152)
C2 Current Data Monitor.
SPE_C2DEXP[7:0] (Table 151)
Expected Value of C2 Byte.
SPE_CNTDC2[3:0] (Table 150)
Continuous Times Detect Count Value for C2.
SPE_C2DMOND (Table 146)
C2 Data Monitor Event Bit.
SPE_C2DMONM (Table 147)
C2 Data Monitor Mask Bit.
SPE_RPLM (Table 148)
Payload Label Mismatch State.
SPE_RPLMD (Table 146)
Payload Label Mismatch Delta Bit.
SPE_RPLMM (Table 147)
Payload Label Mismatch Mask Bit.
SPE_RUNEQ (Table 148)
Unequipped Path State.
SPE_RUNEQD (Table 146)
Unequipped Path Delta Bit.
SPE_RUNEQD (Table 147)
Unequipped Path Mask Bit.
18.14.5 Path User Byte F2 Monitor
The SPE mapper monitors the path user channel in the F2 byte. The current value of the F2 byte is stored in
SPE_F2DMON0[7:0] (Table 152) after a number of consecutive frames (determined by the value programmed in
SPE_CNTDF2[3:0] (Table 150)) of identical F2 byte has been received, i.e., the 8-bit pattern must be identical for a
number of frames equal to the value of SPE_CNTDF2[3:0] prior to updating SPE_F2DMON0[7:0].
Whenever the contents of the F2 byte monitor (SPE_F2DMON0[7:0]) changes, a delta bit SPE_F2DMOND
(Table 146) is set. The interrupt mask is SPE_F2DMONM (Table 147).
The SPE mapper maintains a history of the previous valid F2 byte in SPE_F2DMON1[7:0] (Table 152).
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18 SPE Mapper Functional Description (continued)
Table 539. F2 Monitor
Name
SPE_F2DMON0[7:0] (Table 152)
SPE_F2DMON1[7:0] (Table 152)
SPE_CNTDF2[3:0] (Table 150)
SPE_F2DMOND (Table 146)
SPE_F2DMONM (Table 147)
Function
Fault Location Current Consistent Value.
Fault Location Previous Consistent Value.
Continuous N-Times Detect (3—15).
F2 Data Monitor Delta Bit.
F2 Data Monitor Mask Bit.
18.14.6 Path User Byte F3 Monitor
The SPE mapper monitors the second path user channel in the F3 byte. The current value of the F3 byte is stored
in SPE_F3DMON0[7:0] (Table 152 on page140 ) after a number of consecutive frames (determined by the value
programmed in SPE_CNTDF3[3:0] (Table 150)) of identical F3 bytes has been received, i.e., the 8-bit pattern must
be identical for a number of frames, determined by SPE_CNTDF3[3:0], prior to updating SPE_F3DMON0[7:0].
Whenever the contents of the F3 byte monitor (SPE_F3DMON0[7:0]) changes, a delta bit SPE_F3DMOND
(Table 146) is set. The interrupt mask is in register bit SPE_F3DMONM (Table 147).
The SPE mapper maintains a history of the previous valid F3 byte in SPE_F3DMON1[7:0] (Table 152).
Table 540. F3 Monitor
Name
SPE_F3DMON0[7:0] (Table 152)
SPE_F3DMON1[7:0] (Table 152)
SPE_CNTDF3[3:0] (Table 150)
SPE_F3DMOND (Table 146)
SPE_F3DMONM (Table 147)
Function
User Channel Current Consistent Value.
User Channel Previous Consistent Value.
Continuous N-Times Detect (3—15).
F3 Data Monitor Delta Bit.
F3 Data Monitor Mask Bit.
18.14.7 N1 Monitor
The SPE mapper stores the current value of the N1 byte in SPE_N1DMON[7:0] (Table 152). This is updated after a
number of consecutive frames (determined by the value programmed in bits SPE_CNTDN1[3:0] (Table 150)) of
identical N1 bytes, i.e., the 8-bit pattern must be identical for a number frames determined by the value in register
bits SPE_CNTDN1[3:0] prior to updating the N1 register.
Whenever the contents of the N1 byte monitor (SPE_N1DMON[7:0]) changes, a delta bit SPE_N1DMOND
(Table 146) is set. The interrupt generated by SPE_N1DMOND can be masked off by SPE_N1DMONM
(Table 147).
Table 541. N1 Monitor
Name
SPE_N1DMON[7:0] (Table 152)
SPE_CNTDN1[3:0] (Table 150)
SPE_N1DMOND (Table 146)
SPE_N1DMONM (Table 147)
414
Function
Fault Location Current Consistent Value.
Continuous N-Times Detect (3—15).
N1 Data Monitor Delta Bit.
N1 Data Monitor Mask Bit.
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18 SPE Mapper Functional Description (continued)
18.14.8 K3 Byte Monitor
The SPE mapper stores the current value of the K3 byte in SPE_K3DMON[7:0] (Table 152 on pag e140). This is
updated after a number of consecutive frames (determined by the value programmed in bits SPE_CNTDK3[3:0]
(Table 150 on page139 )) of identical K3 bytes, i.e., the 8-bit pattern must be identical for a number of frames determined by the value of SPE_CNTDK3[3:0] prior to updating the K3 register.
Whenever the contents of the K3 byte monitor (SPE_K3DMON[7:0]) changes, a delta bit SPE_K3DMOND
(Table 146 on page 134) is set. The interrupt generated by SPE_K3DMOND can be masked off by the
SPE_K3DMONM (Table 147 on page 136).
Table 542. K3 Monitor
Name
SPE_K3DMON[7:0] (Table 152)
SPE_CNTDK3[3:0] (Table 150)
SPE_K3DMOND (Table 146)
SPE_K3DMONM (Table 147)
Function
Fault Location Current Consistent Value.
Continuous N-Times Detect (3—15).
K3 Data Monitor Delta Bit.
K3 Data Monitor Mask Bit.
18.14.9 AIS-P and RDI-P Detect
The SPE mapper monitors for path AIS in the H1 and H2 bytes (all H1 and H2 bits = 1) of the TUG-3 pointer. When
path AIS is detected, SPE_RAIS (Table 148 on page137 ) will be set to 1 after three consecutive occurrences. Any
changes to SPE_RAIS will be reported in SPE_RAISD (Table 146 on page134 ) and the interrupt can be masked,
using SPE_RAISM (Table 147 on page136 ).
A remote defect indication-path (RDI-P) signal indicates to STS PTE that its peer STS PTE has detected a defect
on the signal that it originated. The SPE mapper supports both the single bit RDI-P and the 3-bit enhanced RDI-P;
the mode is selectable using bit SPE_RPRDI_MODE (Table 149 on page138 ). When SPE_RPRDI_MODE = 0,
1-bit code is supported and when SPE_RPRDI_MODE = 1, 3-bit enhanced RDI-P code is supported. Three bits of
the G1 byte (G1[3:1]) are reserved for the RDI-P signal.
The SPE mapper monitors for a 1-bit RDI-P code in G1[3] bit or a 3-bit enhanced remote defect indication (RDI-P)
condition in the G1[3:1] bits and stores the current value in bits SPE_PRDIDMON[2:0] (Table 152 on page140 ).
The current value is updated after a number of consecutive frames (determined by the value of bits
SPE_CNTDPRDI[3:0] (Table 150)) of identical G1[3:1], i.e., the 3-bit pattern must be identical for a number of
frames, determined by the value of SPE_CNTDPRDI[3:0] prior to updating SPE_PRDIDMON[2:0].
Whenever the contents of SPE_PRDIDMON[2:0] changes, a delta bit SPE_PRDIDMOND (Table 146 on page 134)
is set. The interrupt generated by SPE_PRDIDMOND can be masked off by SPE_PRDIDMONM (Table 147).
Table 543. AIS-P and RDI-P Detect
Name
SPE_CNTDPRDI[3:0] (Table 150)
SPE_PRDIDMOND (Table 146)
SPE_PRDIDMONM (Table 147)
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Function
Continuous Times Detect Count Value for G1[3:1] Bits (3—15).
Path RDI Delta Bit.
Path RDI Mask Bit.
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18 SPE Mapper Functional Description (continued)
18.14.10 REI-P Detect
Bits 7 through 4 of the G1 byte are allocated for use as a path remote error indication function (REI-P).
■
For STS-1 signals, bits 7 through 4 of the G1 byte are allocated for REI-P which conveys the error count detected
by the PTE (using the path BIP-8 code B3) back to its peer PTE as follows.
Table 544. STS-1 P-REI Interpretation
G1[7:4] Code
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001—1111
Code Interpretation
0 (no errors)
1
2
3
4
5
6
7
8
0 (no errors)
The SPE mapper provides a counter to accumulate G1-REI errored bit count in SPE_G1ECNT[15:0] (Table 160 on
page 147) from G1[7:4]. This counter will hold at its maximum value or roll over (depending on the value of microprocessor bit SMPR_SAT_ROLLOVER (Table 67 on page 68)) and update upon the performance monitoring interval.
18.14.11 Signal Degrade BER Algorithm
A signal degrade state bit is SPE_SDB3 (Table 148 on page 137) with a change of state indication reported in delta
bit SPE_SDB3D (Table 146 on page134 ) and the interrupt mask bit is SPE_SDB3M (Table 147). This bit error rate
algorithm operates on B3 errors.
Declaring the signal degrade state requires the definition of two measurement windows. A monitoring block consisting of a number of frames, Ns (SPE_SDNSSET[18:0] (Table 158 on page 146)), and a measurement interval
consisting of a number of monitoring blocks, B (SPE_SDBSET[11:0] (Table 158)). A block is determined bad when
the number of bit errors equals or exceeds a threshold, L (SPE_SDLSET[3:0] (Table 158)). Signal degrade is
declared when a number of bad monitoring blocks equals or exceeds the threshold, M (SPE_SDMSET[7:0]
(Table 158)), for the measurement interval.
Clearing the signal degrade state requires the definition of two measurement windows. A monitoring block consisting of a number of frames, Ns (SPE_SDNSCLEAR[18:0] (Table 158)), and a measurement interval consisting of a
number of monitoring blocks, B (SPE_SDBCLEAR[11:0] (Table 158)). A block is determined good when the number of bit errors is less than a threshold, L (SPE_SDLCLEAR[3:0] (Table 158)). Signal degrade is cleared when a
number of good monitoring blocks equals or exceeds the threshold, M (SPE_SDMCLEAR[7:0] (Table 158)), for the
measurement interval.
The set parameters are used when the signal degrade state is clear, and the clear parameters are used when the
signal degrade state is declared.
The signal degrade state may be forced to the declared state with bit SPE_SDSET (Table 145 on page134 ) and
forced to the cleared state with bit SPE_SDCLEAR (Table 145). The controls are provided to force the BER algorithm into the failed state or normal state, respectively.
The above algorithm can detect bit error rates from 1 x 10 –3 to 1 x 10 –9.
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18 SPE Mapper Functional Description (continued)
Table 545. Signal Degrade Parameters
Name
SPE_SDNSSET[18:0] (Table 158)
SPE_SDLSET[3:0] (Table 158)
Function
Signal Degrade Ns Set. Number of frames in a monitoring block for SD.
Signal Degrade L Set. Error threshold for determining if a monitoring
block is bad.
SPE_SDMSET[7:0] (Table 158)
Signal Degrade M Set. Threshold of the number of bad monitoring blocks
in an observation interval. If the number of bad blocks is below this threshold, then SD is cleared.
SPE_SDBSET[15:0] (Table 158)
Signal Degrade B Set. Number of monitoring blocks in a measurement
interval.
SPE_SDNSCLEAR[18:0] (Table 158) Signal Degrade Ns Clear. Number of frames in a monitoring block for SD.
SPE_SDLCLEAR[3:0] (Table 158) Signal Degrade L Clear. Error threshold for determining if a monitoring
block is bad.
SPE_SDMCLEAR[7:0] (Table 158) Signal Degrade M Clear. Threshold of the number of bad monitoring
blocks in an observation interval. If the number of bad blocks is below this
threshold, then SD is cleared.
SPE_SDBCLEAR[15:0] (Table 158) Signal Degrade B Clear. Number of monitoring blocks in a measurement
interval.
SPE_SDSET (Table 145)
Signal Degrade Set. Allows the signal degrade algorithm to be forced into
the failed state (active 0 to 1).
SPE_SDCLEAR (Table 145)
Signal Degrade Clear. Allows the signal degrade algorithm to be forced
into the normal state (active 0 to 1).
SPE_SDB3 (Table 148)
Signal Degrade BER Algorithm State Bit.
SPE_SDB3D (Table 146)
Signal Degrade BER Algorithm Delta Bit.
SPE_SDB3M (Table 147)
Signal Degrade BER Algorithm Mask Bit.
Note: The threshold written by the control system is one less than the desired number, except for the SPE_SDLSET[3:0]/SDLCLEAR[3 :0]
parameter.
18.14.12 Signal Fail BER Algorithm
A signal fail state is reported by bit SPE_SFB3 (Table 148 on pag e137) and change of state in bit SPE_SFB3D
(Table 146) with the interrupt mask bit SPE_SFB3M (Table 147). This bit error rate algorithm operates on B3 errors.
Declaring the signal fail state requires the definition of two measurement windows, a monitoring block consisting of
a number of frames, Ns (SPE_SFNSSET[18:0] (Table 159 on page146 )), and a measurement interval consisting
of a number of monitoring blocks, B (SPE_SFBSET[15:0] (Table 159)). A block is determined to be bad when the
number of bit errors equals or exceeds a threshold, L (SPE_SFLSET[3:0] (v)). Signal fail is declared when the
number of bad monitoring blocks equals or exceeds the threshold, M (SPE_SFMSET[7:0] (Table 159)), for the
measurement interval.
Clearing the signal fail state requires the definition of two measurement windows, a monitoring block consisting of a
number of frames, Ns (SPE_SFNSCLEAR[18:0] (Table 159)), and a measurement interval consisting of a number
of monitoring blocks, B (SPE_SFBCLEAR[11:0] (v)). A block is determined to be good when the number of bit
errors is less than a threshold, L (SPE_SFLCLEAR[3:0] (Table 159)). Signal fail is cleared when a number of good
monitoring blocks equals or exceeds the threshold, M (SPE_SFMCLEAR[7:0] (v)), for the measurement interval.
The set parameters are used when the signal fail state is clear, and the clear parameters are used when the signal
fail state is declared.
The signal fail state may be forced to the declared state with bit SPE_SFSET (Table 145 on page134 ) and forced
to the cleared state with bit SPE_SFCLEAR (Table 145).
The above algorithm can detect bit error rates from 1 x 10 –3 to 1 x 10 –9.
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18 SPE Mapper Functional Description (continued)
Table 546. Signal Fail Parameters
Name
SPE_SFNSSET[18:0] (Table 159)
SPE_SFLSET[3:0] (Table 159)
Function
Signal Fail Ns Set. Number of frames in a monitoring block forSF.
Signal Fail L Set. Error threshold for determining if a monitoring block is
bad.
SPE_SFMSET[7:0] (Table 159)
Signal Fail M Set. Threshold of the number of bad monitoring blocks in
an observation interval. If the number of bad blocks is below this threshold, then SF is cleared.
SPE_SFBSET[15:0] (Table 159)
Signal Fail B Set. Number of monitoring blocks.
SPE_SFNSCLEAR[18:0] (Table 159) Signal Fail Ns Clear. Number of frames in a monitoring block forSF.
SPE_SFLCLEAR[3:0] (Table 159) Signal Fail L Clear. Error threshold for determining if a monitoring block
is bad.
SPE_SFMCLEAR[7:0] (Table 159) Signal Fail M Clear. Threshold of the number of bad monitoring blocks in
an observation interval. If the number of bad blocks is below this threshold, then SF is cleared.
SPE_SFBCLEAR[15:0] (Table 159) Signal Fail B Clear. Number of monitoring blocks.
SPE_SFSET (Table 145)
Signal Fail Set. Allows the signal degrade algorithm to be forced into the
failed state (active 0 to 1).
SPE_SFCLEAR (Table 145)
Signal Fail Clear. Allows the signal degrade algorithm to be forced into
the normal state (active 0 to 1).
SPE_SFB3 (Table 148)
Signal Fail BER Algorithm State Bit.
SPE_SFB3D (Table 146)
Signal Fail BER Algorithm Delta Bit.
SPE_SFB3M (Table 147)
Signal Fail BER Algorithm Mask Bit.
Note: The threshold written by the control system is one less than the desired number, except for the SPE_SFLSET[3:0]/SFLCLEAR[3 :0]
parameter.
18.14.13 POAC Drop
The SPE mapper accommodates one path overhead access channel (POAC output channel).
The POAC channel consists of the following signals:
■
A 576 kHz inverted clock signal sourced by the TMUX (RPOACCLK, pin AE3).
■
A 576 kbits/s data signal sourced by the TMUX (RPOACDATA, pin AD4).
■
An 8 kHz synchronization signal, sourced by the TMUX (RPOACSYNC, pin AF4). The sync signal is normally
low; during the last clock period of each frame coincident with the least significant bit of the last byte, the sync
signal is high.
The data signal is partitioned into frames of 9 bytes. The frame repetition rate is 8 kHz. Each byte consists of 8 bits
that are transmitted/received most significant bit first (MSB). The MSB of the second byte of each frame contains
an odd/even parity bit over the 72 bits of the previous frame. The remaining 7 bits of this byte are not specified.
Bytes shown in Table 547 summarize the access capabilities of the receive POAC.
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18 SPE Mapper Functional Description (continued)
Table 547. Path Overhead Byte Access
J1
POH Parity
C2
G1
F2
H4
F3
K3
N1
Even or odd parity can be inserted into the first bit of the second byte of the POAC outgoing frame. Parity is
selected with register bit, SPE_RPOAC_OEPINS (Table 149 on page138 ).
18.14.14 Insertion of AIS-P
The SPE mapper automatically generates AIS path (AIS-P) when:
■
■
■
■
■
The pointer interpreter declares the receive AIS state (SPE_RAIS in Table 148 on page137 ) or receive loss of
pointer state (SPE_RLOP (Table 148)) and the appropriate inhibit signals are inactive.
AIS is requested by signals from the TMUX interface.
AIS is forced by setting bit SPE_PAISINS (Table 149).
Any one of the loss-of-clock or loss-of-sync bits are active and their corresponding inhibit bits are inactive.
Any of bits SPE_RUNEQ, SPE_RPLM, and SPE_RTIM (all are in Table 148) are active, and the appropriate
inhibit signals are inactive.
Criteria for PATH_AIS_GENERATE =
((SPE_RLOP AND (SPE_PAIS_LOPINH)) OR
(SPE_RAIS AND (SPE_PAIS_AISINH)) OR
(SPE_RUNEQ AND (SPE_PAIS_UNEQINH)) OR
(SPE_RPLM AND (SPE_PAIS_PLMINH)) OR
(SPE_RTIM AND (SPE_PAIS_TIMINH)) OR
(SPE_SFB3 AND (SPE_PAIS_SFB3INH)) OR
(SPE_SDB3 AND (SPE_PAIS_SDB3INH)) OR
(SPE_RSY52LOS AND (SPE_AIS_LOSSY52INH)) OR
(SPE_RV1LOS AND (SPE_AIS_LOSV1INH)) OR
(SPE_RSPELOS AND (SPE_AIS_LOSSPEINH)) OR
(SPE_RJ0J1V1LOS AND (SPE_AIS_LOSJ0J1V1INH)) OR
(SPE_RDS3LOC AND (SPE_AIS_LOCDS3INH)) OR
(SPE_RC52LOC AND (SPE_AIS_LOC52INH)) OR
(SPE_RLSLOC AND (SPE_AIS_LOCINH)) OR
SPE_PAISINS OR
RAUTO_AIS (signal from TMUX))
The SPE mapper starts/stops generating AIS-P within 125 µs of the detection/absence of a failure condition.
AIS-P consists of writing all ones into the H1, H2, and H3 bytes and into the entire payload.
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18 SPE Mapper Functional Description (continued)
18.15 Transmit Direction (to SONET/SDH Line)
The transmit block inserts the path overhead (POH) bytes to the payload data and outputs an STS-1 SPE or a
TUG-3 payload as required.
The transmit section is broken down into the following functional parts:
■
Loss of clock and loss of sync detectors
■
N1 insert
■
K3 insert
■
Path user byte F3 insert
■
Path user byte F2 insert
■
AIS-P insert
■
REI-P insert
■
RDI-P insert
■
C2 signal label insert
■
B3 calculation and insert
■
J1 path trace insert
All insert control functions that are inhibited will insert all zeros or all ones into the outgoing bytes depending on the
value of microprocessor register bit SMPR_OH_DEFLT (Table 67).
18.15.1 PATH Insertion Block
POAC INSERT
F2, F3, C2, N1, AND J1
TUG-3 DATA
B3
INSERT
MUX
The path overhead insertion block of the SPE mapper is shown below. The block computes and inserts the B3 BIP
error bytes and the rest of the path overhead bytes to form a TUG-3 frame.
INSERT
AIS-P
TO TMUX INTERFACE
BLOCK
B3
GENERATE
INSERT
J1
K3
APS
INSERT
G1
RDI-P
INSERT
G1
REI-P
INSERT
INSERT
N1
INSERT
C2
J1
K3
G1
G1
N1
C2
INSERT
F3
F3
INSERT
F2
F2
INSERT PATH OVERHEAD BYTES
INSERT H4
FIXED VAL
H4
VC-3 DATA
5-9069(F)
Figure 37. Transmit Direction Path Insertion Block
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18 SPE Mapper Functional Description (continued)
18.15.2 Loss of Clock and Loss of Sync Detectors
The SPE mapper detects and reports the loss of the input clocks for the transmit telecom bus clock, device pin
TLSCLK (AA2), in bit SPE_TLSLOC (Table 148 on page137 ); the 51.84 MHz transmit low-speed clock, device pin
TLSC52 (AC3), in bit SPE_TC52LOC (Table 148), and the external DS3 clock, device pin DS3DATAINCLK (J22), in
bit SPE_TDS3LOC (Table 148). Loss of clock is determined by stuck high or stuck low for time T. The detection
time T will be greater than 10 µs but less than 125 µs. The function uses the microprocessor clock as its reference.
The device will report a change in the loss of clock state for the monitored clocks using bits SPE_TLSLOCD
(Table 146 on page 134), SPE_TC52LOCD (Table 146), and SPE_TDS3LOCD (Table 146), respectively. The
microprocessor interrupt may be masked using bits SPE_TLSLOCM (Table 147 on pag e136), SPE_TC52LOCM
(Table 147), and SPE_TDS3LOCM (Table 147), respectively.
The SPE mapper detects loss-of-sync conditions for the telecom bus sync signals, device pins TLSSYNC52 (AD2),
TLSJ0J1V1 (AB4), TLSSPE (AB2), and TLSV1 (AB3). The loss of sync states are reported in bits
SPE_TSY52LOS (Table 148), SPE_TJ0J1V1LOS (Table 148), SPE_TSPELOS (Table 148), and SPE_TV1LOS
(Table 148), respectively. The device will report a change in the loss of sync state for the monitored sync signals in
bits SPE_TSY52LOSD (Table 146), SPE_TJ0J1V1LOSD (Table 146), SPE_TSPELOSD (Table 146), and
SPE_TV1LOSD (Table 146), respectively. The microprocessor interrupt may be masked using bits
SPE_TSY52LOSM (Table 147), SPE_TJ0J1V1LOSM (Table 147), SPE_TSPELOSM (Table 147), and
SPE_TV1LOSM (Table 147), respectively.
18.15.3 J1 Byte Insert
A 64-byte sequence stored in SPE_TJ1DINS[1—64][7:0] (Table 163 on page 148) will be inserted into the outgoing
J1 byte when bit SPE_TJ1INS = 1 ( Table 154 on page143 ); otherwise, the associated POAC value is inserted
when bit SPE_TPOAC_J1 = 1 (Table 154) or the default value, determined by the value of microprocessor bit
SMPR_OH_DEFLT (Table 67 on pag e68), is inserted when SPE_TPOAC_J1 = 0.
The CRC for the J1 trace has to be programmed into the J1 bytes by the user.
18.15.4 B3 BIP-8 Calculation and Insert
The B3 bytes are allocated for path overhead error monitoring function. This function is a bit interleaved parity 8
code (BIP-8) using even parity. The BIP-8 is computed before scrambling over all bits of the previous AU-3/TUG-3
frame, and is placed in byte B3 of the current frame also before scrambling. When enabled with control bit,
SPE_TB3ERRINS (Table 156), a single B3 byte can be inverted each time bit SPE_BERR_INS (Table 156) is
asserted.
18.15.5 C2 Signal Label Byte Insert
When bit SPE_TC2INS = 1 (Table 154), the value in SPE_TC2DINS[7:0] ( Table 157) is inserted into the outgoing
C2 byte; otherwise, insert the associated POAC value when SPE_TPOAC_C2 = 1 (Table 154) or insert the default
value determined by the microprocessor bit SMPR_OH_DEFLT when bit SPE_TPOAC_C2 = 0.
18.15.6 REI-P G1(7:4) Insert
Four bits of the G1 byte G1(7:4) are allocated for use as a path remote error indication (REI). For AU-3/TUG-3 signals, these bits convey the count (in the range of 0 to 8) of interleaved bit blocks that have been detected in error by
the BIP-8 (B3) detector on the received signal.
This function can be inhibited with bit SPE_TREIP_INH (Table 155) and the value in SPE_TG1DINS[7:4]
(Table 157) is inserted in G1(7:4) bits. A continuous error in the G1 byte can be transmitted using control bit
SPE_TREIERRINS (Table 156). A value of 0x03 will be inserted when SPE_TREIERRINS = 1, subject to
SPE_BERR_INS and SMPR_BER_INSRT being enabled.
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155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
18 SPE Mapper Functional Description (continued)
18.15.7 Path RDI (RDI-P) Insert
When transmit RDI software insert control bit SPE_TPRDIINS = 1 (Table 155), data from SPE_TG1DINS[3:1]
(Table 157) is written into the G1[3:1] output bits. When SPE_TPRDIINS = 0, hardware insert is enabled for RDI-P
insertion. Each defect contribution to the RDI-P outgoing code can be inhibited. There are two modes supported for
path RDI Insertion. One mode conforms to the earlier 1-bit version of the standard. The other mode, enhanced
RDI-P mode, uses a 3-bit RDI-P code and conforms to the current version of the standard. When the mode selection bit SPE_TPRDI_MODE = 0 (Table 155), the SPE mapper sends a 3-bit code that conforms to the earlier 1-bit
version of the standards. When SPE_TPRDI_MODE = 1, the SPE mapper sends a 3-bit code conforming to the
current enhanced path RDI encoding. Note that for nonenhanced RDI-P mode, the relevant defects are AIS-P and
LOP-P. For enhanced RDI-P mode, the relevant defects are AIS-P, LOP-P, TIM-P, PLM-P, and UNEQ-P, and TIM-P.
When a failure condition exists that will cause RDI-P to be generated via hardware, the generation of RDI-P must
last for at least 20 frames before clearing, even if the original failure cause has cleared in less than 20 frames.
The following table describes the encoding of the path-RDI defects.
Table 548. RDI-P Defects for Enhanced RDI-P Mode
Bit 3
0
0
0
0
1
1
1
1
G1
Bit 2
0
0
1
1
0
0
1
1
Triggers
Bit 1
0
1
0
1
0
1
0
1
No defects (nonenhanced RDI-P mode)
No defects (enhanced RDI-P mode)
LCD-P, PLM-P (LCD-P not supported in Super Mapper)
No defects (nonenhanced RDI-P mode)
AIS-P, LOP-P (nonenhanced RDI-P mode)
AIS-P, LOP-P (enhanced RDI-P mode)
TIM-P, UNEQ-P (enhanced RDI-P mode)
AIS-P, LOP-P (nonenhanced RDI-P mode)
18.15.8 F2 Byte Insert
When control bit SPE_TF2INS = 1 (Table 154), insert the value in SPE_TF2DINS[7:0] (Table 157) in the outgoing
F2 byte; otherwise, insert the associated POAC value when bit SPE_TPOAC_F2 = 1 ( Table 154) or insert the
default value determined by the microprocessor bit SMPR_OH_DEFLT (Table 67) when SPE_TPOAC_F2 = 0.
18.15.9 H4 Insert Control
When control bit SPE_TH4INS = 1 (v), insert the value in SPE_TH4DINS[7:0] (Table 157) in the outgoing H4 byte;
otherwise, insert the associated POAC value when bit SPE_TPOAC_H4 = 1 (Table 154) or insert the default value
determined by the microprocessor bit SMPR_OH_DEFLT when SPE_TPOAC_H4 = 0.
18.15.10 F3 Byte Insert
When control bit SPE_TF3INS = 1 (Table 154), insert the value in SPE_TF3DINS[7:0] (Table 157) in the outgoing
F3 byte; otherwise, insert the associated POAC value when bit SPE_TPOAC_F3 = 1 ( Table 154) or insert the
default value determined by the microprocessor bit SMPR_OH_DEFLT (Table 67) when SPE_TPOAC_F3 = 0.
18.15.11 K3 Insert Control Parameters
When control bit SPE_TK3INS = 1 (Table 154), insert the value in SPE_TK3DINS[7:0] (Table 157) in the outgoing
K3 byte; otherwise, insert the associated POAC value when bit SPE_TPOAC_K3 = 1 ( Table 154) or insert the
default value determined by the microprocessor bit SMPR_OH_DEFLT when SPE_TPOAC_K3 = 0.
422
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
18 SPE Mapper Functional Description (continued)
18.15.12 N1 Insert Control Parameters
When control bit SPE_TN1INS = 1 (Table 154), insert the value in SPE_TN1DINS[7:0] (Table 157) in the outgoing
N1 byte; otherwise, insert the associated POAC value when bit SPE_TPOAC_N1 = 1 (Table 154) or insert the
default value determined by the microprocessor bit SMPR_OH_DEFLT when SPE_TPOAC_N1 = 0.
18.16 POAC Insert
One overhead access channel (POAC) is provided on-chip to provision the path overhead portion of the outgoing
frame. A POAC channel consists of the following signals:
■
A 576 kHz inverted clock signal sourced by the SPE mapper (TPOACCLK, pin AE4).
■
A 576 kbits/s data signal received by the SPE mapper in the transmit direction (TPOACDATA, pin AD5).
■
An 8 kHz synchronization signal (TPOACSYNC, pin AC5), sourced by the SPE mapper. The sync signal is normally low; during the first clock period of each frame coincident with the most significant bit of the first byte, the
sync signal is high.
The data signal is partitioned into frames of 9 bytes. The frame repetition rate is 8 kHz. Each byte consists of 8 bits
that are transmitted/received most significant bit first. The MSB of the second byte of each frame contains an odd/
even parity bit over the 72 bits of the previous frame. The remaining 7 bits of this byte are not specified. The POAC
input has full access to all the path overhead bytes of the STS-1 frame. Bytes shown in the table below summarize
the access capabilities of the transmit POAC channel.
Table 549. Path Overhead Byte Access—Transmit Direction
J1
POH Parity
C2
G1
F2
H4
F3
K3
N1
An event indication is provided to indicate parity errors for the POAC channel. Monitoring of odd or even parity is
selected with bit SPE_TPOAC_OEPMON (Table 154 on page143 ). Parity errors are reported with bit
SPE_TPOAC_PE (Table 146). The interrupt can be masked with bit SPE_TPOAC_PM (Table 147 on page136 ).
Table 550 summarizes the insertion options for the specified overhead bytes for POAC. The SPE mapper allows a
predefined default value determined by the value of the microprocessor bit SMPR_OH_DEFLT (Table 67) to be
inserted on the corresponding POAC value.
Agere Systems Inc.
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155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
18 SPE Mapper Functional Description (continued)
Table 550. TPOAC Control Bits
Overhead Bytes
J1
H4
F2
F3
C2
K3
N1
Control Bits
(Table 154)
SPE_TPOAC_J1
SPE_TPOAC_H4
SPE_TPOAC_F2
SPE_TPOAC_F3
SPE_TPOAC_C2
SPE_TPOAC_K3
SPE_TPOAC_N1
Values
0 (Default Value)
SMPR_OH_DEFLT
1
TPOAC Data
18.17 AIS Path Generation
Path AIS is specified as all ones in the entire STS-1 SPE/TUG-3 frame. Path AIS can be forced by setting bit
SPE_TAISPINS = 1 (Table 154 on page143 ).
424
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
19 VT/TU Mapper Functional Description
Table of Contents
Contents
Page
19 VT/TU Mapper Functional Description ........................................................................................................... 425
19.1 VT/TU Mapper Introduction .................................................................................................................... 427
19.2 VT/TU Mapper Features ......................................................................................................................... 427
19.3 VT/TU Mapper Functional Block Diagram .............................................................................................. 428
19.4 VT/TU Mappings ..................................................................................................................................... 430
19.5 VT/TU Locations ..................................................................................................................................... 431
19.6 VT/TU Mapper Receive Path Description ............................................................................................... 432
19.7 VT Demultiplexer (VTDEMUX) ............................................................................................................... 432
19.8 VT Pointer Interpreter (VTPI) .................................................................................................................. 432
19.9 VT Termination (VTTERM) ..................................................................................................................... 435
19.9.1 V5 Termination ............................................................................................................................. 435
19.9.2 Z6/N2 Termination ....................................................................................................................... 436
19.9.3 Z7/K4 Termination ....................................................................................................................... 436
19.9.4 Payload Termination .................................................................................................................... 437
19.10 Output Signal Selection (OUTSEL) ...................................................................................................... 437
19.11 J2 Byte Monitor and Termination (J2MON) .......................................................................................... 438
19.12 Receive Signaling (RX_VTSIG) ............................................................................................................ 439
19.13 Receive Lower-Order Path Overhead (RX_LOPOH) ........................................................................... 440
19.14 VT/TU Mapper Transmit Path Requirements ....................................................................................... 440
19.14.1 Input Selector (INSEL) .............................................................................................................. 441
19.14.2 Transmit Elastic Store (TES) ..................................................................................................... 442
19.14.3 Virtual Tributary Generator (VTGEN) ........................................................................................ 442
19.14.4 Pointer Generation .................................................................................................................... 442
19.14.5 VT Multiplexer (VTMUX) ........................................................................................................... 450
19.14.6 Transmit Signaling (TX_VTSIG) ................................................................................................ 450
19.14.7 Transmit Lower Path Overhead (TX_LOPOH) .......................................................................... 450
19.15 VT Mapper System Interface Timing .................................................................................................... 451
19.15.1 VT Mapper DS1/E1 Receive Interface (to System Interface) .................................................... 451
19.15.2 VT Mapper DS1/E1 Transmit Interface (from System Interface) ............................................... 452
19.16 VT Mapper Lower-Order Path Overhead Interface Timing ................................................................... 452
19.16.1 VT Mapper Receive Path Overhead Interface Description ....................................................... 452
19.16.2 VT Mapper Transmit Path Overhead Interface Description ...................................................... 453
Figures
Page
Figure 38. VT Mapper Interface Diagram ............................................................................................................. 428
Figure 39. VT Mapper Functional Block Diagram................................................................................................. 429
Figure 40. Pointer Interpretation State Diagram................................................................................................... 433
Figure 41. DS1 Mode Gapped Clocking Scheme................................................................................................. 451
Figure 42. E1 Mode Gapped Clocking Scheme ................................................................................................... 451
Figure 43. DS1 Interface ...................................................................................................................................... 451
Figure 44. E1 Interface ......................................................................................................................................... 452
Figure 45. VT Mapper Receive Path Overhead Serial Access Channel .............................................................. 452
Figure 46. VT Mapper Transmit Path Overhead Serial Access Channel ............................................................. 453
Agere Systems Inc.
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TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
19 VT/TU Mapper Functional Description (continued)
Table of Contents (continued)
Tables
Table 551.
Table 552.
Table 553.
Table 554.
Table 555.
Table 556.
Table 557.
Table 558.
Table 559.
Table 560.
Table 561.
Table 562.
Table 563.
Table 564.
Table 565.
Table 566.
Table 567.
Table 568.
Table 569.
Table 570.
Table 571.
Table 572.
Table 573.
Table 574.
426
Page
VT2/TU-12 Payload Mapping ............................................................................................................ 430
VT1.5/TU-11 Payload Mapping ......................................................................................................... 430
VT2/TU-12 Locations ......................................................................................................................... 431
VT1.5/TU-11 Locations ...................................................................................................................... 431
Receive VT/TU Demapping Selection ............................................................................................... 437
Rx Signaling Behavior per Channel ................................................................................................... 439
Data Type Header Definitions ........................................................................................................... 440
Transmit VT/TU Mapping Selection per Channel, VT_TX_MAPTYPE[1—28][3:0] ........................... 441
V5 Overhead Byte Format ................................................................................................................. 443
BIP-2 Error Insertion Modes .............................................................................................................. 443
RDI-V, RFI-V, and REI-V Automatic Generation ............................................................................... 444
VT Signal Label Definition ................................................................................................................. 445
J2 Overhead Byte Insertion Modes Per Channel .............................................................................. 445
Z6/N2 Overhead Byte Insertion Modes Per Channel ........................................................................ 445
Z7/K4 Overhead Byte Insertion Modes Per Channel ........................................................................ 446
O-Bit Insertion Modes Per Channel ................................................................................................... 446
Asynchronous VT1.5 ......................................................................................................................... 447
Bit Synchronous VT1.5 ...................................................................................................................... 447
Byte Synchronous VT1.5 ................................................................................................................... 447
Asynchronous VT2 ............................................................................................................................ 448
Bit Synchronous VT2 ......................................................................................................................... 448
Byte Synchronous VT2 ...................................................................................................................... 448
VC-11 to TU-12 Conversion .............................................................................................................. 449
Framing Byte Generation Per Channel ............................................................................................. 450
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
19 VT/TU Mapper Functional Description (continued)
19.1 VT/TU Mapper Introduction
This section describes the requirements of the SONET/SDH virtual tributary payload mapping block. This block
supports the following mappings:
■
28 asynchronous, byte synchronous, or bit synchronous DS1 signals into seven virtual tributary groups (VTGs).
■
28 asynchronous, byte synchronous, or bit synchronous DS1 signals into seven tributary unit groups (TUG-2s).
■
28 asynchronous, byte synchronous, or bit synchronous J1 signals into seven virtual tributary groups (VTGs).
■
28 asynchronous, byte synchronous, or bit synchronous J1 signals into seven tributary unit groups (TUG-2s).
■
21 asynchronous, byte synchronous, or bit synchronous E1 signals into seven tributary unit groups (TUG-2s).
■
Any valid DS1/E1 combination resulting in mixed VTGs and TUG-2s.
Additionally, this block has two auxiliary channels: one for DS1/E1 signaling insertion and drop, and another for
low-order path overhead (LOPOH) insertion and drop. Control inputs and outputs for each internal block are specified, along with appropriate control register bit definitions.
19.2 VT/TU Mapper Features
■
Maps T1/E1/J1 into VT/TU structures:
— T1 into VT1.5/TU-11/TU-12.
— J1 into VT1.5/TU-11/TU-12.
— E1 into VT2/TU-12.
■
Supports asynchronous, byte synchronous, and bit synchronous mappings.
■
Supports automatic generation or microprocessor overwrite of one bit RDI and one bit RFI.
■
Supports automatic generation or microprocessor overwrite of enhanced RDI.
■
Supports ADM applications via tributary loopback and tributary pointer processing.
■
Supports unidirectional path switch ring (UPSR) applications via low-order path overhead access channel.
■
Supports five J2 trace identifier modes.
■
Programmable BIP-2 error insertion.
■
Monitors BIP-2 bit error rate.
■
Programmable clear-on-read/clear-on-write registers.
■
Supports automatic AIS generation for downstream devices.
■
VC-BIP-2, VC-REI one second error counters.
■
Programmable saturation or rollover of internal counters.
■
Complies with GR-253-CORE, G.707, T1.105, G.704, G.783, JT-G707, GR-499, ETS 300 417-1-1.
Agere Systems Inc.
427
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
19 VT/TU Mapper Functional Description (continued)
19.3 VT/TU Mapper Functional Block Diagram
The following block diagram shows a high-level view of the VT/TU mapper block and the interface to the T1/E1
framer, cross connect, SPE mapper (SPEMPR), digital jitter attenuator (DJA), and control (microprocessor interface).
LOPOHVALIDOUT
DJA
LOPOHDATAOUT
RDI, REI PATH, AND LINE ALARMS RECEIVE
TMUX
SPEMPR RDI, REI
RX PATH SIGNALING
DATA CLOCK
ALARM CONTROL
DATA CLOCK
FSYNC ALARM
RECEIVE VT/TU MAPPER
RECEIVE
SPE
SPEMPR
[28:1]
FRAMER
CROSS
CONNECT
TRIBUTARY
LOOPBACK
RDI-V
REI-V
DATA
DATA CLOCK
FSYNC ALARM
TRANSMIT
SPE
SPEMPR
[28:1]
TRANSMIT VT/TU MAPPER
CLOCK CONTROL
TX PATH SIGNALING
TUG3 RDI, REI
CONTROL INTERFACE
E1XCLK
DS1XCLK
LOPOHDATAIN
LOPOHCLKIN
LOPOHVALIDIN
RDI, REI PATH, AND LINE ALARMS
TRANSMIT
TMUX
5-9011(F)r.2
Figure 38. VT Mapper Interface Diagram
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Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
19 VT/TU Mapper Functional Description (continued)
SPE MAPPER
RDI_L
REI_L[4:0]
RDI_P[2:0]
REI_P[3:0]
TMUX
RDI[2:0]
REI[3:0]
RECEIVE PATH
SIGNALING TO
FRAMERS
LOPOHVALIDOUT
LOPOHDATAOUT
DEVICE I/O
RX_LOPOH
RX_VTSIG
SPE MAPPER
J0TIME
DS1/E1 TO
CROSS CONNECT
J2MON
RAI[28:1]
AUTO_AIS[28:1]
DATA[28:1]
VTDEMUX
OUTSEL
CLK[28:1]
VTRXDATA[7:0]
VTTERM
x28
FSYNC[28:1]
DEVICE I/O
DS1XCLK
J1TIME
RX_EN
CLK7M_RX
VTPI
X28
E1XCLK
VT LOOPBACK (VTLBSEL = 1)
CLK7M_TX
V1TIME
TX_EN
DS1/E1 FROM
CROSS CONNECT
DATA[28:1]
CLK[28:1]
FSYNC[28:1]
VTMUX
INSEL
X28
TES
X28
VTTXDATA[7:0]
VTGEN
X28
RAI[28:1]
DEVICE I/O
RDI[2:0]
REI[3:0]
RDI_L
REI_L[4:0]
TRANSMIT PATH
SIGNALING FROM
FRAMERS
TX_LOPOH
TUG3_RDI[2:0]
TUG3_REI[3:0]
16-BIT MICROPROCESSOR
INTERFACE
TX_VTSIG
LOPOHCLKIN
LOPOHDATAIN
LOPOHVALIDIN
SOFTWARE REGISTERS
TMUX
SPE MAPPER
5-9012(F)
Figure 39. VT Mapper Functional Block Diagram
Agere Systems Inc.
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TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
19 VT/TU Mapper Functional Description (continued)
19.4 VT/TU Mappings
Table 551. VT2/TU-12 Payload Mapping
Column
X
1 2 •••
J1
V
T
2
#
1
B3
C2
V •••
T
2
#
2
G1
2 2 2 •••
0 1 2
V
T
2
#
2
0
V
T
2
#
2
1
V •••
T
2
#
1
2 X 2 •••
8
9
V
T
2
#
7
F
I
X
E
D
V •••
T
2
#
8
4 4 4 •••
1 2 3
V
T
2
#
2
0
V
T
2
#
2
1
V •••
T
2
#
1
5 X 5 •••
6
7
V
T
2
#
1
4
S
T
U
F
F
F2
H4
Z3
F
I
X
E
D
V •••
T
2
#
1
5
6 6 •••
3 4
V
T
2
#
2
1
8 8
3 4
V •••
T
2
#
1
V
T
2
#
2
1
V
T
2
#
2
0
S
T
U
F
F
Z4
Z5
Table 552. VT1.5/TU-11 Payload Mapping
Column
X
1
2
•••
2
7
2
8
X 2
9
3
0
•••
5
5
5
6
X 5
7
5
8
•••
8
3
J1
V
T
1
.
5
#
1
V
T
1
.
5
#
2
•••
v
T
1
.
5
#
2
7
V
T
1
.
5
#
2
8
F
I
X
E
D
V
T
1
.
5
#
S 1
T
U
F
F
V
T
1
.
5
#
2
•••
V
T
1
.
5
#
2
7
V
T
1
.
5
#
2
8
F
I
X
E
D
V
T
1
.
5
#
S 1
T
U
F
F
V
T
1
.
5
#
2
•••
V V
T T
1 1
. .
5 5
# #
2 2
7 8
B3
C2
G1
F2
H4
Z3
8
4
Z4
Z5
430
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
19 VT/TU Mapper Functional Description (continued)
19.5 VT/TU Locations
Table 554. VT1.5/TU-11 Locations
Table 553. VT2/TU-12 Locations
VTG
VT
E1*
Columns†
1
1
1
1, 22, 43, 64
2
1
2
2, 23, 44, 65
3
1
3
3, 24, 45, 66
4
1
4
4, 25, 46, 67
5
1
5
5, 26, 47, 68
6
1
6
6, 27, 48, 69
7
1
7
7, 28, 49, 70
1
2
8
8, 29, 50, 71
2
2
9
9, 30, 51, 72
3
2
10
10, 31, 52, 73
4
2
11
11, 32, 53, 74
5
2
12
12, 33, 54, 75
6
2
13
13, 34, 55, 76
7
2
14
14, 35, 56, 77
1
3
15
15, 36, 57, 78
2
3
16
16, 37, 58, 79
3
3
17
17, 38, 59, 80
4
3
18
18, 39, 60, 81
5
3
19
19, 40, 61, 82
6
3
20
20, 41, 62, 83
7
3
21
21, 42, 63, 84
* This column is for the I/O of the VTMPR. The cross connect can be
provisioned to map any external E1 to any VT2.
† See VT2/TU-12 Payload Mapping on page 430.
VTG
VT
DS1*
Columns†
1
1
1
1, 29, 57
2
1
2
2, 30, 58
3
1
3
3, 31, 59
4
1
4
4, 32, 60
5
1
5
5, 33, 61
6
1
6
6, 34, 62
7
1
7
7, 35, 63
1
2
8
8, 36, 64
2
2
9
9, 37, 65
3
2
10
10, 38, 66
4
2
11
11, 39, 67
5
2
12
12, 40, 68
6
2
13
13, 41, 69
7
2
14
14, 42, 70
1
3
15
15, 43, 71
2
3
16
16, 44, 72
3
3
17
17, 45, 73
4
3
18
18, 46, 74
5
3
19
19, 47, 75
6
3
20
20, 48, 76
7
3
21
21, 49, 77
1
4
22
22, 50, 78
2
4
23
23, 51, 79
3
4
24
24, 52, 80
4
4
25
25, 53, 81
5
4
26
26, 54, 82
6
4
27
27, 55, 83
7
4
28
28, 56, 84
* This column is for the I/O of the VTMPR. The cross connect can be
provisioned to map any external DS1 to any VT1.5.
† See VT1.5/TU-11 Payload Mapping on page 430.
Agere Systems Inc.
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TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
19 VT/TU Mapper Functional Description (continued)
19.6 VT/TU Mapper Receive Path Description
This section describes all necessary functions of the receive logic (see Figure 39, right to left):
■
Virtual tributary demultiplexor (VTDEMUX)
■
Virtual tributary pointer interpreter (VTPI)
■
Virtual tributary terminator (VTTERM)
■
Output selector (OUTSEL)
■
J2 16-byte sequence monitor (J2MON)
■
Receive VT/TU signaling (RX_VTSIG)
■
Receive low-order path overhead (RX_LOPOH)
19.7 VT Demultiplexer (VTDEMUX)
The VTDEMUX logic block (in Figure 39 on page429 ) will perform all necessary functions to decode which virtual
tributary (VT) is active on the data bus.
This block monitors the H4 byte and frames on the H4 multiframe indication. In frame (VT_H4LOMF = 0
(Table 176)) will be declared following two consecutive, nonerrored multiframe indications. A multiframe indication
consists of four consecutive frames containing a (00, 01, 10, 11) pattern in the two LSBs of the H4 byte. Once
framed, H4 loss of multiframe (VT_H4LOMF = 1) will be declared following the number of consecutive mismatches
in the H4 multiframe indication programmed into bits VT_H4_NTIME[3:0] (Table 182). Loss of H4 multiframe alignment will generate AIS downstream. A change in H4 multiframe alignment is indicated by bit VT_H4LOMF_D
(Table 168) and will generate an interrupt unless the mask is set (VT_H4LOMF_M = 1 (Table 180)).
Bits VT_RX_GRP_TYPE[6:0] (Table 180) are programmed to determine whether the incoming tributary is a
VT1.5/TU-11 or a VT2/TU-12.
See Table 551 through Table 554 on page 430 through page 431 for VT/TU mapping formats.
19.8 VT Pointer Interpreter (VTPI)
The VTPI logic block (in Figure 39 on page429 ) will perform all necessary functions to support VT/TU pointer interpretation. The following features are implemented:
The pointer interpreter consists of the following states:
■
Loss of pointer (LOP-V)
■
VT-AIS (AIS-V) (all ones in V1 and V2)
■
NDF enabled (NDF) (1001, 0001, 1101, 1011, 1000)
■
Normal (NORM) (disabled NDF, normal pointer)
■
Increment (INC) (inverted I bits)
■
Decrement (DEC) (inverted D bits)
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19 VT/TU Mapper Functional Description (continued)
NDF ENABLE
INC
DEC
3 NEW POINTERS
3 ANY
POINTERS
3 ANY
POINTERS
NDF
DECREMENT
INDICATION ENABLE
INCREMENT
INDICATION
3 NEW POINTERS
3 NEW POINTERS
NORM
3 ANY POINTERS
NDF
NDF ENABLE
NDF
ENABLE
8 INVALID
POINTERS
FROM ALL STATES
8 INVALID POINTERS*
FROM ALL STATES
3 AIS INDICATIONS
NDF
ENABLE
3 NEW POINTERS
LOP
*
8 INVALID POINTERS
AIS
8 NDF ENABLE
5-9007(F)
* This state diagram is based on the ETS 417-1-1 pointer interpretation state diagram (Figure B.1). Transitions of eight invalid pointers from the
INC, DEC, and NDF states into the LOP state have been added.
Figure 40. Pointer Interpretation State Diagram
■
The pointer interpreter will transition into the LOP-V state based on the following conditions:
— Continuous NDF. If NDF (1001, 0001, 1101, 1011, 1000) is received for the number of consecutive superframes programmed in bits VT_NDF_NTIME[3:0] (Table 183), then LOP-V will be declared.
— Invalid pointer values. If the number of consecutive superframes programmed in register bits
VT_INV_NTIME[3:0] (Table 183) are received with a pointer that is not a normal value, NDF, AIS-V, increment,
or decrement, then LOP-V will be declared. The SS bits contribute to an invalid pointer indication.
■
The pointer interpreter will transition out of the LOP-V state based on the following conditions:
— Following three consecutive superframes with all ones in the V1 and V2 bytes the pointer interpreter will transition from the LOP-V state into the AIS-V state.
— Following three new consecutive, consistent, and valid pointers the pointer interpreter will transition from the
LOP-V state into the NORM state.
— The pointer interpreter does not transition from the LOP-V state into the NDF state.
■
The pointer interpreter will transition into the AIS-V state based on the following conditions:
— Following three consecutive superframes with all ones in the V1 and V2 bytes AIS-V will be declared.
■
The pointer interpreter will transition out of the AIS-V state based on the following conditions:
— Following three new consecutive, consistent, and valid pointers the pointer interpreter will transition from the
AIS-V state into the NORM state.
— Following the number of consecutive invalid pointers programmed in bits VT_INV_NTIME[3:0], the pointer interpreter will transition from the AIS-V state into the LOP-V state.
— If NDF is enabled on the incoming V1 and V2 bytes, the pointer interpreter will transition from the AIS-V state
into the NDF state.
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19 VT/TU Mapper Functional Description (continued)
■
The pointer interpreter will transition into the NDF state based on the following conditions:
— If NDF is enabled on the incoming V1 and V2 bytes, the pointer interpreter will transition from the NORM, NDF,
AIS, INC, and DEC states into the NDF state.
■
The pointer interpreter will transition out of the NDF state based on the following conditions:
— Continuous NDF. If NDF (1001, 0001, 1101, 1011, 1000) is received for the number of consecutive superframes programmed in bits VT_NDF_NTIME[3:0] (Table 183), the pointer interpreter will transition from the
NDF state into the LOP-V state.
— Following any three consecutive, consistent, and valid pointers, the pointer interpreter will transition from the
NDF state into the NORM state.
— Following three consecutive superframes with all ones in the V1 and V2 bytes, the pointer interpreter will transition from the NDF state into the AIS-V state.
— Following three new consecutive, consistent, and valid pointers, the pointer interpreter will transition from the
NDF state into the NORM state.
— Following the number of consecutive invalid pointers programmed in bits VT_INV_NTIME[3:0] (Table 183), the
pointer interpreter will transition from the NDF state into the LOP-V state.
■
The pointer interpreter will transition into the NORM state based on the following conditions:
— Following three new consecutive, consistent, and valid pointers, the pointer interpreter will transition into the
NORM state.
— Following any three consecutive, consistent, and valid pointers, the pointer interpreter will transition into the
NORM state. i.e., transitioning from the INC, DEC, and NDF states.
■
The pointer interpreter will transition out of the NORM state based on the following conditions:
— Following the number of consecutive invalid pointers programmed in bits VT_INV_NTIME[3:0], the pointer interpreter will transition from the NORM state into the LOP-V state.
— If NDF is enabled on the incoming V1 and V2 bytes, the pointer interpreter will transition from the NORM state
into the NDF state.
— Following three consecutive superframes with all ones in the V1 and V2 bytes, the pointer interpreter will transition from the NORM state into the AIS-V state.
— When operating in the 8 of 10 mode (VT_8ORMAJORITY = 1 (Table 181)), if 8 of the 10 I and D bits are correct
for a pointer decrement on the incoming V1 and V2 bytes, the pointer interpreter will transition from the NORM
state into the DEC state. Otherwise, if 3 of the 5 I bits and 3 of the 5 D bits are correct for a pointer decrement
on the incoming V1 and V2 bytes, the pointer interpreter will transition from the NORM state into the DEC state.
— When operating in the 8 of 10 mode (VT_8ORMAJORITY = 1), if 8 of the 10 I and D bits are correct for a pointer
increment on the incoming V1 and V2 bytes, the pointer interpreter will transition from the NORM state into the
INC state. Otherwise, if 3 of the 5 I bits and 3 of the 5 D bits are correct for a pointer increment on the incoming
V1 and V2 bytes, the pointer interpreter will transition from the NORM state into the INC state.
■
The pointer interpreter will transition into the INC state based on the following conditions:
— When operating in the 8 of 10 mode (VT_8ORMAJORITY = 1), if 8 of the 10 I and D bits are correct for a pointer
increment on the incoming V1 and V2 bytes, the pointer interpreter will transition into the INC state. Otherwise,
if 3 of the 5 I bits and 3 of the 5 D bits are correct for a pointer increment on the incoming V1 and V2 bytes, the
pointer interpreter will transition into the INC state.
■
The pointer interpreter will transition out of the INC state based on the following conditions:
— If NDF is enabled on the incoming V1 and V2 bytes, the pointer interpreter will transition from the INC state into
the NDF state.
— Following three consecutive superframes with all ones in the V1 and V2 bytes, the pointer interpreter will transition from the INC state into the AIS-V state.
— Following three new consecutive, consistent, and valid pointers, the pointer interpreter will transition from the
INC state into the NORM state.
— Following any three consecutive, consistent, and valid pointers, the pointer interpreter will transition from the
INC state into the NORM state.
— Following the number of consecutive invalid pointers programmed in bits VT_INV_NTIME[3:0], the pointer interpreter will transition from the INC state into the LOP-V state.
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19 VT/TU Mapper Functional Description (continued)
■
The pointer interpreter will transition into the DEC state based on the following conditions:
— When operating in the 8 of 10 mode (VT_8ORMAJORITY = 1 (Table 181)), if 8 of the 10 I and D bits are correct
for a pointer decrement on the incoming V1 and V2 bytes, the pointer interpreter will transition into the DEC
state. Otherwise, if 3 of the 5 I bits and 3 of the 5 D bits are correct for a pointer decrement on the incoming V1
and V2 bytes, the pointer interpreter will transition into the DEC state.
■
The pointer interpreter will transition out of the DEC state based on the following conditions:
— If NDF is enabled on the incoming V1 and V2 bytes, the pointer interpreter will transition from the DEC state
into the NDF state.
— Following three consecutive superframes with all ones in the V1 and V2 bytes, the pointer interpreter will transition from the DEC state into the AIS-V state.
— Following three new consecutive, consistent, and valid pointers, the pointer interpreter will transition from the
DEC state into the NORM state.
— Following any three consecutive, consistent, and valid pointers, the pointer interpreter will transition from the
DEC state into the NORM state.
— Following the number of consecutive invalid pointers programmed in bits VT_INV_NTIME[3:0] (Table 183), the
pointer interpreter will transition from the DEC state into the LOP-V state.
Pointer increments and decrements are monitored and counted internally. The performance monitoring reset signal
transfers the count to the holding registers for pointer increment (VT_PTR_INC[1—28][3:0] (Table 208)), and
pointer decrement (VT_PTR_DEC[1—28][3:0] (Table 208)) for microprocessor read and resets the running count
registers to 0. When SMPR_SAT_ROLLOVER = 1 (Table 67), the internal running counts will hold at their maximum value. Otherwise, the counts will roll over. The running count and holding register counts will be forced to 0, if
the SPE mapper is requesting AUTO AIS or VT_LOP[1—28] = 1 (loss of pointer) (Table 177) or VT_AIS[1—28] = 1
(VT AIS) (Table 177) (or VT_H4LOMF = 1 (loss of H4 multiframe alignment) (Table 176)).
LOP-V (VT_LOP) and AIS-V (VT_AIS) will be detected and reported to the microprocessor. Both the LOP-V and
AIS-V conditions will contribute to the VT/TU mapper automatic AIS generation that is driven over a 28-bit internal
output bus to the cross connect (XC). Any change in state of VT_LOP or VT_AIS will be reported to the microprocessor via VT_LOP_D[1—28] and VT_AIS_D[1—28] (Table 169). Unless the appropriate mask bit is set
(VT_LOP_M[1—28] or VT_AIS_M[1—28]) (Table 173), VT_LOP_D[1—28] = 1 or VT_AIS_D[1—28] = 1 will generate an interrupt.
A check for VT/TU size mismatches is performed by comparing the expected VT/TU size bits (VT1.5 = 11,
VT2 = 10) with the actual received SS bits in the V1 byte. After three consecutive mismatches, size errors will be
reported with bit VT_SIZERR[1—28] (Table 177). Any change in state of VT_SIZERR[1—28] will be reported with
bit VT_SIZERR_D[1—28] (Table 169). Unless the VT_SIZERR_M[1—28] (Table 173) mask bit is set,
VT_SIZERR_D[1—28] = 1 will generate an interrupt.
The accepted pointer is stored and accessible by the microprocessor.
This block supports tributary loopback.
19.9 VT Termination (VTTERM)
The VTTERM logic block (in Figure 39) will perform all necessary functions to support complete VT/TU termination.
The following features are implemented.
19.9.1 V5 Termination
The V5 byte is checked for BIP-2 errors. If BIP-2 errors are detected, REI-V is transmitted in the V5 byte of the corresponding transmit VT, if enabled by bit VT_REI_EN[1—28] = 1 (Table 198). BIP-2 errors and reception of REI-V
in the V5 byte is counted on a per-superframe basis. BIP-2 errors can counted on either a bit or block basis
selected by bit, VT_BIT_BLOCK_CNT (1 = bit, 0 = block) (Table 181).
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19 VT/TU Mapper Functional Description (continued)
BIP-2 errors and REI-V reception are monitored and counted internally. The performance monitoring reset signal
transfers the count to the holding registers for BIP-2 error count (VT_BIP2ERR_CNT[1—28][11:0]; Table 206), and
REI-V count (VT_REI_CNT[1—28][10:0] (Table 207)) for microprocessor read, and resets the running count registers to 0. When SMPR_SAT_ROLLOVER = 1 (Table 67), the internal running counts will hold at their maximum
value. Otherwise, the counts will roll over. The running count and holding register counts will be forced to 0, if the
SPE mapper is requesting AUTO AIS, VT_LOP[1—28] = 1 (loss of pointer), VT_AIS[1—28] = 1 (VT AIS)
(Table 177) or VT_H4LOMF = 1 (loss of H4 multiframe alignment) (Table 176).
The V5 byte will be checked for received RFI-V via VT_RFI[1—28] bits (Table 177). New values will be latched into
the register after the number of consecutive values programmed in bits VT_RDI_NTIME[3:0] (Table 184) have been
received. A VT_RFI[1—28] change of state is reported by bit VT_RFI_D[1—28] (Table 169). When operating in the
DS1 byte synchronous mode, RFI-V = 1 will force DS1 RAI downstream to the framer. Unless the VT_RFI_M mask
bit (Table 173) is set, VT_RFI_D[1—28] = 1 will generate and cause an interrupt.
When operating in normal RDI-V mode (VT_RX_ERDI_EN[1—28] = 1 (Table 204, starting on page168 )), the V5
byte will be checked for received RDI-V and reported via VT_RDI[1—28] bits (Table 177). New values will be
latched to this register after VT_RDI_NTIME[3:0] consecutive values have been received. A VT_RDI[1—28]
change of state is reported via VT_RDI_D[1—28] (Table 169). Unless the VT_RDI_M[1—28] (Table 173) mask bit
is set, VT_RDI_D[1—28] = 1 will generate and cause an interrupt.
When operating in enhanced RDI-V mode (VT_RX_ERDI_EN[1—28] = 0 (Table 204, starting on page168 )), the
V5 byte will be checked for received RDI-V and reported via VT_RDI[1—28] bit (Table 177). New values will be
latched to this register after VT_ERDI_NTIME[3:0] (Table 184) consecutive ERDI-V values (V5 bit 8 and Z7 bits
5—7) have been received. A VT_ERDI[1—28][2:0] change of state is reported via VT_ERDI_D[1—28] (Table 169).
Unless the VT_ERDI_M[1—28] mask bit (Table 173) is set, VT_ERDI_D[1—28] = 1 will generate and cause an
interrupt.
The V5 byte VT/TU signal label will be monitored and reported to the microprocessor using bits
VT_LAB[1—28][2:0] (Table 177). New values will be latched to the microprocessor after the number of consecutive
values programmed in bits VT_LAB_NTIME[3:0] (Table 184) have been received. An all zeros signal label will set
bit VT_UNEQ[1—28] (Table 177). Any change in state of VT_UNEQ[1—28] will be reported to the microprocessor
via bit VT_UNEQ_D[1—28] (Table 169). Unless the VT_UNEQ_M[1—28] (Table 173) mask bit is set,
VT_UNEQ_D[1—28] = 1 will generate an interrupt. VT_UNEQ[1—28] will contribute to automatic AIS generation.
The latched signal label will be compared to the expected signal label. If the expected signal label is 001 or if
VT_UNEQ[1—28] is detected, the detection of PLM-V is disabled. Otherwise, any mismatch is reported to the
microprocessor via bit VT_PLM[1—28] (Table 177). Any change in state of VT_PLM[1—28] will be reported to the
microprocessor via bit VT_PLM_D[1—28] (Table 169). Unless the VT_PLM_M[1—28] mask bit is set (Table 173),
VT_PLM_D[1—28] = 1 will generate an interrupt.
19.9.2 Z6/N2 Termination
For SONET applications, the Z6 byte is monitored and presented to the microprocessor using bits
VT_Z6_BYTE[1—28][7:0] (Table 205) for growth and monitoring purposes only. The Z6 byte is updated to when
three consecutive consistent bytes are received. N2 is defined for tandem connection applications per
ETS 300 417-1-1 and ITU-T G.707/G.783. Low-order tandem connection is not supported.
19.9.3 Z7/K4 Termination
This termination will support enhanced RDI when bit VT_RX_ERDI_EN[1—28] = 1(Table 204, starting on
page 168). The Z7/K4[3:1] byte will be monitored and reported to the microprocessor with bits
VT_ERDI[1—28][2:0] (Table 177). New values will be latched to the microprocessor after the number of consecutive values programmed in register bits VT_ERDI_NTIME[3:0] (Table 184) have been received. A change of state is
reported using bit VT_ERDI_D[1—28] (Table 169). Unless the VT_ERDI_M[1—28] (Table 173) mask bit is set,
VT_ERDI_D[1—28] = 1 will generate an interrupt.
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19 VT/TU Mapper Functional Description (continued)
The Z7/K4[7:4] byte will be monitored and reported to the microprocessor via bits VT_APS[1—28][3:0] (Table 178).
New values will be latched to the microprocessor after the number of consecutive values programmed in bits
VT_APS_NTIME[3:0] (Table 184) have been received. A change of state is reported using bit VT_APS_D[1—28]
(Table 169). Unless the VT_APS_M[1—28] (Table 173) mask bit is set, VT_APS_D[1—28] = 1 will generate an
interrupt.
19.9.4 Payload Termination
Payload termination will support asynchronous, byte synchronous, and bit synchronous demappings for SONET
VT1.5s and VT2s per Bellcore GR-253 and ANSI T1.105.
Payload termination will support asynchronous, byte synchronous, and bit synchronous demappings for
SDH TU11s and TU12s per ITU-T G.707 and ETS 300 417-4-1.
Demapping modes are selected with bits VT_RX_MAPTYPE[1—28][3:0] ( Table 204, starting on page168 ), as
defined in Table 555.
Table 555. Receive VT/TU Demapping Selection
VT_RX_MAPTYPE[1—28][3:0] (See Table 204.)
Description
0
0
0
0
Asynchronous VT1.5/TU-11 (DS1 output)
0
0
0
1
Asynchronous VT2/TU-12 (E1 output)
0
0
1
0
Byte synchronous VT1.5/TU-11 (DS1 output)
0
0
1
1
Byte synchronous VT2/TU-12 (E1 output)
0
1
0
0
Bit synchronous VT1.5/TU-11 (DS1 output)
0
1
0
1
Bit synchronous VT2/TU-12 (E1 output)
0110—0111
Undefined, generates AIS
1
0
0
0
Asynchronous VT2/TU-12 (DS1 output)
1
0
0
1
Byte synchronous VT2/TU-12 (DS1 output)
1
0
1
0
Bit synchronous VT2/TU-12 (DS1 output)
1011—1111
Undefined, generates AIS
The payload termination provides an elastic store for rate adoption. An elastic store overflow is indicated in bit
VT_RX_ESOVFL_D[1—28] (Table 169). Unless the VT_RX_ESOVFL_M[1—28] mask bit is set (Table 173),
VT_RX_ESOVFL_D[1—28] = 1 will generate an interrupt.
When an overflow condition exists, the read/write count will be forced to the center of the FIFO. The FIFO is 64 bits
deep.
The payload termination circuitry will generate a gapped DS1/E1 clock (VT_TERM_CLK). Figure 41 and Figure 42
on page451 describe the DS1 and E1 gapped clocking schemes, respectively. A frame sync is generated and
transmitted from the device coincident with the frame bit for DS1 and the MSB of time slot 0 for E1 when demapping a byte synchronous payload.
19.10 Output Signal Selection (OUTSEL)
The OUTSEL logic block (in Figure 39 on page429 ) will perfor