Dual Channel, 128-/256-Position, I2C, Nonvolatile Digital Potentiometer AD5122A/AD5142A Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM 10 kΩ and 100 kΩ resistance options Resistor tolerance: 8% maximum Wiper current: ±6 mA Low temperature coefficient: 35 ppm/°C Wide bandwidth: 3 MHz Fast start-up time < 75 μs Linear gain setting mode Single- and dual-supply operation Independent logic supply: 1.8 V to 5.5 V Wide operating temperature: −40°C to +125°C 3 mm × 3 mm package option 4 kV ESD protection VLOGIC VDD INDEP POWER-ON RESET AD5122A/ AD5142A RDAC1 INPUT REGISTER 1 RESET SCL SDA B1 SERIAL INTERFACE RDAC2 7/8 INPUT REGISTER 2 ADDR1 A2 W2 B2 EEPROM MEMORY GND 10939-001 ADDR0 APPLICATIONS A1 W1 VSS Portable electronics level adjustment LCD panel brightness and contrast controls Programmable filters, delays, and time constants Programmable power supplies Figure 1. GENERAL DESCRIPTION The AD5122A/AD5142A potentiometers provide a nonvolatile solution for 128-/256-position adjustment applications, offering guaranteed low resistor tolerance errors of ±8% and up to ±6 mA current density in the Ax, Bx, and Wx pins. The low resistor tolerance and low nominal temperature coefficient simplify open-loop applications as well as applications requiring tolerance matching. The linear gain setting mode allows independent programming of the resistance between the digital potentiometer terminals, through RAW and RWB the string resistors, allowing very accurate resistor matching. The high bandwidth and low total harmonic distortion (THD) ensure optimal performance for ac signals, making it suitable for filter design. The low wiper resistance of only 40 Ω at the ends of the resistor array allows for pin-to-pin connection. Table 1. Family Models Model AD51231 AD5124 AD5124 AD51431 AD5144 AD5144 AD5144A AD5122 AD5122A AD5142 AD5142A AD5121 AD5141 1 Channel Quad Quad Quad Quad Quad Quad Quad Dual Dual Dual Dual Single Single Position 128 128 128 256 256 256 256 128 128 256 256 128 256 Interface I2C SPI/I2C SPI I2C SPI/I2C SPI I2C SPI I2C SPI I2C SPI/I2C SPI/I2C Package LFCSP LFCSP TSSOP LFCSP LFCSP TSSOP TSSOP LFCSP/TSSOP LFCSP/TSSOP LFCSP/TSSOP LFCSP/TSSOP LFCSP LFCSP Two potentiometers and two rheostats. The wiper values can be set through an I2C-compatible digital interface that is also used to read back the wiper register and EEPROM contents. The AD5122A/AD5142A are available in a compact, 16-lead, 3 mm × 3 mm LFCSP and a 16-lead TSSOP. The parts are guaranteed to operate over the extended industrial temperature range of −40°C to +125°C. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2012 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD5122A/AD5142A Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 RDAC Register and EEPROM .................................................. 20 Applications ....................................................................................... 1 Input Shift Register .................................................................... 20 Functional Block Diagram .............................................................. 1 I2C Serial Data Interface ............................................................ 20 General Description ......................................................................... 1 I2C Address.................................................................................. 20 Revision History ............................................................................... 2 Advanced Control Modes ......................................................... 22 Specifications..................................................................................... 3 EEPROM or RDAC Register Protection ................................. 23 Electrical Characteristics—AD5122A ....................................... 3 INDEP Pin................................................................................... 23 Electrical Characteristics—AD5142A ....................................... 6 RDAC Architecture .................................................................... 26 Interface Timing Specifications .................................................. 9 Programming the Variable Resistor ......................................... 26 Shift Register and Timing Diagrams ....................................... 10 Programming the Potentiometer Divider ............................... 27 Absolute Maximum Ratings .......................................................... 11 Terminal Voltage Operating Range ......................................... 27 Thermal Resistance .................................................................... 11 Power-Up Sequence ................................................................... 27 ESD Caution ................................................................................ 11 Layout and Power Supply Biasing ............................................ 27 Pin Configurations and Function Descriptions ......................... 12 Outline Dimensions ....................................................................... 28 Typical Performance Characteristics ........................................... 14 Ordering Guide .......................................................................... 29 Test Circuits ..................................................................................... 19 Theory of Operation ...................................................................... 20 REVISION HISTORY 12/12—Rev. 0 to Rev. A Changes to Table 9 .......................................................................... 20 10/12—Revision 0: Initial Version Rev. A | Page 2 of 32 Data Sheet AD5122A/AD5142A SPECIFICATIONS ELECTRICAL CHARACTERISTICS—AD5122A VDD = 2.3 V to 5.5 V, VSS = 0 V; VDD = 2.25 V to 2.75 V, VSS = −2.25 V to −2.75 V; VLOGIC = 1.8 V to 5.5 V, −40°C < TA < +125°C, unless otherwise noted. Table 2. Parameter DC CHARACTERISTICS—RHEOSTAT MODE (ALL RDACs) Resolution Resistor Integral Nonlinearity 2 Resistor Differential Nonlinearity2 Nominal Resistor Tolerance Resistance Temperature Coefficient3 Wiper Resistance3 Bottom Scale or Top Scale Nominal Resistance Match DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (ALL RDACs) Integral Nonlinearity 4 Differential Nonlinearity4 Full-Scale Error Zero-Scale Error Voltage Divider Temperature Coefficient3 Symbol Test Conditions/Comments N R-INL Min Typ 1 Max 7 RAB = 10 kΩ VDD ≥ 2.7 V VDD < 2.7 V RAB = 100 kΩ VDD ≥ 2.7 V VDD < 2.7 V R-DNL ΔRAB/RAB (ΔRAB/RAB)/ΔT × 106 RW Unit Bits −1 −2.5 ±0.1 ±1 +1 +2.5 LSB LSB −0.5 −1 −0.5 −8 +0.5 +1 +0.5 +8 Code = full scale Code = zero scale RAB = 10 kΩ RAB = 100 kΩ ±0.1 ±0.25 ±0.1 ±1 35 LSB LSB LSB % ppm/°C 55 130 125 400 Ω Ω RAB = 10 kΩ RAB = 100 kΩ Code = 0xFF −1 40 60 ±0.2 80 230 +1 Ω Ω % RAB = 10 kΩ RAB = 100 kΩ −0.5 −0.25 −0.25 ±0.1 ±0.1 ±0.1 +0.5 +0.25 +0.25 LSB LSB LSB RAB = 10 kΩ RAB = 100 kΩ −1.5 −0.5 −0.1 ±0.1 +0.5 LSB LSB RBS or RTS RAB1/RAB2 INL DNL VWFSE VWZSE (ΔVW/VW)/ΔT × 106 RAB = 10 kΩ RAB = 100 kΩ Code = half scale Rev. A | Page 3 of 32 1 0.25 ±5 1.5 0.5 LSB LSB ppm/°C AD5122A/AD5142A Parameter RESISTOR TERMINALS Maximum Continuous Current Terminal Voltage Range 5 Capacitance A, Capacitance B3 Capacitance W3 Common-Mode Leakage Current3 DIGITAL INPUTS Input Logic3 High Low Input Hysteresis3 Input Current3 Input Capacitance3 DIGITAL OUTPUTS Output High Voltage3 Output Low Voltage3 Data Sheet Symbol Negative Supply Current EEPROM Store Current3, 6 EEPROM Read Current3, 7 Logic Supply Current Power Dissipation 8 Power Supply Rejection Ratio Min RAB = 10 kΩ RAB = 100 kΩ −6 −1.5 VSS Typ 1 Max Unit +6 +1.5 VDD mA mA V IA, IB, and IW CA, CB CW VINH f = 1 MHz, measured to GND, code = half scale RAB = 10 kΩ RAB = 100 kΩ f = 1 MHz, measured to GND, code = half scale RAB = 10 kΩ RAB = 100 kΩ VA = V W = V B −500 VLOGIC = 1.8 V to 2.3 V VLOGIC = 2.3 V to 5.5 V 0.8 × VLOGIC 0.7 × VLOGIC VINL VHYST IIN CIN VOH VOL Three-State Leakage Current Three-State Output Capacitance POWER SUPPLIES Single-Supply Power Range Dual-Supply Power Range Logic Supply Range Positive Supply Current Test Conditions/Comments 25 12 pF pF 12 5 ±15 pF pF nA +500 0.2 × VLOGIC 0.1 × VLOGIC ±1 5 RPULL-UP = 2.2 kΩ to VLOGIC ISINK = 3 mA ISINK = 6 mA, VLOGIC > 2.3 V VLOGIC −1 0.4 0.6 +1 V V V µA pF 5.5 ±2.75 VDD VDD V V V V 5.5 µA nA µA mA µA nA µW dB 2 VSS = GND IDD ISS IDD_EEPROM_STORE IDD_EEPROM_READ ILOGIC PDISS PSRR Single supply, VSS = GND Dual supply, VSS < GND VIH = VLOGIC or VIL = GND VDD = 5.5 V VDD = 2.3 V VIH = VLOGIC or VIL = GND VIH = VLOGIC or VIL = GND VIH = VLOGIC or VIL = GND VIH = VLOGIC or VIL = GND VIH = VLOGIC or VIL = GND ∆VDD/∆VSS = VDD ± 10%, code = full scale Rev. A | Page 4 of 32 2.3 ±2.25 1.8 2.25 −5.5 0.7 400 −0.7 2 320 1 3.5 −66 V V V V µA pF 120 −60 Data Sheet Parameter DYNAMIC CHARACTERISTICS 9 Bandwidth Total Harmonic Distortion Resistor Noise Density VW Settling Time AD5122A/AD5142A Symbol Test Conditions/Comments BW −3 dB RAB = 10 kΩ RAB = 100 kΩ VDD/VSS = ±2.5 V, VA = 1 V rms, VB = 0 V, f = 1 kHz RAB = 10 kΩ RAB = 100 kΩ Code = half scale, TA = 25°C, f = 10 kHz RAB = 10 kΩ RAB = 100 kΩ VA = 5 V, VB = 0 V, from zero scale to full scale, ±0.5 LSB error band RAB = 10 kΩ RAB = 100 kΩ RAB = 10 kΩ RAB = 100 kΩ THD eN_WB tS Crosstalk (CW1/CW2) CT Analog Crosstalk Endurance 10 CTA Min TA = 25°C Typ 1 Unit 3 0.43 MHz MHz −80 −90 dB dB 7 20 nV/√Hz nV/√Hz 2 12 10 25 −90 1 µs µs nV-sec nV-sec dB Mcycles kcycles Years 100 Data Retention 11 Max 50 Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V. Resistor integral nonlinearity (R-INL) error is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to (0.7 × VDD)/RAB. 3 Guaranteed by design and characterization, not subject to production test. 4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground referenced bipolar signal adjustment. 6 Different from operating current; supply current for EEPROM program lasts approximately 30 ms. 7 Different from operating current; supply current for EEPROM read lasts approximately 20 µs. 8 PDISS is calculated from (IDD × VDD) + (ILOGIC × VLOGIC). 9 All dynamic characteristics use VDD/VSS = ±2.5 V, and VLOGIC = 2.5 V. 10 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C to +125°C. 11 Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime, based on an activation energy of 1 eV, derates with junction temperature in the Flash/EE memory. 1 2 Rev. A | Page 5 of 32 AD5122A/AD5142A Data Sheet ELECTRICAL CHARACTERISTICS—AD5142A VDD = 2.3 V to 5.5 V, VSS = 0 V; VDD = 2.25 V to 2.75 V, VSS = −2.25 V to −2.75 V; VLOGIC = 1.8 V to 5.5 V, −40°C < TA < +125°C, unless otherwise noted. Table 3. Parameter DC CHARACTERISTICS—RHEOSTAT MODE (ALL RDACs) Resolution Resistor Integral Nonlinearity 2 Resistor Differential Nonlinearity2 Nominal Resistor Tolerance Resistance Temperature Coefficient3 Wiper Resistance3 Bottom Scale or Top Scale Nominal Resistance Match DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (ALL RDACs) Integral Nonlinearity 4 Differential Nonlinearity4 Full-Scale Error Zero-Scale Error Voltage Divider Temperature Coefficient3 Symbol Test Conditions/Comments N R-INL Min Typ 1 Max 8 RAB = 10 kΩ VDD ≥ 2.7 V VDD < 2.7 V RAB = 100 kΩ VDD ≥ 2.7 V VDD < 2.7 V R-DNL ΔRAB/RAB (ΔRAB/RAB)/ΔT × 106 RW Unit Bits −2 −5 ±0.2 ±1.5 +2 +5 LSB LSB −1 −2 −0.5 −8 ±0.1 ±0.5 ±0.2 ±1 35 +1 +2 +0.5 +8 LSB LSB LSB % ppm/°C 55 130 125 400 Ω Ω −1 40 60 ±0.2 80 230 +1 Ω Ω % RAB = 10 kΩ RAB = 100 kΩ −1 −0.5 −0.5 ±0.2 ±0.1 ±0.2 +1 +0.5 +0.5 LSB LSB LSB RAB = 10 kΩ RAB = 100 kΩ −2.5 −1 −0.1 ±0.2 +1 LSB LSB Code = full scale Code = zero scale RAB = 10 kΩ RAB = 100 kΩ RBS or RTS RAB = 10 kΩ RAB = 100 kΩ Code = 0xFF RAB1/RAB2 INL DNL VWFSE VWZSE (ΔVW/VW)/ΔT × 106 RAB = 10 kΩ RAB = 100 kΩ Code = half scale Rev. A | Page 6 of 32 1.2 0.5 ±5 3 1 LSB LSB ppm/°C Data Sheet Parameter RESISTOR TERMINALS Maximum Continuous Current Terminal Voltage Range 5 Capacitance A, Capacitance B3 Capacitance W3 Common-Mode Leakage Current3 DIGITAL INPUTS Input Logic3 High Low Input Hysteresis3 Input Current3 Input Capacitance3 DIGITAL OUTPUTS Output High Voltage3 Output Low Voltage3 AD5122A/AD5142A Symbol Negative Supply Current EEPROM Store Current3, 6 EEPROM Read Current3, 7 Logic Supply Current Power Dissipation 8 Power Supply Rejection Ratio Min RAB = 10 kΩ RAB = 100 kΩ −6 −1.5 VSS Typ 1 Max Unit +6 +1.5 VDD mA mA V IA, IB, and IW CA, CB CW VINH f = 1 MHz, measured to GND, code = half scale RAB = 10 kΩ RAB = 100 kΩ f = 1 MHz, measured to GND, code = half scale RAB = 10 kΩ RAB = 100 kΩ VA = V W = V B −500 VLOGIC = 1.8 V to 2.3 V VLOGIC = 2.3 V to 5.5 V 0.8 × VLOGIC 0.7 × VLOGIC VINL VHYST IIN CIN VOH VOL Three-State Leakage Current Three-State Output Capacitance POWER SUPPLIES Single-Supply Power Range Dual-Supply Power Range Logic Supply Range Positive Supply Current Test Conditions/Comments 25 12 pF pF 12 5 ±15 pF pF nA +500 0.2 × VLOGIC 0.1 × VLOGIC ±1 5 RPULL-UP = 2.2 kΩ to VLOGIC ISINK = 3 mA ISINK = 6 mA, VLOGIC > 2.3 V VLOGIC −1 0.4 0.6 +1 V V V µA pF 5.5 ±2.75 VDD VDD V V V V 5.5 µA nA µA mA µA nA µW dB 2 VSS = GND IDD ISS IDD_EEPROM_STORE IDD_EEPROM_READ ILOGIC PDISS PSR Single supply, VSS = GND Dual supply, VSS < GND VIH = VLOGIC or VIL = GND VDD = 5.5 V VDD = 2.3 V VIH = VLOGIC or VIL = GND VIH = VLOGIC or VIL = GND VIH = VLOGIC or VIL = GND VIH = VLOGIC or VIL = GND VIH = VLOGIC or VIL = GND ∆VDD/∆VSS = VDD ± 10%, code = full scale Rev. A | Page 7 of 32 2.3 ±2.25 1.8 2.25 −5.5 0.7 400 −0.7 2 320 1 3.5 −66 V V V V µA pF 120 −60 AD5122A/AD5142A Parameter DYNAMIC CHARACTERISTICS 9 Bandwidth Total Harmonic Distortion Resistor Noise Density VW Settling Time Data Sheet Symbol Test Conditions/Comments BW −3 dB RAB = 10 kΩ RAB = 100 kΩ VDD/VSS = ±2.5 V, VA = 1 V rms, VB = 0 V, f = 1 kHz RAB = 10 kΩ RAB = 100 kΩ Code = half scale, TA = 25°C, f = 10 kHz RAB = 10 kΩ RAB = 100 kΩ VA = 5 V, VB = 0 V, from zero scale to full scale, ±0.5 LSB error band RAB = 10 kΩ RAB = 100 kΩ RAB = 10 kΩ RAB = 100 kΩ THD eN_WB tS Crosstalk (CW1/CW2) CT Analog Crosstalk Endurance 10 CTA Min TA = 25°C Typ 1 Unit 3 0.43 MHz MHz −80 −90 dB dB 7 20 nV/√Hz nV/√Hz 2 12 10 25 −90 1 µs µs nV-sec nV-sec dB Mcycles kcycles Years 100 Data Retention 11 Max 50 Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V. Resistor integral nonlinearity (R-INL) error is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to (0.7 × VDD)/RAB. 3 Guaranteed by design and characterization, not subject to production test. 4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground referenced bipolar signal adjustment. 6 Different from operating current; supply current for EEPROM program lasts approximately 30 ms. 7 Different from operating current; supply current for EEPROM read lasts approximately 20 µs. 8 PDISS is calculated from (IDD × VDD) + (ILOGIC × VLOGIC). 9 All dynamic characteristics use VDD/VSS = ±2.5 V, and VLOGIC = 2.5 V. 10 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C to +125°C. 11 Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime, based on an activation energy of 1 eV, derates with junction temperature in the Flash/EE memory. 1 2 Rev. A | Page 8 of 32 Data Sheet AD5122A/AD5142A INTERFACE TIMING SPECIFICATIONS VLOGIC = 1.8 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 4. Parameter 1 fSCL 2 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t11A t12 tSP 3 tRESET tEEPROM_PROGRAM 4 tEEPROM_READBACK tPOWER_UP 5 tRESET Test Conditions/Comments Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Min Fast mode Standard mode Fast mode Fast mode 0.1 20 + 0.1 CL Typ 4.0 0.6 4.7 1.3 250 100 0 0 4.7 0.6 4 0.6 4.7 1.3 4 0.6 Max 100 400 1000 300 300 300 1000 300 1000 Unit kHz kHz µs µs µs µs ns ns µs µs µs µs µs µs µs µs µs µs ns ns ns ns ns ns ns 300 300 300 50 10 ns ns ns ns µs 50 30 75 ms µs µs µs 3.45 0.9 20 + 0.1 CL 20 + 0.1 CL 20 + 0.1 CL 20 + 0.1 CL 0 15 7 30 Description Serial clock frequency SCL high time, tHIGH SCL low time, tLOW Data setup time, tSU; DAT Data hold time, tHD; DAT Setup time for a repeated start condition, tSU; STA Hold time (repeated) for a start condition, tHD; STA Bus free time between a stop and a start condition, tBUF Setup time for a stop condition, tSU; STO Rise time of SDA signal, tRDA Fall time of SDA signal, tFDA Rise time of SCL signal, tRCL Rise time of SCL signal after a repeated start condition and after an acknowledge bit, tRCL1 (not shown in Figure 3) Fall time of SCL signal, tFCL Pulse width of suppressed spike (not shown in Figure 3) RESET low time (not shown in Figure 3) Memory program time (not shown in Figure 3) Memory readback time (not shown in Figure 3) Power-on EEPROM restore time (not shown in Figure 3) Reset EEPROM restore time (not shown in Figure 3) Maximum bus capacitance is limited to 400 pF. The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate; however, it has a negative effect on the EMC behavior of the part. 3 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode. 4 The EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at lower temperatures and higher write cycles. 5 Maximum time after VDD − VSS is equal to 2.3 V. 1 2 Rev. A | Page 9 of 32 AD5122A/AD5142A Data Sheet SHIFT REGISTER AND TIMING DIAGRAMS C3 C2 C1 C0 A3 A2 A1 DB8 DB7 A0 D7 DB0 (LSB) D6 D5 D4 D3 D2 D1 D0 10939-002 DB15 (MSB) DATA BITS ADDRESS BITS CONTROL BITS Figure 2. Input Shift Register Contents t11 t12 t6 t8 t2 SCL t5 t1 t6 t4 t10 t3 t9 t7 P S S Figure 3. I2C Serial Interface Timing Diagram (Typical Write Sequence) Rev. A | Page 10 of 32 P 10939-003 SDA Data Sheet AD5122A/AD5142A ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 5. Parameter VDD to GND VSS to GND VDD to VSS VLOGIC to GND VA, VW, VB to GND IA, IW, IB Pulsed 1 Frequency > 10 kHz RAW = 10 kΩ RAW = 100 kΩ Frequency ≤ 10 kHz RAW = 10 kΩ RAW = 100 kΩ Digital Inputs Operating Temperature Range, TA 3 Maximum Junction Temperature, TJ Maximum Storage Temperature Range Reflow Soldering Peak Temperature Time at Peak Temperature Package Power Dissipation ESD 4 FICDM Rating −0.3 V to +7.0 V +0.3 V to −7.0 V 7V −0.3 V to VDD + 0.3 V or +7.0 V (whichever is less) VSS − 0.3 V, VDD + 0.3 V +7.0 V (whichever is less) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θJA is defined by the JEDEC JESD51 standard, and the value is dependent on the test board and test environment. Table 6. Thermal Resistance Package Type 16-Lead LFCSP 16-Lead TSSOP ±6 mA/d 2 ±1.5 mA/d2 1 ±6 mA/√d2 ±1.5 mA/√d2 −0.3 V to VLOGIC + 0.3 V or +7 V (whichever is less) −40°C to +125°C 150°C θJA 89.51 150.41 JEDEC 2S2P test board, still air (0 m/sec airflow). ESD CAUTION −65°C to +150°C 260°C 20 sec to 40 sec (TJ max − TA)/θJA 4 kV 1.5 kV Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 2 d = pulse duty factor. 3 Includes programming of EEPROM memory. 4 Human body model (HBM) classification. 1 Rev. A | Page 11 of 32 θJC 3 27.6 Unit °C/W °C/W AD5122A/AD5142A Data Sheet 14 ADDR0 PIN 1 INDICATOR VSS 5 12 SDA 11 SCL 10 VLOGIC 9 VDD B2 8 TOP VIEW (Not to Scale) W2 7 B1 4 A2 6 W1 3 AD5122A/ AD5142A A1 2 NOTES 1. INTERNALLY CONNECT THE EXPOSED PAD TO VSS. 10939-004 GND 1 13 ADDR1 16 RESET 15 INDEP PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 4. 16-Lead LFCSP Pin Configuration Table 7. 16-Lead LFCSP Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Mnemonic GND A1 W1 B1 VSS A2 W2 B2 VDD VLOGIC SCL SDA ADDR1 ADDR0 INDEP 16 RESET EPAD Description Ground Pin, Logic Ground Reference. Terminal A of RDAC1. VSS ≤ VA ≤ VDD. Wiper Terminal of RDAC1. VSS ≤ VW ≤ VDD. Terminal B of RDAC1. VSS ≤ VB ≤ VDD. Negative Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors. Terminal A of RDAC2. VSS ≤ VA ≤ VDD. Wiper Terminal of RDAC2. VSS ≤ VW ≤ VDD. Terminal B of RDAC2. VSS ≤ VB ≤ VDD. Positive Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors. Logic Power Supply; 1.8 V to VDD. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors. Serial Clock Line. Serial Data Input/Output. Programmable Address (ADDR1) for Multiple Package Decoding. Programmable Address (ADDR0) for Multiple Package Decoding. Linear Gain Setting Mode at Power-Up. Each string resistor is loaded from its associated memory location. If INDEP is enabled, it cannot be disabled by the software. Hardware Reset Pin. Refresh the RDAC registers from EEPROM. RESET is activated at logic low. If this pin is not used, tie RESET to VLOGIC. Internally Connect the Exposed Pad to VSS. Rev. A | Page 12 of 32 Data Sheet AD5122A/AD5142A INDEP 1 16 ADDR0 RESET 2 15 ADDR1 14 SDA 13 SCL 3 A1 4 W1 5 B1 6 AD5122A/ AD5142A 12 VLOGIC TOP VIEW (Not to Scale) 11 VDD VSS 7 10 B2 A2 8 9 W2 10939-005 GND Figure 5. 16-Lead TSSOP Pin Configuration Table 8. 16-Lead TSSOP Pin Function Descriptions Pin No. 1 Mnemonic INDEP 2 RESET 3 4 5 6 7 8 9 10 11 12 13 14 15 16 GND A1 W1 B1 VSS A2 W2 B2 VDD VLOGIC SCL SDA ADDR1 ADDR0 Description Linear Gain Setting Mode at Power-Up. Each string resistor is loaded from its associated memory location. If INDEP is enabled, it cannot be disabled by the software. Hardware Reset Pin. Refresh the RDAC registers from EEPROM. RESET is activated at logic low. If this pin is not used, tie RESET to VLOGIC. Ground Pin, Logic Ground Reference. Terminal A of RDAC1. VSS ≤ VA ≤ VDD. Wiper Terminal of RDAC1. VSS ≤ VW ≤ VDD. Terminal B of RDAC1. VSS ≤ VB ≤ VDD. Negative Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors. Terminal A of RDAC2. VSS ≤ VA ≤ VDD. Wiper Terminal of RDAC2. VSS ≤ VW ≤ VDD. Terminal B of RDAC2. VSS ≤ VB ≤ VDD. Positive Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors. Logic Power Supply; 1.8 V to VDD. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors. Serial Clock Line. Serial Data Input/Output. Programmable Address (ADDR1) for Multiple Package Decoding. Programmable Address (ADDR0) for Multiple Package Decoding. Rev. A | Page 13 of 32 AD5122A/AD5142A Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0.5 0.2 10kΩ, +125°C 10kΩ, +25°C 10kΩ, –40°C 100kΩ, +125°C 100kΩ, +25°C 100kΩ, –40°C 0.4 0.3 0.1 0 R-DNL (LSB) R-INL (LSB) 0.2 0.1 0 –0.1 –0.1 –0.2 –0.3 –0.2 –0.4 –0.3 100 0 200 CODE (Decimal) –0.6 10939-006 –0.5 10kΩ, +125°C 10kΩ, +25°C 10kΩ, –40°C 100kΩ, +125°C 100kΩ, +25°C 100kΩ, –40°C 100 0 200 CODE (Decimal) Figure 6. R-INL vs. Code (AD5142A) 10939-009 –0.5 –0.4 Figure 9. R-DNL vs. Code (AD5142A) 0.20 0.10 0.15 0.05 0.10 0 R-DNL (LSB) R-INL (LSB) 0.05 0 –0.05 –0.05 –0.10 –0.15 –0.10 10kΩ, +125°C 10kΩ, +25°C 10kΩ, –40°C 100kΩ, +125°C 100kΩ, +25°C 100kΩ, –40°C –0.25 0 –0.25 50 100 CODE (Decimal) –0.30 10kΩ, +125°C 10kΩ, +25°C 10kΩ, –40°C 0 100 Figure 10. R-DNL vs. Code (AD5122A) 0.10 10kΩ, –40°C 10kΩ, +25°C 10kΩ, +125°C 100kΩ, –40°C 100kΩ, +25°C 100kΩ, +125°C 0.2 50 CODE (Decimal) Figure 7. R-INL vs. Code (AD5122A) 0.3 100kΩ, +125°C 100kΩ, +25°C 100kΩ, –40°C 10939-010 –0.20 –0.20 10939-007 –0.15 0.05 0 DNL (LSB) 0 –0.05 –0.10 –0.15 –0.1 –0.20 –0.2 –0.3 0 100 CODE (Decimal) 200 Figure 8. INL vs. Code (AD5142A) –0.30 10kΩ, –40°C 10kΩ, +25°C 10kΩ, +125°C 0 100 CODE (Decimal) Figure 11. DNL vs. Code (AD5142A) Rev. A | Page 14 of 32 100kΩ, –40°C 100kΩ, +25°C 100kΩ, +125°C 200 10939-011 –0.25 10939-008 INL (LSB) 0.1 Data Sheet AD5122A/AD5142A 0.15 0.06 10kΩ, –40°C 10kΩ, +25°C 10kΩ, +125°C 100kΩ, –40°C 100kΩ, +25°C 100kΩ, +125°C 0.10 100kΩ, –40°C 100kΩ, +25°C 100kΩ, +125°C 0.02 0 DNL (LSB) 0.05 INL (LSB) 10kΩ, –40°C 10kΩ, +25°C 10kΩ, +125°C 0.04 0 –0.05 –0.02 –0.04 –0.06 –0.08 –0.10 –0.10 –0.14 10939-012 50 0 100 CODE (Decimal) 50 0 450 RHEOSTAT MODE TEMPERATURE COEFFICIENT (ppm/°C) 350 300 250 200 150 100 50 350 300 250 200 150 100 50 0 0 0 50 100 150 200 255 AD5142A 0 25 50 75 CODE (Decimal) 100 127 AD5122A –50 Figure 13. Potentiometer Mode Temperature Coefficient ((ΔVW/VW)/ΔT × 106) vs. Code 0 50 100 150 200 255 AD5142A 0 25 50 75 CODE (Decimal) 100 127 AD5122A Figure 16. Rheostat Mode Temperature Coefficient ((ΔRWB/RWB)/ΔT × 106) vs. Code 1200 800 700 VLOGIC = 1.8V VLOGIC = 2.3V VLOGIC = 3.3V VLOGIC = 5V VLOGIC = 5.5V 1000 ILOGIC CURRENT (µA) 500 400 IDD, VDD = 2.3V IDD, VDD = 3.3V IDD, VDD = 5V ILOGIC, VLOGIC = 2.3V ILOGIC, VLOGIC = 3.3V ILOGIC, VLOGIC = 5V 300 200 100 600 400 200 10 60 TEMPERATURE (°C) 110 125 0 0 1 2 3 4 INPUT VOLTAGE (V) Figure 17. ILOGIC Current vs. Digital Input Voltage Figure 14. Supply Current vs. Temperature Rev. A | Page 15 of 32 5 10939-017 0 –40 800 VDD = VLOGIC VSS = GND 10939-014 CURRENT (nA) 600 10939-016 –50 10kΩ 100kΩ 400 10939-013 POTENTIOMETER MODE TEMPERATURE COEFFICIENT (ppm/°C) Figure 15. DNL vs. Code (AD5122A) 100kΩ 10kΩ 400 100 CODE (Decimal) Figure 12. INL vs. Code (AD5122A) 450 10939-015 –0.12 –0.15 AD5122A/AD5142A Data Sheet 10 0 0x80, (0x40) 0 –10 0x40, (0x20) 0x20, (0x10) 0x20, (0x10) –20 0x10, (0x08) 0x10, (0x08) 0x8, (0x04) 0x8, (0x04) –30 –30 0x4, (0x02) GAIN (dB) GAIN (dB) –20 0x80, (0x40) –10 0x40, (0x20) 0x4, (0x02) 0x2, (0x01) –40 –50 –40 0x1, (0x00) 0x2, (0x01) 0x1, (0x00) 0x00 –60 0x00 –70 –50 –80 1k 10k 100k 1M 10M FREQUENCY (Hz) –90 10 10939-018 100 100 –50 0 1M 10M 10kΩ 100kΩ –10 –20 –30 THD + N (dB) –60 THD + N (dB) 100k Figure 21. 100 kΩ Gain vs. Frequency and Code 10kΩ 100kΩ VDD/VSS = ±2.5V VA = 1V rms VB = GND CODE = HALF SCALE NOISE FILTER = 22kHz 10k FREQUENCY (Hz) Figure 18. 10 kΩ Gain vs. Frequency and Code –40 1k 10939-021 AD5142A (AD5122A) AD5142A (AD5122A) –60 10 –70 –40 –50 –60 –80 –70 –80 200 2k 20k 200k FREQUENCY (Hz) –90 0.001 10939-019 –100 20 Figure 19. Total Harmonic Distortion Plus Noise (THD + N) vs. Frequency VDD/VSS = ±2.5V fIN = 1kHz CODE = HALF SCALE NOISE FILTER = 22kHz 0.01 10939-022 –90 1 0.1 VOLTAGE (V rms) Figure 22. Total Harmonic Distortion Plus Noise (THD + N) vs. Amplitude 10 20 VDD/VSS = ±2.5V RAB = 10kΩ 0 0 –10 PHASE (Degrees) –40 –60 –40 –50 –70 QUARTER SCALE MIDSCALE FULL-SCALE 100 1k –80 10k 100k 1M 10M FREQUENCY (Hz) –90 10 QUARTER SCALE MIDSCALE FULL-SCALE 100 VDD/VSS = ±2.5V RAB = 100kΩ 1k 10k 100k 1M FREQUENCY (Hz) Figure 23. Normalized Phase Flatness vs. Frequency, RAB = 100 kΩ Figure 20. Normalized Phase Flatness vs. Frequency, RAB = 10 kΩ Rev. A | Page 16 of 32 10939-023 –80 –100 10 –30 –60 10939-020 PHASE (Degrees) –20 –20 Data Sheet AD5122A/AD5142A 300 1.0 200 0.8 0.0015 0.6 0.0010 0.4 0.0005 0.2 100 0 2 1 4 3 5 VOLTAGE (V) 0 0 10939-024 0 –600 –500 –400 –300 –200 –100 0 10kΩ + 0pF 10kΩ + 75pF 10kΩ + 150pF 10kΩ + 250pF 100kΩ + 0pF 100kΩ + 75pF 100kΩ + 150pF 100kΩ + 250pF 200 300 400 500 600 VDD = 5V ±10% AC VSS = GND, VA = 4V, VB = GND CODE = MIDSCALE –20 –30 6 5 4 –40 –50 –60 3 –70 2 –90 10 0 20 40 0 10 20 80 100 120 AD5142A 40 30 CODE (Decimal) 50 60 60 AD5122A 100k 1M 10M 0.020 0.015 RELATIVE VOLTAGE (V) 0.6 0.5 0.4 0.3 0.2 0.1 0.010 0.005 0 –0.005 –0.010 5 10 TIME (µs) 15 10939-026 0 Figure 26. Maximum Transition Glitch –0.020 0 500 1000 1500 TIME (ns) Figure 29. Digital Feedthrough Rev. A | Page 17 of 32 2000 10939-029 –0.015 0 –0.1 10k Figure 28. Power Supply Rejection Ratio (PSRR) vs. Frequency 0x80 TO 0x7F, 100kΩ 0x80 TO 0x7F, 10kΩ 0.7 1k FREQUENCY (Hz) Figure 25. Maximum Bandwidth vs. Code and Net Capacitance 0.8 100 10939-025 0 10939-028 –80 1 RELATIVE VOLTAGE (V) 10kΩ 100kΩ –10 PSRR (dB) BANDWIDTH (MHz) 7 100 Figure 27. Resistor Lifetime Drift 10 8 0 RESISTOR DRIFT (ppm) Figure 24. Incremental Wiper On Resistance vs. VDD 9 CUMULATIVE PROBABILITY 400 1.2 0.0020 PROBABILITY DENSITY 500 WIPER ON RESISTANCE (Ω) 0.0025 100kΩ, V DD = 2.3V 100kΩ, V DD = 2.7V 100kΩ, V DD = 3V 100kΩ, V DD = 3.6V 100kΩ, V DD = 5V 100kΩ, V DD = 5.5V 10kΩ, VDD = 2.3V 10kΩ, VDD = 2.7V 10kΩ, VDD = 3V 10kΩ, VDD = 3.6V 10kΩ, VDD = 5V 10kΩ, VDD = 5.5V 10939-027 600 AD5122A/AD5142A 0 10kΩ 100kΩ Data Sheet 7 SHUTDOWN MODE ENABLED 6 THEORETICAL IMAX (mA) –20 –60 –80 5 4 3 2 10kΩ –100 1 100kΩ 100 1k 10k 100k 1M FREQUECNY (Hz) 10M 0 0 50 100 0 25 50 75 CODE (Decimal) 150 200 100 250 AD5142A 125 AD5122A Figure 31. Theoretical Maximum Current vs. Code Figure 30. Shutdown Isolation vs. Frequency Rev. A | Page 18 of 32 10939-031 –120 10 10939-030 GAIN (dB) –40 Data Sheet AD5122A/AD5142A TEST CIRCUITS Figure 32 to Figure 36 define the test conditions used in the Specifications section. NC VA IW V+ = VDD ±10% VDD B V+ VMS ~ Figure 32. Resistor Integral Nonlinearity Error (Rheostat Operation; R-INL, R-DNL) PSRR (dB) = 20 LOG W B 10939-032 NC = NO CONNECT A VMS PSS (%/%) = RSW = ΔVDD% 0.1V ISW CODE = 0x00 W V+ B VMS B A = NC Figure 33. Potentiometer Divider Nonlinearity Error (INL, DNL) IW = VDD/RNOMINAL DUT W VW B RW = VMS1/IW NC = NO CONNECT 10939-034 VMS1 – VSS TO VDD Figure 36. Incremental On Resistance NC A 0.1V ISW 10939-036 W + V+ = VDD 1LSB = V+/2N 10939-033 DUT A Figure 34. Wiper Resistance Rev. A | Page 19 of 32 ΔVMS ΔVDD ) ΔVMS% Figure 35. Power Supply Sensitivity and Power Supply Rejection Ratio (PSS, PSRR) DUT ( 10939-035 DUT A W AD5122A/AD5142A Data Sheet THEORY OF OPERATION The AD5122A/AD5142A digital programmable potentiometers are designed to operate as true variable resistors for analog signals within the terminal voltage range of VSS < VTERM < VDD. The resistor wiper position is determined by the RDAC register contents. The RDAC register acts as a scratchpad register that allows unlimited changes of resistance settings. A secondary register (the input shift register) can be used to preload the RDAC register data. The RDAC register can be programmed with any position setting using the I2C interface. When a desirable wiper position is found, this value can be stored in the EEPROM memory. Thereafter, the wiper position is always restored to that position for subsequent power-ups. The storing of EEPROM data takes approximately 15 ms; during this time, the device is locked and does not acknowledge any new command, preventing any changes from taking place. I2C SERIAL DATA INTERFACE The AD5122A/AD5142A have 2-wire, I2C-compatible serial interfaces. The device can be connected to an I2C bus as a slave device, under the control of a master device. See Figure 3 for a timing diagram of a typical write sequence. The AD5122A/AD5142A supports standard (100 kHz) and fast (400 kHz) data transfer modes. Support is not provided for 10-bit addressing and general call addressing. The 2-wire serial bus protocol operates as follows: 1. RDAC REGISTER AND EEPROM The RDAC register directly controls the position of the digital potentiometer wiper. For example, when the RDAC register is loaded with 0x80 (AD5142A, 256 taps), the wiper is connected to half scale of the variable resistor. The RDAC register is a standard logic register; there is no restriction on the number of changes allowed. It is possible to both write to and read from the RDAC register using the digital interface (see Table 10). 2. The contents of the RDAC register can be stored to the EEPROM using Command 9 (see Table 10). Thereafter, the RDAC register always sets at that position for any future on-off-on power supply sequence. It is possible to read back data saved into the EEPROM with Command 3 (see Table 10). 3. Alternatively, the EEPROM can be written to independently using Command 11 (see Table 16). INPUT SHIFT REGISTER For the AD5122A/AD5142A, the input shift register is 16 bits wide, as shown in Figure 2. The 16-bit word consists of four control bits, followed by four address bits and by eight data bits. If the AD5122A RDAC or EEPROM registers are read from or written to, the lowest data bit (Bit 0) is ignored. Data is loaded MSB first (Bit 15). The four control bits determine the function of the software command, as listed in Table 10 and Table 16. The master initiates a data transfer by establishing a start condition, which is when a high-to-low transition on the SDA line occurs while SCL is high. The following byte is the address byte, which consists of the 7-bit slave address and an R/W bit. The slave device corresponding to the transmitted address responds by pulling SDA low during the ninth clock pulse (this is called the acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to, or read from, its shift register. If the R/W bit is set high, the master reads from the slave device. However, if the R/W bit is set low, the master writes to the slave device. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL. When all data bits have been read from or written to, a stop condition is established. In write mode, the master pulls the SDA line high during the tenth clock pulse to establish a stop condition. In read mode, the master issues a no acknowledge for the ninth clock pulse (that is, the SDA line remains high). The master then brings the SDA line low before the tenth clock pulse, and then high again during the tenth clock pulse to establish a stop condition. I2C ADDRESS The facility to make hardwired changes to ADDR allows the user to incorporate up to nine of these devices on one bus as outlined in Table 9. Table 9. Device Address Selection ADDR0 Pin VLOGIC No connect1 GND VLOGIC No connect1 GND VLOGIC No connect1 GND 1 ADDR1 Pin VLOGIC VLOGIC VLOGIC No connect1 No connect1 No connect1 GND GND GND 7-Bit I2C Device Address 0100000 0100010 0100011 0101000 0101010 0101011 0101100 0101110 0101111 Not available in bipolar mode (VSS < 0 V) or in low voltage mode (VLOGIC = 1.8 V). Rev. A | Page 20 of 32 Data Sheet AD5122A/AD5142A Table 10. Reduced Commands Operation Truth Table Command Number 0 1 Control Bits[DB15:DB12] C3 C2 C1 C0 0 0 0 0 0 0 0 1 Address Bits[DB11:DB8]1 A3 A2 A1 A0 X X X X 0 0 0 A0 2 0 0 1 0 0 0 0 3 0 0 1 1 0 0 9 10 14 15 0 0 1 1 1 1 0 1 1 1 1 0 1 1 1 0 0 0 X A3 0 0 X 0 1 D7 X D7 Data Bits[DB7:DB0]1 D6 D5 D4 D3 D2 D1 X X X X X X D6 D5 D4 D3 D2 D1 D0 X D0 A0 D7 D6 D5 D4 D3 D2 D1 D0 A1 A0 X X X X X X D1 D0 0 0 X 0 A0 A0 X A0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 0 X D0 Operation NOP: do nothing Write contents of serial register data to RDAC Write contents of serial register data to input shift register Read back contents D1 D0 Data 0 1 EEPROM 1 1 RDAC Copy RDAC register to EEPROM Copy EEPROM into RDAC Software reset Software shutdown D0 Condition 0 Normal mode 1 Shutdown mode X = don’t care. Table 11. Reduced Address Bits Table A3 1 0 0 0 1 A2 X1 0 0 0 A1 X1 0 0 1 A0 X1 0 1 0 Channel All channels RDAC1 RDAC2 Not applicable X = don’t care. Rev. A | Page 21 of 32 Stored Channel Memory Not applicable RDAC1 Not applicable RDAC2 AD5122A/AD5142A Data Sheet ADVANCED CONTROL MODES Low Wiper Resistance Feature The AD5122A/AD5142A digital potentiometers include a set of user programming features to address the wide number of applications for these universal adjustment devices (see Table 16 and Table 18). The AD5122A/AD5142A include two commands to reduce the wiper resistance between the terminals when the device achieves full scale or zero scale. These extra positions are called bottom scale, BS, and top scale, TS. The resistance between Terminal A and Terminal W at top scale is specified as RTS. Similarly, the bottom scale resistance between Terminal B and Terminal W is specified as RBS. Key programming features include the following: • • • • • • • • Input register Linear gain setting mode A low wiper resistance feature Linear increment and decrement instructions ±6 dB increment and decrement instructions Burst mode Reset Shutdown mode The contents of the RDAC registers are unchanged by entering in these positions. There are three ways to exit from top scale and bottom scale: by using Command 12 or Command 13 (see Table 16); by loading new data in an RDAC register, which includes increment/decrement operations; or by entering shutdown mode, Command 15 (see Table 16). Input Register The AD5122A/AD5142A include one input register per RDAC register. These registers allow preloading of the value for the associated RDAC register. These registers can be written to using Command 2 and read back from using Command 3 (see Table 16). This feature allows a synchronous update of one or both RDAC registers at the same time. Table 12 and Table 13 show the truth tables for the top scale position and the bottom scale position, respectively, when potentiometer or linear gain setting mode is enabled. Table 12. Top Scale Truth Table Linear Gain Setting Mode RAW RWB RAB RAB RAW RTS Potentiometer Mode RWB RAB Table 13. Bottom Scale Truth Table The transfer from the input register to the RDAC register is done synchronously by Command 8 (see Table 16). If new data is loaded in an RDAC register, this RDAC register automatically overwrites the associated input register. Linear Gain Setting Mode The patented architecture of the AD5122A/AD5142A allows the independent control of each string resistor, RAW, and RWB. To enable linear gain setting mode, use Command 16 (see Table 16) to set Bit D2 of the control register (see Table 18). This mode of operation can control the potentiometer as two independent rheostats connected at a single point, W terminal, as opposed to potentiometer mode where each resistor is complementary, RAW = RAB − RWB. This mode enables a second input and an RDAC register per channel, as shown in Table 16; however, the actual RDAC contents remain unchanged. The same operations are valid for potentiometer and linear gain setting mode. Linear Gain Setting Mode RAW RWB RTS RBS RAW RAB Potentiometer Mode RWB RBS Linear Increment and Decrement Instructions The increment and decrement commands (Command 4 and Command 5 in Table 16) are useful for linear step adjustment applications. These commands simplify microcontroller software coding by allowing the controller to send an increment or decrement command to the device. The adjustment can be individual or in a ganged potentiometer arrangement, where all wiper positions are changed at the same time. For an increment command, executing Command 4 automatically moves the wiper to the next RDAC position. This command can be executed in a single channel or in multiple channels. If the INDEP pin is pulled high, the device powers up in linear gain setting mode and loads the values stored in the associated memory locations for each channel (see Table 17). The INDEP pin and the D2 bit are connected internally to a logic OR gate; if one or both are set to 1, the parts cannot operate in potentiometer mode. Rev. A | Page 22 of 32 Data Sheet AD5122A/AD5142A ±6 dB Increment and Decrement Instructions Reset Two programming instructions produce logarithmic taper increment or decrement of the wiper position control by an individual potentiometer or by a ganged potentiometer arrangement where all RDAC register positions are changed simultaneously. The +6 dB increment is activated by Command 6, and the −6 dB decrement is activated by Command 7 (see Table 16). For example, starting with the zero-scale position and executing Command 6 ten times moves the wiper in 6 dB steps to the fullscale position. When the wiper position is near the maximum setting, the last 6 dB increment instruction causes the wiper to go to the full-scale position (see Table 14). The AD5122A/AD5142A can be reset through software by executing Command 14 (see Table 16) or through hardware on the low pulse of the RESET pin. The reset command loads the RDAC registers with the contents of the EEPROM and takes approximately 30 µs. The EEPROM is preloaded to midscale at the factory, and initial power-up is, accordingly, at midscale. Tie RESET to VLOGIC if the RESET pin is not used. Incrementing the wiper position by +6 dB essentially doubles the RDAC register value, whereas decrementing the wiper position by −6 dB halves the register value. Internally, the AD5122A/AD5142A use shift registers to shift the bits left and right to achieve a ±6 dB increment or decrement. These functions are useful for various audio/video level adjustments, especially for white LED brightness settings in which human visual responses are more sensitive to large adjustments than to small adjustments. Table 14. Detailed Left Shift and Right Shift Functions for the ±6 dB Step Increment and Decrement Left Shift (+6 dB/Step) 0000 0000 0000 0001 0000 0010 0000 0100 0000 1000 0001 0000 0010 0000 0100 0000 1000 0000 1111 1111 Right Shift (−6 dB/Step) 1111 1111 0111 1111 0011 1111 0001 1111 0000 1111 0000 0111 0000 0011 0000 0001 0000 0000 0000 0000 The AD5122A/AD5142A can be placed in shutdown mode by executing the software shutdown command, Command 15 (see Table 16), and setting the LSB (D0) to 1. This feature places the RDAC in a zero power consumption state where the device operates in potentiometer mode, Terminal A is open-circuited and the wiper, Terminal W, is connected to Terminal B; however, a finite wiper resistance of 40 Ω is present. When the device is configured in linear gain setting mode, the resistor addressed, RAW or RWB, is internally placed at high impedance. Table 15 shows the truth table depending on the device operating mode. The contents of the RDAC register are unchanged by entering shutdown mode. However, all commands listed in Table 16 are supported while in shutdown mode. Execute Command 15 (see Table 16) and set the LSB (D0) to 0 to exit shutdown mode. Table 15. Truth Table for Shutdown Mode Linear Gain Setting Mode RAW RWB High impedance High impedance Potentiometer Mode RAW RWB High impedance RBS EEPROM OR RDAC REGISTER PROTECTION The EEPROM and RDAC registers can be protected by disabling any update to these registers. This can be done by using software or by using hardware. If these registers are protected by software, set Bit D0 and/or Bit D1 (see Table 18), which protects the RDAC and EEPROM registers independently. Burst Mode By enabling the burst mode, multiple data bytes can be sent to the part consecutively. After the command byte, the part interprets the following consecutive bytes as data bytes for the command. A new command can be sent by generating a repeat start or by a stop and start condition. The burst mode is activated by setting Bit D3 of the control register (see Table 18). Shutdown Mode When RDAC is protected, the only operation allowed is to copy the EEPROM into the RDAC register. INDEP PIN If the INDEP pin is pulled high at power-up, the part operates in linear gain setting mode, loading each string resistor, RAWX and RWBX, with the value stored into the EEPROM (see Table 17). If the pin is pulled low, the part powers up in potentiometer mode. The INDEP pin and the D2 bit are connected internally to a logic OR gate; if one or both are set to 1, the part cannot operate in potentiometer mode (see Table 18). Rev. A | Page 23 of 32 AD5122A/AD5142A Data Sheet Table 16. Advanced Command Operation Truth Table Command Number 0 1 Command Bits[DB15:DB12] C3 C2 C1 C0 0 0 0 0 0 0 0 1 Address Bits[DB11:DB8]1 A3 A2 A1 A0 X X X X 0 A2 0 A0 D7 X D7 2 0 0 1 0 0 A2 0 A0 3 0 0 1 1 X A2 A1 4 5 6 7 8 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 0 0 1 1 0 A3 A3 A3 A3 0 A2 A2 A2 A2 A2 9 0 1 1 1 0 10 11 0 1 1 0 1 0 1 0 12 1 0 0 13 1 0 14 15 1 1 16 1 1 D6 X D6 Data Bits[DB7:DB0]1 D5 D4 D3 D2 D1 X X X X X D5 D4 D3 D2 D1 D0 X D0 D7 D6 D5 D4 D3 D2 D1 D0 A0 X X X X X X D1 D0 0 0 0 0 0 A0 A0 A0 A0 A0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 0 1 0 X A2 0 A0 X X X X X X X 1 0 0 A2 0 0 A1 A0 A0 X D7 X D6 X D5 X D4 X D3 X D2 X D1 0 D0 1 A3 A2 0 A0 1 X X X X X X D0 0 1 A3 A2 0 A0 0 X X X X X X D0 0 1 1 0 1 0 X A3 X A2 X 0 X A0 X X X X X X X X X X X X X X X D0 1 0 1 X X X X X X X X D3 D2 D1 D0 Operation NOP: do nothing Write contents of serial register data to RDAC Write contents of serial register data to input register Read back contents D1 D0 Data 0 0 Input register 0 1 EEPROM 1 0 Control register 1 1 RDAC Linear RDAC increment Linear RDAC decrement +6 dB RDAC increment −6 dB RDAC decrement Copy input register to RDAC (software LRDAC) Copy RDAC register to EEPROM Copy EEPROM into RDAC Write contents of serial register data to EEPROM Top scale D0 = 0; normal mode D0 = 1; shutdown mode Bottom scale D0 = 1; enter D0 = 0; exit Software reset Software shutdown D0 = 0; normal mode D0 = 1; device placed in shutdown mode Copy serial register data to control register X = don’t care. Table 17. Address Bits A3 1 0 0 0 0 0 0 1 A2 X1 0 1 0 1 0 0 A1 X1 0 0 0 0 1 1 A0 X1 0 0 1 1 0 1 Potentiometer Mode Input Register RDAC Register All channels All channels RDAC1 RDAC1 Not applicable Not applicable RDAC2 RDAC2 Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Linear Gain Setting Mode Input Register RDAC Register All channels All channels RWB1 RWB1 RAW1 RAW1 RWB2 RWB2 RAW2 RAW2 Not applicable Not applicable Not applicable Not applicable X = don’t care. Rev. A | Page 24 of 32 Stored Channel Memory Not applicable RDAC1/RWB1 Not applicable RAW1 Not applicable RDAC2/RWB2 RAW2 Data Sheet AD5122A/AD5142A Table 18. Control Register Bit Descriptions Bit Name D0 D1 D2 D3 Description RDAC register write protect 0 = wiper position frozen to value in EEPROM memory 1 = allows update of wiper position through digital interface (default) EEPROM program enable 0 = EEPROM program disabled 1 = enables device for EEPROM program (default) Linear setting mode/potentiometer mode 0 = potentiometer mode (default) 1 = linear gain setting mode Burst mode (I2C only) 0 = disabled (default) 1 = enabled (no disable after stop or repeated start condition) Rev. A | Page 25 of 32 AD5122A/AD5142A Data Sheet RDAC ARCHITECTURE PROGRAMMING THE VARIABLE RESISTOR To achieve optimum performance, Analog Devices, Inc., has patented the RDAC segmentation architecture for all the digital potentiometers. In particular, the AD5122A/AD5142A employ a three-stage segmentation approach, as shown in Figure 37. The AD5122A/AD5142A wiper switch is designed with the transmission gate CMOS topology and with the gate voltage derived from VDD and VSS. Rheostat Operation—±8% Resistor Tolerance A A W STS B B W B The nominal resistance between Terminal A and Terminal B, RAB, is 10 kΩ or 100 kΩ, and has 128/256 tap points accessed by the wiper terminal. The 7-bit/8-bit data in the RDAC latch is decoded to select one of the 128/256 possible wiper settings. The general equations for determining the digitally programmed output resistance between Terminal W and Terminal B are RM RM RL W AD5122A: RL 7-BIT/8-BIT ADDRESS DECODER W Figure 38. Rheostat Mode Configuration RH RH A 10939-038 A The AD5122A/AD5142A operate in rheostat mode when only two terminals are used as a variable resistor. The unused terminal can be floating, or it can be tied to Terminal W, as shown in Figure 38. RWB (D ) RM RH D R AB RW 128 From 0x00 to 0x7F (1) D R AB RW 256 From 0x00 to 0xFF (2) AD5142A: RM RH RWB (D ) SBS 10939-037 B Figure 37. AD5122A/AD5142A Simplified RDAC Circuit Top Scale/Bottom Scale Architecture In addition, the AD5122A/AD5142A include new positions to reduce the resistance between terminals. These positions are called bottom scale and top scale. At bottom scale, the typical wiper resistance decreases from 130 Ω to 60 Ω (RAB = 100 kΩ). At top scale, the resistance between Terminal A and Terminal W is decreased by 1 LSB, and the total resistance is reduced to 60 Ω (RAB = 100 kΩ). where: D is the decimal equivalent of the binary code in the 7-bit/8-bit RDAC register. RAB is the end-to-end resistance. RW is the wiper resistance. In potentiometer mode, similar to the mechanical potentiometer, the resistance between Terminal W and Terminal A also produces a digitally controlled complementary resistance, RWA. RWA also gives a maximum of 8% absolute resistance error. RWA starts at the maximum resistance value and decreases as the data loaded into the latch increases. The general equations for this operation are AD5122A: RAW (D ) 128 D RAB RW 128 From 0x00 to 0x7F 256 D RAB RW 256 From 0x00 to 0xFF (4) (3) AD5142A: RAW (D ) where: D is the decimal equivalent of the binary code in the 7-bit/8-bit RDAC register. RAB is the end-to-end resistance. RW is the wiper resistance. Rev. A | Page 26 of 32 Data Sheet AD5122A/AD5142A If the part is configured in linear gain setting mode, the resistance between Terminal W and Terminal A is directly proportional to the code loaded in the associate RDAC register. The general equations for this operation are AD5122A: R AW (D ) D R AB RW 128 From 0x00 to 0x7F (5) AD5142A: TERMINAL VOLTAGE OPERATING RANGE The AD5122A/AD5142A are designed with internal ESD diodes for protection. These diodes also set the voltage boundary of the terminal operating voltages. Positive signals present on Terminal A, Terminal B, or Terminal W that exceed VDD are clamped by the forward-biased diode. There is no polarity constraint between VA, VW, and VB, but they cannot be higher than VDD or lower than VSS. VDD From 0x00 to 0xFF (6) A where: D is the decimal equivalent of the binary code in the 7-bit/8-bit RDAC register. RAB is the end-to-end resistance. RW is the wiper resistance. In the bottom scale condition or top scale condition, a finite total wiper resistance of 40 Ω is present. Regardless of which setting the part is operating in, limit the current between Terminal A to Terminal B, Terminal W to Terminal A, and Terminal W to Terminal B, to the maximum continuous current or to the pulse current specified in Table 5. Otherwise, degradation or possible destruction of the internal switch contact can occur. PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output Operation The digital potentiometer easily generates a voltage divider at wiper-to-B and wiper-to-A that is proportional to the input voltage at A to B, as shown in Figure 39. Figure 40. Maximum Terminal Voltages Set by VDD and VSS POWER-UP SEQUENCE Because there are diodes to limit the voltage compliance at Terminal A, Terminal B, and Terminal W (see Figure 40), it is important to power up VDD first before applying any voltage to Terminal A, Terminal B, and Terminal W. Otherwise, the diode is forward-biased such that VDD is powered unintentionally. The ideal power-up sequence is VSS, VDD, VLOGIC, digital inputs, and VA, VB, and VW. The order of powering VA, VB, VW, and digital inputs is not important as long as they are powered after VSS, VDD, and VLOGIC. Regardless of the power-up sequence and the ramp rates of the power supplies, once VDD is powered, the power-on preset activates, which restores EEPROM values to the RDAC registers. LAYOUT AND POWER SUPPLY BIASING VOUT B Figure 39. Potentiometer Mode Configuration Connecting Terminal A to 5 V and Terminal B to ground produces an output voltage at the Wiper W to Terminal B ranging from 0 V to 5 V. The general equation defining the output voltage at VW with respect to ground for any valid input voltage applied to Terminal A and Terminal B is VW (D) VSS R (D) RWB (D) VA AW VB RAB RAB (7) It is always a good practice to use a compact, minimum lead length layout design. Ensure that the leads to the input are as direct as possible with a minimum conductor length. Ground paths should have low resistance and low inductance. It is also good practice to bypass the power supplies with quality capacitors. Apply low equivalent series resistance (ESR) 1 μF to 10 μF tantalum or electrolytic capacitors at the supplies to minimize any transient disturbance and to filter low frequency ripple. Figure 41 illustrates the basic supply bypassing configuration for the AD5122A/AD5142A. VDD where: RWB(D) can be obtained from Equation 1 and Equation 2. RAW(D) can be obtained from Equation 3 and Equation 4. Operation of the digital potentiometer in the divider mode results in a more accurate operation over temperature. Unlike the rheostat mode, the output voltage is dependent mainly on the ratio of the internal resistors, RAW and RWB, and not the absolute values. Therefore, the temperature drift reduces to 5 ppm/°C. VSS Rev. A | Page 27 of 32 + C3 10µF C1 0.1µF + C4 10µF C2 0.1µF VDD VLOGIC AD5122A/ AD5142A C5 0.1µF C6 10µF + VLOGIC VSS GND 10939-041 W VB B A 10939-039 VA W 10939-040 D R AW (D ) R AB RW 256 Figure 41. Power Supply Bypassing AD5122A/AD5142A Data Sheet OUTLINE DIMENSIONS 3.10 3.00 SQ 2.90 0.50 BSC PIN 1 INDICATOR 16 13 1 12 EXPOSED PAD 1.75 1.60 SQ 1.45 9 TOP VIEW 0.80 0.75 0.70 4 5 8 0.50 0.40 0.30 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 0.25 MIN BOTTOM VIEW 08-16-2010-E PIN 1 INDICATOR 0.30 0.23 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6. Figure 42. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 3 mm × 3 mm Body, Very Very Thin Quad (CP-16-22) Dimensions shown in millimeters 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.65 BSC 0.30 0.19 COPLANARITY 0.10 SEATING PLANE 8° 0° COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 43. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters Rev. A | Page 28 of 32 0.75 0.60 0.45 Data Sheet AD5122A/AD5142A ORDERING GUIDE Model 1, 2 AD5122ABCPZ10-RL7 AD5122ABCPZ100-RL7 AD5122ABRUZ10 AD5122ABRUZ100 AD5122ABRUZ10-RL7 AD5122ABRUZ100-RL7 AD5142ABCPZ10-RL7 AD5142ABCPZ100-RL7 AD5142ABRUZ10 AD5142ABRUZ100 AD5142ABRUZ10-RL7 AD5142ABRUZ100-RL7 EVAL-AD5142ADBZ 1 2 RAB (kΩ) 10 100 10 100 10 100 10 100 10 100 10 100 Resolution 128 128 128 128 128 128 256 256 256 256 256 256 Interface I2 C I2 C I2 C I2 C I2 C I2 C I2 C I2 C I2 C I2 C I2 C I2 C Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 16-Lead LFCSP_WQ 16-Lead LFCSP_WQ 16-lead TSSOP 16-lead TSSOP 16-lead TSSOP 16-lead TSSOP 16-Lead LFCSP_WQ 16-Lead LFCSP_WQ 16-lead TSSOP 16-lead TSSOP 16-lead TSSOP 16-lead TSSOP Evaluation Board Package Option CP-16-22 CP-16-22 RU-16 RU-16 RU-16 RU-16 CP-16-22 CP-16-22 RU-16 RU-16 RU-16 RU-16 Z = RoHS Compliant Part. The evaluation board is shipped with the 10 kΩ RAB resistor option; however, the board is compatible with both of the available resistor value options. Rev. A | Page 29 of 32 Branding DHA DHG DH7 DH4 AD5122A/AD5142A Data Sheet NOTES Rev. A | Page 30 of 32 Data Sheet AD5122A/AD5142A NOTES Rev. A | Page 31 of 32 AD5122A/AD5142A Data Sheet NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10939-0-12/12(A) Rev. A | Page 32 of 32