Order this document by MC13028A/D The MC13028A is a third generation C–QUAM stereo decoder targeted for use in low voltage, low cost AM/FM E.T.R. radio applications. Advanced features include a signal quality detector that analyzes signal strength, signal to noise ratio, and stereo pilot tone before switching to the stereo mode. A “blend function” much like FM stereo has been added to improve the transition from mono to stereo. The audio output level is adjustable to allow easy interface with a variety of AM/FM tuner chips. The external components have been minimized to keep the total system cost low. • Adjustable Audio Output Level • • • • • • • • C–QUAM AM STEREO ADVANCED WIDE VOLTAGE IF and DECODER for E.T.R. RADIOS SEMICONDUCTOR TECHNICAL DATA 16 Stereo Blend Function 1 Stereo Threshold Adjustment P SUFFIX PLASTIC PACKAGE CASE 648 Operation from 2.2 V to 12 V Supply Precision Pilot Tone Detector Forced Mono Function Single Pinout VCO IF Amplifier with IF AGC Circuit 16 1 VCO Shutdown Mode at Weak Signal Condition D SUFFIX PLASTIC PACKAGE CASE 751B (SO–16) The purchase of the Motorola C–QUAM AM Stereo Decoder does not carry with such purchase any license by implication, estoppel or otherwise, under any patent rights of Motorola or others covering any combination of this decoder with other elements including use in a radio receiver. Upon application by an interested party, licenses are available from Motorola on its patents applicable to AM Stereo radio receivers. PIN CONNECTIONS Representative Block Diagram 16 15 14 13 VCO 12 11 10 9 B8 AM Stereo Decoder Pilot Tone Detector IF Amp Signal Quality Detector AGC Stereo Threshold Adjust AGC Bypass Filter IF Feedback Bypass 1 2 Right Channel Output 15 Left Channel Output 16 3 14 Loop Filter IF Signal Input 4 13 VCO Output Gnd 5 12 VCC Stereo Indicator Drive 6 1.0 V Reference 7 Blend 8 Pilot Signal Input 10 Pilot Q Detector Output 9 Pilot I Detector Output 11 ORDERING INFORMATION Reg Device MC13028AD 1 2 3 4 5 6 7 8 MC13028AP Operating Temperature Range TA = – 25° to +70°C Package SO–16 DIP–16 This device contains 679 active transistors. Motorola, Inc. 1996 MOTOROLA ANALOG IC DEVICE DATA Rev 2 1 MC13028A MAXIMUM RATINGS (TA = 25°C, unless otherwise noted.) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ Rating Symbol Value Unit VCC 14 Vdc Operating Junction Temperature TJ 150 °C Operating Ambient Temperature TA –25 to +70 °C Storage Temperature Range Tstg –55 to +150 °C LED Indicator Current ILED 10 mA Power Supply Input Voltage ELECTRICAL CHARACTERISTICS (VCC = 8.0 Vdc, TA = 25°C, Input Signal Level = 74 dBµV, Modulation = 1.0 kHz @ 50% Modulation, unless otherwise noted.) Characteristic Symbol Min Typ Max – – 9.0 11 11 – 22 150 80 – 33 200 130 50 44 250 180 – 35 340 80 460 106 580 THD1 THD2 THD3 – – – 0.6 0.3 – 1.8 0.6 1.5 L or R 23 35 – dB Vin – 33 – dBµV – 0.25 0.3 – Vdc – – – 50 55 48 55 – – 40 40 62 59 – – Supply Current Drain VCC = 2.2 V VCC = 8.0 V ICC Audio Output Level, L+R, Mono Modulation RO = 1.8 k, VCC = 2.2 V, Input 55 dBµV RO = 10 k, VCC = 8.0 V, Input 50 dBµV RO = 10 k, VCC = 8.0 V, Input 40 dBµV RO = 10 k, VCC = 8.0 V, Input 31 dBµV Vout Audio Output Level, L or R Only, Stereo Modulation RO = 1.8 k, VCC = 2.2 V, 55 dBµV Input RO = 10 k, VCC = 8.0 V Vout Output THD 50% Stereo, L or R Only 50% Mono, L+R 90% Mono, L+R, Input 86 dBµV Channel Separation 50% L or R Only Decoder Input Sensitivity Vout = –10 dB Force to Mono Mode, (Pin 10) Unit mA mVrms mVrms % dBµV µ Stereo Threshold Adjust (Pin 1) Pin 1 Open R1 = 15 k (Gnd) R1 = 680 k (VCC) STA Signal to Noise Ratio, RO = 10 k 50% Stereo, L or R Only 50% Mono, L+R S/N Input Impedance (Reference Specification) Rin Cin – – 10 8.0 – – kΩ pF Maximum Input Signal Level for THD ≤ 1.5% – – – 86 dBµV Blend Voltage Mono Mode Stereo Mode Out of Lock BI 0.7 1.20 – – 1.30 0.12 0.9 1.35 0.2 dB Vdc VCO Lock Range OSCtun – ± 2.5 – kHz AGC Range AGCrng – 44 – dB C–B –1.0 – 1.0 dB – – 2.5 4.0 % Channel Balance Pilot Sensitivity 2 MOTOROLA ANALOG IC DEVICE DATA MC13028A Standard Test Circuit VCC R1 Right IF Amp 1 10 k Left 15 2 + RO RO + 0.47 µF 14 3 AM Stereo Decoder IFin 4 13 47 2.2 k 2.2 k Loop 43 pF 5 Pilot Ind Signal Quality Detector B8 Gnd 7 10 µF 12 47 µF 11 6 + 47 µF + 3.6 MHz 0.01 µF LED Audio Output L 10 k AGC VCO 10 µF R 16 Reg 0.22 µF 10 0.47 µF Pilot Tone Detector Blend + 10 µF 9 8 10 µF + VCC + + 2.2 k + ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ PIN FUNCTION DESCRIPTION Pin Symbol 1 STA Internal Equivalent Circuit Description/External Circuit Requirements Stereo Threshold Adjustment Pin The function of this circuit is to provide the freedom to achieve a desired value of incoming IF signal level which will cause full stereo operation of the decoder. The level can be determined by the value of R1, a resistor from Pin 1 that can be connected to either VCC or to ground. This resistor may also be omitted in some designs (Pin 1 left open). The approximate dc level with the pin left open is 0.6 Vdc. VCC 1 2.4 k 2 AGCcap 2 AGC Filter Bypass Capacitor An electrolytic capacitor is used as a bypass filter and it sets the time constant for the AGC circuit action. The recommended capacitor value is 10 µF from Pin 2 to ground. The dc level at this pin varies as shown in the curve in Figure 13, AGC Voltage versus Input Level. 3 IFFBcap VCC IF Amplifier Feedback Capacitor A capacitor which is specified to have a low ESR at 450 kHz is normally used at Pin 3. The value recommended for this capacitor is 0.47 µF from Pin 3 to ground. This component forms a low pass filter which has a corner frequency around 30 kHz. 3 2.0 k MOTOROLA ANALOG IC DEVICE DATA 3 MC13028A ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ PIN FUNCTION DESCRIPTION Pin Symbol 4 IFin Internal Equivalent Circuit Description/External Circuit Requirements IF Amplifier Input Pin 4 is the IF input pin. The typical input impedance at this pin is 10 k. The input should be ac coupled through a 0.01 µF capacitor. 4 10 k Vref 5 Gnd Circuit 5 Gnd Supply Ground In the PCB layout, the ground pin should be connected to the chassis ground directly. This pin is the internal circuit ground and the silicon substrate ground. Substrate 6 SIND Stereo Indicator Driver This driver circuit is intended to light an LED or other indicator when the decoder receives the proper input signals and switches into the stereo mode. The maximum amount of current that the circuit can sink is 10 mA. VCC 6 A current limiting resistor is applied externally to control LED brightness versus total power supply current. 30 k 7 VRef 7 8 Regulated Voltage, 1.0 V An electrolytic capacitor used as a bypass filter is recommended from Pin 7 to ground. The capacitor value should be 10 µF. Reference Voltage 1.0 V CAPBlend Blend Cap Charging Circuit VCC Pilot Indicator Driver Circuit 8 Blend Capacitor The value of the capacitor on this pin will effect the time constant of the decoder blend function. The recommended value is 10 µF from Pin 8 to ground. The dc level at Pin 8 is internally generated in response to input signal level and signal quality. This pin is a key indicator of the operational state of the IC (see text Functional Description). It is recommended to discharge the blend capacitor externally when changing stations. Blend Algorithm Circuit 9 IPilot VCC 9 43 k Pilot I Detector Output The Pilot I Detector output requires a 10 µF electrolytic capacitor to ground. The value of this capacitor sets the pilot acquisition time. The dc level at Pin 9 is approximately 1.0 Vdc, unlocked, and 1.1 to 2.4 Vdc in the locked condition. Vreg 4 MOTOROLA ANALOG IC DEVICE DATA MC13028A ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ PIN FUNCTION DESCRIPTION Pin Symbol 10 QPilot Internal Equivalent Circuit Pilot Q Detector Output This pin is connected to the Pilot Q detector and requires a 0.47 µF capacitor to ground to filter the error line voltage at the PLL pilot tone detector. If the value of this capacitor is made too large, the decoder may be prevented from coming back into stereo after a signal drop out has been experienced in the field. The force to mono function is also accomplished at this pin by pulling the dc voltage level at the pin below 1.0 V. VCC 10 5.0 k 11 PILOTfil VCC Description/External Circuit Requirements Pilot Signal Input A capacitor to ground forms a filter for the pilot input signal. The recommended value of the capacitor is 0.22 µF. The dc level at Pin 11 is approximately 1.0 Vdc. VCC 30 k 11 2.0 k 12 VCC Supply Voltage (VCC) The operating supply voltage range is from 1.8 Vdc to 12 Vdc. VCC 12 VCC 13 OSCin 13 Vreg 2.2 k Oscillator Input The oscillator pin requires a ceramic resonator and parallel capacitor connected to ground. The recommended source for the ceramic resonator is Murata, part number CSA 3.60MGF108. A 43 pF NPO capacitor is in parallel with the resonator. The dc level at Pin 13 is approximately 1.1 Vdc. Vreg 3.1 k 3.0 k 6.3 pF MOTOROLA ANALOG IC DEVICE DATA 15 k 5 MC13028A ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ PIN FUNCTION DESCRIPTION Pin Symbol 14 LOOPFilter Internal Equivalent Circuit Description/External Circuit Requirements VCC VCC Fast Lock High Idrive 390 14 VCC Idrive Loop Filter A capacitor which forms the loop filter is connected from Pin 14 to ground. The recommended value is 47 µF in series with 47 Ω. This capacitor should be of good construction quality so it will have a very low specification for leakage current in order to prevent stereo distortion. The 47 Ω resistor in series with the capacitor controls the PLL corner frequency response, keeping the response shape critically damped and not peaked up. The dc level at Pin 14 is approximately 0.6 Vdc in the locked condition. Fast Lock Low 10 k 15 LEFTout Left Channel Audio Output This is the left channel audio output pin from which the IC can provide 1.3 µApp drive current for each percent of mono modulation. A resistor to ground sets the level of the audio output. VCC VCC 1.0 k 15 16 RIGHTout Right Channel Audio Output This is the right channel audio output pin. A resistor to ground sets the level of the audio output. See the explanation under the Left Channel Audio Output description above. VCC VCC For example, 100% (mono mod) x 1.3 µApp (IC drive per % mod) = 130 µApp flowing through the load resistor. (For a 2.2 k load, 286 mVpp is then the output signal voltage.) When dealing with stereo signals, multiply the mod level by 2; i.e. 50% (left only mod) x 2 (stereo factor) x 1.3 µApp (IC drive per % mod) = 130 µApp flowing through the load resistor. 1.0 k 16 6 MOTOROLA ANALOG IC DEVICE DATA MC13028A Figure 1. Typical Circuit for E.T.R. Applications NRSC Roll–Off Filter VCC RO Right Output Left Output 16 0.22 µF (Note 2) RO (Note 4) + 47 µF (Note 1) 47 43 pF (Note 3) 15 13 14 12 Pilot Input 11 0.47 µF 10 µF + + Pilot Q Input 10 Pilot I Input 9 + 47 µF B8 VCO Optional Force to Mono Pilot Tone Detector AM Stereo Decoder IF Amp Signal Quality Detector AGC Reg RF AGC’d IF Signal from Mixer (450 kHz from Tuner IC Section) 1 Stereo Threshold Adjust + R1 10 µF 2 3 AGC IF Bypass Bypass + 0.47 µF (Note 5) 0.01 µF 4 IF Input 5 Gnd 6 7 Ref Stereo Indicator + 10 µF 8 Blend + 10 µF (Note 6) Scan Mute NOTES: 1. The 47 µF capacitor is recommended to be a low leakage type capacitor. Leakage current due to this capacitor causes increase in stereo distortion and decreased separation performance. 2. The recommended source for this part is Murata Products. CSA3.60MGF108. The location of this part should be carefully considered during the layout of the decoder circuit. This part should not be near the audio signal paths, the 25 Hz pilot filter lines, or the VCC high current lines, and the ceramic element ground line should be direct to the chassis ground lead in order to avoid any oscillator inter–modulation. 3. The 43 pF capacitor is recommended to be a NPO type ceramic part. Changing the value of this capacitor alters the lock range of the decoder PLL. 4. The tolerance on the value of the 0.22 µF capacitor should be within ± 20% for the full design temperature range of operation. Any reduction in the value of this capacitor due to temperature excursions will reduce the pilot tone circuit sensitivity. 5. The 0.47 µF capacitor is recommended to be a low ESR type capacitor, (less than 1.5 Ω) in order to avoid increased audio output distortions under weak input signal conditions with higher modulation levels. 6. The scan/mute function is located on the Blend pin at Pin 8. To provide this function, Pin 8 should be pulled down below 0.3 V until the decoder and the synthesizer have both locked to a new station. MOTOROLA ANALOG IC DEVICE DATA 7 MC13028A FUNCTIONAL DESCRIPTION Introduction The MC13028A is designed as a low voltage, low cost decoder for the C–QUAM AM Stereo technology and is completely compatible with existing monaural AM transmissions. The IC requires relatively few, inexpensive external parts to produce a full featured C–QUAM AM Stereo implementation. The layout is straightforward and should produce excellent stereo performance. This device performs the function of IF amplification, AGC, modulation detection, pilot tone detection, signal quality inspection, and left and right audio output matrix operation. The IC is targeted for use in portable and home AM Stereo radio applications. A simple overview follows which traces the path of the input signal information to the MC13028A all the way to the audio output pins of the decoder IC. From the appropriate pin of an AM IC, the IF amplifier circuit of the MC13028A receives its input at Pin 4 as a 450 kHz, typically modulated C–QUAM signal. The input signal level for stereo operation can vary from 47 dBµV to about 90 dBµV. A specific threshold level between these limits can be designed into a receiver by the choice of the resistor value for R1 connected to Pin 1. This IC design incorporates feedback in the IF circuit section which provides excellent dc balance in the IF amplifier. This balanced condition also guarantees excellent monophonic performance from the decoder. An IF feedback filter at Pin 3 is formed by a 0.47 µF low leakage capacitor. It is used to filter out the unwanted audio which is present on the IF amplifier feedback line at higher modulation levels under weak input RF signal conditions. Elimination of the unwanted signal helps to decrease the amount of distortion in the audio output of the stereo decoder under these particular input conditions. An AGC circuit controls the level of IF signal which is subsequently fed to the detector circuits. An AGC bypass capacitor is connected to Pin 2 and forms a single pole low pass filter. The value of this part also sets the time constant for the AGC circuit action. The amplified C–QUAM IF signal is fed simultaneously to the envelope detector circuit, and to a C–QUAM converter circuit. The envelope detector provides the L+R (mono) signal output which is fed to the stereo matrix. In the converter circuit, the C–QUAM signal is restored to a Quam signal. This is accomplished by dividing the C–QUAM IF signal by the demodulated cos φ term. The cos φ term is derived from the phase modulated IF signal in an active feedback loop. Cosine φ is detected by comparing the envelope detector and the in–phase detector outputs in the high speed comparator/feedback loop. Cosine φ is extracted from the I detector output and is actively transferred through feedback to the output of the comparator. The output of the comparator is in turn fed to the control input of the divider, thus closing the feedback loop of the converter circuit. In this process, the cos φ term is removed from the divider IF output, thus allowing direct detection of the L–R by the quadrature detector. The audio outputs from both the envelope and the L–R detectors are first filtered to minimize the second harmonic of the IF signal. Then they are fed into a matrix 8 circuit where the Left channel and the Right channel outputs can be extracted at Pins 15 and 16. (The outputs from the I and Q detectors are also filtered similarly.) At this time, a stereo indicator driver circuit, which can sink up to 10 mA, is also enabled. The stereo output will occur if the input IF signal is: larger than the stereo threshold level, not too noisy, and if a proper pilot tone is present. If these three conditions are not met, the blend circuit will begin to force monaural operation at that time. A blend circuit is included in this design because conditions occur during field use that can cause input signal strength fluctuation, strong unwanted co–channel or power line interference, and/or multi–path or re–radiation. When these aberrant conditions occur, rapid switching between stereo and mono might occur, or the stereo quality might be degraded enough to sound displeasing. Since these conditions could be annoying to the normal listener, the stereo information is blended towards a monaural output. This circuit action creates a condition for listening where these aberrant effects are better tolerated by the consumer. Intentional mono operation is a feature sometimes required in receiver designs. There are several ways in which to accomplish this feat. First, a resistor from Pin 10 to ground can be switched into the circuit. A value of 1.0 k is adequate as is shown in the schematic in Figure 18. A second method to force the decoder into mono is simply to shunt Pin 10 to ground through an NPN transistor (collector to Pin 10, emitter to ground), where the base lead is held electrically “high” to initiate the action. A third method to force a mono condition upon the decoder is to shunt Pin 8 of the decoder to ground through an NPN transistor as described above. Effectively, this operation discharges the blend capacitor (10 µF), and the blend function takes over internally forcing the decoder into mono. This third method does not necessarily require extra specific parts for the forced mono function as the first two examples do. The reason for this is that most electronically tuned receiver designs require an audio muting function during turn on/turn off, tuning/scanning, or band switching (FM to AM). When the muting function is designed into an AM Stereo receiver, it also should include a blend capacitor reset (discharge) function which is accomplished in this case by the use of an NPN transistor shunting Pin 8 to ground, (thus making the addition of a forced mono function almost “free”). The purpose of the blend reset during muting is to re–initialize the decoder back into the “fast lock” mode from which stereo operation can be attained much quicker after any of the interruptive activities mentioned earlier, (i.e. turn on, tuning, etc.). The VCO in this IC is a phase shift oscillator type design that operates with a ceramic resonator at eight times the IF frequency, or 3.60 MHz. With IF input levels below the stereo threshold level, the oscillator is not operational. This feature helps to eliminate audio tweets under low level, noisy input conditions. MOTOROLA ANALOG IC DEVICE DATA MC13028A The phase locked loop (PLL) in the MC13028A is locked to the L–R signal. This insures good stereo distortion performance at the higher levels of left only or right only modulations. Under normal operating conditions, the PLL remains locked because of the current flow capability of the loop driver circuit. This high gain, high impedance circuit performs optimally when the current flow is balanced. The balanced condition is enhanced by the loop driver filter circuit connected between Pin 14 and ground. The filter circuit consists of a 47 Ω resistor in series with a 47 µF capacitor. The 47 Ω resistor is to set the Fast Lock rate. It is recommended that the capacitor be a very low leakage type electrolytic, or a tantalum composition part because any significant amount of leakage current flowing through the capacitor will unbalance the loop driver circuit and result in less than optimum stereo performance, see Figures 10 and 11. The pilot tone detector circuit is fed internally from the Q detector output signal. The circuit input employs a low pass filter at Pin 11 that is designed to prevent the pilot tone detector input from being overloaded by higher levels of L–R modulation. The filter is formed by a 0.22 µF capacitor and the input impedance of the first amplifier. A pilot I detector circuit employs a capacitor to ground at Pin 9 to operate in conjunction with an internal resistor to create an RC integration time. The value of the capacitor determines the amount of time required to produce a stereo indication. This amount must include the time it takes to check for the presence of detector falsing due to noise or interference, station retuning by the customer, and pilot dropout in the presence of heavy interference. The pilot Q detector utilizes a filter on its pilot tone PLL error line at Pin 10. This capacitor to ground (usually 0.47 µF) is present to filter any low frequency L–R information that may be present on the error line. If the value of this capacitor is allowed to be too small, L–R modulation ripple on the error line may get large enough to cause stereo dropout. If the capacitor value is made too large, the pilot tone may be prevented from being reacquired if it is somehow lost due to fluctuating field conditions. A 1.0 V reference level is created internally from the VCC source to the IC. This regulated line is used extensively by circuits throughout the MC13028A design. An electrolytic capacitor from Pin 7 to ground is used as a filter for the reference voltage. DISCUSSION OF GRAPHS AND FIGURES If the general recommendations put forth in this application guide are followed, excellent stereo performance should result. The curves in Figures 2 through 7 depict the separation and the distortion performance in stereo for 30%, 50%, and 65% single channel modulations respectively. The data for these figures were collected under the conditions of VCC = 8.0 V and RO = 10 k in both the left and the right channels as applied to the application circuit of Figure 1. A very precise laboratory generator was used to produce the AM Stereo test signal of 450 kHz at 70 dBµV fed to Pin 4. An NRSC post detection filter was not present at the time of these measurements. The audio separation shows an average performance at 30% and 50% modulations of – 45 dB in the frequency range of 2.0 kHz to 5.0 kHz. The corresponding audio distortions under these conditions are about 0.28% at 30% modulation, and about 0.41% at 50% modulation. Figure 6 shows that the typical separation at 65% modulation in the 2.0 kHz to 5.0 kHz region is about – 37 dB, and the corresponding audio distortion shown in Figure 7 is about 1.0%. The performance level of these sinusoidal signals is somewhat less than those discussed in the MOTOROLA ANALOG IC DEVICE DATA previous paragraph due to the internal operation of the clamping circuits. In the field, the transmitters at AM Stereo radio stations are not usually permitted to modulate single channel levels past 70%. Therefore these conditions do not occur very often during normal broadcast material. The roll–off at both the low and high frequencies of the 30% single channel driven responses is due to the fact that a post detection bandpass filter of 60 Hz to 10 kHz was used in the measurement of the data, while a post detection filter of 2.0 Hz to 20 kHz was used for the collection of data in the 50% and 65% modulation examples. The tighter bandwidth was used while collecting the performance data at 30% modulation levels in order to assure that the distortion measurement was indicative of the true distortion products measured near the noise floor and thus not encumbered by residual noise and hum levels which would erroneously add to the magnitude of the harmonic distortion data. Note in Figure 8 the traces of noise response for the four different bandwidths of post detection filtering. It can be seen that the noise floors improve steadily with increasing levels of incoming 450 kHz as the value of the lower corner frequency of the filter is increased. Data for the stereo noise floors was collected with the decoder in the forced stereo mode. 9 MC13028A Figure 2. Single Channel Separation at 30% Modulation Figure 3. Single Channel Distortion at 30% Modulation 0 10 Desired Channel See Text DISTORTION (%) SEPARATION (dB) –10 – 20 Undesired Channel – 30 1.0 – 40 – 50 100 1.0 k 0.1 10 k 100 f, FREQUENCY (Hz) 1.0 k 10 k f, FREQUENCY (Hz) Figure 4. Single Channel Separation at 50% Modulation Figure 5. Single Channel Distortion at 50% Modulation 0 10 Desired Channel DISTORTION (%) SEPARATION (dB) –10 – 20 Undesired Channel – 30 1.0 – 40 – 50 100 1.0 k 0.1 10 k 100 f, FREQUENCY (Hz) 1.0 k 10 k f, FREQUENCY (Hz) Figure 6. Single Channel Separation at 65% Modulation Figure 7. Single Channel Distortion at 65% Modulation 10 0 Desired Channel DISTORTION (%) SEPARATION (dB) –10 – 20 Undesired Channel – 30 1.0 – 40 – 50 100 1.0 k f, FREQUENCY (Hz) 10 10 k 0.1 100 1.0 k 10 k f, FREQUENCY (Hz) MOTOROLA ANALOG IC DEVICE DATA 10 7.0 Stereo Audio Level 6.0 0 Stereo Composite Distortion 5.0 –10 4.0 – 20 Noise 5.0 Hz to 3.0 kHz – 30 – 40 400 Hz to 3.0 kHz 50 Hz to 3.0 kHz 100 Hz to 3.0 kHz 3.0 2.0 1.0 – 50 – 60 40 50 60 70 80 10 46 48 50 52 54 56 58 60 Figure 11. Decoder Distortion versus Filter Capacitor (Pin 14) Leakage Current DISTORTION, 50% SINGLE CHANNEL MOD 40 35 30 – 600 – 400 – 200 0 200 400 – 600 – 400 – 200 0 200 400 LEAKAGE CURRENT (10–9) Figure 12. Low Frequency Corner of PLL Response Figure 13. AGC Voltage versus Input Signal Level 600 500 Loop Filter 4.7 µF Loop Filter 47 µF 0 – 4.0 – 8.0 10 1.0 600 Loop Filter 15 µF 4.0 2.0 LEAKAGE CURRENT (10–9) 100 MODULATION FREQUENCY (Hz) MOTOROLA ANALOG IC DEVICE DATA AGC VOLTAGE LEVEL (mV) SEPARATION (dB) R1 to Gnd Figure 10. Decoder Separation versus Filter Capacitor (Pin 14) Leakage Current 25 PLL LOOP RESPONSE (dB) 100 STEREO THRESHOLD (dBµV) 45 –12 R1 to VCC SIGNAL STRENGTH (dBµV) 50 20 0 Figure 9. R1 versus Stereo Threshold Point 1000 R1 (k Ω) Figure 8. Stereo Noise and Stereo Composite Distortion when Mono Transmitted DISTORTION FOR 80% MONO MODULATION (%) RESPONSE FOR 30%, MONO MODULATION (dB) MC13028A 400 300 200 100 0 40 50 60 70 80 90 INPUT SIGNAL STRENGTH (dBµV) 11 MC13028A Figure 9 presents more detailed information with respect to the value of resistor R1 at Pin 1 versus the desired incoming signal level for stereo threshold. Figures 10 and 11, discussed briefly in the Pin Function Description Section, show the importance of using a quality component at Pin 14 to ground. It can be seen that an electrolytic capacitor leakage current of 600 nA can unbalance the PLL to the point where stereo performance may degrade to only 25 dB of separation with a corresponding 2.0% distortion at 50% modulation levels. The value of the capacitor connected to Pin 14 (47 µF) is also a factor in the determination of the low frequency corner of the PLL circuit response. Three traces of PLL response appear in Figure 12 where they have been plotted for three different values of loop filter capacitor. The recommended value of 47 µF provides the best response shape in this particular circuit set–up where a Murata Products CSA3.60MGF108 part is used. Figure 13 presents the response of the AGC voltage versus decoder input signal level. This is a typical response when the IC is used as shown in the application schematic of Figure 1. The trace begins approximately at the point of decoder sensitivity, and rises rapidly until reaching the area of stereo sensitivity, approximately 50 dBµV. Thereafter, the circuit responds in a linear fashion for the next 30 dB of input signal increase. Figures 14 through 17 inclusively depict the VCC ripple rejection performance for the MC13028A under mono and stereo conditions for nominal and for low values of VCC. It should be noted that this data was collected without any VCC filtering. As one might expect, the ripple rejection is better in mono than in stereo. When the decoder operates in stereo, the VCO is functional, thus the decoder becomes more susceptible to audio ripple on the VCC line. Under normal operating conditions, with the recommended value of 47 µF at Pin 12 and 10 µF at Pin 7, a VCC ripple reading will be virtually the same as measuring the noise floor of the IC. AM STEREO TUNER / FM STEREO IF Description of Application This application combines a Sanyo LA1832M with the Motorola MC13028A AM Stereo decoder IC. The LA1832 provides an FM IF, FM multiplex detection, AM tuning, and the AM IF functions. The MC13028A provides the AM Stereo detection as well as Left and Right audio outputs. An MC145151 synthesizer provides the frequency control of the local oscillator contained within the LA1832. Frequency selection is by means of a switch array attached to the synthesizer. The application circuit is shown in Figure 18. Circuit Board Description The copper side layout and the component locations are shown in Figure 19. The view is from the plating side of the board, with the components shown in hidden view. Several jumper wires are placed on the component side of the board to complete the circuit. Posts are provided for electrical connections to the circuit. The circuit board has been scaled to fit the page, however, the dimensions provide the true size. Circuit Description The Sanyo data sheet for the LA1832 should be consulted for an understanding of the FM detection and multiplex decoding. 12 Special Parts The following information provides circuit function, part number, and the manufacturer’s name for special parts identified by their schematic symbol. Where the part is not limited to a single source, a description sufficient to select a part is given. U1 IC – AM Stereo Decoder MC13028AD by Motorola U2 IC – AM/FM IF and Multiplex Tuner LA1832M by Sanyo U3 IC – Frequency Synthesizer MC145151DW2 by Motorola T1 AM IF Coil A7NRES–11148N by TOKO F1 AM IF Ceramic Filter SFG450F by Murata F2 FM IF Detector Resonator CDA10.7MG46A by Murata F3 FM Multiplex Decoder Resonator CSB456F15 by Murata F4 AM Tuner Block BL–70 by Korin Giken X1 10.24 MHz Crystal, Fundamental Mode, AT Cut, 18 pF Load Cap, 35 Ω maximum series R. HC–18/U Holder X2 3.6 MHz AM Stereo Decoder Resonator CSA3.60MGF108 by Murata S5 8 SPST DIP Switch MOTOROLA ANALOG IC DEVICE DATA MC13028A Figure 15. Mono Low Voltage VCC Ripple Rejection Figure 14. Mono VCC Ripple Rejection – 20 – 20 300 µF Decoder 100 mVpp 50 10 k – 30 10 k VCC VCC = 6.0 V RESIDUAL (dB) RESIDUAL (dB) – 30 VCC = 4.0 V – 40 VCC = 8.0 V – 50 – 60 VCC = 10 V VCC = 12 V 1.0 k Figure 16. Stereo VCC Ripple Rejection Figure 17. Stereo Low Voltage VCC Ripple Rejection 0 Decoder – 30 50 10 k VCC VCC = 8.0 V VCC = 6.0 V VCC = 10 V VCC = 12 V L R –10 VCC = 2.0 V 10 k RESIDUAL (dB) 300 µF 100 mVpp RESIDUAL (dB) 100 RIPPLE FREQUENCY (Hz) VCC = 4.0 V – 50 VCC = 4.0 V RIPPLE FREQUENCY (Hz) – 20 – 40 VCC = 2.5 V VCC = 3.0 V – 60 1.0 k VCC = 2.1 V – 40 – 50 100 VCC = 2.0 V L R – 20 – 30 – 40 VCC = 2.5 V VCC = 3.0 V – 50 VCC = 4.0 V – 60 100 1.0 k RIPPLE FREQUENCY (Hz) MOTOROLA ANALOG IC DEVICE DATA – 60 100 1.0 k RIPPLE FREQUENCY (Hz) 13 14 1 3 4 6 5 4 L.O. 3 1 2 F4 6 2 C36 22 µF C15 0.01 BL-70 Ant. Tuning Block Korin Giken C37 C35 FM IF Input 12 C51 0.68 R35 681 D2 R29 127 R23 127 Q2 2N3904 Q4 2N3906 VCC C30 C27 0.047 C26 0.047 C52 0.01 C50 0.022 R25 R21 301 51.1 10 k C28 10 µF LA1832M 13 12 14 11 15 10 16 9 17 8 18 U2 7 19 6 20 5 21 4 22 3 23 2 24 1 C29 0.01 R34 1.0 µF C53 100 µF C25 R17 43 k T1 0.01 F2 R18 392 R22 332 R24 3.65 k 6 4 D8 1N4148 R14 R28 2.74 k D9 1N4148 R27 2.21 k R26 392 Q3 2N3904 TOKO A7NRES–11148N C22 10 µF C1 10 µF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 U3 28 27 26 25 24 23 22 21 20 19 18 17 16 15 C57 10 C47 30 VAR C48 10 C8 0.1 AM Frequency Set Switch (Binary Coded, 8 Bits) Local Osc. Frequency ÷ 10 kHz S5 C49 68 X1 10.24 MHz C7 100 µF R36 1.0 k AM Audio C4 47 µF Right Left C9 43 C13 0.001 C19 10 µF C14 0.001 C20 10 µF Mono 3.6 MHz S4 Stereo AM MC145151DW C2 0.47 R40 47.5 0.22 C3 X2 R2 6.81 k R3 6.81 k 1 2 3 4 5 6 7 8 C6 47 µF MC13028A 1 16 2 15 3 14 4 U1 13 5 12 6 11 7 10 8 9 C5 0.1 SFG450F Murata C10 10 µF 10.2 k C23 10 µF F1 CDA10.7 MG46A Murata C11 0.47 µF Q1 2N3904 R30 332 450 kHz IF 1N4148 D7 1 2 3 C12 D3 Stereo Tuning R19 Gnd C38 0.0012 0.0047 0.047 FM FM S3 S2 Mono AM R15 3.01 k 1.0 k VCC 8.0 V C34 2.2 µF F3 0.01 C43 Stereo C34 2.2 µF R20 1.0 k AM Ant. Input C40 1.0 µF C44 0.01 Left FM Audio 10C42 µF Right C41 10 µF C39 1.0 µF Figure 18. MC13028A Decoder IC Application MC13028A Figure 18. MC13028A Decoder IC Application R39 3.32 k MOTOROLA ANALOG IC DEVICE DATA MC13028A Figure 19. MC13028A Decoder IC Application Circuit Board 8 C57 C49 X1 C47 + C7 C48 D9 C15 S5 U3 C8 1 R28 R27 1 R24 Q1 Q4 Q3 BL70 F4 C50 C29 C51 C28 R21 R25 R35 R39 R26 R29 R30 D7 R22 D8 R23 Q2 + C26 C34 + C27 D3 F1 T1 11.50 cm R34 C12 1 D2 R20 F2 12.50 cm C36 + U2 R19 R18 C35 C37 C52 + R15 R17 C53 C30 C22 + C25 + C39 C24 + C38 C40 + + + + C41 S2 C23 F3 C42 S3 + C43 + C10 + C44 C14 R14 C11 C20 + C6 C5 U1 X2 1 R3 C9 + C1 C19 + R2 + R36 R40 S4 C2 + C3 MC13028A C13 C4 0.50 cm 0.50 cm 8.0 cm 9.0 cm MOTOROLA ANALOG IC DEVICE DATA 15 MC13028A The LA1832 tuner IC (U2) is set for AM operation by switch S2 connecting Pin 12 to ground. An AM Stereo signal source is applied to Pin 2 of the RF coil contained within the BL–70 tuning block. That coil applies the signal to Pin 21 of U2. The L.O. coil is connected from Pin 23 to VCC. The secondary is tuned by a varactor which is controlled by a dc voltage output from the synthesizer circuit. The reactance of this oscillator tank is coupled back to Pin 23. It is through this reactance that the frequency of the L.O. is determined. A buffered output from the L.O. emerges at Pin 24. This signal is routed to Pin 1 of the synthesizer (U3), thus completing the frequency control loop. The mixer output at Pin 2 is applied to the IF coil T1. Coil T1 provides the correct impedance to drive the ceramic bandpass filter F1. The IF signal returns to U2 through Pin 4, and also to the input, Pin 4 of the AM Stereo decoder (U1). The ceramic filter F1 is designed to operate into a load resistance of 2.0 kΩ. This load is provided at Pin 4 of U2. The stereo outputs exit from Pins 15 and 16 of U1. The design amplitudes of the audio outputs will vary according to the values used for the resistors to ground at Pins 15 and 16 of the decoder, (labeled RO in the Electrical Characteristics Table and the Test Circuit on page 2 and 3, and in Figure 1, and called R2 and R3 in Figure 18). While the values chosen for RO are left to the discretion of the designer, the numbers chosen in this data sheet are reflective of those required to set the general industry standard levels of audio outputs in receiver designs. Pins 15 and 16 are also good locations for the insertion of simple RC filters that are used to comply with the United States NRSC requirement for the shape of the overall receiver audio response. The following curve, Figure 20, shows the response of this U.S. standard. Figure 20. NRSC De–Emphasis Curve for the United States ATTENUATION (dB) 0 – 2.0 – 4.0 – 6.0 – 8.0 –10 100 200 500 1.0 k 2.0 k 5.0 k 10 k f, FREQUENCY (Hz) There are many design factors that affect the shape of the receiver response, and they must all be considered when trying to approximate the NRSC de–emphasis response. The mixer output transformer (IF coil, T1), and ceramic filter probably have the greatest contribution to the frequency response. The ceramic filter can be tailored from its rated response by the choice of transformer impedance and bandwidth. When designing an overall audio response shape, the response of the speakers or earphones should also be considered. 16 Component Values. The Pin Function Description table gives specific information on the choice of components to be used at each pin of U1. A similar section in the Sanyo LA1832 data sheet should be consulted as to the components to be used with U2. Tuning The frequency to which the test circuit will tune is set by the eight binary switches contained in the S5 assembly, numbered from 1 to 8. Number 1 connects to Pin 11 of U3 and number 8 connects to Pin 18. The other switches connect to the pins in between and in order. Each individual switch is a SPST type. To tune to a specific RF frequency, a computation must be made in order to ascertain the divide ratio to input to the synthesizer via the switch array. The divide ratio is simply the eight digit binary equivalent number for the local oscillator frequency divided by 10 kHz. The local oscillator frequency is the desired RF frequency plus 450 kHz, the IF frequency. Any local oscillator value within the AM band can be represented by a binary number. Each binary bit represents a switch setting where a “1” is an open switch and a “0” is a closed switch. The most significant bit represents switch 8 which is connected to Pin 18. To illustrate, consider the setting for an input frequency of 1070 kHz. (This frequency was used to test the circuit board as described further on.) The local oscillator frequency is 1070 kHz plus 450 kHz which equals 1520 kHz. Dividing by 10 kHz yields the number 152. The binary number for 152 is 10011000. Thus the switches are set to: Switch Position Number 8 Open 1 7 Closed 0 6 Closed 0 5 Open 1 4 Open 1 3 Closed 0 2 Closed 0 1 Closed 0 Circuit Adjustments The FM circuit requires no adjustment. The AM L.O. must be able to tune from 980 to 2150 kHz to cover the broadcast range. Adjust the core of the L.O. coil if needed in order to be able to cover this range. The AM RF coil and trimmer can be adjusted for best signal after connection to the loop antenna. The coil is adjusted near the low end of the band, and the trimmer is adjusted at the top of the band. The IF coil, T1, is first adjusted for maximum signal out of the filter, F1. This is a “coarse” adjustment. The final “fine tune” adjustment occurs after the following conditions are met. From an AM Stereo generator with the pilot tone off, feed the decoder an input signal of approximately 70 dBµV that is modulated with an 80% L–R audio signal at 3.0 kHz. While monitoring either the left or the right output from the decoder on an oscilloscope, precisely fine tune the IF coil for a minimum residual signal, see the following diagram. If there is no sideband tilt in the system, this adjustment should hold for both channels. Otherwise, the best compromise adjustment for both channels should be used. MOTOROLA ANALOG IC DEVICE DATA MC13028A Figure 21. Decoder Signal Output for Mistuned and Tuned Condition with Input Signal of 80% L–R at 3.0 kHz AM Circuit Test The connections for test are as shown in Figure 22. A 50 Ω resistor is placed on the AM antenna input. The AM Stereo generator is connected to the AM antenna input. Measurements of audio level in mono mode are made with an audio voltmeter connected through a FET probe (pilot signal “off”). Measurements of audio level and distortion in stereo mode (pilot signal “on”) are made using a pilot rejection filter ahead of the distortion analyzer or the audio meter. The pilot rejection filter has a rejection ratio that should exceed 20 to 25 dB. Typical data is shown in Figures 23–26. Figures 23 and 24 were read on the left channel in mono mode. Figures 25–26 were in stereo mode. Mistuned Tuned Figure 22. MC13028A/LA1832 Application Circuit Board Test Setup Audio Voltmeter AM Ant. Input Am Stereo Generator 1070 kHz 50 Ω Output 50 Ω FET Probe Ant. Tuning Block + 1 Left Pilot Filter and Buffer Amp Right U1 MC13028A/LA1832 Application Circuit Board Test MC13028A + Distortion Analyzer and Audio Voltmeter AM Stereo Audio Output For Stereo Measurements, Pilot On MOTOROLA ANALOG IC DEVICE DATA 17 MC13028A Figure 23. Left AM Output at 30% Modulation 10 6.0 6.0 5.0 5.0 1000 kHz 4.0 3.0 – 30 – 40 % DISTORTION 0 dB = 90 mVrms % DISTORTION dB OUT –10 – 20 7.0 1000 kHz Out 0 Figure 24. Left AM Output at 80% Modulation 7.0 4.0 3.0 2.0 2.0 1.0 1.0 Noise – 50 Distortion 60 80 100 0 120 40 20 60 80 100 PEAK (dBµV) Figure 25. AM Output Right Channel Only Modulated at 50% Figure 26. AM Output Left Channel Only Modulated at 50% Out 0 5.0 10 4.0 0 0 dB = 150 mVrms dB OUT 0 INPUT (dBµV) 10 3.0 –10 Distortion – 20 2.0 – 30 1.0 Channel Separation – 40 100 1.0 k TONE (Hz) 18 0 0 10 k 120 5.0 Out 4.0 0 dB = 150 mVrms –10 – 20 3.0 Distortion 2.0 – 30 % DISTORTION 40 20 dB OUT 0 % DISTORTION – 60 1.0 Channel Separation – 40 100 1.0 k 0 10 k TONE (Hz) MOTOROLA ANALOG IC DEVICE DATA MC13028A OUTLINE DIMENSIONS D SUFFIX PLASTIC PACKAGE CASE 751B–05 (SO–16) ISSUE J –A – 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 –B – 1 P 8 PL 0.25 (0.010) 8 M B M G K F R X 45° C –T SEATING – J M PLANE D 16 PL 0.25 (0.010) M T B S A S DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 4.00 3.80 1.75 1.35 0.49 0.35 1.25 0.40 1.27 BSC 0.25 0.19 0.25 0.10 7° 0° 6.20 5.80 0.50 0.25 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 7° 0° 0.229 0.244 0.010 0.019 P SUFFIX PLASTIC PACKAGE CASE 648–08 ISSUE R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. –A – 16 9 1 8 B F C L S –T – SEATING PLANE K H J G D 16 PL 0.25 (0.010) MOTOROLA ANALOG IC DEVICE DATA M T A M M DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.070 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0° 10° 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0° 10° 0.51 1.01 19 MC13028A Motorola reserves the right to make changes without further notice to any products herein. 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How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315 MFAX: [email protected] – TOUCHTONE 602–244–6609 INTERNET: http://Design–NET.com ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 20 ◊ MOTOROLA ANALOG IC DEVICE DATA *MC13028A/D* MC13028A/D