LINER LTC1404IS8

LTC1404
Complete SO-8, 12-Bit,
600ksps ADC with Shutdown
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FEATURES
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DESCRIPTION
Complete 12-Bit ADC in SO-8
Single Supply 5V or ±5V Operation
Sample Rate: 600ksps
Power Dissipation: 75mW (Typ)
72dB S/(N + D) and – 80dB THD at Nyquist
No Missing Codes over Temperature
Nap Mode with Instant Wake-Up: 7.5mW
Sleep Mode: 60µW
High Impedance Analog Input
Input Range (1mV/LSB): 0V to 4.096V or ± 2.048V
Internal Reference Can Be Overdriven Externally
3-Wire Interface to DSPs and Processors (SPI and
MICROWIRETM Compatible)
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APPLICATIONS
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High Speed Data Acquisition
Digital Signal Processing
Multiplexed Data Acquisition Systems
Audio and Telecom Processing
Digital Radio
Spectrum Analysis
Low Power and Battery-Operated Systems
Handheld or Portable Instruments
The LTC1404 converts 0V to 4.096V unipolar inputs from
a single 5V supply and ±2.048V bipolar inputs from ±5V
supplies. Maximum DC specs include ±1LSB INL, ±1LSB
DNL and 45ppm/°C full-scale drift over temperature.
Guaranteed AC performance includes 69dB S/(N + D)
and – 76dB THD at an input frequency of 100kHz over
temperature.
The 3-wire serial port allows compact and efficient data
transfer to a wide range of microprocessors, microcontrollers
and DSPs.
, LTC and LT are registered trademarks of Linear Technology Corporation.
MICROWIRE is a trademark of National Semiconductor Corp.
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The LTC ®1404 is a complete 600ksps, 12-bit A/D converter which draws only 75mW from a 5V or ± 5V supplies.
This easy-to-use device comes complete with a 160ns
sample-and-hold and a precision reference. Unipolar and
bipolar conversion modes add to the flexibility of the ADC.
The LTC1404 has two power saving modes: Nap and
Sleep. In Nap mode, it consumes only 7.5mW of power
and can wake up and convert immediately. In the Sleep
mode, it consumes 60µW of power typically. Upon powerup from Sleep mode, a reference ready (REFRDY) signal
is available in the serial data word to indicate that the
reference has settled and the chip is ready to convert.
TYPICAL APPLICATION
Power Consumption vs Sample Rate
Single 5V Supply, 600kHz, 12-Bit Sampling A/D Converter
100
5V
10µF*
VCC
VSS
NORMAL CONVERSION
8
10
0.1µF
MPU
LTC1404
2
ANALOG INPUT
(0V TO 4.096V)
REFOUT
2.43V +
10µF
3
0.1µF
4
*AVX TPSD106M035R0300
AIN
CONV
VREF
CLK
GND
DOUT
7
P1.4
6
P1.3
5
P1.2
SERIAL
DATA LINK
SUPPLY CURRENT (mA)
1
+
NAP MODE
BETWEEN CONVERSION
1
SLEEP MODE
BETWEEN CONVERSION
0.1
0.01
9.6MHz CLOCK
LTC1404 • TA01
0.001
0.01 0.1
1
10 100 1k 10k 100k 1M
SAMPLE RATE (Hz)
LTC1404 • TA02
1
LTC1404
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PACKAGE/ORDER INFORMATION
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(Notes 1, 2)
Supply Voltage (VCC) ................................................. 7V
Negative Supply Voltage (VSS).................... – 6V to GND
Total Supply Voltage (VCC to VSS)
Bipolar Operation Only ........................................ 12V
Analog Input Voltage (Note 3)
Unipolar Operation .................. – 0.3V to (VCC + 0.3V)
Bipolar Operation........... (VSS – 0.3V) to (VCC + 0.3V)
Digital Input Voltage (Note 4)
Unipolar Operation ................................– 0.3V to 12V
Bipolar Operation.........................(VSS – 0.3V) to 12V
Digital Output Voltage
Unipolar Operation .................. – 0.3V to (VCC + 0.3V)
Bipolar Operation........... (VSS – 0.3V) to (VCC + 0.3V)
Power Dissipation.............................................. 300mW
Operating Ambient Temperature Range
LTC1404C................................................ 0°C to 70°C
LTC1404I............................................ – 40°C to 85°C
Junction Temperature.......................................... 125°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
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POWER REQUIRE E TS
SYMBOL
VCC
PARAMETER
Positive Supply Voltage
VSS
ICC
Negative Supply Voltage
Positive Supply Current
ISS
Negative Supply Current
PD
Power Dissipation
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A ALOG I PUT
ORDER PART
NUMBER
TOP VIEW
VCC 1
8 VSS
AIN 2
7 CONV
VREF 3
6 CLK
GND 4
5 DOUT
S8 PACKAGE
8-LEAD PLASTIC SO
LTC1404CS8
LTC1404IS8
S8 PART MARKING
TJMAX = 125°C, θJA = 130°C/ W
1404
1404I
Consult factory for PDIP packages and Military grade parts.
(Note 5)
CONDITIONS
Unipolar
Bipolar
Bipolar Only
fSAMPLE = 600ksps
Nap Mode
Sleep Mode
fSAMPLE = 600ksps, VSS = – 5V
Nap Mode
Sleep Mode
fSAMPLE = 600ksps
Nap Mode
Sleep Mode
MIN
4.75
4.75
– 2.45
TYP
15
1.3
8.0
0.2
0.2
4
75
7.5
60
●
●
●
●
●
●
●
●
●
MAX
5.25
5.25
– 5.25
30
3.0
20.0
0.6
0.5
10
160
20
150
UNITS
V
V
V
mA
mA
µA
mA
mA
µA
mW
mW
µW
(Note 5)
SYMBOL PARAMETER
CONDITIONS
VIN
Analog Input Range
4.75V ≤ VCC ≤ 5.25V (Unipolar)
4.75V ≤ VCC ≤ 5.25V, – 5.25V ≤ VSS ≤ – 2.45V (Bipolar)
IIN
Analog Input Leakage Current
During Conversions (Hold Mode)
CIN
Analog Input Capacitance
Between Conversions (Sample Mode)
During Conversions (Hold Mode)
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ABSOLUTE MAXIMUM RATINGS
MIN
TYP
MAX
0 to 4.096
0 to ±2.048
V
V
±1
●
45
5
UNITS
µA
pF
pF
LTC1404
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CO VERTER CHARACTERISTICS
PARAMETER
With internal reference (Notes 5, 7)
CONDITIONS
MIN
Resolution (No Missing Codes)
●
Integral Linearity Error
(Note 8)
Differential Linearity Error
Offset Error
TYP
12
Bits
±1
LSB
●
±1
LSB
●
±6
±8
LSB
LSB
±15
LSB
±10
±45
ppm/°C
MIN
TYP
MAX
UNITS
69
72
72
Full-Scale Error
IOUT(REF) = 0
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DY A IC ACCURACY
UNITS
●
(Note 9)
Full-Scale Tempco
MAX
●
VCC = 5V, VSS = – 5V, fSAMPLE = 600kHz
SYMBOL PARAMETER
CONDITIONS
S/(N + D) Signal-to-Noise
100kHz Input Signal
300kHz Input Signal
●
THD
Total Harmonic Distortion
Up to 5th Harmonic
100kHz Input Signal
300kHz Input Signal
●
– 82
– 80
– 76
dB
dB
Peak Harmonic or
Spurious Noise
100kHz Input Signal
300kHz Input Signal
●
– 84
– 82
– 76
dB
dB
Intermodulation Distortion
fIN1 = 99.17kHz, fIN2 = 102.69kHz
fIN1 = 298.68kHz, fIN2 = 304.83kHz
IMD
dB
dB
– 82
– 70
dB
dB
Full Power Bandwidth
5
MHz
Full Linear Bandwidth (S/(N + D) ≥ 68dB)
1
MHz
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I TER AL REFERE CE CHARACTERISTICS
(Note 5)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VREF Output Voltage
IOUT = 0
2.410
2.430
2.450
V
VREF Output Tempco
IOUT = 0
±10
±45
VREF Line Regulation
4.75V ≤ VCC ≤ 5.25V
– 5.25V ≤ VSS ≤ 0V
VREF Load Regulation
0 ≤ IOUT ≤ 1mA
VREF Wake-Up Time from Sleep Mode
CVREF = 10µF
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DIGITAL I PUTS AND OUTPUTS
●
ppm/°C
0.5
0.01
LSB/ V
LSB/ V
1
LSB/mA
2.5
ms
(Note 5)
SYMBOL PARAMETER
CONDITIONS
VIH
High Level Input Voltage
VCC = 5.25V
●
VIL
Low Level Input Voltage
VCC = 4.75V
●
0.8
V
IIN
Digital Input Current
VIN = 0V to VCC
●
±10
µA
CIN
Digital Input Capacitance
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
MIN
VCC = 4.75V, IO = – 10µA
VCC = 4.75V, IO = – 200µA
●
VCC = 4.75V, IO = 160µA
VCC = 4.75V, IO = 1.6mA
●
TYP
MAX
2.0
UNITS
V
5
pF
4.7
V
V
4.0
0.05
0.10
0.4
V
V
3
LTC1404
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DIGITAL I PUTS AND OUTPUTS
(Note 5)
SYMBOL PARAMETER
CONDITIONS
IOZ
Hi-Z Output Leakage DOUT
VOUT = 0V to VCC
COZ
Hi-Z Output Capacitance DOUT
15
pF
ISOURCE
Output Source Current
VOUT = 0V
– 10
mA
ISINK
Output Sink Current
VOUT = VCC
10
mA
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TI I G CHARACTERISTICS
SYMBOL
PARAMETER
fSAMPLE(MAX)
Maximum Sampling Frequency
tCONV
Conversion Time
tACQ
Acquisition Time (Unipolar Mode)
(Bipolar Mode VSS = – 5V)
fCLK
CLK Frequency
tCLK
CLK Pulse Width
tWK(NAP)
Time to Wake Up from Nap Mode
t1
MIN
TYP
●
MAX
UNITS
±10
µA
(Note 5, see Figures 12, 13, 14)
CONDITIONS
MIN
●
TYP
MAX
600
fCLK = 9.6MHz
UNITS
kHz
1.36
µs
200
160
ns
ns
●
0.1
●
40
CLK Pulse Width to Return to Active Mode
●
40
ns
t2
CONV↑ to CLK↑ Setup Time
●
70
ns
t3
CONV↑ After Leading CLK↑
t4
CONV Pulse Width
t5
Time from CLK↑ to Sample Mode
t6
Aperture Delay of Sample-and-Hold
t7
Minimum Delay Between Conversion (Unipolar Mode)
(Note 6)
(Bipolar Mode VSS = – 5V)
●
●
220
180
310
300
ns
ns
t8
Delay Time, CLK↑ to DOUT Valid
CLOAD = 20pF
●
40
70
ns
t9
Delay Time, CLK↑ to DOUT Hi-Z
CLOAD = 20pF
●
40
70
ns
t10
Time from Previous Data Remains Valid After CLK↑
CLOAD = 20pF
●
The ● denotes specifications which apply over the full operating
temperature range; all other limits and typicals apply to TA = 25°C.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to GND.
Note 3: When these pin voltages are taken below VSS (ground for unipolar
mode) or above VCC, they will be clamped by internal diodes. This product
can handle input currents greater than 60mA without latch-up if the pin is
driven below VSS (ground for unipolar mode) or above VCC.
Note 4: When these pin voltages are taken below VSS (ground for unipolar
mode), they will be clamped by internal diodes. This product can handle
input currents greater than 60mA without latch-up if the pin is driven
below VSS (ground for unipolar mode). These pins are not clamped to VCC.
Note 5: VCC = 5V, fSAMPLE = 600kHz, tr = tf = 5ns unless otherwise
specified.
4
(Note 6)
9.6
ns
350
(Note 10)
MHz
ns
●
0
ns
●
40
ns
Jitter < 50ps
10
60
ns
40
ns
30
ns
Note 6: Guaranteed by design, not subject to test.
Note 7: Linearity, offset and full-scale specifications apply for unipolar and
bipolar modes.
Note 8: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 9: Bipolar offset is the offset voltage measured from – 0.5LSB when
the output code flickers between 0000 0000 0000 and 1111 1111 1111.
Note 10: The rising edge of CONV starts a conversion. If CONV returns
low at a bit decision point during the conversion, it can create small errors.
For best performance, ensure that CONV returns low either within 100ns
after the conversion starts (i.e., before the first bit decision) or after the 14
clock cycles. (Figure 13 Timing Diagram).
LTC1404
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TYPICAL PERFORMANCE CHARACTERISTICS
Unipolar Mode Differential
Nonlinearity vs Output Code
Unipolar Mode Integral
Nonlinearity vs Output Code
1.00
1.00
0.75
0.50
0.25
0
–0.25
–0.50
–0.75
DIFFERENTIAL NONLINEARITY (LSBs)
fSAMPLE = 600kHz
fSAMPLE = 600kHz
INTEGRAL NONLINEARITY (LSBs)
DIFFERENTIAL NONLINEARITY (LSBs)
1.00
0.75
0.50
0.25
0
–0.25
–0.50
–0.75
–1.00
–1.00
0
0.75
–20
–30
–0.50
–0.75
1404 G03
Unipolar Mode 4096 Nonaverage
FFT with 300kHz Signal
0.25
0
–0.25
–0.50
–0.75
0
–20
–30
–40
–50
– 60
–70
–80
–50
–60
–70
–80
–90
–100
–100
–110
–110
–120
–120
0
30 60 90 120 150 180 210 240 270 300
FREQUENCY (kHz)
0
1404 G06
NYQUIST
FREQUENCY
62
56
50
8
7
6
5
4
3
2
fSAMPLE = 600kHz
Bipolar Mode
Signal-to-Noise Ratio (Without
Harmonics) vs Input Frequency
80
80
70
70
SIGNAL-TO-NOISE RATIO (dB)
68
SIGNAL/(NOISE + DISTORTION) (dB)
74
SIGNAL-TO-NOISE RATIO (dB)
Unipolar Mode
Signal-to-Noise Ratio (Without
Harmonics) vs Input Frequency
11
60
50
40
30
20
60
50
40
30
20
10
10
fSAMPLE = 600kHz
fSAMPLE = 600kHz
0
0
0
1000
1404 G07
30 60 90 120 150 180 210 240 270 300
FREQUENCY (kHz)
1404 G05
Unipolar Mode
ENOB and Signal/(Noise +
Distortion) vs Input Frequency
100
INPUT FREQUENCY (kHz)
–40
–90
1404 G04
12
fSAMPLE = 600kHz
fIN = 298.681kHz
SINAD = 71dB
THD = –73dB
–10
AMPLITUDE (dB)
0.50
AMPLITUDE (dB)
INTEGRAL NONLINEARITY (LSBs)
–0.25
fSAMPLE = 600kHz
fIN = 99.1699kHz
SINAD = 71dB
THD = –77dB
–10
–1.00
0
–2048
2048
–1024
1024
1536
–1536
–512
512
OUTPUT CODE
EFFECTIVE NUMBER OF BITS
0
0
fSAMPLE = 600kHz
10
0.25
Unipolar Mode 4096 Nonaverage
FFT with 100kHz Signal
1.00
1
0.50
1404 G02
Bipolar Mode Integral
Nonlinearity vs Output Code
9
fSAMPLE = 600kHz
0.75
–1.00
0
–2048
2048
–1024
1024
1536
–1536
–512
512
OUTPUT CODE
512 1024 1536 2048 2560 3072 3584 4096
OUTPUT CODE
0
512 1024 1536 2048 2560 3072 3584 4096
OUTPUT CODE
1404 G01
10
Bipolar Mode Differential
Nonlinearity vs Output Code
10
100
INPUT FREQUENCY (kHz)
1000
1404 G08
10
100
INPUT FREQUENCY (kHz)
1000
1404 G09
5
LTC1404
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TYPICAL PERFORMANCE CHARACTERISTICS
Unipolar Mode Intermodulation
Distortion Plot at 100kHz
0
0
fSAMPLE = 600kHz
–10
fa fb
–10
–20
–20
fSAMPLE = 600kHz
fa = 99.16992188kHz
fb = 102.6855469kHz
–30
–30
–40
–50
–60
2ND HARMONIC
–70
–90
–50
– 60
–70
–80
2fa
2fa – fb
–90
THD
–80
–40
AMPLITUDE (dB)
AMPLITUDE (dB BELOW THE FUNDAMENTAL)
Unipolar Mode
Distortion vs Input Frequency
2fb
–100
3RD HARMONIC
–110
–120
–100
100
INPUT FREQUENCY (kHz)
10
0
1000
30 60 90 120 150 180 210 240 270 300
FREQUENCY (kHz)
1404 G10
1404 G11
Unipolar Mode Intermodulation Distortion Plot at 300kHz
0
fa
fSAMPLE = 600kHz
fa = 298.6816406kHz
fb = 304.8339844kHz
–10
–20
fb
–30
AMPLITUDE (dB)
–40
2fa + fb
–50
3fa
– 60
2fb – fa
2fa
–70
fa + fb
2fb
–80
3fb
–90
–100
–110
–120
0
20
40
60
80
100
120
140
160
FREQUENCY (kHz)
180
200
220
240
260
280
300
1404 G12
Bipolar Mode Intermodulation Distortion Plot at 300kHz
0
fa
fSAMPLE = 600kHz
fa = 298.6816406kHz
fb = 304.8339844kHz
–10
–20
fb
–30
2fa + fb
3fa
AMPLITUDE (dB)
–40
–50
2fb + fa
2fa
– 60
fa + fb
–70
2fb – fa
fb – fa
–80
3fb
2fb
–90
–100
–110
–120
0
20
40
60
80
100
120
140
160
FREQUENCY (kHz)
180
200
220
240
260
280
300
1404 G12
6
LTC1404
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TYPICAL PERFORMANCE CHARACTERISTICS
Bipolar Mode S/(N + D) vs Input
Frequency and Amplitude
Unipolar Mode S/(N + D) vs Input
Frequency and Amplitude
VIN = –20dB
50
40
30
20
VIN = –60dB
10
70
60
VIN = –20dB
50
40
30
20
VIN = –60dB
10
fSAMPLE = 600kHz
fSAMPLE = 600kHz
0
10
1000
100
INPUT FREQUENCY (kHz)
–20
–30
–40
–50
–60
–70
–80
–90
10
1000
100
INPUT FREQUENCY (kHz)
1404 G14
Bipolar Mode Power Supply
Feedthrough vs Ripple Frequency
0
0
–40
–50
–60
–70
–80
–90
–20
–30
POWER SUPPLY FEEDTHROUGH (dB)
–30
AIN = 0dB
AIN FREQUENCY = 100kHz
fSAMPLE = 600kHz
VCC (VRIPPLE = 1mV)
–10
POWER SUPPLY FEEDTHROUGH (dB)
–20
–40
–50
–60
–70
–80
–90
10
100
INPUT FREQUENCY (kHz)
1000
1
10
100
RIPPLE FREQUENCY (kHz)
–30
–40
–50
VSS (VRIPPLE = 10mV)
–60
–70
–80
VCC (VRIPPLE = 1mV)
–90
1
1000
10
100
RIPPLE FREQUENCY (kHz)
2.440
1000
1404 G19
Reference Voltage vs
Load Current
Reference Voltage vs Temperature
Acquisition Time vs
Source Impedance
4.0
2.45
TA = 25°C
2.438
3.5
2.434
2.432
2.430
2.428
2.426
2.424
ACQUISITION TIME (µs)
2.44
2.436
REFERENCE VOLTAGE (V)
REFERENCE VOLTAGE (V)
–20
1404 G18
1404 G17
2.43
2.42
2.41
2.40
50
75
0
25
TEMPERATURE (°C)
100
125
1404 G20
2.39
3.0
2.5
2.0
1.5
1.0
0.5
2.422
2.420
–50 –25
AIN = 0dB
AIN FREQUENCY = 100kHz
fSAMPLE = 600kHz
–10
–100
–100
–100
1000
1404 G16
Unipolar Mode Power Supply
Feedthrough vs Ripple Frequency
0
fSAMPLE = 600kHz
100
INPUT FREQUENCY (kHz)
1404 G15
Bipolar Mode Peak Harmonic or
Spurious Noise vs Input Frequency
–10
fSAMPLE = 600kHz
–10
–100
0
10
SPURIOUS-FREE DYNAMIC RANGE (dB)
SPURIOUS-FREE DYNAMIC RANGE (dB)
VIN = 0dB
70
60
0
80
VIN = 0dB
SIGNAL/(NOISE + DISTORTION) (dB)
SIGNAL/(NOISE + DISTORTION) (dB)
80
Unipolar Mode Peak Harmonic or
Spurious Noise vs Input Frequency
0
–8 –7
–6
–5 –4 –3 –2 –1
LOAD CURRENT (mA)
0
1
10
100
1k
SOURCE RESISTANCE (Ω)
10k
1404 G22
1404 G21
7
LTC1404
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TYPICAL PERFORMANCE CHARACTERISTICS
Unipolar Mode VCC Supply Current
vs Temperature
15.0
20
300
VCC SUPPLY CURRENT (mA)
12.5
15
250
VCC CURRENT
10.0
10
5
200
VSS CURRENT
7.5
150
5.0
100
2.5
fSAMPLE = 600kHz
0
–50 –25
0
25
50
75
TEMPERATURE (°C)
VSS SUPPLY CURRENT (µA)
VCC SUPPLY CURRENT (mA)
Bipolar Mode Supply Current
vs Temperature
50
fSAMPLE = 600kHz
100
125
1404 G23
0
–50 –25
50
75
0
25
TEMPERATURE (°C)
100
0
125
1404 G24
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PIN FUNCTIONS
VCC (Pin 1): Positive Supply, 5V. Bypass to GND (10µF
tantalum in parallel with 0.1µF ceramic).
AIN (Pin 2): Analog Input. 0V to 4.096V (Unipolar), ±2.048V
(Bipolar).
VREF (Pin 3): 2.43V Reference Output. Bypass to GND
(10µF tantalum in parallel with 0.1µF ceramic).
GND (Pin 4): Ground. GND should be tied directly to an
analog ground plane.
DOUT (Pin 5): The A/D conversion result is shifted out from
this pin.
8
CLK (Pin 6): Clock. This clock synchronizes the serial data
transfer. A minimum CLK pulse of 40ns signals the ADC to
wake up from Nap or Sleep mode.
CONV (Pin 7): Conversion Start Signal. This active high
signal starts a conversion on its rising edge. Keeping CLK
low and pulsing CONV two/four times will put the ADC into
Nap/Sleep mode.
VSS (Pin 8): Negative Supply. – 5V for bipolar operation.
Bypass to GND with 10µF tantalum in parallel with 0.1µF
ceramic. VSS should be tied to GND for unipolar operation.
LTC1404
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FUNCTIONAL BLOCK DIAGRA
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ZEROING SWITCH
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CSAMPLE
VCC
AIN
GND
VSS
VREF
2.43V REF
12-BIT CAPACITIVE DAC
COMP
CLK
CONV
12
CONTROL
LOGIC
SUCCESSIVE APPROXIMATION
REGISTER/PARALLEL TO
SERIAL CONVERTER
DOUT
1404 BD
TEST CIRCUITS
5V
3k
DOUT
DOUT
3k
Hi-Z TO VOH
VOL TO VOH
VOH TO Hi-Z
CLOAD
CLOAD
Hi-Z TO VOL
VOH TO VOL
VOL TO Hi-Z
1404 TC01
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LTC1404
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APPLICATIONS INFORMATION
Conversion Details
Dynamic Performance
The LTC1404 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 12-bit serial output based on a precision
internal reference. The control logic provides easy interface to microprocessors and DSPs through 3-wire connections.
The LTC1404 has excellent high speed sampling capability. FFT (Fast Fourier Transform) test techniques are used
to test the ADC’s frequency response, distortion and noise
at the rated throughput. By applying a low distortion sine
wave and analyzing the digital output using an FFT algorithm, the ADC’s spectral content can be examined for
frequencies outside the fundamental. Figure 2a shows a
typical LTC1404 FFT plot.
A rising edge on the CONV input starts a conversion. At the
start of a conversion the successive approximation register (SAR) is reset. Once a conversion cycle has begun, it
cannot be restarted.
0
fSAMPLE = 600kHz
fIN = 99.169kHz
SINAD = 72dB
THD = – 88dB
–10
SAMPLE
S1
SAMPLE
CSAMPLE
–
AIN
–20
AMPLITUDE (dB)
–30
–40
–50
– 60
–70
–80
–90
–100
–110
–120
0
30 60 90 120 150 180 210 240 270 300
FREQUENCY (kHz)
1404 F02a
Figure 2a. LTC1404 Nonaveraged, 4096 Point FFT
Plot with 100kHz Input Frequency in Bipolar Mode
0
fSAMPLE = 600kHz
fIN = 298.681kHz
SINAD = 71dB
THD = – 84dB
–10
–20
–30
AMPLITUDE (dB)
During conversion, the internal 12-bit capacitive DAC
output is sequenced by the SAR from the most significant
bit (MSB) to the least significant bit (LSB). Referring to
Figure 1, the AIN input connects to the sample-and-hold
capacitor during the acquired phase and the comparator
offset is nulled by the feedback switch. In this acquire
phase, it typically takes 160ns for the sample-and-hold
capacitor to acquire the analog signal. During the convert
phase, the comparator feedback switch opens, putting the
comparator into the compare mode. The input switches
connect CSAMPLE to ground, injecting the analog input
charge onto the summing junction. This input charge is
successively compared with the binary-weighted charges
supplied by the capacitive DAC. Bit decisions are made by
the high speed comparator. At the end of a conversion, the
DAC output balances the AIN input charge. The SAR
contents (a 12-bit data word) which represent the input
voltage, are presented through the serial pin DOUT.
–40
–50
– 60
–70
–80
–90
–100
HOLD
+
DAC
COMP
–110
–120
0
CDAC
VDAC
S
A
R
DOUT
1404 F01
Figure 1. AIN Input
10
30 60 90 120 150 180 210 240 270 300
FREQUENCY (kHz)
1404 F02b
Figure 2b. LTC1404 Nonaveraged, 4096 Point FFT
Plot with 300kHz Input Frequency in Bipolar Mode
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Signal-to-Noise Ratio
Total Harmonic Distortion
The signal-to-noise plus distortion ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
to frequencies from DC to half the sampling frequency.
Figure 2a shows a typical spectral content with a 600kHz
sampling rate and a 100kHz input. The dynamic performance is excellent for input frequencies up to the Nyquist
limit of 300kHz as shown in Figure 2b.
Total harmonic distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half of the sampling frequency. THD
is expressed as:
The effective number of bits (ENOBs) is a measurement of
the effective resolution of an ADC and is directly related to
the S/(N + D) by the equation:
N=
S /(N + D) – 1.76
6.02
where N is the effective number of bits of resolution and
S/(N + D) is expressed in dB. At the maximum sampling
rate of 600kHz, the LTC1404 maintains very good ENOBs
up to the Nyquist input frequency of 300kHz (refer to
Figure 3).
74
12
EFFECTIVE NUMBER OF BITS
NYQUIST
FREQUENCY
10
62
9
56
8
50
7
6
5
4
3
2
1
SIGNAL/(NOISE + DISTORTION) (dB)
68
11
fSAMPLE = 600kHz
0
10k
100k
INPUT FREQUENCY (Hz)
1M
1404 F03
Figure 3. Effective Bits and Signal-to-Noise +
Distortion vs Input Frequency in Bipolar Mode
where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the
second through nth harmonics. THD vs input frequency is
shown in Figure 4. The LTC1404 has good distortion
performance up to the Nyquist frequency and beyond.
AMPLITUDE (dB BELOW THE FUNDAMENTAL)
Effective Number of Bits
V22 + V32 + V42 + …Vn2
THD = 20 log
V1
0
–10
fSAMPLE = 600kHz
–20
–30
–40
–50
–60
–70
–80
3RD HARMONIC
THD
2ND HARMONIC
–90
–100
10k
100k
INPUT FREQUENCY (Hz)
1M
1404 F04
Figure 4. Distortion vs Input Frequency in
Bipolar Mode
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
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If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer function can create distortion products at sum and difference
frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc.
For example, the 2nd order IMD terms include (fa + fb) and
(fa – fb) while the 3rd order IMD terms includes (2fa + fb),
(2fa – fb), (fa + 2fb) and (fa – 2fb). If the two input sine
waves are equal in magnitude, the value (in decibels) of the
2nd order IMD products can be expressed by the following
formula.
IMD( fa ± fb) = 20log
Amplitude at (fa ± fb)
Amplitude at fa
Figure 5 shows the IMD performance at a 100kHz input.
0
fa
–10
fb
fSAMPLE = 600kHz
fa = 99.16992188kHz
fb = 102.6855469kHz
–20
AMPLITUDE (dB)
–30
–40
–50
–60
2fa + fb
–70
fa + fb
–80
2fa – fb
–90
2fb – fa
2fa
2fb
3fa
2fb + fa
3fb
–110
–120
20
40
60
80 100 120 140 160 180 200 220 240 260 280 300
FREQUENCY (kHz)
1404 F05
Figure 5. Intermodulation Distortion Plot in Bipolar Mode
Peak Harmonic or Spurious Noise
The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This
value is expressed in decibels relative to the RMS value of
a full-scale input signal.
Full Power and Full Linear Bandwidth
The full power bandwidth is the input frequency at which
the amplitude of the reconstructed fundamental is reduced by 3dB for a full-scale input signal.
The full linear bandwidth is the input frequency at which
the S/(N + D) has dropped to 68dB (11 effective bits). The
12
Driving the Analog Input
The analog input of the LTC1404 is easy to drive. It draws
only one small current spike while charging the sampleand-hold capacitor at the end of a conversion. During
conversion, the analog input draws only a small leakage
current. The only requirement is that the amplifier driving
the analog input must settle after the small current spike
before the next conversion starts. Any op amp that settles
in 160ns to small load current transient will allow maximum speed operation. If a slower op amp is used, more
settling time can be provided by increasing the time
between conversions. Suitable devices capable of driving
the ADC’s AIN input include the LT ® 1360 and the LT1363
op amps.
The LTC1404 comes with a built-in unipolar/bipolar detection circuit. If the VSS potential is forced below GND, the
internal circuitry will automatically switch to bipolar mode.
–100
0
LTC1404 has been designed to optimize input bandwidth,
allowing the ADC to undersample input signals with frequencies above the converter’s Nyquist Frequency. The
noise floor stays very low at high frequencies; S/(N + D)
becomes dominated by distortion at frequencies far beyond Nyquist.
The following list is a summary of the op amps that are
suitable for driving the LTC1404, more detailed information is available in the Linear Technology databooks and
the LinearViewTM CD-ROM.
LT 1215/LT1216: Dual and quad 23MHz, 50V/µs single
supply op amps. Single 5V to ±15V supplies, 6.6mA
specifications, 90ns settling to 0.5LSB.
LT1223: 100MHz video current feedback amplifier. ±5V
to ±15V supplies, 6mA supply current. Low distortion up
to and above 600kHz. Low noise. Good for AC applications.
LT1227: 140MHz video current feedback amplifier. ±5V
to ±15V supplies, 10mA supply current. Lowest distortion at frequencies above 600kHz. Low noise. Best for AC
applications.
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LT1229/LT1230: Dual and quad 100MHz current feedback
amplifiers. ±2V to ±15V supplies, 6mA supply current
each amplifier. Low noise. Good AC specs.
LT1360: 37MHz voltage feedback amplifier. ±5V to ±15V
supplies. 3.8mA supply current. Good AC and DC specs.
70ns settling to 0.5LSB.
LT1363: 50MHz, 450V/µs op amps. ±5V to ±15V supplies.
6.3mA supply current. Good AC and DC specs. 60ns
settling to 0.5LSB.
LT1364/LT1365: Dual and quad 50MHz, 450V/µs op amps.
±5V to ±15V supplies, 6.3mA supply current per amplifier.
60ns settling to 0.5LSB.
Internal Reference
The LTC1404 has an on-chip, temperature compensated,
curvature corrected, bandgap reference, which is factory
trimmed to 2.43V. It is internally connected to the DAC and
is available at Pin 3 to provide up to 1mA of current to an
external load. For minimum code transition noise, the
reference output should be decoupled with a capacitor to
filter wideband noise from the reference (10µF tantalum in
parallel with a 0.1µF ceramic). The VREF pin can be driven
with a DAC or other means to provide input span adjustment in bipolar mode. The VREF pin must be driven to at
least 2.46V to prevent conflict with the internal reference.
The reference should not be driven to more than 5V.
Figure 6 shows an LT 1360 op amp driving the reference
pin. Figure 7 shows a typical reference, the LT1019A-5
connected to the LTC1404. This will provide an improved
5V
INPUT RANGE
±0.843 • VREF(OUT)
AIN VCC
+
VREF(OUT) ≥ 2.46V
–
LTC1404
VREF
LT1360
3Ω
10µF
GND VSS
1404 F06
–5V
Figure 6. Driving the VREF with the LT1360 Op Amp
5V
INPUT RANGE ±4.215V
(= ±0.843 • VREF)
AIN
VCC
10V
VIN
LTC1404
VREF
VOUT
3Ω
LT1019A-5
10µF
GND
GND VSS
1404 F07
–5V
Figure 7. Supplying a 5V Reference Voltage to the
LTC1404 with the LT1019A-5
drift (equal to the maximum 5ppm/°C of the LT1019A-5)
and a ±4.215V full scale. If VREF is forced lower than
2.43V, the REFRDY bit in the serial data output will be
forced to low.
UNIPOLAR / BIPOLAR OPERATION AND ADJUSTMENT
Figure 8 shows the ideal input/output characteristics for
the LTC1404. The code transitions occur midway between
successive integer LSB values (i.e., 0.5LSB, 1.5LSB,
2.5LSB, … FS – 1.5LSB). The output code is natural binary
with 1LSB = 4.096/4096 = 1mV. Figure 9 shows the
input/output transfer characteristics for the bipolar mode
in two’s complement format.
Unipolar Offset and Full-Scale Error Adjustments
In applications where absolute accuracy is important,
offset and full-scale errors can be adjusted to zero. Figure
10a shows the extra components required for full-scale
error adjustment. Figure 10b shows offset and full-scale
adjustment. Offset error must be adjusted before fullscale error. Zero offset is achieved by applying 0.5mV (i.e.,
0.5LSB) at the input and adjusting the offset trim until the
LTC1404 output code flickers between 0000 0000 0000
and 0000 0000 0001. For zero full-scale error, apply an
analog input of 4.0945V (FS – 1.5LSB or last code transition) at the input and adjust R5 until the LTC1404 output
code flickers between 1111 1111 1110 and 1111 1111
1111.
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1LSB = FS = 4.096
4096
4096
111...111
ANALOG
INPUT
0V TO 4.096V
111...110
R1
10k
OUTPUT CODE
111...101
10k
111...100
+
–
5V
R9
20Ω
R4
100k
LTC1404
R5
4.3k
FULL-SCALE
ADJUST
UNIPOLAR
ZERO
000...011
AIN
A1
R2
10k
000...010
R3
100k
000...001
000...000
0V
1
LSB
FS – 1LSB
5V
R7
100k
R8
10k
OFFSET
ADJUST
R6
400Ω
INPUT VOLTAGE (V)
1404 F08
1404 F10b
Figure 8. LTC1404 Unipolar Transfer Characteristics
ANALOG
INPUT
±2.048V
011...111
BIPOLAR
ZERO
OUTPUT CODE
011...110
Figure 10b. LTC1404 Offset and Full-Scale Adjust Circuit
R1
10k
+
R2
10k
A1
–
000...001
000...000
AIN
R4
100k
R5
4.3k
FULL-SCALE
ADJUST
111...111
111...110
100...001
R3
R7
100k 100k
100...000
–FS/2
–1 0V 1
LSB
LSB
INPUT VOLTAGE (V)
FS/2 – 1LSB
R6
200Ω
LTC1404
5V
R8
20k
OFFSET
ADJUST
–5V
1404 F10c
1404 F09
Figure 9. LTC1404 Bipolar Transfer Characteristics
R1
50Ω
Bipolar Offset and Full-Scale Error Adjustments
+
VIN
A1
–
R2
10k
AIN
R4
100Ω
LTC1404
R3
10k
FULL-SCALE
ADJUST
GND
ADDITIONAL PINS OMITTED FOR CLARITY
±20LSB TRIM RANGE
1404 F10a
Figure 10a. LTC1404 Full-Scale Adjust Circuit
14
Figure 10c. LTC1404 Bipolar Offset and Full-Scale Adjust Circuit
Bipolar offset and full-scale errors are adjusted in a similar
fashion to the unipolar case. Bipolar offset error adjustment is achieved by applying an input voltage of – 0.5mV
(– 0.5LSB) to the input in Figure 10c and adjusting the op
amp until the ADC output code flickers between 0000 0000
0000 and 1111 1111 1111. For full-scale adjustment, an
input voltage of 2.0465V (FS – 1.5LSBs) is applied to the
input and R5 is adjusted until the output code flickers
between 0111 1111 1110 and 0111 1111 1111.
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BOARD LAYOUT AND BYPASSING
To obtain the best performance from the LTC1404, a
printed circuit board is required. Layout for the printed
circuit board should ensure that digital and analog signal
lines are separated as much as possible. In particular, care
should be taken not to run any digital traces alongside an
analog signal trace or underneath the ADC. The analog
input should be screened by GND.
High quality 10µF surface mount AVX capacitor with a
0.1µF ceramic should be used at the VCC, VSS and VREF
pins. For better results, another 10µF AVX capacitor can be
added to the VCC pin. At 600ksps, the CLK frequency can
be as high as 9.6MHz. A poor quality capacitor can lose
more than 80% of its capacitance at this frequency range.
Therefore, it is important to consult the manufacturer’s
data sheet before the capacitor is used. For the LTC1404,
at 600ksps, every bit decision must be determined within
104ns (9.6MHz). During this short time interval, the
supply disturbance due to a CLK transition needs to settle.
The ADC must update its DAC, make a comparator decision based on sub-mV overdrive, latch the new DAC
information and output the serial data. This ADC provides
one power supply, VCC, which is connected to both the
internal analog and digital circuitry. Any ringing due to
poor supply or reference bypassing, inductive trace runs,
CLK and CONV over- or undershoot, or unnecessary DOUT
loading can cause ADC errors. Therefore, the bypass
capacitors must be located as close to the pins as possible.
The traces connecting the pins and the bypass capacitors
must be kept short and should be made as wide as
possible. In unipolar mode operation, VSS must be connected to the GND pin directly.
Input signal leads to AIN and signal return leads from GND
(Pin 4) should be kept as short as possible to minimize
noise coupling. In applications where this is not possible,
a shielded cable between the analog input signal and the
ADC is recommended. Also, any potential difference in
grounds between the analog signal and the ADC appears
as an error voltage in series with the analog input signal.
Attention should be paid to reducing the ground circuit
impedance as much as possible.
Figure 11 shows the recommended system ground connections. All analog circuitry grounds should be terminated at the LTC1404 GND pin. The ground return from the
LTC1404 Pin 4 to the power supply should be low impedance for noise free operation. Digital circuitry grounds
must be connected to the digital supply common. As an
alternative, instead of a direct short between the digital and
analog circuitry, a 10Ω or a ferrite bead jumper helps
reduce the digital noise.
ANALOG SUPPLY
–5V
GND
+
VSS
GND
LTC1404
DIGITAL SUPPLY
5V
GND
+
VCC
5V
+
GND
VCC
DIGITAL CIRCUITRY
1404 F11
Figure 11. Power Supply Connection
In applications where the ADC data outputs and control
signals are connected to a continuously active microprocessor bus, it is possible to get errors in the conversion
results. These errors are due to feedthrough from the
microprocessor to the successive approximation comparator. The problem can be eliminated by forcing the
microprocessor into a Wait state during conversion or by
using three-state buffers to isolate the ADC data bus.
Power-Down Mode
Upon power-up, the LTC1404 is initialized to the active
state and is ready for conversion. However, the chip can be
easily placed into Nap or Sleep mode by exercising the
right combination of CLK and CONV signals. In Nap mode,
all power is off except for the internal reference, which is
still active and provides 2.43V output voltage to the other
circuitry. In this mode, the ADC draws only 7.5mW of
power instead of 75mW (for minimum power, the logic
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version will result in an all-zero output code, including the
REFRDY bit. If no conversion is attempted, the DOUT pin
remains in a high impedance state. If the ADC wakes from
Sleep mode, this can be determined by monitoring the
state of the REFRDY bit at the DOUT pin.
inputs must be within 500mV of the supply rails). In Sleep
mode, power consumption is reduced to a minimum by
cutting off power to all internal circuitry including the
reference. Figure 12 illustrates power-down modes for the
LTC1404. The chip enters Nap mode by keeping the CLK
signal low and pulsing the CONV signal twice. For Sleep
mode operation, the CONV signal should be pulsed four
times while CLK is kept low. Nap and Sleep modes are
activated on the falling edge of the CONV pulse.
DIGITAL INTERFACE
The digital interface requires only three digital lines. CLK
and CONV are both inputs, and the DOUT output provides
the conversion result in serial form.
The LTC1404 returns to active mode easily. The rising
edge of CLK wakes up the LTC1404. From Nap mode,
wake-up occurs within 350ns. During the transition from
Sleep mode to active mode, the VREF voltage ramp-up time
is a function of its loading conditions. With a 10µF bypass
capacitor, the wake-up time from Sleep mode is typically
2.5ms. A REFRDY signal is activated once the reference
has settled and is ready for an A/D conversion. This
REFRDY bit is sent to the DOUT pin as the first bit followed
by the 12-bit data word (refer to Figure 13). To save power
during wake-up from Sleep mode, the chip is designed to
enter Nap mode automatically until the reference is ready.
Once REFRDY goes high, the comparator powers up
immediately and is ready for a conversion. During the Nap
interval, any attempt to perform an analog-to-digital con-
Figure 13 shows the digital timing diagram of the LTC1404
during the A/D conversion. The CONV rising edge starts
the conversion. Once initiated, it can not be restarted until
the conversion is completed. If the time from CONV signal
to CLK rising edge is less than t2, the digital output will be
delayed by one clock cycle.
The digital output data is updated on the rising edge of the
CLK line. The digital output data consists of a REFRDY bit
followed by a valid 12-bit data word. DOUT data should be
captured by the receiving system on the rising CLK edge.
Data remains valid for a minimum time of t10 after the
rising CLK edge to allow capture to occur.
CLK
t1
t1
CONV
NAP
SLEEP
VREF
REFRDY
REFRDY = 1
REFRDY = 0
Hi-Z
Hi-Z
DOUT
NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS.
REFRDY APPEARS AS THE FIRST BIT IN THE DOUT WORD
Hi-Z
ALL ZERO
REFRDY BIT +12-BIT
DATA WORD
Hi-Z
1 11 10
1
0
REFRDY BIT
+12-BIT
DATA WORD
1404 F12
Figure 12. Nap Mode and Sleep Mode Waveforms
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t2
t7
t3
1
2
3
4
5
6
7
8
9
10
11
12
13
15
14
16
1
2
CLK
t4
t5
CONV
t6
INTERNAL
S/H STATUS
tACQ
SAMPLE
HOLD
SAMPLE
HOLD
t8
Hi-Z
DOUT
REFRDY
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Hi-Z
REFRDY
REFRDY BIT + 12-BIT DATA WORD
tCONV
tSAMPLE
1404 F13
Figure 13. ADC Digital Timing Diagram
CLK
CLK
VIH
VIH
t8
t9
t 10
90%
VOH
D OUT
D OUT
VOL
10%
1404 F14
Figure 14. CLK to DOUT Delay
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Hardware Interface to the TMS320C50’s TDM Serial Port (Frame Sync is Generated from TFSX)
5V
+
0.1µF
10µF
UNIPOLAR
INPUT
7.8MHz
EXTERNAL CLOCK
1
6
VCC
CLK
2
7
AIN
CONV
LTC1404
5
3
VREF
DOUT
+
10µF
0.1µF
VSS
GND
8
4
TMS320C50-40MHZ
TCLKX
TCLKR
TFSX
TFSR
TDR
1404 TA04a
Logic Analyzer Waveforms Show 2.05µs Throughput Rate (Input Voltage = 1.606V, Output Code = 0110 0100 0110 = 160610)
NOTE: THE TMS320C50-40MHz HAS A LIMITED SERIAL PORT CLOCK SPEED OF 7.8MHz. TO ALLOW THE LTC1404 TO RUN AT
ITS MAXIMUM SPEED OF 9.6MHz, THE TMS320C50-57 OR TMS320C50-80MHz IS NEEDED
Data from the LTC1404 Loaded into the TMS320C50’s TRCV Register
X RDY D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
1404 TA04c
Data Stored in the TMS320C50’s Memory (in Right Justified Format)
0
0
0
RDY D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1404 TA04d
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TMS320C50 Code for Circuit
THIS PROGRAM DEMONSTRATES THE LTC1404 INTERFACE TO THE
TMS320C50. FRAME SYNC PULSE IS GENERATED FROM TFSX.
DATA SHIFT CLOCK IS EXTERNALLY GENERATED.
*Initialization*
.mmregs
;- - Initialized data memory to zero
.ds
0F00h
DATA0 .word
0
DATA1 .word
0
DATA2 .word
0
DATA3 .word
0
DATA4 .word
0
DATA5 .word
0
;- - Set up the ISR vector
.ps
080Ah
rint :
B
RECEIVE
xint :
B
TRANSMIT
trnt :
B
TREC
txnt :
B
TTRANX
;- - Setup the reset vector
.ps 0A00h
.entry
START:
; Defines global symbolic names
; Initialize data to zero
; Begin sample data location
;.
; Location of data
;.
;.
; End sample data location
; Serial ports interrupts
; 0A;
; 0C;
; 0E;
; 10;
*TMS320C50 Initialization*
SETC INTM
; Temporarily disable all interrupts
LDP #0
; Set data page pointer to zero
OPL #0834h, PMST ; Set up the PMST status and control register
LACC #0
SAMM CWSR
; Set software wait state to 0
SAMM PDWSR
;
*Configure Serial Port*
SPLK #0028h, TSPC ; Set TDM Serial Port
; TDM = 0 Stand Alone mode
; DLB=0 Not loop back
; FO=0 16 Bits
; FSM=1 Burst Mode
; MCM=0 CLKR is generated externally
; TXM=1 FSX as output pin
; Put serial port into reset
; (XRST=RRST=0)
SPLK #00E8h, TSPC ; Take Serial Port out of reset
; (XRST=RRST=1)
SPLK #0FFFFh, IFR ; Clear all the pending interrupts
*Start Serial Communication*
SACL TDXR
; Generate frame sync pulse
SPLK #040h, IMR
; Turn on TRNT receiver interrupt
CLRC INTM
; Enable interrupt
CLRC SXM
; For Unipolar input, set for right shift
; with no sign extension
MAR *, AR7
; Load the auxiliary register pointer with seven
LAR AR7, #0F00h ; Load the auxiliary register seven with #0F00h
; as the begin address for data storage
WAIT:
NOP
; Wait for a receive interrupt
NOP
;
NOP
;
SACL TDXR
; !! Regenerate the frame sync pulse
B
WAIT
;
; - - - - - - - end of main program - - - - - - - - - - ;
*Receiver Interrupt Service Routine*
TREC:
LAMM TRCV
; Load the data received from LTC1404
SFR
; Shift right two times
SFR
;
AND #1FFFh, 0
; ANDed with #1FFFh
; For converting the data to right
; justified format
;
SACL *+, 0
; Write to data memory pointed by AR7 and
; increase the memory address by one
LACC AR7
;
SUB #0F05h,0
; Compare to end sample address #0F05h
BCND END_TRCV, GEQ ; If the end sample address has exceeded jump
to END_TRCV
;
SPLK #040h, IMR
; Else Re-enable the TRNT receive interrupt
RETE
; Return to main program and enable interrupt
*After Obtained the Data from LTC1404, Program Jump to END_TRCV*
END_TRCV:
SPLK #002h, IMR
; Enable INT2 for program to halt
CLRC INTM
SUCCESS:
B
SUCCESS
*Fill the Unused Interrupt with RETE, to avoid program get “lost”*
TTRANX:
RETE
RECEIVE:
RETE
TRANSMIT:
RETE
INT2:
B halt
; Halts the running CPU
19
LTC1404
U
TYPICAL APPLICATIONS
LTC1404 Interface to the ADSP2181’s SPORT0 (Frame Sync is Generated from RFS0)
9.6MHz
EXTERNAL CLOCK
5V
1
+
10µF
0.1µF
UNIPOLAR
INPUT
2
AIN
CONV
LTC1404
3
VREF
DOUT
+
0.1µF
10µF
CLK
VCC
VSS
GND
8
4
ADSP2181
6
SCLKO
7
RFSO
5
DR0
1404 TA05a
Logic Analyzer Waveforms Show 1.67µs Throughput Rate (Input Voltage = 1.604V, Output Code = 0110 0100 0100 = 160410)
1404 TA05b
NOTE: WITHOUT THE EXTERNAL CLOCKING SIGNAL, THE ADSP2181 SCLK0 CAN BE PROGRAMMED TO RUN AT 8.3MHz
Data from the LTC1404 (Normal Mode)
X
RDY D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
1404 TA05c
Data Stored in the ADSP2181’s Memory (Normal Mode, SLEN = D)
0
0
0
RDY D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1404 TA05d
20
LTC1404
U
TYPICAL APPLICATIONS
ADSP2181 Code for Circuit
THIS PROGRAM DEMONSTRATES THE LTC1404 INTERFACE TO
THE ADSP-2181. FRAME SYNC PULSE IS GENERATED FROM RFS.
DATA SHIFT CLOCK IS EXTERNALLY GENERATED.
/*Section 1: Initialization*/
.module/ram/abs = 0 adspltc; /*define the program module*/
jump start;
/*jump over interrupt vectors*/
nop; nop; nop;
rti; rti; rti; rti;
/*code vectors here upon IRQ2 int*/
rti; rti; rti; rti;
/*code vectors here upon IRQL1 int*/
rti; rti; rti; rti;
/*code vectors here upon IRQL0 int*/
rti; rti; rti; rti;
/*code vectors here upon SPORT0 TX int*/
ax0 = rx0;
/*Section 5*/
dm (0x2000) = ax0; /*begin of SPORT0 receive interrupt*/
rti;
/* */
/* */
/*end of SPORT0 receive interrupt*/
rti; rti; rti; rti;
/*code vectors here upon /IRQE int*/
rti; rti; rti; rti;
/*code vectors here upon BDMA interrupt*/
rti; rti; rti; rti;
/*code vectors here upon SPORT1 TX (IRQ1) int*/
rti; rti; rti; rti;
/*code vectors here upon SPORT1 RX (IRQ0) int*/
rti; rti; rti; rti;
/*code vectors here upon TIMER int*/
rti; rti; rti; rti;
/*code vectors here upon POWER DOWN int*/
/*Section 2: Configure SPORT0*/
start:
/*to configure SPORT0 control reg*/
/*SPORT0 address = 0X3FF6*/
/*RFS is used for frame sync generation*/
/*RFS is internal, TFS is not used*/
/*bit 0-3 = Slen*/
/*F = 15 = 1111*/
/*E = 14 = 1110*/
/*D = 13 = 1101*/
/*bit 4,5 data type right justified zero filled MSB*/
/*bit 6 INVRFS = 0*/
/*bit 7 INVTFS = 0*/
/*bit 8 IRFS=1 receive internal frame sync*/
/*bit 9,10,11 are for TFS (don’t care)*/
/*bit 12 RFSW=0 receive is Normal mode*/
/*bit 13 RTFS=1 receive is framed mode*/
/*bit 14 ISCLK=0 SCLK is external */
/*bit 15 multichannel mode = 0*/
ax0 = 0x2F0D;
/*normal mode, bit 12=0*/
/*if alternate mode bit 12=1, ax0=0x3F0E*/
dm (0x3FF6) =ax0;
/*Section 3: configure CLKDIV and RFSDIV, setup interrupts*/
/*Using an external clock source=9.6MHz*/
/*Does not need to configure CLKDIV*/
/*to Configure RFSDIV*/
ax0 = 15;
/*set the RFSDIV reg = 15*/
/*=> the frame sync pulse for every 16 SCLK*/
/*if frame sync pulse in every 15 SCLK, ax0=14*/
dm(0x3FF4) =ax0;
/*to setup interrupt*/
ifc= 0x0066;
/*clear any extraneous SPORT interrupts*/
icntl= 0;
/*IRQXB = level sensitivity*/
/*disable nesting interrupt*/
imask= 0x0020;
/*bit 0 = timer int = 0*/
/*bit 1 = SPORT1 or IRQ0B int = 0*/
/*bit 2 = SPORT1 or IRQ1B int = 0*/
/*bit 3 = BDMA int = 0*/
/*bit 4 = IRQEB int = 0*/
/*bit 5 = SPORT0 receive int = 1*/
/*bit 6 = SPORT0 transmit int = 0*/
/*bit 7 = IRQ2B int = 0*/
/*enable SPORT0 receive interrupt*/
/*Section 4: Configure System Control Register and Start Communication*/
/*to configure system control reg*/
ax0 = dm(0x3FFF);
/*read the system control reg*/
ay0 = 0xFFF0;
ar = ax0 AND ay0;
/*set wait state to zero*/
ay0 = 0x1000;
ar = ar OR ay0;
/*bit 12 = 1, enable SPORT0*/
dm(0x3FFF) = ar;
/*frame sync pulse regenerated automatically*/
cntr = 5000;
do waitloop until ce;
nop;
nop;
nop;
nop;
nop;
nop;
waitloop: nop;
rts;
.endmod;
21
LTC1404
U
TYPICAL APPLICATIONS
Quick Look Circuit for Converting Data to Parallel Format
5V
5V
1 V
CC
+
10µF
VSS 8
CONV
0.1µF
LTC1404
2.43V
REFERENCE
OUTPUT
ANALOG INPUT
(0V TO 4.096V)
2
3
+
10µF
0.1µF
4
CONV
AIN
VREF
GND
CLK
DOUT
7
12
10
SRCLR
QA
QB
11
QC
SRCK
QD
74HC595
14
QE
SER
QF
13
QG
G
QH
QH'
6
5
3-WIRE SERIAL
INTERFACE LINK
12
CLK
RCK
10
SRCLR
QA
QB
11
QC
SRCK
QD
74HC595
14
QE
SER
QF
13
QG
G
QH
QH'
RCK
15
1
2
3
4
5
6
7
9
15
1
2
3
4
5
6
7
9
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
REFRDY
1404 TA03
22
LTC1404
U
PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 – 0.197*
(4.801 – 5.004)
8
7
6
5
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
1
0.010 – 0.020
× 45°
(0.254 – 0.508)
0.008 – 0.010
(0.203 – 0.254)
0.053 – 0.069
(1.346 – 1.752)
0°– 8° TYP
0.016 – 0.050
0.406 – 1.270
0.014 – 0.019
(0.355 – 0.483)
2
3
4
0.004 – 0.010
(0.101 – 0.254)
0.050
(1.270)
TYP
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
SO8 0996
23
LTC1404
U
TYPICAL APPLICATIONS
LTC1404 Interface to TMS320C50 Running at 5MHz without External Clock
TMS320C50
5V
1
+
6
AIN
+
0.1µF
10µF
CLK
7
CONV
LTC1404
5
3
VREF
DOUT
UNIPOLAR
INPUT
0.1µF
10µF
VCC
2
TCLKX
TCLKR
TFSX
TFSR
VSS
GND
8
4
TDR
1404 TA07
LTC1404 Interface to ADSP2181 Running at 8.3MHz without External Clock
ADSP2181
5V
1
+
10µF
0.1µF
UNIPOLAR
INPUT
2
CLK
AIN
CONV
LTC1404
3
VREF
DOUT
+
0.1µF
10µF
VCC
VSS
GND
8
4
6
7
5
SCLKO
(8.3MHz)
RFSO
DR0
1404 TA06
RELATED PARTS
12-Bit Parallel Output ADCs
PART NUMBER
DESCRIPTION
COMMENTS
LTC1273/LTC1275/
LTC1276
Complete 5V Sampling 12-Bit ADCs with 70dB
SINAD at Nyquist
Lower Power and Cost Effective for fSAMPLE ≤ 300ksps
LTC1274/LTC1277
Low Power 12-Bit ADCs with Nap and Sleep Mode Shutdown
Lowest Power (10mW) for fSAMPLE ≤ 100ksps
LTC1278/LTC1279
High Speed Sampling 12-Bit ADCs with Shutdown
Cost Effective 12-Bit ADCs with Convert Start Input
Best for 300ksps < fSAMPLE ≤ 600ksps
LTC1282
Complete 3V 12-Bit ADCs with 12mW Power Dissipation
Fully Specified for 3V Powered Applications, fSAMPLE ≤ 140ksps
LTC1409
Low Power 12-Bit, 800ksps Sampling ADC
Best Dynamic Performance fSAMPLE ≤ 800ksps,
80mW Dissipation
LTC1410
12-Bit, 1.25Msps Sampling ADC with Shutdown
Best Dynamic Performance, THD = 84 and SINAD = 71 at Nyquist
12-Bit Serial Output ADCs
PART NUMBER
VCC
SAMPLE RATE
POWER DISSIPATION
LTC1285/LTC1288
3V
7.5/6.6ksps
0.48mW
3V, One or Two Input, Micropower, SO-8
LTC1286/LTC1298
DESCRIPTION
5V
12.5/11.1ksps
1.25mV
One or Two Input, Micropower, SO-8
LTC1290
5/±5V
50ksps
30mW
8 Input, Full-Duplex Serial I/O
LTC1296
5/±5V
46.5ksps
30mW
8 Input, Half-Duplex Serial I/O, Power Shutdown Output
LTC1400
5/±5V
400ksps
75mW
Complete 12-Bit, 400ksps, SO-8 ADC with Shutdown
LTC1401
3V
200ksps
15mW
Complete 12-Bit, 200ksps, SO-8 ADC with Shutdown
24
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417● (408)432-1900
FAX: (408) 434-0507● TELEX: 499-3977 ● www.linear-tech.com
1404f LT/TP 0398 4K • PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 1998