For:char Printed on:Mon, Feb 6, 1995 09:48:26 From book:DL121CH4 (5) VIEW Document:MC74F323 (5) VIEW Last saved on:Fri, Feb 3, 1995 16:04:13 MC74F323 8-INPUT SHIFT/STORAGE REGISTER WITH SYNCHRONOUS RESET AND COMMON I/O PINS The MC74F323 is an 8-Bit Universal Shift/Storage Register with 3-state outputs. Its function is similar to the F299 with the exception of Synchronous Reset. The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins. Separate outputs are provided for flip-flops Q0 and Q7 to allow easy cascading. A separate active LOW Master Reset is used to reset the register. Four modes of operation are possible: hold (store), shift left, shift right and parallel load. All modes are activated on the LOW-to-HIGH transition of the clock. • Common I/O For Reduced Pin Count • Four Operation Modes: Shift Left, Shift Right, Parallel Load and Store • Separate Continuous Inputs and Outputs from Q0 and Q7 Allow Easy 8-INPUT SHIFT/STORAGE REGISTER WITH SYNCHRONOUS RESET AND COMMON I/O PINS FAST SCHOTTKY TTL J SUFFIX CERAMIC CASE 732-03 20 1 Cascading • Fully Synchronous Reset • 3-State Outputs for Bus Oriented Applications • Input Clamp Diodes Limit High-Speed Termination Effects N SUFFIX PLASTIC CASE 738-03 20 1 CONNECTION DIAGRAM VCC 20 S1 19 DS7 Q7 18 17 I/O7 I/O5 I/O3 I/O1 CP 16 15 14 13 12 DS0 11 DW SUFFIX SOIC CASE 751D-03 20 1 ORDERING INFORMATION 1 S0 2 3 4 5 6 8 7 OE1 OE2 I/O6 I/O4 I/O2 I/O0 Q0 MC74FXXXJ Ceramic MC74FXXXN Plastic MC74FXXXDW SOIC 9 10 SR GND GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit 5.5 V VCC Supply Voltage 74 4.5 5.0 TA Operating Ambient Temperature Range 74 0 25 70 °C IOH Output Current — High 74 –1.0/– 3.0 mA IOL Output Current — Low 74 20/24 mA FAST AND LS TTL DATA 4-150 MC74F323 FUNCTION TABLE Inputs SR L H H H H S1 X H L H L S0 X H H L L CP Response ↑ ↑ ↑ ↑ X Synchronous Reset: Q0–Q7 = LOW Parallel Load: I/On º Qn Shift Right: DS0 º Q0, Q0 º Q1, etc. Shift Left: DS7 º Q7, Q7 º Q6, etc. Hold H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care ↑ = LOW-to-HIGH clock transition. FUNCTIONAL DESCRIPTION The MC74F323 contains eight edge-triggered D-type flips-flops and the interstage logic necessary to perform synchronous reset, shift left, shift right, parallel load and hold operations. The type of operation is determined by S0 and S1, as shown in the Function Table. All flip-flop outputs are brought out through 3-state buffers to separate I/O pins that also serve as data inputs in the parallel load mode. Q0 and Q7 are also brought out on other pins for expansion in serial shifting of longer words. A LOW signal on SR overrides the Select inputs and allows the flip-flops to be reset by the next rising edge of CP. All other state changes are initiated by the LOW-to-HIGH CP transition. Inputs can change when the clock is in either state provided only that the recommended set-up and hold times, relative to the rising edge of CP, are observed. A HIGH signal on either OE1 or OE2 disables the 3-state buffers and puts the I/O pins in the high impedance state. In this condition the shift, hold, load and reset operations can still occur. The 3-state buffers are also disabled by HIGH signals on both S0 and S1 in preparation for a parallel load operation. DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (Unless otherwise specified) Limits Symbol Parameter VIH VIL Input HIGH Voltage Input LOW Voltage VIK Input Clamp Diode Voltage Min Q0/Q7 VOH Output HIGH Voltage I/O VOL IIH Max IOZH Off-State Output Current, High-Level Voltage Applied IOZL Off-State Output Current, Low-Level Voltage Applied 2.5 74 2.7 74 2.7 74 2.4 0.8 V Guaranteed Input LOW Voltage –1.2 V VCC = MIN, IIN = –18 mA VCC = 4.5 V IOH = –1.0 mA VCC = 4.75 V V 3.4 0.5 0.5 Q0/Q7 20 I/O 70 Q0/Q7 0.1 I/O 1.0 S0, S1 Other Inputs –1.2 Output Short Circuit Current (Note 2) – 0.6 – 60 Total Supply Current Test Conditions Guaranteed Input HIGH Voltage I/O Input HIGH Current Input LOW Current 74 Unit V Q0/Q7 Output LOW Voltage IIL IOS ICC Typ 2.0 V IOH = – 3.0 mA VCC = 4.75 V VCC = 4.5 V V IOL = 20 mA IOL = 24 mA VCC = MIN µA VCC = MAX, VIN = 2.7 V mA VCC = MAX mA VCC = MAX, VIN = 0.5 V 70 µA 1.0 mA – 0.6 mA –150 mA 95 mA VCC = MAX VIN = 7.0 V VIN = 5.5 V VOUT = 2.7 V VOUT = 5.5 V VCC = MAX, VOUT = 0.5 V VCC = MAX VOUT = 0 V Outputs Disabled NOTES: 1. For conditions shown as MIN or MAX, use appropriate value specified under recommended operating conditions for the applicable device type. 2. Not more than one output should be shorted at a time, nor for more than 1 second. FAST AND LS TTL DATA 4-151 MC74F323 AC ELECTRICAL CHARACTERISTICS Symbol Parameter 74F 74F TA = +25°C VCC = +5.0 V CL = 50 pF Min Max TA = 0°C to +70°C VCC = +5.0 V ±10% CL = 50 pF Min Max Unit fMAX tPLH tPHL Maximum Input Frequency 70 70 MHz Propagation Delay CP to Q0 or Q7 3.5 3.5 9.0 8.5 3.5 3.5 10 9.5 ns tPLH tPHL Propagation Delay CP to I/On 3.5 5.0 9.0 11 3.5 5.0 10 12 ns tPZH tPZL Output Enable Time to HIGH or LOW Level 3.5 4.0 8.0 10 3.5 4.0 9.0 11 ns tPHZ tPLZ Output Disable Time to HIGH or LOW Level 2.0 2.0 6.0 5.5 2.0 2.0 7.0 6.5 ns AC SETUP REQUIREMENTS Symbol Parameter 74F 74F TA = +25°C VCC = +5.0 V CL = 50 pF TA = 0°C to +70°C VCC = +5.0 V ±10% CL = 50 pF Min Typ Max Min Unit Max ts(H) ts(L) Set-Up Time, HIGH or LOW S0 or S1 to CP 8.5 8.5 8.5 8.5 ns th(H) th(L) Hold Time, HIGH or LOW S0 or S1 to CP 0.0 0.0 0.0 0.0 ns ts(H) ts(L) Set-Up Time, HIGH or LOW I/On, DS0, DS7 to CP 5.0 5.0 5.0 5.0 ns th(H) th(L) Hold Time, HIGH or LOW I/On, DS0, DS7 to CP 2.0 2.0 2.0 2.0 ns ts(H) ts(L) Set-Up Time, HIGH or LOW SR to CP 10 10 10 10 ns th(H) th(L) Hold Time, HIGH or LOW SR to CP 0.0 0.0 0.0 0.0 ns tw(H) tw(L) CP Pulse Width, HIGH or LOW 7.0 7.0 7.0 7.0 ns S1 19 S0 LOGIC DIAGRAM 1 VCC = PIN 20 GND = PIN 10 = PIN NUMBERS 18 DS7 DS0 SR CP Q0 OE1 OE2 11 9 12 8 D CP Q D CP Q D CP Q D CP Q D CP Q D CP Q D CP Q D CP Q 17 Q7 2 3 7 I/O0 6 13 I/O1 I/O2 14 I/O3 FAST AND LS TTL DATA 4-152 4 15 5 I/O4 I/O5 I/O6 16 I/O7