Nonvolatile, I2C®-Compatible 64-Position, Digital Potentiometer AD5258 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAMS RDAC VDD RDAC EEPROM VLOGIC GND SCL SDA A RDAC REGISTER W B I2C SERIAL INTERFACE 6 DATA 6 CONTROL AD0 AD1 COMMAND DECODE LOGIC ADDRESS DECODE LOGIC POWERON RESET AD5258 05029-001 Nonvolatile memory maintains wiper settings 64-position digital potentiometer Compact MSOP-10 (3 mm × 4.9 mm) I2C-compatible interface VLOGIC pin provides increased interface flexibility End-to-end resistance 1 kΩ, 10 kΩ, 50 kΩ, 100 kΩ Resistance tolerance stored in EEPROM (0.1% accuracy) Power-on EEPROM refresh time <1 ms Software write protect command Address Decode Pin AD0 and Address Decode Pin AD1 allow four packages per bus 100-year typical data retention at 55°C Wide operating temperature −40°C to +85°C 3 V to 5 V single supply CONTROL LOGIC Figure 1. Block Diagram VDD VLOGIC APPLICATIONS A EEPROM SCL SDA AD0 AD1 RDAC REGISTER AND LEVEL SHIFTER I2C SERIAL INTERFACE COMMAND DECODE LOGIC W ADDRESS DECODE LOGIC CONTROL LOGIC GND B 05029-002 LCD panel VCOM adjustment LCD panel brightness and contrast control Mechanical potentiometer replacement in new designs Programmable power supplies RF amplifier biasing Automotive electronics adjustment Gain control and offset adjustment Fiber to the home systems Electronics level settings Figure 2. Block Diagram Showing Level Shifters GENERAL DESCRIPTION The AD5258 provides a compact, nonvolatile 3 mm × 4.9 mm packaged solution for 64-position adjustment applications. These devices perform the same electronic adjustment function as mechanical potentiometers 1 or variable resistors, but with enhanced resolution and solid-state reliability. The wiper settings are controllable through an I2C-compatible digital interface that is also used to read back the wiper register and EEPROM content in addition, resistor tolerance is stored within EEPROM, providing an end-to-end tolerance accuracy Rev. D of 0.1%. There is also a software write protection function that ensures data cannot be written to the EEPROM register. A separate VLOGIC pin delivers increased interface flexibility. For users who need multiple parts on one bus, Address Bit AD0 and Address Bit AD1 allow up to four devices on the same bus. 1 The terms digital potentiometer, VR (variable resistor), and RDAC are used interchangeably. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2005–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD5258 Data Sheet TABLE OF CONTENTS Writing ......................................................................................... 15 Features .............................................................................................. 1 Storing/Restoring ....................................................................... 15 Applications ....................................................................................... 1 Reading ........................................................................................ 15 Functional Block Diagrams ............................................................. 1 I C Byte Formats ............................................................................. 16 General Description ......................................................................... 1 Generic Interface ........................................................................ 16 Revision History ............................................................................... 2 Write Modes ................................................................................ 16 Specifications..................................................................................... 3 Read Modes ................................................................................. 17 Electrical Characteristics ............................................................. 3 Store/Restore Modes .................................................................. 17 Timing Characteristics ................................................................ 5 Tolerance Readback Modes ...................................................... 18 Absolute Maximum Ratings ............................................................ 6 ESD Protection of Digital Pins and Resistor Terminals ........ 19 ESD Caution .................................................................................. 6 Power-Up Sequence ................................................................... 19 Pin Configuration and Function Descriptions ............................. 7 Layout and Power Supply Bypassing ....................................... 19 Typical Performance Characteristics ............................................. 8 Multiple Devices on One Bus ................................................... 19 Test Circuits ..................................................................................... 13 Display Applications ...................................................................... 20 Theory of Operation ...................................................................... 14 Circuitry ...................................................................................... 20 Programming the Variable Resistor ......................................... 14 Outline Dimensions ....................................................................... 21 Programming the Potentiometer Divider ............................... 14 Ordering Guide .......................................................................... 21 2 I C Interface ..................................................................................... 15 2 REVISION HISTORY 1/13—Rev. C to Rev. D 3/07—Rev. 0 to Rev. A Changes to Zero-Scale Error Parameter and Logic Supply Parameter, Table 1.............................................................................. 3 Removed Evaluation Board Section and Figure 43, Renumbered Sequentially ......................................................................................19 Updated Format .................................................................. Universal Changes to Features Section ............................................................1 Changes to General Description Section .......................................1 Changes to Table 4.............................................................................7 Changes to I2C Interface Section .................................................. 15 Changes to Table 5.......................................................................... 16 Changes to Multiple Devices on One Bus Section ..................... 19 5/10—Rev. B to Rev. C Changes to Storing/Restoring Section ......................................... 15 Changes to Table 7 .......................................................................... 16 Changes to Table 14 ........................................................................ 17 3/05—Revision 0: Initial Version 1/10—Rev. A to Rev. B Changes to Figure 44 ...................................................................... 20 Updated Outline Dimensions ....................................................... 21 Rev. D | Page 2 of 24 Data Sheet AD5258 SPECIFICATIONS ELECTRICAL CHARACTERISTICS VDD = VLOGIC = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +85°C, unless otherwise noted. Table 1. Parameter DC CHARACTERISTICS—RHEOSTAT MODE Resistor Differential Nonlinearity 1 kΩ 10 kΩ/50 kΩ/100 kΩ Resistor Integral Nonlinearity 1 kΩ 10 kΩ/100 kΩ 50 kΩ Nominal Resistor Tolerance 1 kΩ 10 kΩ/50 kΩ/100 kΩ Resistance Temperature Coefficient Total Wiper Resistance DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE Differential Nonlinearity 1 kΩ 10 kΩ/50 kΩ/100 kΩ Integral Nonlinearity 1 kΩ 10 kΩ/50 kΩ/100 kΩ Full-Scale Error 1 kΩ 10 kΩ 50 kΩ/100 kΩ Zero-Scale Error 1 kΩ Symbol Conditions R-DNL RWB, VA = no connect R-INL Capacitance W Common-Mode Leakage DIGITAL INPUTS AND OUTPUTS Input Logic High Input Logic Low Leakage Current SDA, AD0, AD1 SCL – Logic High SCL – Logic Low Input Capacitance Typ 1 Max −1.5 −0.25 ±0.3 ±0.1 +1.5 +0.25 −5 −0.5 −0.25 ±0.5 ±0.1 ±0.1 +5 +0.5 +0.25 Unit LSB RWB, VA = no connect LSB TA = 25°C, VDD = 5.5 V RAB ΔRAB (ΔRAB × 106)/(RAB × ΔT) RWB 0.9 −30 Code = 0x00/0x20 Code = 0x00 1.5 +30 200/15 75 350 −1 −0.25 ±0.3 ±0.1 +1 +0.25 −1 −0.25 ±0.3 ±0.1 +1 +0.25 −6 −1 −1 −3 −0.3 −0.1 0 0 0 0 3 0 0.3 0 0.1 120/15 5 6 1 1.5 0.5 DNL INL LSB VWFSE Code = 0x3F VWZSE Code = 0x00 −40°C < TA < 85°C 85°C < TA < 125°C −40°C < TA < 85°C 85°C < TA < 125°C (ΔVW × 106)/(VW × ΔT) VA, VB ,VW CA, CB CW ICM kΩ % ppm/°C Ω LSB 10 kΩ 50 kΩ/100 kΩ Voltage Divider Temperature Coefficient RESISTOR TERMINALS Voltage Range Capacitance A, Capacitance B Min LSB Code = 0x00/0x20 GND f = 1 MHz, measured to GND, code = 0x20 f = 1 MHz, measured to GND, code = 0x20 VA = VB = VDD/2 VIH VIL IIL VDD 45 V pF 60 pF 10 nA 0.7 × VL −0.5 VIN = 0 V or 5 V VIN = 0 V VIN = 5 V CIL Rev. D | Page 3 of 24 −2.5 LSB LSB LSB LSB LSB LSB ppm/°C VL + 0.5 +0.3 × VL 0.01 −1.4 0.01 5 V V µA ±1 +1 ±1 pF AD5258 Parameter POWER SUPPLIES Power Supply Range Positive Supply Current Logic Supply Logic Supply Current Symbol VDD IDD VLOGIC ILOGIC Programming Mode Current (EEPROM) Power Dissipation ILOGIC(PROG) PDISS Power Supply Rejection Ratio PSRR DYNAMIC CHARACTERISTICS Bandwidth −3 dB 1 Data Sheet BW Total Harmonic Distortion THDW VW Settling Time tS Resistor Noise Voltage Density eN_WB Conditions Min Typ 1 Max Unit 0.5 5.5 2 5.5 V µA V 6 9 2.7 2.7 VIH = 5 V or VIL = 0 V −40°C < TA < 85°C 85°C < TA < 125°C VIH = 5 V or VIL = 0 V VIH = 5 V or VIL = 0 V, VDD = 5 V VDD = +5 V ± 10%, Code = 0x20 Code = 0x20 RAB = 1 kΩ RAB = 10 kΩ RAB = 50 kΩ RAB = 100 kΩ RAB = 10 kΩ, VA = 1 V rms, VB = 0, f = 1 kHz RAB = 10 kΩ, VAB = 5 V, ±1 LSB error band RWB = 5 kΩ, f = 1 kHz Typical values represent average readings at 25°C and VDD = 5 V. Rev. D | Page 4 of 24 3 35 20 40 µA µA mA µW ±0.01 ±0.06 %/% 18000 1000 190 100 0.1 kHz kHz kHz kHz % 500 ns 9 nV/√Hz Data Sheet AD5258 TIMING CHARACTERISTICS VDD = VLOGIC = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +85°C, unless otherwise noted. Table 2. Parameter I2C INTERFACE TIMING CHARACTERISTICS SCL Clock Frequency tBUF Bus-Free Time Between Stop and Start tHD;STA Hold Time (Repeated start) tLOW Low Period of SCL Clock tHIGH High Period of SCL Clock tSU;STA Setup Time for Repeated Start Condition tHD;DAT Data Hold Time tSU;DAT Data Setup Time tF Fall Time of Both SDA and SCL Signals tR Rise Time of Both SDA and SCL Signals tSU;STO Setup Time for Stop Condition EEPROM Data Storing Time EEPROM Data Restoring Time at Power On 1 EEPROM Data Restoring Time upon Restore Command1 EEPROM Data Rewritable Time 2 FLASH/EE MEMORY RELIABILITY Endurance 3 Data Retention 4 Symbol Conditions fSCL t1 t2 Min After this period, the first clock pulse is generated. t3 t4 t5 t6 t7 t8 t9 t10 tEEMEM_STORE tEEMEM_RESTORE1 tEEMEM_RESTORE2 Typ 0 1.3 0.6 1.3 0.6 0.6 0 100 Max Unit 400 kHz µs µs 26 300 µs µs µs µs ns ns ns µs ms µs 300 µs 540 µs 700 100 kCycles Years 0.9 300 300 0.6 VDD rise time dependant. Measure without decoupling capacitors at VDD and GND. VDD = 5 V. tEEMEM_REWRITE 100 During power-up, the output is momentarily preset to midscale before restoring EEPROM content. Delay time after power-on preset prior to writing new EEPROM data. 3 Endurance is qualified to 100,000 cycles per JEDEC Std. 22 Method A117 and is measured at −40°C, +25°C, and +85°C; typical endurance at +25°C is 700,000 cycles. 4 Retention lifetime equivalent at junction temperature (TJ) = 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV derates with junction temperature. 1 2 t8 t2 t4 t3 t8 t6 t9 t5 t10 t7 t9 t1 SDA P S P 2 Figure 3. I C Interface Timing Diagram Rev. D | Page 5 of 24 05029-004 SCL AD5258 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter VDD to GND VA, VB, VW to GND IMAX Pulsed 1 Continuous Digital Inputs and Output Voltage to GND Operating Temperature Range Maximum Junction Temperature (TJMAX) Storage Temperature Reflow Soldering Peak Temperature Time at Peak Temperature Thermal Resistance 2 θJA: MSOP-10 Rating −0.3 V to +7 V GND − 0.3 V, VDD + 0.3 V ±20 mA ±5 mA 0 V to 7 V −40°C to +85°C 150°C −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION 260°C 20 sec to 40 sec 200°C/W Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 2 Package power dissipation = (TJMAX – TA)/θJA. 1 Rev. D | Page 6 of 24 Data Sheet AD5258 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS W 1 AD0 2 AD5258 10 A 9 B 8 VDD TOP VIEW SDA 4 (Not to Scale) 7 GND SCL 5 6 VLOGIC 05029-005 AD1 3 Figure 4. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 Mnemonic W AD0 AD1 SDA SCL VLOGIC GND VDD B A Description W Terminal, GND ≤ VW ≤ VDD. Programmable Pin 0 for Multiple Package Decoding. State is registered on power-up. Programmable Pin 1 for Multiple Package Decoding. State is registered on power-up. Serial Data Input/Output. Serial Clock Input. Positive edge triggered. Logic Power Supply. Digital Ground. Positive Power Supply. B Terminal, GND ≤ VB ≤ VDD. A Terminal, GND ≤ VA ≤ VDD. Rev. D | Page 7 of 24 AD5258 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS VDD = VLOGIC = 5.5 V, RAB = 10 kΩ, TA = 25°C, unless otherwise noted. 0.10 0.4 0.08 0.2 2.7V 0.1 0 5.5V –0.1 –0.2 –0.3 05029-006 RHEOSTAT MODE INL (LSB) 0.3 –0.4 –0.5 0 8 16 24 32 40 48 56 0.06 0.04 0.02 0 –0.02 –40°C –0.04 +85°C –0.06 –0.08 –0.10 64 0 16 8 24 0.10 0.20 0.08 0.15 0.10 5.5V 0.05 0 –0.05 –0.10 2.7V –0.15 –0.20 –0.25 24 32 40 48 56 –0.06 –0.08 –0.10 64 0 8 16 –0.02 –0.04 +25ºC –0.08 –0.10 40 40 48 48 56 0.06 2.7V 0.04 0.02 0 –0.02 –0.04 5.5V –0.06 05029-011 POTENTIOMETER MODE DNL (LSB) +85ºC 0 05029-008 POTENTIOMETER MODE INL (LSB) 0.04 32 32 Figure 9. INL vs. Code vs. Supply Voltages 0.08 24 24 CODE (Decimal) 0.06 16 64 5.5V –0.04 0.08 8 56 0 –0.02 0.10 0 64 2.7V 0.02 0.10 –0.06 56 0.04 Figure 6. R-DNL vs. Code vs. Supply Voltages –40°C 64 0.06 CODE (Decimal) 0.02 56 05029-010 POTENTIOMETER MODE INL (LSB) 0.25 16 48 Figure 8. DNL vs. Code vs. Temperature 05029-007 RHEOSTAT MODE DNL (LSB) Figure 5. R-INL vs. Code vs. Supply Voltages 8 40 32 CODE (Decimal) CODE (Decimal) 0 +25°C 05029-009 POTENTIOMETER MODE DNL (LSB) 0.5 –0.08 –0.10 64 0 CODE (Decimal) 8 16 24 32 40 48 CODE (Decimal) Figure 7. INL vs. Code vs. Temperature Figure 10. DNL vs. Code vs. Supply Voltages Rev. D | Page 8 of 24 Data Sheet AD5258 0.50 0.25 0.45 ZSE @ VDD = 2.7V 0.40 0.15 0.35 0.10 0.05 ZSE (LSB) –40°C +85°C 0 –0.05 ZSE @ VDD = 5.5V 0.30 0.25 0.20 0.15 –0.10 +25°C 0.10 –0.15 0.05 05029-012 –0.20 –0.25 0 8 16 24 32 40 48 56 05029-015 RHEOSTAT MODE INL (LSB) 0.20 0 –40 64 –20 0 20 40 60 80 TEMPERATURE (°C) CODE (Decimal) Figure 14. Zero-Scale Error vs. Temperature Figure 11. R-INL vs. Code vs. Temperature 1 0.25 0.15 0.10 VDD = 5.5V +85°C –40°C +25°C IDD (µA) 0.05 0 –0.05 –0.10 –0.20 –0.25 0 8 16 24 32 40 48 56 0.1 –40 64 05029-016 –0.15 05029-013 RHEOSTAT MODE DNL (LSB) 0.20 –20 0 20 40 60 80 TEMPERATURE (°C) CODE (Decimal) Figure 15. Supply Current vs. Temperature Figure 12. R-DNL vs. Code vs. Temperature 6 0 –0.10 –0.20 –0.25 FSE @ VDD = 5.5V –0.30 –0.35 FSE @ VDD = 2.7V –0.40 05029-014 FSE (LSB) –0.15 –0.45 –0.50 –40 –20 0 20 40 60 5 VLOGIC = 5.5V 4 3 2 1 VLOGIC = 2.7V 0 –40 80 –20 0 20 05029-017 ILOGIC, LOGIC SUPPLY CURRENT (µA) –0.05 40 60 80 TEMPERATURE (°C) TEMPERATURE (ºC) Figure 16. Logic Supply Current vs. Temperature vs. VLOGIC Figure 13. Full-Scale Error vs. Temperature Rev. D | Page 9 of 24 AD5258 Data Sheet 120 200 100k R T @ VDD = 5.5V 100 150 TOTAL RESISTANCE (kΩ) 1k 100 50k 50 10k 0 –50 80 60 50k RT @ VDD = 5.5V 40 10k RT @ VDD = 5.5V 100k –150 0 8 16 24 32 40 48 56 1k RT @ VDD = 5.5V 20 0 –40 64 05029-021 –100 05029-018 RHEOSTAT MODE TEMPCO (ppm/°C) 250 –20 0 CODE (Decimal) Figure 17. Rheostat Mode Tempco (ΔRAB ×106)/(RAB × ∆T) vs. Code 60 80 0 0x20 –6 100 1k 0x10 –12 0x08 80 –18 GAIN (dB) 60 40 50k 20 0x04 0x02 –24 0x01 –30 –36 –42 05029-019 10k 100k 0 8 16 24 32 40 48 56 05029-022 –48 0 –20 –54 –60 10k 64 100k CODE (Decimal) 10M 100M Figure 21. Gain vs. Frequency vs. Code, RAB = 1 kΩ 350 0 0x20 –6 300 0x10 –12 RWB @ VDD = 2.7V 250 0x08 –18 GAIN (dB) 200 150 100 0x04 –24 0x02 –30 0x01 –36 –42 –20 0 20 40 05029-020 RWB @ VDD = 5.5V 60 05029-023 –48 50 0 –40 1M FREQUENCY (Hz) Figure 18. Potentiometer Mode Tempco (ΔVW × 106)/(VW × ΔT) vs. Code RWB @ 0x00 40 Figure 20. Total Resistance vs. Temperature 120 POTENTIOMETER MODE TEMPCO (ppm/°C) 20 TEMPERATURE (°C) –54 –60 1k 80 TEMPERATURE (°C) 10k 100k 1M FREQUENCY (Hz) Figure 19. RWB vs. Temperature Figure 22. Gain vs. Frequency vs. Code, RAB = 10 kΩ Rev. D | Page 10 of 24 10M Data Sheet AD5258 10k 0 0x20 –6 0x10 –12 0x08 0x04 –24 0x02 –30 0x01 –36 VDD = VLOGIC = 5V 1k ILOGIC (µA) GAIN (dB) –18 VDD = VLOGIC = 3V 100 –42 –54 –60 1k 10k 100k 10 1M 05029-026 05029-024 –48 0 1 2 Figure 23. Gain vs. Frequency vs. Code, RAB = 50 kΩ 4 5 Figure 25. Logic Supply Current vs. Input Voltage 80 0 CODE = MIDSCALE, VA = VLOGIC, VB = 0V 0x20 –6 0x10 –12 PSRR @ VLOGIC = 5V DC ± 10% p-p AC 60 0x08 –18 PSRR (dB) 0x04 –24 0x02 –30 0x01 –36 –42 40 PSRR @ VLOGIC = 3V DC ± 10% p-p AC 20 –54 –60 1k 10k 100k 0 100 1M FREQUENCY (Hz) 05029-027 –48 05029-025 GAIN (dB) 3 VIH (V) FREQUENCY (Hz) 1k 10k FREQUENCY (Hz) 100k Figure 26. Power Supply Rejection Ratio vs. Frequency Figure 24. Gain vs. Frequency vs. Code, RAB = 100 kΩ Rev. D | Page 11 of 24 1M Data Sheet 2V/DIV 500mV/DIV AD5258 VW 1 VW 5V/DIV SCL 2 400ns/DIV 05029-030 200ns/DIV Figure 27. Digital Feedthrough Figure 29. Large-Signal Settling Time VW 1 05029-029 200mV/DIV SCL 2 05029-028 5V/DIV 1 1µs/DIV Figure 28. Midscale Glitch, Code 0×7F to Code 0×80 Rev. D | Page 12 of 24 Data Sheet AD5258 TEST CIRCUITS Figure 30 through Figure 35 illustrate the test circuits that define the test conditions used in the product specification tables. VA V+ W W V+ B VMS V+ = VDD ± 10% ΔVMS% PSSR (%/%) = ΔVDD% DUT ΔVDD A B VMS 05029-031 A Figure 30. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL) 05029-034 V+ = VDD 1LSB = V+/2N DUT Figure 33. Test Circuit for Power Supply Sensitivity (PSS, PSSR) NO CONNECT DUT A IW AD8610 B OFFSET GND 05029-032 B VMS Figure 34. Test Circuit for Gain vs. Frequency RSW = 0.1V ISW DUT DUT CODE = 0x00 W IW = VDD/RNOMINAL VW ISW B RW = [VMS1 – VMS2]/IW VMS1 0.1V B 05029-033 W VMS2 VOUT –5V +2.5V Figure 31. Test Circuit for Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL) A +5V W VIN 05029-035 A W GND TO VDD 05029-036 DUT Figure 35. Test Circuit for Common-Mode Leakage Current Figure 32. Test Circuit for Wiper Resistance Rev. D | Page 13 of 24 AD5258 Data Sheet THEORY OF OPERATION The AD5258 is a 64-position digitally controlled variable resistor (VR) device. The wipers default value prior to programming the EEPROM is midscale. PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation The nominal resistance (RAB) of the RDAC between Terminal A and Terminal B is available in 1 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ. The nominal resistance of the VR has 64 contact points accessed by the wiper terminal. The 6-bit data in the RDAC latch is decoded to select one of 64 possible settings. A A B B B W W W 64 − D 64 × R AB + 2 × RW (2) Typical device-to-device matching is process lot dependent and may vary by up to ±30%. For this reason, resistance tolerance is stored in the EEPROM such that the user will know the actual RAB within 0.1%. Voltage Output Operation Figure 36. Rheostat Mode Configuration The general equation determining the digitally programmed output resistance between Wiper W and Terminal B is RWB (D ) = RWA (D ) = PROGRAMMING THE POTENTIOMETER DIVIDER 05029-037 A Similar to the mechanical potentiometer, the resistance of the RDAC between Wiper W and Terminal A produces a digitally controlled complementary resistance, RWA. The resistance value setting for RWA starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value. The general equation for this operation is D × R AB + 2 × RW 64 (1) The digital potentiometer easily generates a voltage divider at Wiper W-to-Terminal B and Wiper W-to-Terminal A proportional to the input voltage at Terminal A-to-Terminal B. Unlike the polarity of VDD-to-GND, which must be positive, voltage across Terminal A-to-Terminal B, Wiper W-to-Terminal A, and Wiper W-to-Terminal B can be at either polarity. where: VI A B VO Figure 38. Potentiometer Mode Configuration If ignoring the effect of the wiper resistance for approximation, connecting the A terminal to 5 V and the B terminal to ground produces an output voltage at Wiper W-to-Terminal B starting at 0 V up to 1 LSB less than 5 V. The general equation defining the output voltage at VW with respect to ground for any valid input voltage applied to Terminal A and Terminal B is A RS D5 D4 D3 D2 D1 D0 W 05029-039 D is the decimal equivalent of the binary code loaded in the 6-bit RDAC register. RAB is the end-to-end resistance. RW is the wiper resistance contributed by the on resistance of each internal switch. RS RS VW (D ) = W 64 − D D VA + VB 64 64 (3) A more accurate calculation, which includes the effect of wiper resistance (VW) is RS B VW (D) = 05029-038 RDAC LATCH AND DECODER Figure 37. AD5258 Equivalent RDAC Circuit Note that in the zero-scale condition, there is a relatively low value finite wiper resistance. Care should be taken to limit the current flow between Wiper W and Terminal B in this state to a maximum pulse current of no more than 20 mA. Otherwise, degradation or destruction of the internal switch contact may occur. R (D ) RWB (D) V A + WA VB R AB R AB (4) Operation of the digital potentiometer in the divider mode results in a more accurate operation over temperature. Unlike the rheostat mode, the output voltage is dependent mainly on the ratio of internal resistors (RWA and RWB) and not the absolute values. Rev. D | Page 14 of 24 Data Sheet AD5258 I2C INTERFACE Note that the wiper’s default value prior to programming the EEPROM is midscale. The master initiates a data transfer by establishing a start condition when a high-to-low transition on the SDA line occurs while SCL is high (see Figure 3). The next byte is the slave address byte, which consists of the slave address (first seven bits) followed by an R/W bit (see Table 6). When the R/W bit is high, the master reads from the slave device. When the R/W bit is low, the master writes to the slave device. The slave address of the part is determined by two configurable address pins, AD0 and AD1. The state of these two pins is registered upon power-up and decoded into a corresponding I2C 7-bit address (see Table 5). The slave address corresponding to the transmitted address bits responds by pulling the SDA line low during the ninth clock pulse (this is termed the slave acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. WRITING In the write mode, the last bit (R/W) of the slave address byte is logic low. The second byte is the instruction byte. The first three bits of the instruction byte are the command bits (see Table 6). The user must choose whether to write to the RDAC register or EEPROM register or to activate the software write protect (see Table 7 to Table 10). The final five bits are all zeros (see Table 13 and Table 14). The slave again responds by pulling the SDA line low during the ninth clock pulse. The final byte is the data byte MSB first. Don’t cares can be left either high or low. In the case of the write protect mode, data is not stored; rather, a logic high in the LSB enables write protect. Likewise, a logic low disables write protect. The slave again responds by pulling the SDA line low during the ninth clock pulse. STORING/RESTORING READING Assuming the register of interest was not just written to, it is necessary to write a dummy address and instruction byte. The instruction byte will vary depending on whether the data that is wanted is the RDAC register, EEPROM register, or tolerance register (see Table 11 to Table 16). After the dummy address and instruction bytes are sent, a repeat start is necessary. After the repeat start, another address byte is needed, except this time the R/W bit is logic high. Following this address byte is the readback byte containing the information requested in the instruction byte. Read bits appear on the negative edges of the clock. Don’t cares may be in either a high or low state. The tolerance register can be read back individually (see Table 15) or consecutively (see Table 16). Refer to the Read Modes section for detailed information on the interpretation of the tolerance bytes. After all data bits have been read or written, a stop condition is established by the master. A stop condition is defined as a lowto-high transition on the SDA line while SCL is high. In write mode, the master pulls the SDA line high during the 10th clock pulse to establish a stop condition (see Table 8). In read mode, the master issues a no acknowledge for the ninth clock pulse (that is, the SDA line remains high). The master then brings the SDA line low before the 10th clock pulse and raises SDA high to establish a stop condition (see Table 11). A repeated write function provides the user with the flexibility of updating the RDAC output multiple times after addressing and instructing the part only once. For example, after the RDAC has acknowledged its slave address and instruction bytes in the write mode, the RDAC output is updated on each successive byte until a stop condition is received. If different instructions are needed, the write/read mode must restart with a new slave address, instruction, and data byte. Similarly, a repeated read function of the RDAC is also allowed. In this mode, only the address and instruction bytes are necessary. The last bit (R/W) of the address byte is logic low. The first three bits of the instruction byte are the command bits (see Table 6). The two choices are transfer data from RDACto-EEPROM (store) or from EEPROM-to-RDAC (restore). The final five bits are all zeros (see Table 13 and Table 14). In addition, users should issue an NOP command immediately after restoring the EEMEM setting to RDAC, thereby minimizing supply current dissipation. Rev. D | Page 15 of 24 AD5258 Data Sheet I2C BYTE FORMATS The following generic, write, read, and store/restore control registers for the AD5258 refer to the device addresses listed in Table 5, and following is the mode/condition reference key. • S = Start Condition • P = Stop Condition • SA = Slave Acknowledge • MA = Master Acknowledge • NA = No Acknowledge • W = Write • R = Read • X = Don’t Care • AD1 and AD0 are two-state address pins. Table 5. Device Address Lookup AD1 Address Pin 0 1 0 1 AD0 Address Pin 0 0 1 1 I2 C Device Address 0011000 0011010 1001100 1001110 GENERIC INTERFACE Table 6. Generic Interface Format S 7-Bit Device Address (See Table 5) Slave Address Byte R/W SA C2 C1 C0 A4 A3 A2 A1 A0 SA D7 D6 D5 D4 D3 D2 D1 D0 SA P Instruction Byte Data Byte Table 7. RDAC-to-EEPROM Interface Command Descriptions C2 0 0 0 1 1 1 1 C1 0 0 1 0 0 1 C0 0 1 0 0 1 0 Command Description Operation between I2C and RDAC Operation between I2C and EEPROM Operation between I 2C and Write Protection Register. See Table 10. NOP Restore EEPROM to RDAC 1 Store RDAC to EEPROM This command leaves the device in the EEMEM read power state, which consumes power. Issue the NOP command to return the device to its idle state. WRITE MODES Table 8. Writing to RDAC Register S 7-Bit Device Address (See Table 5) Slave Address Byte 0 SA 0 0 0 0 0 0 0 Instruction Byte 0 SA X X SA X X D5 SA 0 D5 D4 D3 D2 Data Byte D1 D0 SA P Table 9. Writing to EEPROM Register S 7-Bit Device Address (See Table 5) Slave Address Byte 0 SA 0 0 1 0 0 0 0 Instruction Byte 0 D4 D3 D2 Data Byte D1 D0 SA P SA P The wiper’s default value prior to programming the EEPROM is midscale. Table 10. Activating/Deactivating Software Write Protect S 7-Bit Device Address (See Table 5) Slave Address Byte 0 SA 0 1 0 0 0 0 Instruction Byte 0 0 0 0 0 0 0 Data Byte 0 WP To activate the write protection mode, the WP bit in Table 10 must be logic high. To deactivate the write protection, the command must be resent except with the WP in logic zero state. Rev. D | Page 16 of 24 Data Sheet AD5258 READ MODES interested in reading a register that was previously written to. For example, if the EEPROM was just written to, the user can skip the two dummy bytes and proceed directly to the slave address byte followed by the EEPROM readback data. Read modes are referred to as traditional because the first two bytes for all three cases are dummy bytes that function to place the pointer toward the correct register. This is the reason for the repeat start. In theory, this step can be avoided if the user is Table 11. Traditional Readback of RDAC Register Value 7-Bit Device Address (See Table 5) Slave Address Byte S 7-Bit Device Address (See Table 5) Slave Address Byte 0 SA 0 0 0 0 0 0 0 0 SA S Instruction Byte 1 SA X X D5 D4 D3 D2 D1 D0 NA P Read-back Data ↑ Repeat Start Table 12. Traditional Readback of Stored EEPROM Value 7-Bit Device Address (See Table 5) Slave Address Byte S 7-Bit Device Address (See Table 5) Slave Address Byte 0 SA 0 0 1 0 0 0 0 0 SA S Instruction Byte ↑ 1 SA X X D5 D4 D3 D2 D1 D0 NA P Read-back Data Repeat Start STORE/RESTORE MODES Table 13. Storing RDAC Value to EEPROM S 7-Bit Device Address (See Table 5) 0 SA 1 1 0 Slave Address Byte 0 0 0 0 0 0 0 0 Instruction Byte 0 SA P Instruction Byte Table 14. Restoring EEPROM to RDAC 1 S 1 7-Bit Device Address (See Table 5) Slave Address Byte 0 SA 1 User should issue an NOP command immediately after this command to conserve power. Rev. D | Page 17 of 24 0 1 0 SA P AD5258 Data Sheet TOLERANCE READBACK MODES Table 15. Traditional Readback of Tolerance (Individually) S 7-Bit Device Address (See Table 5) Slave Address Byte 7-Bit Device Address (See Table 5) Slave Address Byte 0 SA 0 0 1 1 1 1 1 0 SA S Instruction Byte ↑ 1 SA D7 D6 D5 D4 D3 D2 D1 D0 NA P Sign + Integer Byte Repeat Start S 7-Bit Device Address (See Table 5) Slave Address Byte 7-Bit Device Address (See Table 5) Slave Address Byte 0 SA 0 0 1 1 1 1 1 1 SA S Instruction Byte ↑ 1 SA D7 D6 D5 D4 D3 D2 D1 D0 NA P Decimal Byte Repeat Start Table 16. Traditional Readback of Tolerance (Consecutively) S 7-Bit Device Address 7-Bit Device Address (See Table 5) (See Table 5) 0 SA 0 0 1 1 1 1 1 0 SA S 1 SA D7 D6 D5 D4 D3 D2 D1 D0 MA D7 D6 D5 D4 D3 D2 D1 D0 NA P Slave Address Byte Instruction Byte Slave Address Byte Sign + Integer Byte Decimal Byte ↑ Repeat Start Calculating RAB Tolerance Stored in Read-Only Memory D7 D6 D5 D4 D3 D2 D1 D0 SIGN 26 25 24 23 22 21 20 SIGN A D7 D6 D5 D4 D3 D2 D1 D0 2–1 2–2 2–3 2–4 2–5 2–6 2–7 2–8 SEVEN BITS FOR AN INTEGER NUMBER EIGHT BITS FOR A DECIMAL NUMBER A 05029-040 A Figure 39. Format of Stored Tolerance in Sign Magnitude Format with Bit Position Descriptions (Unit is Percent; Only Data Bytes are Shown) The AD5258 features a patented RAB tolerance storage in the nonvolatile memory. Tolerance is stored in the memory during factory production and can be read by users at any time. The knowledge of stored tolerance allows users to accurately calculate RAB. This feature is valuable for precision, rheostat mode, and open-loop applications where knowledge of absolute resistance is critical. The stored tolerance resides in the read-only memory and is expressed as a percentage. The tolerance is stored in two memory location bytes in sign magnitude binary form (see Figure 39). The two EEPROM address bytes are 11110 (sign + integer) and 11111 (decimal number). The two bytes can be individually accessed with two separate commands (see Table 15). Alternatively, readback of the first byte followed by the second byte can be done in one command (see Table 16). In the latter case, the memory pointer automatically increments from the first to the second EEPROM location (increments from 11110 to 11111) if read consecutively. In the first memory location, the MSB is designated for the sign (0 = + and 1 = −) and the seven LSBs are designated for the integer portion of the tolerance. In the second memory location, all eight data bits are designated for the decimal portion of tolerance. Note that the decimal portion has a limited accuracy of only 0.1%. For example, if the rated RAB = 10 kΩ and the data readback from Address 11110 shows 0001 1100 and from Address 11111 shows 0000 1111, the tolerance can be calculated as MSB: 0 = + Next 7 MSB: 001 1100 = 28 8 LSB: 0000 1111 = 15 × 2–8 = 0.06 Tolerance = 28.06% Rounded Tolerance = 28.1% and therefore RAB_ACTUAL = 12.810 kΩ Rev. D | Page 18 of 24 Data Sheet AD5258 ESD PROTECTION OF DIGITAL PINS AND RESISTOR TERMINALS of powering VA, VB, VW and the digital inputs is not important as long as they are powered after GND, VDD, and VLOGIC. The AD5258 VDD, VLOGIC, and GND power supplies define the boundary conditions for proper 3-terminal and digital input operation. Supply signals present on Terminal A, Terminal B, and Terminal W that exceed VDD or GND are clamped by the internal forward-biased ESD protection diodes (see Figure 40). Digital Input SCL and Digital Input SDA are clamped by ESD protection diodes with respect to VLOGIC and GND as shown in Figure 41. LAYOUT AND POWER SUPPLY BYPASSING VDD A W 05029-041 B GND It is good practice to employ compact, minimum lead length layout design. The leads to the inputs should be as direct as possible with minimum conductor length. Ground paths should have low resistance and low inductance. Similarly, it is also good practice to bypass the power supplies with quality capacitors for optimum stability. Supply leads to the device should be bypassed with disc or chip ceramic capacitors of 0.01 µF to 0.1 µF. In addition, low ESR 1 µF to 10 µF tantalum or electrolytic capacitors should be applied at the supplies to minimize any transient disturbance and low frequency ripple (see Figure 42). As well, the digital ground should be joined remotely to the analog ground at one point to minimize the ground bounce. Figure 40. Maximum Terminal Voltages Set by VDD and GND VDD C2 10µF VLOGIC + VDD C1 0.1µF AD5258 SCL GND 05029-042 GND 05029-043 SDA Figure 42. Power Supply Bypassing Figure 41. Maximum Terminal Voltages Set by VLOGIC and GND MULTIPLE DEVICES ON ONE BUS POWER-UP SEQUENCE Because the ESD protection diodes limit the voltage compliance at Terminal A, Terminal B, and Terminal W (see Figure 40), it is important to power GND/VDD/VLOGIC before applying any voltage to Terminal A, Terminal B, and Terminal W; otherwise, the diode is forward-biased such that VDD and VLOGIC are powered unintentionally and may affect the user’s circuit. The ideal power-up sequence is in the following order: GND, VDD, VLOGIC, digital inputs, and then VA, VB, VW. The relative order The AD5258 has two configurable address pins, AD0 and AD1. The state of these two pins is registered upon power-up and decoded into a corresponding I2C-compatible 7-bit address (see Table 5). This allows up to four devices on the bus to be written to or read from independently. Rev. D | Page 19 of 24 AD5258 Data Sheet DISPLAY APPLICATIONS CIRCUITRY affect that node’s bias because it is only on the order of microamps. VLOGIC is tied to the microcontroller’s (MCU) 3.3 V digital supply because VLOGIC will draw the 35 mA that is needed when writing to the EEPROM. It would be impractical to try to source 35 mA through the 70 kΩ resistor; therefore, VLOGIC is not connected to the same node as VDD. A special feature of the AD5258 is its unique separation of the VLOGIC and VDD supply pins. The reason for doing this is to provide greater flexibility in applications that do not always provide the needed supply voltages. In particular, LCD panels often require a VCOM voltage in the range of 3 V to 5 V. The circuit in Figure 43 is the rare exception in which a 5 V supply is available to power the digital potentiometer. 5V SUPPLIES POWER VCC (~3.3V) TO BOTH THE MCU AND THE LOGIC SUPPLY OF THE DIGITAL POTENTIOMETER 14.4V R1 70kΩ C1 1µF C1 1µF AD5258 R6 10kΩ R5 10kΩ VLOGIC MCU SCL SDA R2 A 10kΩ B W R5 10kΩ – VDD VLOGIC U1 AD8565 + R1 70kΩ AD5258 R6 10kΩ – VDD 14.4V A 3.5V < VCOM < 4.5V MCU SCL SDA B R2 10kΩ W U1 AD8565 + 3.5V < VCOM < 4.5V GND GND R3 25kΩ 05029-045 R3 25kΩ Figure 44. Circuitry When a Separate Supply Is Not Available for VDD Figure 43. VCOM Adjustment Application More commonly, only analog 14.4 V and digital logic 3.3 V supplies are available (see Figure 44). By placing discrete resistors above and below the digital potentiometer, VDD can be tapped off the resistor string itself. Based on the chosen resistor values, the voltage at VDD in this case equals 4.8 V, allowing the wiper to be safely operated up to 4.8 V. The current draw of VDD will not 05029-046 VCC (~3.3V) For this reason, VLOGIC and VDD are provided as two separate supply pins that can either be tied together or treated independently; VLOGIC supplies the logic/EEPROM with power, and VDD biases up the A, B, and W terminals for added flexibility. For a more detailed look at this application, refer to the article, “Simple VCOM Adjustment uses any Logic-Supply Voltage” in the September 30, 2004, issue of EDN magazine. Rev. D | Page 20 of 24 Data Sheet AD5258 OUTLINE DIMENSIONS 3.10 3.00 2.90 10 3.10 3.00 2.90 1 5.15 4.90 4.65 6 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.30 0.15 6° 0° 0.23 0.13 0.70 0.55 0.40 COMPLIANT TO JEDEC STANDARDS MO-187-BA 091709-A 0.15 0.05 COPLANARITY 0.10 Figure 45. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD5258BRMZ1 AD5258BRMZ1-R7 AD5258BRMZ10 AD5258BRMZ10-R7 AD5258BRMZ50 AD5258BRMZ50-R7 AD5258BRMZ100 AD5258BRMZ100-R7 EVAL-AD5258DBZ 1 2 RAB (kΩ) 1 1 10 10 50 50 100 100 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 2 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP Evaluation Board Package Option RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 Z = RoHS Compliant Part. The evaluation board is shipped with the 10 kΩ RAB resistor option; however, the board is compatible with all available resistor value options. Rev. D | Page 21 of 24 Branding D4K D4K D4L D4L D4M D4M D4N D4N AD5258 Data Sheet NOTES Rev. D | Page 22 of 24 Data Sheet AD5258 NOTES Rev. D | Page 23 of 24 AD5258 Data Sheet NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2005–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05029-0-1/13(D) Rev. D | Page 24 of 24