Single-Channel, 64-Position, Push Button, ±8% Resistor Tolerance, Nonvolatile Digital Potentiometer AD5116 Data Sheet FEATURES APPLICATIONS Single-channel, 64-position resolution 5 kΩ, 10 kΩ, 80 kΩ nominal resistance Maximum ±8% nominal resistor tolerance error Low minimum A-W and B-W resistance feature End scale resistance indicator 2.3 V to 5.5 V single-supply operation ±6 mA maximum continuous A, B, and W current density Simple push button manual configurable control Built-in adaptive debouncer Discrete step-up/step-down control Auto scan up/down control Auto or manual save of wiper position Power-on EEPROM refresh time < 50 μs Rheostat mode temperature coefficient: 35 ppm/°C Potentiometer mode temperature coefficient: 5 ppm/°C 50-year typical data retention at 125°C 1 million write cycles Wide operating temperature: −40°C to +125°C Thin, 2 mm × 2 mm × 0.55 mm 8-lead LFCSP package Mechanical potentiometer replacement Portable electronics level adjustment Audio volume control Low resolution DAC LCD panel brightness and contrast control Programmable voltage to current conversion Programmable filters, delays, time constants Feedback resistor programmable power supply Sensor calibration FUNCTIONAL BLOCK DIAGRAM VDD DATA CONTROL LOGIC BLOCK DATA RDAC REGISTER ASE A PU ADAPTIVE DEBOUNCER PD W B AD5116 GND 09657-001 VDD EEPROM Figure 1. GENERAL DESCRIPTION The AD5116 provides a nonvolatile digital potentiometer solution for 64-position adjustment applications, offering guaranteed low resistor tolerance errors of ±8% and up to ±6 mA current density in the A, B, and W pins. The low resistor tolerance, low nominal temperature coefficient, and high bandwidth simplify open-loop applications, as well as tolerance matching applications. The new low A-W and B-W resistance feature minimizes the wiper resistance in the extremes of the resistor array to typically 45 Ω. A simple push button interface allows manual control with just two external push button switches. The AD5116 is designed with a built-in adaptive debouncer that ignores invalid bounces due to contact bounce (commonly found in mechanical switches). The debouncer is adaptive, accommodating a variety of push buttons. The AD5116 can automatically save the last wiper position into EEPROM, making it suitable for applications that require a power-up in the last wiper position, for example, audio equipment. The AD5116 is available in a 2 mm × 2 mm 8-lead LFCSP package. The part is guaranteed to operate over the extended industrial temperature range of −40°C to +125°C. Table 1. NVM ±8% Resistance Tolerance Family Model AD5110 AD5111 AD5112 AD5113 AD5116 AD5114 AD5115 Resistance (kΩ) 10, 80 10, 80 5, 10, 80 5, 10, 80 5, 10, 80 10, 80 10, 80 Position 128 128 64 64 64 32 32 Interface I2C Up/down I2C Up/down Push button I2C Up/down Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. AD5116 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Test Circuits ..................................................................................... 12 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 13 Functional Block Diagram .............................................................. 1 RDAC Register............................................................................ 13 General Description ......................................................................... 1 EEPROM ..................................................................................... 13 Revision History ............................................................................... 2 Automatic Save Enable .............................................................. 13 Specifications..................................................................................... 3 End Scale Resistance Indicator ................................................. 14 Electrical Characteristics ............................................................. 3 RDAC Architecture .................................................................... 14 Interface Timing Specifications .................................................. 5 Programming the Variable Resistor ......................................... 14 Timing Diagrams.......................................................................... 5 Programming the Potentiometer Divider ............................... 15 Absolute Maximum Ratings............................................................ 6 Terminal Voltage Operating Range ......................................... 15 Thermal Resistance ...................................................................... 6 Power-Up Sequence ................................................................... 15 ESD Caution .................................................................................. 6 Layout and Power Supply Biasing ............................................ 15 Pin Configuration and Function Descriptions ............................. 7 Outline Dimensions ....................................................................... 16 Typical Performance Characteristics ............................................. 8 Ordering Guide .......................................................................... 16 REVISION HISTORY 10/11—Revision 0: Initial Version Rev. 0 | Page 2 of 16 Data Sheet AD5116 SPECIFICATIONS ELECTRICAL CHARACTERISTICS 5 kΩ, 10 kΩ, and 80 kΩ versions: VDD = 2.3 V to 5.5 V, VA = VDD, VB = 0 V, −40°C < TA < +125°C, unless otherwise noted. Table 2. Parameter DC CHARACTERISTICS—RHEOSTAT MODE Resolution Resistor Integral Nonlinearity 2 Resistor Differential Nonlinearity2 Nominal Resistor Tolerance Resistance Temperature Coefficient 3 Wiper Resistance DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE Integral Nonlinearity 4 Differential Nonlinearity4 Full-Scale Error Zero-Scale Error Voltage Divider Temperature Coefficient3 RESISTOR TERMINALS Maximum Continuous IA, IB, and IW Current3 Symbol N R-INL R-DNL ΔRAB/RAB (ΔRAB/RAB)/ΔT × 106 RW RBS RTS INL DNL VWFSE VWZSE (ΔVW/VW)/ΔT × 106 CA, CB Capacitance W3, 6 CW Output High Voltage3 Output Current3 Three-State Leakage Current3 Input Capacitance3 RAB = 5 kΩ, VDD = 2.3 V to 2.7 V RAB = 5 kΩ, VDD = 2.7 V to 5.5 V RAB = 10 kΩ RAB = 80 kΩ RAB = 5 kΩ RAB =10 kΩ RAB = 80 kΩ RAB = 5 kΩ RAB =10 kΩ RAB = 80 kΩ Code = half scale Typ 1 Max 6 −2.5 −1 −1 −0.25 −1 −8 ±0.5 ±0.25 ±0.25 ±0.1 ±0.25 +2.5 +1 +1 +0.25 +1 +8 −0.5 −0.5 −2.5 −1.5 −1 35 70 45 70 140 80 140 ±0.15 ±0.15 +0.5 +0.5 +1.5 +1 +0.25 ±10 −6 −1.5 GND f = 1 MHz, measured to GND, code = half scale, VW = VA = 2.5 V or VW = VB = 2.5 V f = 1 MHz, measured to GND, code = half scale, VA = VB = 2.5 V VA = VW = VB VINH VINL IN CIN VOH IO IOZ CIN Min Code = full scale Code = zero scale Code = bottom scale Code = top scale RAB = 5 kΩ, 10 kΩ RAB = 80 kΩ Terminal Voltage Range 5 Capacitance A, Capacitance B3, 6 Common-Mode Leakage Current3 DIGITAL INPUTS (PU AND PD) Input Logic3 High Low Input Current3 Input Capacitance3 DIGITAL OUTPUT (ASE) Test Conditions/Comments +6 +1.5 VDD LSB LSB LSB LSB LSB LSB LSB LSB ppm/°C 20 35 pF 50 nA 0.8 ±1 V V µA pF 16 ±1 V mA µA pF 5 4.8 5 Rev. 0 | Page 3 of 16 Bits LSB LSB LSB LSB LSB % ppm/°C Ω Ω Ω mA mA V pF 2 ISINK = 2 mA, VDD = 5 V VDD = 5 V Unit AD5116 Parameter POWER SUPPLIES Single-Supply Power Range Positive Supply Current EEMEM Store Current3, 7 EEMEM Read Current3, 8 Power Dissipation 9 Power Supply Rejection3 DYNAMIC CHARACTERISTICS3, 10 Bandwidth Total Harmonic Distortion VW Settling Time Resistor Noise Density FLASH/EE MEMORY RELIABILITY3 Endurance 11 Data Sheet Symbol Test Conditions/Comments IDD IDD_NVM_STORE IDD_NVM_READ PDISS PSR VDD = 5 V Min Typ 1 Max Unit 5.5 750 2 320 5 V nA mA µA µW −43 −50 −64 dB dB dB 4 2 200 MHz MHz kHz −75 −80 −85 dB dB dB 2.5 3 10 µs µs µs 7 9 20 nV/√Hz nV/√Hz nV/√Hz 1 MCycles kCycles Years 2.3 BW THD ts eN_WB VIH = VLOGIC or VIL = GND ∆VDD/∆VSS = 5 V ± 10% RAB = 5 kΩ RAB =10 kΩ RAB = 80 kΩ Code = half scale − 3 dB RAB = 5 kΩ RAB = 10 kΩ RAB = 80 kΩ VA = VDD/2 + 1 V rms, VB = VDD/2, f = 1 kHz, code = half scale RAB = 5 kΩ RAB = 10 kΩ RAB = 80 kΩ VA = 5 V, VB = 0 V, ±0.5 LSB error band RAB = 5 kΩ RAB = 10 kΩ RAB = 80 kΩ Code = half scale, TA = 25°C, f = 100 kHz RAB = 5 kΩ RAB = 10 kΩ RAB = 80 kΩ TA = 25°C 100 Data Retention 12 50 Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V. Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to 0.8 × VDD/RAB. 3 Guaranteed by design and characterization, not subject to production test. 4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. 6 CA is measured with VW = VA = 2.5 V, CB is measured with VW = VB = 2.5 V, and CW is measured with VA = VB = 2.5 V. 7 Different from operating current; supply current for NVM program lasts approximately 30 ms. 8 Different from operating current; supply current for NVM read lasts approximately 20 µs. 9 PDISS is calculated from (IDD × VDD). 10 All dynamic characteristics use VDD = 5.5 V, and VLOGIC = 5 V. 11 Endurance is qualified at 100,000 cycles per JEDEC Standard 22, Method A117 and measured at 150°C. 12 Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV derates with junction temperature in the Flash/EE memory. 1 2 Rev. 0 | Page 4 of 16 Data Sheet AD5116 INTERFACE TIMING SPECIFICATIONS VDD = 2.3 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter t1 t2 t3 t4 t5 tEEPROM_PROGRAM1 tPOWER_UP2 1 2 Test Conditions/Comments Min 8 1 140 1 8 ASE = 0 V, PD = GND, PU = GND ASE = VDD Typ Max 15 50 50 Unit ms sec ms sec ms ms μs Description Debounce time Manual to auto scan time Auto scan step Auto save execute time Low pulse time to manual storage Memory program time Power-on EEPROM restore time EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at a lower temperature and higher write cycles. Maximum time after VDD is equal to 2.3 V. TIMING DIAGRAMS PD/PU (LOW) t1 tEEPROM PROGRAM t5 PU ASE DATA EEPROM 09657-002 RW Figure 2. Manual Increment Mode Timing NEW DATA Figure 5. Manual Save Mode Timing t1 t3 t1 PD t2 PU RW = 45Ω 09657-003 RW ASE Figure 6. End Scale Indication Timing Figure 3. Auto Increment Mode Timing t1 t4 tEEPROM PROGRAM PD RW DATA NEW DATA 09657-004 ASE (LOW) EEPROM 09657-006 RW PD (LOW) Figure 4. Auto Save Mode Timing Rev. 0 | Page 5 of 16 09657-005 PD (LOW) AD5116 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 4. Parameter VDD to GND VA, VW , VB to GND IA, IW , IB Pulsed1 Frequency > 10 kHz RAW = 5 kΩ and 10 kΩ RAW = 80 kΩ Frequency ≤ 10 kHz RAW = 5 kΩ and 10 kΩ RAW = 80 kΩ Continuous RAW = 5 kΩ and 10 kΩ RAW = 80 kΩ Push Button Inputs Operating Temperature Range3 Maximum Junction Temperature (TJ Max) Storage Temperature Range Reflow Soldering Peak Temperature Time At Peak Temperature Package Power Dissipation Rating –0.3 V to +7.0 V GND − 0.3 V to VDD + 0.3 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE ±6 mA/d2 ±1.5 mA/d2 θJA is defined by JEDEC specification JESD-51, and the value is dependent on the test board and test environment. Table 5. Thermal Resistance ±6 mA/√d2 ±1.5 mA/√d2 Package Type 8-Lead LFCSP ±6mA ±1.5mA −0.3 V to +7 V or VDD + 0.3 V (whichever is less) −40°C to +125°C 150°C −65°C to +150°C 1 θJA 901 JEDEC 2S2P test board, still air (0 m/sec air flow). ESD CAUTION 260°C 20 sec to 40 sec (TJ max − TA)/θJA 1 Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 2 Pulse duty factor. 3 Includes programming of EEPROM memory. Rev. 0 | Page 6 of 16 θJC 25 Unit °C/W Data Sheet AD5116 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VDD 1 8 ASE A 2 AD5116 7 PU W 3 TOP VIEW (Not to Scale) 6 PD 5 GND NOTES 1. THE EXPOSED PAD IS INTERNALLY FLOATING. 09657-007 B 4 Figure 7. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1 2 3 4 5 6 Mnemonic VDD A W B GND PD 7 PU 8 ASE EPAD Description Positive Power Supply. This pin should be decoupled with 0.1µF ceramic capacitors and 10 µF capacitors. Terminal A of RDAC. GND ≤ VA ≤ VDD. Wiper terminal of RDAC. GND ≤ VW ≤ VDD. Terminal B of RDAC. GND ≤ VB ≤ VDD. Ground Pin. Push-Down Pin. Connect to the external push button. Active high. An internal 100 kΩ pull-down resistor is connected to GND. Push-Up Pin. Connect to the external push button. Active high. An internal 100 kΩ pull-down resistor is connected to GND. Automatic Save Enable. Automatic save enable is configured at power-up. Active low. This pin requires a pull resistor connected between VDD or GND. If ASE is enabled, this pin also indicates when the end scale (maximum or minimum resistance) has been reached. Exposed Pad. The exposed pad is internally floating. Rev. 0 | Page 7 of 16 AD5116 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0.08 0.02 5kΩ, –40°C 5kΩ, +25°C 5kΩ, +125°C 10kΩ, –40°C 80kΩ, –40°C 10kΩ, +25°C 80kΩ, +25°C 10kΩ, +125°C 80kΩ, +125°C 0.01 0.06 0 0.04 R-DNL (LSB) 0.02 0 5kΩ, –40°C 5kΩ, +25°C 5kΩ, +125°C 10kΩ, –40°C 10kΩ, +25°C 10kΩ, +125°C 80kΩ, –40°C 80kΩ, +25°C 80kΩ, +125°C –0.04 –0.06 –0.02 –0.03 –0.04 –0.05 –0.06 0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63 CODE (Decimal) –0.07 0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63 CODE (Decimal) Figure 8. R-INL vs. Code Figure 11. R-DNL vs. Code 0.08 0.04 5kΩ, –40°C 10kΩ, –40°C 0.01 5kΩ, +125°C 10kΩ, +125°C –0.01 0 –0.02 –0.04 –0.02 –0.03 –0.04 –0.06 80kΩ, –40°C –0.06 Figure 9. INL vs. Code 800 700 80kΩ, +25°C 80kΩ, +125°C 0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63 CODE (Decimal) 09657-012 0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63 CODE (Decimal) 09657-009 –0.05 –0.08 Figure 12. DNL vs. Code 1.2 VDD = 2.3V VDD = 3.3V VDD = 5V TA = 25°C VDD = 5V VDD = 3.3V VDD = 2.3V 1.0 SUPPLY CURRENT (mA) 600 500 400 300 200 0.8 0.6 0.4 100 0.2 –100 –40 –25 –10 5 20 35 50 65 TEMPERATURE (°C) 80 95 110 125 Figure 10. Supply Current vs. Temperature 0 0.05 0.65 1.25 1.85 2.45 3.05 3.65 4.25 4.85 DIGITAL INPUT VOLTAGE (V) Figure 13. Supply Current (IDD) vs. Digital Input Voltage Rev. 0 | Page 8 of 16 09657-013 0 09657-010 SUPPLY CURRENT (nA) 5kΩ, +25°C 10kΩ, +25°C 0 DNL (LSB) 0.02 INL (LSB) 0.02 5kΩ, –40°C 5kΩ, +25°C 5kΩ, +125°C 10kΩ, –40°C 10kΩ, +25°C 10kΩ, +125°C 80kΩ, –40°C 80kΩ, +25°C 80kΩ, +125°C 0.06 09657-011 –0.02 09657-008 R-INL (LSB) –0.01 Data Sheet AD5116 0 0 0x20 0x20 –10 –10 0x10 0x10 0x08 0x08 0x04 GAIN (dB) 0x02 –30 0x01 –40 0x00 –30 0x04 0x02 0x01 0x00 –40 –50 –50 –60 100k 1M 10M 100M FREQUENCY (Hz) –70 10k 09657-014 –60 10k 100k 1M 10M FREQUENCY (Hz) Figure 14. 5 kΩ Gain vs. Frequency vs. Code 09657-017 GAIN (dB) –20 –20 Figure 17. 10 kΩ Gain vs. Frequency vs. Code 0 0 0x20 –10 0x10 –10 0x08 –20 PHASE (Degrees) 0x02 –30 GAIN (dB) –20 0x04 0x01 0x00 –40 –50 –30 –40 –50 –60 –60 –70 –70 RAB = 10kΩ 1M FREQUENCY (Hz) –80 10k 200 POTENTIOMETER MODE TEMPCO (ppm/°C) 140 120 100 80 60 40 20 0 10 20 30 40 50 60 CODE (Decimal) VDD = 5V 10kΩ 80kΩ 5kΩ 180 160 140 120 100 80 60 40 20 0 0 10 20 30 40 50 60 CODE (Decimal) Figure 16. Rheostat Mode Tempco ΔRWB/ΔT vs. Code Figure 19. Potentiometer Mode Tempco ΔRWB/ΔT vs. Code Rev. 0 | Page 9 of 16 09657-019 0 09657-016 RHEOSTAT MODE TEMPCO (ppm/°C) 160 10M Figure 18. Normalized Phase Flatness vs. Frequency VDD = 5V 10kΩ 80kΩ 5kΩ 180 1M FREQUENCY (Hz) Figure 15. 80 kΩ Gain vs. Frequency vs. Code 200 100k 09657-018 100k 09657-015 –80 10k FULL SCALE HALF SCALE QUARTER SCALE AD5116 0 Data Sheet –10 –20 0 5kΩ 10kΩ 80kΩ VDD = 5V VA = 2.5V + 1VRMS VB = 2.5V CODE = HALF SCALE NOISE FILTER = 22kHz –10 VDD = 5V VA = 2.5V + VIN VB = 2.5V fIN = 1kHz CODE = HALF SCALE NOISE FILTER = 22kHz –20 –30 –30 THD + N (dB) THD + N (dB) 5kΩ 10kΩ 80kΩ –40 –50 –60 –40 –50 –60 –70 –70 –80 20 200 2k 20k –90 0.001 09657-020 –100 200k FREQUENCY (Hz) 0.35 60 80k + 150pF 80k + 250pF 5k + 0pF 5k + 75pF 5k + 150pF 10k + 0pF VDD = 5V VA = VDD VB = GND 0.30 5kΩ 10kΩ 80kΩ 0.25 RELATIVE VOLTAGE (V) 5k + 250pF 10k + 75pF 10k + 150pF 10k + 250pF 80k + 0pF 80k + 75pF 70 50 40 30 20 0.20 0.15 0.10 0.05 0 10 20 30 40 50 60 CODE (Decimal) –0.10 –1 3 5 TIME (µs) 7 9 Figure 24. Maximum Transition Glitch Figure 21. Maximum Bandwidth vs. Code vs. Net Capacitance 150 1 1.2 0.0025 TA = 25°C 5.5V 5V 3.3V 2.7V 2.3V 1.0 0.0020 PROBABILITY DENSITY 120 90 60 30 0.8 0.0015 0.6 0.0010 0.4 0.0005 1 2 3 4 5 VDD (V) 6 0 09657-022 0 0.2 0 –600 –500 –400 –300 –200 –100 0 100 200 300 RESISTOR DRIFT (ppm) Figure 25. Resistor Lifetime Drift Figure 22. Incremental Wiper on Resistance vs. VDD Rev. 0 | Page 10 of 16 CUMULATIVE PROBABILITY 10 09657-021 0 09657-024 –0.05 0 400 500 600 09657-047 BANDWIDTH (MHz) 1 Figure 23. Total Harmonic Distortion + Noise (THD + N) vs. Amplitude 80 INCREMENTAL WIPER ON RESISTANCE (Ω) 0.1 AMPLITUDE (V rms) Figure 20. Total Harmonic Distortion + Noise (THD + N) vs. Frequency 0 0.01 09657-023 –80 –90 Data Sheet AD5116 0 7 5kΩ 10kΩ 80kΩ VDD = 5V ± 10% AC VA = 4V VB = GND –10 HALF SCALE TA = 25°C 6 THEORETICAL IMAX (mA) –20 PSRR (dB) 10kΩ 80kΩ 5kΩ –30 –40 –50 5 4 3 2 –60 1k 10k 100k 1M FREQUENCY (Hz) 0 0 10 20 30 40 50 60 CODE (Decimal) Figure 26. Power Supply Rejection Ratio (PSRR) vs. Frequency 09657-029 100 09657-026 1 –70 10 Figure 29. Theoretical Maximum Current vs. Code 20 0.4 VDD = 5V VA = VDD VB = GND 0.3 TA = 25°C 18 16 0.2 CURRENT (mA) 0 –0.1 12 10 8 –0.2 6 –0.3 4 10kΩ 80kΩ 5kΩ –0.5 0 2 0.6 1.2 1.8 2.5 TIME (µs) 0 0 1 2 3 4 09657-044 –0.4 09657-027 VOLTAGE (mV) 14 0.1 5 VDD (V) Figure 27. Digital Feedthrough Figure 30. Maximum ASE Output Current vs. Voltage 8 0 5kΩ 10kΩ 80kΩ –10 VDD = 3V 7 6 CURRENT (mA) –30 –40 –50 5 4 3 2 –60 –70 1k 10k 1M FREQUENCY (Hz) 10M Figure 28. Shutdown Isolation vs. Frequency 0 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 31. Maximum ASE Output Current vs. Temperature Rev. 0 | Page 11 of 16 09657-045 1 09657-028 GAIN (dB) –20 AD5116 Data Sheet TEST CIRCUITS Figure 32 to Figure 37 define the test conditions used in the Specifications section. NC DUT A W IW VA B B Figure 32. Resistor Position Nonlinearity Error (Rheostat Operation: R-INL, R-DNL) Figure 35. Power Supply Sensitivity (PSS, PSRR) DUT –15V Figure 36. Gain and Phase vs. Frequency GND VDD RW = DUT A W 0.1V IWB GND VDD + IWB – GND TO VDD NC = NO CONNECT 0.1V DUT GND 09657-032 B VOUT 09657-034 2.5V Figure 33. Potentiometer Divider Nonlinearity Error (INL, DNL) NC OP42 B OFFSET GND VDD Figure 34. Wiper Resistance A ICM W B VDD GND 09657-035 VMS W VIN W B +15V A V+ = VDD 1LSB = V+/2N 09657-031 A V+ VMS 09657-030 NC = NO CONNECT ∆VMS PSRR (dB) = 20 log ∆V DD ∆VMS% PSS (%/%) = ∆VDD% W V+ ~ VMS DUT A 09657-033 V+ = VDD ± 10% VDD Figure 37. Common-Mode Leakage Current Rev. 0 | Page 12 of 16 Data Sheet AD5116 THEORY OF OPERATION The AD5116 digital programmable resistor is designed to operate as a true variable resistor for analog signals within the terminal voltage range of GND < VTERM < VDD. The resistor wiper position is determined by the RDAC register contents. The RDAC register is a standard logic register; there is no restriction on the number of changes allowed. The RDAC register can be programmed with any position setting using the push button interface. Once a desirable wiper position is found, this value can be stored in the EEPROM memory. Thereafter, the wiper position is always restored to that position for subsequent power-up. The storing of EEPROM data takes approximately 20 ms; during this time, the device is locked and does not accept any new operation, thus preventing any changes from taking place. steps are not equal to 1 LSB, and are not included in the INL, DNL, R-INL, and R-DNL specifications. Whenever the minimum RWB (= RBS) is reached, the resistance stops decrementing. Any continuous holding of the PD to logic high simply elevates the supply current. When RAW reaches the minimum resistance (= RTS), continuous holding of PU only elevates the supply current. EEPROM The AD5116 contains an EEPROM memory that allows wiper position storage. Once a desirable wiper position is found, this value can be saved into the EEPROM. Thereafter, the wiper position will always be set at that position for any future on-off-on power supply sequence. AUTOMATIC SAVE ENABLE RDAC REGISTER The RDAC register directly controls the position of the digital potentiometer wiper. For example, when the RDAC register is 0x20, the wiper is connected to midscale of the variable resistor. The RDAC register is controlled using the PD and PU push buttons. The step-up and step-down operations require the activation of the PU (push-up) and PD (push-down) pins. These pins have 100 kΩ internal pull-up resistors that PU and PD activate at logic high. The following paragraphs explain how to increment the RDAC register, but all the descriptions are valid to decrement the RDAC register, swapping PU by PD. At power-up, the AD5116 checks the level in the ASE pin. If the pin is pulled low, as shown in Figure 38, the automatic store is enabled. If the pin is pulled high, as shown in Figure 39, automatic store is disabled and the RDAC register should be stored manually. During the storage cycle, the device is locked and does not accept any new operation preventing any changes from taking place. ASE AD5116 100kΩ GND 09657-036 The AD5116 is designed to support external push buttons (tactile switches) directly, as shown in Figure 1. Figure 38. Automatic Store Enables Manual Increment The AD5116 features an adaptive debouncer that monitors the duration of the logic high level of PU signal between bounces. If the PU logic high level signal duration is shorter than 8 ms, the debouncer ignores it as an invalid incrementing command. Whenever the logic high level of PU signal lasts longer than 8 ms, the debouncer assumes that the last bounce is met and, therefore, increments the RDAC register by one step. The wiper is incremented by one tap position, as shown in Figure 2. Auto Scan Increment If the PU button is held for longer than 1 second, continuously holding it activates auto scan mode, and the AD5116 increments the RDAC register by one step every 140 ms until PU is released. Typical timing is shown in Figure 3. Auto Save If there is no activity on inputs during 1 second, the AD5116 stores the RDAC register data into EEPROM, as shown in Figure 4. Manual Store The storage is controlled by the ASE pin, which is connected to an adaptive debouncer. If the ASE pin is pulled low longer than 8 ms, the AD5116 saves the RDAC register data into EEPROM, as shown in Figure 5. Low Wiper Resistance Feature VDD VDD 100kΩ The AD5116 includes extra steps to achieve a minimum wiper resistance. Between Terminal W and Terminal B, this extra step is called bottom scale and the wiper resistance decreases from 70 Ω to 45 Ω. Between Terminal A and Terminal W, this extra step is called top scale and connects the A and W terminals, reducing the 1 LSB resistor typical at full-scale code. These new extra steps are loaded automatically in the RDAC register after zero-scale or full-scale position has been reached. The extra Rev. 0 | Page 13 of 16 AD5116 09657-037 ASE Figure 39. Automatic Store Disables with Manual Storage Push Button AD5116 Data Sheet END SCALE RESISTANCE INDICATOR PROGRAMMING THE VARIABLE RESISTOR When the auto save mode is enabled, the ASE pin also indicates when the RDAC register reaches the maximum or minimum scale. The AD5116 pulls the ASE pin high and holds it as long as PD or PU is active, and the part is placed in the end scale resistance (RTS or RBS), as shown in Figure 6. The typical pin configuration is shown in Figure 40. Rheostat Operation—±8% Resistor Tolerance ASE AD5116 100kΩ 09657-038 GND A B RWB RBS To achieve optimum performance, Analog Devices, Inc., has patented the RDAC segmentation architecture for all the digital potentiometers. In particular, the AD5116 employs a two-stage segmentation approach as shown in Figure 41. The AD5116 wiper switch is designed with the transmission gate CMOS topology and with the gate voltage derived from VDD. SW RW RWB (D ) D R AB RW 64 Bottom scale (1) From 0 to 64 (2) where: D is the decimal equivalent of the binary code in the 6-bit RDAC register. RAB is the end-to-end resistance. RBS is the wiper resistance at bottom scale. RAW RAB RW W RW R AW (D ) RL RL B Similar to the mechanical potentiometer, the resistance of the RDAC between the W terminal and the A terminal also produces a digitally controlled complementary resistance, RWA. RWA starts at the maximum resistance value and decreases as the data loaded into the latch increases. The general equation for this operation is: TS RL 6-BIT ADDRESS DECODER B W The nominal resistance between Terminal A and Terminal B, RAB, is available in 5 kΩ, 10 kΩ, and 80 kΩ and has 64 tap points accessed by the wiper terminal. The 6-bit data in the RDAC latch is decoded to select one of the 64 possible wiper settings. The general equation for determining the digitally programmed output resistance between the W terminal and B terminal is: RDAC ARCHITECTURE RL A W Figure 42. Rheostat Mode Configuration Figure 40. Typical End Scale Indicator Circuit A A W 09657-040 When the part is placed at the end of the resistance scale (RTS or RBS), the ASE pin is pulled high during the debounce time, until the RDAC register is incremented (RBS) or decremented (RTS) by activating PU or PD. The AD5116 operates in rheostat mode when only two terminals are used as a variable resistor. The unused terminal can be floating or tied to the W terminal as shown in Figure 42. RAW RTS BS 64 D R AB RW 64 Bottom scale (3) From 0 to 63 (4) Top scale (5) where: D is the decimal equivalent of the binary code in the 6-bit RDAC register. RAB is the end-to-end resistance. RW is the wiper resistance. RTS is the wiper resistance at top scale. 09657-039 B Figure 41. Simplified RDAC Circuit Top Scale/Bottom Scale Architecture In addition, the AD5116 includes a new feature to reduce the resistance between terminals. These extra steps are called bottom scale and top scale. At bottom scale, the typical wiper resistance decreases from 70 Ω to 45 Ω. At top scale, the resistance between Terminal A and Terminal W is decreased by 1 LSB and the total resistance is reduced to 70 Ω. The extra steps are not equal to 1 LSB and are not included in the INL, DNL, R-INL, and R-DNL specifications. Regardless of which setting the part is operating in, take care to limit the current between the A terminal to B terminal, W terminal to A terminal, and W terminal to B terminal, to the maximum continuous current or pulsed current specified in Table 4. Otherwise, degradation or possible destruction of the internal switch contact can occur. Rev. 0 | Page 14 of 16 Data Sheet AD5116 PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output Operation The digital potentiometer easily generates a voltage divider at wiper-to-B and wiper-to-A that is proportional to the input voltage at A to B, as shown in Figure 43. Unlike the polarity of VDD to GND, which must be positive, voltage across A-to-B, Wto-A, and W-to-B can be at either polarity. A W VDD VOUT B 09657-041 VIN any voltage to Terminal A, Terminal B, and Terminal W. Otherwise, the diodes are forward-biased such that VDD is powered on unintentionally and can affect other parts of the circuit. Similarly, VDD should be powered down last. The ideal power-on sequence is in the following order: GND, VDD, and VA/VB/VW. The order of powering VA, VB, and VW is not important as long as they are powered on after VDD. The states of the PU and PD pins can be logic low or floating, but they should not be logic high during power-on. A Figure 43. Potentiometer Mode Configuration W If ignoring the effect of the wiper resistance for simplicity, connecting Terminal A to 5 V and Terminal B to ground produces an output voltage at the Wiper W to Terminal B ranging from 0 V to 5 V. The general equation defining the output voltage at VW, with respect to ground for any valid input voltage applied to Terminal A and Terminal B, is: 09657-042 GND Figure 44. Maximum Terminal Voltages Set by VDD and VSS R (D ) RWB (D) VA AW VB RAB RAB (6) where: RWB(D) can be obtained from Equation 1 or Equation 2. RAW(D) can be obtained from Equation 3 to Equation 5 . Operation of the digital potentiometer in the divider mode results in a more accurate operation over temperature. Unlike the rheostat mode, the output voltage is dependent mainly on the ratio of the internal resistors, RWA and RWB, and not the absolute values. Therefore, the temperature drift reduces to 5 ppm/°C. LAYOUT AND POWER SUPPLY BIASING It is always a good practice to use compact, minimum lead length layout design. The leads to the input should be as direct as possible with a minimum conductor length. Ground paths should have low resistance and low inductance. It is also good practice to bypass the power supplies with quality capacitors. Low equivalent series resistance (ESR) 1 μF to 10 μF tantalum or electrolytic capacitors should be applied at the supplies to minimize any transient disturbance and to filter low frequency ripple. Figure 45 illustrates the basic supply bypassing configuration for the AD5116. AD5116 TERMINAL VOLTAGE OPERATING RANGE The AD5116 is designed with internal ESD diodes for protection. These diodes also set the voltage boundary of the terminal operating voltages. Positive signals present on Terminal A, Terminal B, or Terminal W that exceed VDD are clamped by the forward-biased diode. There is no polarity constraint between VA, VW, and VB, but they cannot be higher than VDD or lower than GND. POWER-UP SEQUENCE Because of the ESD protection diodes that limit the voltage compliance at Terminal A, Terminal B, and Terminal W (see Figure 44), it is important to power on VDD before applying Rev. 0 | Page 15 of 16 VDD VDD C2 + 10µF C1 0.1µF GND AGND Figure 45. Power Supply Bypassing 09657-043 VW (D) B AD5116 Data Sheet OUTLINE DIMENSIONS 1.70 1.60 1.50 2.00 BSC SQ 0.50 BSC 8 5 PIN 1 INDEX AREA 1.10 1.00 0.90 EXPOSED PAD 0.425 0.350 0.275 1 4 TOP VIEW 0.60 0.55 0.50 BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.05 MAX 0.02 NOM 0.30 0.25 0.20 PIN 1 INDICATOR (R 0.15) 07-11-2011-B SEATING PLANE 0.175 REF 0.20 REF Figure 46. 8-Lead Lead Frame Chip Scale Package [LFCSP_UD] 2.00 mm × 2.00 mm Body, Ultra Thin, Dual Lead (CP-8-10) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD5116BCPZ5-RL7 AD5116BCPZ5-500R7 AD5116BCPZ10-RL7 AD5116BCPZ10-500R7 AD5116BCPZ80-RL7 AD5116BCPZ80-500R7 EVAL-AD5116SDZ 1 RAB (kΩ) 5 5 10 10 80 80 Resolution 64 64 64 64 64 64 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 8-Lead LFCSP_UD 8-Lead LFCSP_UD 8-Lead LFCSP_UD 8-Lead LFCSP_UD 8-Lead LFCSP_UD 8-Lead LFCSP_UD Evaluation Board Z = RoHS Compliant Part. ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09657-0-10/11(0) Rev. 0 | Page 16 of 16 Package Option CP-8-10 CP-8-10 CP-8-10 CP-8-10 CP-8-10 CP-8-10 Branding Code 7G 7G 7F 7F 7H 7H