2 ADC, 6 DAC, 96 kHz, 24-Bit Sigma-Delta Codec AD1839A FEATURES GENERAL DESCRIPTION 5 V stereo audio system with 3.3 V tolerant digital interface Supports up to 96 kHz sample rates 192 kHz sample rate available on 1 DAC Supports 16-/20-/24-bit word lengths Multibit Σ-∆ modulators with perfect differential linearity restoration for reduced idle tones and noise floor Data-directed scrambling DACs—least sensitive to jitter Single-ended output ADCs: −95 dB THD + N, 105 dB SNR and dynamic range DACs: −92 dB THD + N, 108 dB SNR and dynamic range On-chip volume controls per channel with 1024-step linear scale DAC and ADC software controllable clickless mutes Digital de-emphasis processing Supports 256 × fS, 512 × fS, and 768 × fS master mode clocks Power-down mode and soft power-down mode Flexible serial data port with right-justified, left-justified, I2S compatible, and DSP serial modes TDM interface mode supports 8-in/8-out operation using a single SHARC® SPORT 52-lead MQFP plastic package The AD1839A is a high performance single-chip codec that features three stereo DACs and one stereo ADC. Each DAC comprises a high performance digital interpolation filter, a multibit Σ-∆ modulator featuring Analog Devices’ patented technology, and a continuous-time voltage-out analog section. Each DAC has independent volume control and clickless mute functions. The ADC comprises two 24-bit conversion channels with multibit Σ-∆ modulators and decimation filters. The AD1839A also contains an on-chip reference with a nominal value of 2.25 V. The AD1839A contains a flexible serial interface that allows glueless connection to a variety of DSP chips, AES/EBU receivers, and sample rate converters. The AD1839A can be configured in left-justified, right-justified, I2S, or DSP compatible serial modes. Control of the AD1839A is achieved by means of an SPI® compatible serial port. While the AD1839A can be operated from a single 5 V supply, it also features a separate supply pin for its digital interface that allows the device to be interfaced to other devices using 3.3 V power supplies. The AD1839A is available in a 52-lead MQFP package and is specified for the −40°C to +85°C industrial temperature range. APPLICATIONS DVD video and audio players Home theater systems Automotive audio systems Audio/visual receivers Digital audio effects process FUNCTIONAL BLOCK DIAGRAM DVDD DVDD ODVDD ALRCLK ABCLK ASDATA CCLK CLATCH CIN COUT CONTROL PORT VOLUME VOLUME SERIAL DATA I/O PORT VOLUME VOLUME ADCLP ADCLN Σ-∆ ADC DIGITAL FILTER ADCRP ADCRN Σ-∆ ADC DIGITAL FILTER VOLUME VOLUME CLOCK OUTL1 DIGITAL FILTER Σ-∆ DAC DIGITAL FILTER Σ-∆ DAC OUTR2 DIGITAL FILTER Σ-∆ DAC OUTR3 OUTR1 OUTL2 OUTL3 FILTD AD1839A DGND DGND AGND AGND AGND AGND VREF FILTR 03627-B-001 AAUXDATA3 DLRCLK DBCLK DSDATA1 DSDATA2 DSDATA3 DAUXDATA MCLK PD/RST M/S AVDD AVDD Figure 1. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. AD1839A TABLE OF CONTENTS Specifications..................................................................................... 3 DAC and ADC Coding.............................................................. 12 Test Conditions............................................................................. 3 AD1839A Clocking Scheme ..................................................... 12 Timing Specifications....................................................................... 5 RESET and Power-Down .......................................................... 13 Absolute Maximum Ratings............................................................ 7 Power Supply and Voltage Reference....................................... 13 Temperature Range ...................................................................... 7 Serial Control Port ..................................................................... 13 ESD Caution.................................................................................. 7 Serial Data Ports—Data Format............................................... 14 Pin Configuration and Function Descriptions............................. 8 Packed Modes ............................................................................. 14 Typical Performance Characteristics ............................................. 9 Auxiliary Time Division Multiplexing (TDM) Mode ........... 14 Terminology .................................................................................... 11 Control/Status Registers ............................................................ 19 Functional Overview...................................................................... 12 Cascade Mode............................................................................. 22 ADCs............................................................................................ 12 Outline Dimensions ....................................................................... 24 DACs ............................................................................................ 12 Ordering Guide .......................................................................... 24 REVISION HISTORY 5/04—Data Sheet Changed from Rev. A to Rev. B Updated FormatUniversal Changes to Data Sheet Title1 2/04—Data Sheet Changed from Rev. 0 to Rev. A Changes to Ordering Guide ............................................................. 6 Deleted Clock Signals Section ....................................................... 11 Added AD1835A Clocking Scheme Section................................ 11 Added Table II and Table III and renumbered following tables 11 Changes to Auxiliary (TDM Mode) Section................................ 13 Changes to Figure 5......................................................................... 14 Changes to Figure 6......................................................................... 14 Added Figures 7a and 8a................................................................. 15 Renamed Figure 7 and Figure 8 to Figure 7b and Figure 8b ..... 15 Changes to Figure 9......................................................................... 15 Changes to Table VIII ..................................................................... 21 Updated Outline Dimensions ........................................................ 24 Rev. B | Page 2 of 24 AD1839A SPECIFICATIONS TEST CONDITIONS Supply Voltages Ambient Temperature Input Clock DAC Input Signal ADC Input Signal Input Sample Rate (fS) Measurement Bandwidth Word Width Load Capacitance Load Impedance 5.0 V (AVDD, DVDD) 25°C 12.288 MHz (256 × fS mode) 1.0078125 kHz, 0 dBFS 1.0078125 kHz, −1 dBFS 48 kHz 0 Hz to 20 kHz 24 bits 100 pF 47 kΩ Performance of all channels is identical (except for the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications). Table 1. Parameter ANALOG-TO-DIGITAL CONVERTERS ADC Resolution Dynamic Range (20 Hz to 20 kHz, –60 dB Input) No Filter A-Weighted (48 kHz and 96 kHz) Total Harmonic Distortion + Noise (THD + N) 48 kHz 96 kHz Interchannel Isolation Interchannel Gain Mismatch Analog Inputs Differential Input Range (±Full Scale) Common-Mode Input Voltage Input Impedance Input Capacitance VREF DC Accuracy Gain Error Gain Drift DIGITAL-TO-ANALOG CONVERTERS DAC Resolution Dynamic Range (20 Hz to 20 kHz, –60 dBFS Input) No Filter A-Weighted Filter (48 kHz and 96 kHz) Total Harmonic Distortion + Noise (48 kHz and 96 kHz) Interchannel Isolation DC Accuracy Gain Error Interchannel Gain Mismatch Gain Drift Interchannel Phase Deviation Volume Control Step Size (1023 Linear Steps) Volume Control Range (Maximum Attenuation) Mute Attenuation De-emphasis Gain Error Full-Scale Output Voltage at Each Pin (Single-Ended) Output Resistance at Each Pin Common-Mode Output Voltage Min 100 Typ Bits 103 105 dB dB –88.5 –87.5 dB dB dB dB +2.828 2.25 4 15 2.25 V V kΩ pF V ±5 35 % ppm/°C 24 Bits 105 108 –92 110 dB dB dB dB –2.828 ±4 0.025 200 ±0.1 0.098 60 –100 ±0.1 1.0 (2.8) 180 2.25 Rev. B | Page 3 of 24 Unit 24 –95 –95 100 0.025 103 105 Max –90 % dB ppm/°C Degrees % dB dB dB V rms (V p-p) Ω V AD1839A Parameter ADC DECIMATION FILTER, 48 kHz1 Pass Band Pass-Band Ripple Stop Band Stop-Band Attenuation Group Delay ADC DECIMATION FILTER, 96 kHz Pass Band Pass-Band Ripple Stop Band Stop-Band Attenuation Group Delay DAC INTERPOLATION FILTER, 48 kHz Pass Band Pass-Band Ripple Stop Band Stop-Band Attenuation Group Delay DAC INTERPOLATION FILTER, 96 kHz Pass Band Pass-Band Ripple Stop Band Stop-Band Attenuation Group Delay DAC INTERPOLATION FILTER, 192 kHz Pass Band Pass-Band Ripple Stop Band Stop-Band Attenuation Group Delay DIGITAL I/O Input Voltage High Input Voltage Low Output Voltage High Output Voltage Low Leakage Current POWER SUPPLIES Supply Voltage (AVDD and DVDD) Supply Voltage (ODVDD) Supply Current IANALOG Supply Current IANALOG, Power-Down Supply Current IDIGITAL Supply Current IDIGITAL, Power-Down Dissipation Operation, Both Supplies Operation, Analog Supply Operation, Digital Supply Power-Down, Both Supplies Power Supply Rejection Ratio 1 kHz, 300 mV p-p Signal at Analog Supply Pins 20 kHz, 300 mV p-p Signal at Analog Supply Pins Min Typ Max Unit 21.77 ±0.01 26.23 120 910 kHz dB kHz dB µs 43.54 ±0.01 52.46 120 460 kHz dB kHz dB µs 1 1 21.77 kHz dB kHz dB µs 43.54 kHz dB kHz dB µs 81.2 kHz dB kHz dB µs ±0.01 28 55 340 1 ±0.01 52 55 160 1 1 ±0.06 97 80 110 2.4 0.4 ±10 V V V V µA 5.5 DVDD 95 67 74 4.5 V V mA mA mA mA 0.8 ODVDD – 0.4 4.5 3.0 5.0 84 55 64 1 Guaranteed by design. Rev. B | Page 4 of 24 740 420 320 280 mW mW mW mW –70 –75 dB dB AD1839A TIMING SPECIFICATIONS Table 2. Parameter MASTER CLOCK AND RESET tMH tML tPDR SPI PORT tCCH tCCL tCCP tCDS tCDH tCLS tCLH tCOE tCOD tCOTS DAC SERIAL PORT (48 kHz and 96 kHz) Normal Mode (Slave) tDBH tDBL fDB tDLS tDLH tDDS tDDH Packed 128/256 Modes (Slave) tDBH tDBL fDB tDLS tDLH tDDS tDDH ADC SERIAL PORT (48 kHz and 96 kHz) Normal Mode (Master) tABD tALD tABDD Normal Mode (Slave) tABH tABL fAB tALS tALH tABDD Packed 128/256 Mode (Master) tPABD tPALD tPABDD Min Max Unit MCLK High MCLK Low PD/RST Low 15 15 20 ns ns ns CCLK High CCLK Low CCLK Period CDATA Setup CDATA Hold CLATCH Setup CLATCH Hold COUT Enable COUT Delay COUT Three-State 40 40 80 10 10 10 10 ns ns ns ns ns ns ns ns ns ns DBCLK High DBCLK Low DBCLK Frequency DLRCLK Setup DLRCLK Hold DSDATA Setup DSDATA Hold 60 60 64 × fS 10 10 10 10 DBCLK High DBCLK Low DBCLK Frequency DLRCLK Setup DLRCLK Hold DSDATA Setup DSDATA Hold 15 15 256 × fS 10 10 10 10 15 20 25 ABCLK Delay ALRCLK Delay ASDATA Delay ABCLK High ABCLK Low ABCLK Frequency ALRCLK Setup ALRCLK Hold ASDATA Delay ns ns ns ns To DBCLK rising edge From DBCLK rising edge To DBCLK rising edge From DBCLK rising edge ns ns 60 60 64 × fS 5 15 Rev. B | Page 5 of 24 To CCLK rising edge From CCLK rising edge To CCLK rising edge From CCLK rising edge From CLATCH falling edge From CCLK falling edge From CLATCH rising edge ns ns 25 5 10 ABCLK Delay LRCLK Delay ASDATA Delay Comments ns ns ns ns To DBCLK rising edge From DBCLK rising edge To DBCLK rising edge From DBCLK rising edge ns ns ns From MCLK rising edge From ABCLK falling edge From ABCLK falling edge ns ns 15 ns ns ns To ABCLK rising edge From ABCLK rising edge From ABCLK falling edge 40 5 10 ns ns ns From MCLK rising edge From ABCLK falling edge From ABCLK falling edge AD1839A Parameter TDM256 MODE (Master, 48 kHz and 96 kHz) tTBD BCLK Delay tFSD FSTDM Delay tTABDD ASDATA Delay tTDDS DSDATA1 Setup tTDDH DSDATA1 Hold TDM256 MODE (Slave, 48 kHz and 96 kHz) fAB BCLK Frequency tTBCH BCLK High tTBCL BCLK Low tTFS FSTDM Setup tTFH FSTDM Hold tTBDD ASDATA Delay tTDDS DSDATA1 Setup tTDDH DSDATA1 Hold TDM512 MODE (Master, 48 kHz) tTBD BCLK Delay tFSD FSTDM Delay tTABDD ASDATA Delay tTDDS DSDATA1 Setup tTDDH DSDATA1 Hold TDM512 MODE (Slave, 48 kHz) fAB BCLK Frequency tTBCH BCLK High tTBCL BCLK Low tTFS FSTDM Setup tTFH FSTDM Hold tTBDD ASDATA Delay tTDDS DSDATA1 Setup tTDDH DSDATA1 Hold AUXILIARY INTERFACE (48 kHz and 96 kHz) tAXDS AAUXDATA Setup tAXDH AAUXDATA Hold tDXD DAUXDATA Delay fABP AUXBCLK Frequency Slave Mode tAXBH AUXBCLK High tAXBL AUXBCLK Low tAXLS AUXLRCLK Setup tAXLH AUXLRCLK Hold Master Mode tAUXBCLK AUXBCLK Delay tAUXLRCLK AUXLRCLK Delay Min Max Unit Comments 40 5 10 ns ns ns ns ns From MCLK rising edge From BCLK rising edge From BCLK rising edge To BCLK falling edge From BCLK falling edge ns ns ns ns ns ns ns To BCLK falling edge From BCLK falling edge From BCLK rising edge To BCLK falling edge From BCLK falling edge ns ns ns ns ns From MCLK rising edge From BCLK rising edge From BCLK rising edge To BCLK falling edge From BCLK falling edge 15 15 256 × fS 17 17 10 10 15 15 15 40 5 10 15 15 512 × fS 17 17 10 10 15 15 15 ns ns ns ns ns ns 10 10 10 64 × fS ns ns ns ns 15 15 10 10 ns ns ns ns To AUXBCLK rising edge From AUXBCLK rising edge 20 15 ns ns From MCLK rising edge From AUXBCLK falling edge To BCLK falling edge From BCLK falling edge From BCLK rising edge To BCLK falling edge From BCLK falling edge To AUXBCLK rising edge From AUXBCLK rising edge From AUXBCLK falling edge tMCLK tMH MCLK PD/RST tPDR Figure 2. MCLK and PD/RST Timing Rev. B | Page 6 of 24 03627-B-002 tML AD1839A ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter AVDD, DVDD, ODVDD to AGND, DGND AGND to DGND Digital I/O Voltage to DGND Analog I/O Voltage to AGND Operating Temperature Range Industrial (A Version) Rating −0.3 V to +6.0 V −0.3 V to +0.3 V −0.3 V to ODVDD + 0.3 V −0.3 V to AVDD + 0.3 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. −40°C to +85°C TEMPERATURE RANGE Table 4. Parameter Specifications Guaranteed Functionality Guaranteed Storage Min −40 −65 Typ +25 Max +85 +150 Unit °C °C °C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. B | Page 7 of 24 AD1839A 52 51 50 49 48 47 46 DGND DSDATA1 DSDATA2 DSDATA3 AAUXDATA3 ABCLK ALRCLK MCLK ODVDD ASDATA COUT CCLK DGND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 45 44 43 42 41 40 DVDD 1 39 DVDD CLATCH 2 38 DBCLK CIN 3 37 DLRCLK PD/RST 4 36 DAUXDATA AGND 5 AD1839A 35 M/S TOP VIEW (Not to Scale) 34 AGND 33 NC NC 8 32 NC OUTR1 9 31 NC AGND 10 30 AGND AVDD 11 29 AVDD NC 12 28 OUTR3 OUTL2 13 27 NC NC 6 OUTL1 7 03627-B-003 OUTL3 NC AGND ADCRP ADCRN ADCLP ADCLN AVDD FILTR FILTD AGND NC OUTR2 NC = NO CONNECT 14 15 16 17 18 19 20 21 22 23 24 25 26 Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1, 39 2 3 4 5, 10, 16, 24, 30, 34 6, 8, 12, 14, 25, 27, 31–33 7, 13, 26 9, 15, 28 11, 19, 29 17 18 20 21 22 23 35 36 37 38 40, 52 41–43 44 45 46 47 48 49 50 51 Mnemonic DVDD CLATCH CIN PD/RST AGND NC OUTLx OUTRx AVDD FILTD FILTR ADCLN ADCLP ADCRN ADCRP M/S DAUXDATA DLRCLK DBCLK DGND DSDATAx AAUXDATA3 ABCLK ALRCLK MCLK ODVDD ASDATA COUT CCLK Input/Output I I I O O I I I I I O I/O I/O I I I/O I/O I O O I Description Digital Power Supply. Connect to digital 5 V supply. Latch Input for Control Data. Serial Control Input. Power-Down/Reset. Analog Ground. Not connected. DACx Right Channel Negative Output. DACx Right Channel Positive Output. Analog Power Supply. Connect to analog 5 V supply. Filter Capacitor Connection. Recommended 10 µF/100 nF. Reference Filter Capacitor Connection. Recommended 10 µF/100 nF. ADC Left Channel Negative Input. ADC Left Channel Positive Input. ADC Right Channel Negative Input. ADC Right Channel Positive Input. ADC Master/Slave Select. Auxiliary DAC Output Data. DAC LR Clock. DAC Bit Clock. Digital Ground. DACx Input Data (left and right channels). Auxiliary ADC3 Digital Input. ADC Bit Clock. ADC LR Clock. Master Clock Input. Digital Output Driver Power Supply. ADC Serial Data Output. Output for Control Data. Control Clock Input for Control Data. Rev. B | Page 8 of 24 AD1839A TYPICAL PERFORMANCE CHARACTERISTICS 0 5 0 –5 MAGNITUDE (dB) MAGNITUDE (dB) –50 –100 –10 –15 –20 –150 5 10 FREQUENCY (Normalized to fS) 15 –30 0 Figure 4. ADC Composite Filter Response 5 10 FREQUENCY (Hz) 15 20 03627-B-007 0 03627-B-004 –25 Figure 7. ADC High-Pass Filter Response, fS = 96 kHz 5 0 0 MAGNITUDE (dB) MAGNITUDE (dB) –5 –10 –15 –50 –100 –20 10 15 20 FREQUENCY (Hz) 0 –50 –50 MAGNITUDE (dB) 0 –100 –150 2.0 03627-B-006 MAGNITUDE (dB) 50 100 FREQUENCY (kHz) 150 Figure 8. DAC Composite Filter Response, fS = 48 kHz 0 0.5 1.0 1.5 FREQUENCY (Normalized to fS) 200 –150 Figure 5. ADC High-Pass Filter Response, fS = 48 kHz 0 200 03627-B-008 5 03627-B-009 –30 0 03627-B-005 –25 –100 –150 0 50 100 FREQUENCY (kHz) 150 Figure 9. DAC Composite Filter Response, fS = 96 kHz Figure 6. ADC Composite Filter Response (Pass-Band Section) Rev. B | Page 9 of 24 AD1839A 0.2 0 0.1 MAGNITUDE (dB) MAGNITUDE (dB) –50 –100 0 –0.1 50 100 FREQUENCY (kHz) 150 200 0 10 20 30 FREQUENCY (kHz) 40 50 Figure 12. DAC Composite Filter Response, fS = 96 kHz (Pass-Band Section) Figure 10. DAC Composite Filter Response, fS = 192 kHz 0.10 0.10 0.05 0.05 MAGNITUDE (dB) 0 –0.05 0 –0.10 0 5 10 FREQUENCY (kHz) 15 20 03627-B-011 –0.05 Figure 11. DAC Composite Filter Response, fS = 48 kHz (Pass-Band Section) –0.10 0 20 40 60 FREQUENCY (kHz) 80 100 03627-B-013 MAGNITUDE (dB) –0.2 03627-B-012 0 03627-B-010 –150 Figure 13. DAC Composite Filter Response, fS = 192 kHz (Pass-Band Section) Rev. B | Page 10 of 24 AD1839A TERMINOLOGY Dynamic Range Gain Drift The ratio of a full-scale input signal to the integrated input noise in the pass band (20 Hz to 20 kHz), expressed in decibels. Dynamic range is measured with a −60 dB input signal and is equal to (S/[THD + N]) + 60 dB. Note that spurious harmonics are below the noise with a −60 dB input, so the noise level establishes the dynamic range. The dynamic range is specified with and without an A-weight filter applied. Change in response to a near full-scale input with a change in temperature, expressed as parts-per-million (ppm) per °C. Signal-to-(Total Harmonic Distortion + Noise) [S/(THD + N)] Power Supply Rejection The ratio of the root-mean-square (rms) value of the fundamental input signal to the rms sum of all other spectral components in the pass band, expressed in decibels. Crosstalk (EIAJ Method) Ratio of response on one channel with a grounded input to a full-scale 1 kHz sine wave input on the other channel, expressed in decibels. With no analog input, signal present at the output when a 300 mV p-p signal is applied to the power supply pins, expressed in decibels of full scale. Group Delay Intuitively, the time interval required for an input pulse to appear at the converter’s output, expressed in microseconds. More precisely, the derivative of radian phase with respect to the radian frequency at a given frequency. Pass Band The region of the frequency spectrum unaffected by the attenuation of the digital decimator’s filter. Pass-Band Ripple The peak-to-peak variation in amplitude response from equalamplitude input signal frequencies within the pass band, expressed in decibels. Stop Band The region of the frequency spectrum attenuated by the digital decimator’s filter to the degree specified by stop-band attenuation. Gain Error With identical near full-scale inputs, the ratio of actual output to expected output, expressed as a percentage. Interchannel Gain Mismatch With identical near full-scale inputs, the ratio of outputs of the two stereo channels, expressed in decibels. Group Delay Variation The difference in group delays at different input frequencies. Specified as the difference between the largest and the smallest group delays in the pass band, expressed in microseconds. Acronyms ADC—Analog-to-digital converter. DAC—Digital-to-analog converter. DSP—Digital signal processor. IMCLK—Internal master clock signal used to clock the ADC and DAC engines. MCLK—External master clock signal applied to the AD1839A. Rev. B | Page 11 of 24 AD1839A FUNCTIONAL OVERVIEW ADCS DAC AND ADC CODING There are two ADC channels in the AD1839A, configured as a stereo pair. Each ADC has fully differential inputs. The ADC section can operate at a sample rate of up to 96 kHz. The ADCs include on-board digital decimation filters with 120 dB stopband attenuation and linear phase response, operating at an oversampling ratio of 128 (for 48 kHz operation) or 64 (for 96 kHz operation). The DAC and ADC output data stream is in a twos complement encoded format. A 16-bit, 20-bit, or 24-bit word width can be selected. The coding scheme is detailed in Table 6. The peak level information for each ADC may be read from the ADC Peak 0 and ADC Peak 1 registers. The data is supplied as a 6-bit word with a maximum range of 0 dB to −63 dB and a resolution of 1 dB. The registers hold peak information until read; after reading, the registers are reset so that new peak information can be acquired. (Refer to the register description in Table 10 for details of the format.) The two ADC channels have a common serial bit clock and a left-right framing clock. The clock signals are all synchronous with the sample rate. The ADC digital pins, ABCLK and ALRCLK, can be set to operate as inputs or outputs by connecting the M/S pin to ODVDD or DGND, respectively. When the pins are set as outputs, the AD1839A generates the timing signals. When the pins are set as inputs, the timing must be generated by the external audio controller. DACS The AD1839A has six DAC channels arranged as three independent stereo pairs, with six single-ended analog outputs. Each channel has its own independently programmable attenuator, adjustable in 1,024 linear steps. Digital inputs are supplied through three serial data input pins (one for each stereo pair) and a common frame (DLRCLK) and bit clock (DBCLK). Alternatively, one of the packed data modes can be used to access all six channels on a single TDM data pin. A stereo replicate feature is included where the DAC data sent to the first DAC pair is also sent to the other DACs in the part. The AD1839A can accept DAC data at a sample rate of 192 kHz on DAC 1 only. The stereo replicate feature can then be used to copy the audio data to the other DACs. Each of the output pins sits at a dc level of VREF and swings ±1.4 V for a 0 dB digital input signal. A single op amp, thirdorder, external low-pass filter is recommended to remove high frequency noise present on the output pins. Note that the use of op amps with low slew rate or low bandwidth may cause high frequency noise and tones to fold down into the audio band; care should be exercised in selecting these components. The FILTD pin should be connected to an external grounded capacitor. This pin reduces the noise of the internal DAC bias circuitry, thus reducing the DAC output noise. At times, this capacitor may be eliminated with little effect on performance. Table 6. Coding Scheme Code 01111......1111 00000......0000 10000......0000 Level +FS 0 (Ref level) −FS AD1839A CLOCKING SCHEME By default, the AD1839A requires an MCLK signal that is 256 times the required sample frequency up to a maximum of 12.288 MHz. The AD1839A uses a clock scaler to double the clock frequency for use internally. The default setting of the clock scaler is Multiply by 2. The clock scaler can also be set to Multiply by 1 (bypass) or Multiply by 2/3. The clock scaler is controlled by programming the bits in the ADC Control 3 register. The internal MCLK signal, IMCLK, should not exceed 24.576 MHz to ensure correct operation. The MCLK of the AD1839A should remain constant during normal operation of the DAC and ADC. If it is required to change the MCLK rate, the AD1838A should be reset. Also, if MCLK scaler needs to be modified so that the IMCLK does not exceed 24.576 MHz, this should be done during the internal reset phase of the AD1839A by programming the bits in the first 3,072 MCLK periods following the reset. Selecting the DAC Sampling Rate The AD1839A DAC engine has a programmable interpolator that allows the user to select different interpolation rates based on the required sample rate and MCLK value available. Table 7 shows the settings required for sample rates based on a fixed MCLK of 12.288 MHz. Table 7. DAC Sample Rate Settings Sample Rate 48 kHz 96 kHz 192 kHz Interpolator Rate 8× 4× 2× DAC Control 1 Register 000000xxxxxxxx00 000000xxxxxxxx01 000000xxxxxxxx10 Selecting an ADC Sample Rate The AD1839A ADC engine has a programmable decimator that allows the user to select the sample rate based on the MCLK value. By default, the output sample rate is IMCLK/512. To achieve a sample rate of IMCLK/256, the sample rate bit in the ADC Control 1 register should be set as shown in Table 8. Table 8. ADC Sample Rate Settings Sample Rate IMCLK/512 IMCLK/256 Rev. B | Page 12 of 24 ADC Control 1 Register 1100000xx0xxxxxx (48 kHz) 1100000xx1xxxxxx (96 kHz) AD1839A To maintain the highest performance possible, the clock jitter of the master clock signal should be limited to less than 300 ps rms, measured using the edge-to-edge technique. Even at these levels, extra noise or tones may appear in the DAC outputs if the jitter spectrum contains large spectral peaks. It is highly recommended that the master clock be generated by an independent crystal oscillator. In addition, it is especially important that the clock signal not be passed through an FPGA or other large digital chip before being applied to the AD1839A. In most cases, this induces clock jitter because the clock signal is sharing common power and ground connections with unrelated digital output signals. pickup. A bulk aluminum electrolytic capacitor of at least 22 µF should also be provided on the same PC board as the codec. For critical applications, improved performance is obtained with separate supplies for the analog and digital sections. If this is not possible, it is recommended that the analog and digital supplies be isolated by two ferrite beads in series with the bypass capacitor of each supply. It is important that the analog supply be as clean as possible. The internal voltage reference is brought out on the FILTR pin and should be bypassed as close as possible to the chip, with a parallel combination of 10 µF and 100 nF. The reference voltage may be used to bias external op amps to the common-mode voltage of the analog input and output signal pins. The current drawn from the VREF pin should be limited to less than 50 µA. RESET AND POWER-DOWN PD/RST powers down the chip and sets the control registers to their default settings. After PD/RST is deasserted, an initialization routine runs inside the device to clear all memories to zero. The initialization lasts approximately 20 LRCLK intervals. During this time, it is recommended that no SPI writes occur. SERIAL CONTROL PORT The AD1839A has an SPI compatible control port to permit programming the internal control registers for the ADCs and DACs, and for reading the ADC signal levels from the internal peak detectors. The SPI port is a 4-wire serial control port. The format is similar to the Motorola SPI format except the input data-word is 16 bits wide. The maximum serial bit clock frequency is 12.5 MHz and may be completely asynchronous to the sample rate of the ADCs and DACs. Figure 15 shows the format of the SPI signal. POWER SUPPLY AND VOLTAGE REFERENCE The AD1839A is designed for 5 V supplies. Separate power supply pins are provided for the analog and digital sections. These pins should be bypassed with 100 nF ceramic chip capacitors, as close to the pins as possible, to minimize noise DAC ENGINE DAC INPUT 48kHz/96kHz/192kHz INTERPOLATION FILTER Σ-∆ MODULATOR DAC ANALOG OUTPUT CLOCK SCALING ×1 MCLK IMCLK = 24.576MHz ×2 12.288MHz ×2/3 ADC OUTPUT OPTIONAL HPF DECIMATOR/ FILTER Σ-∆ MODULATOR ANALOG INPUT 03627-B-014 ADC ENGINE 48kHz/96kHz Figure 14. Modular Clocking Scheme tCLS CLATCH tCLH tCCH tCCL tCCP tCOTS CCLK CIN COUT D15 D14 D9 tCOE D9 D8 D0 D8 D0 tCOD Figure 15. Format of SPI Timing Rev. B | Page 13 of 24 03627-B-015 tCDS tCDH AD1839A SERIAL DATA PORTS—DATA FORMAT 2 The ADC serial data output mode defaults to the popular I S format, where the data is delayed by 1 BCLK interval from the edge of the LRCLK. By changing Bits 6 to 8 in ADC Control Register 2, the serial mode can be changed to right-justified (RJ), left-justified DSP (DSP), or left-justified (LJ). In the RJ mode, it is necessary to set Bits 4 and 5 to define the width of the data-word. The DAC serial data input mode defaults to I2S. By changing Bits 5, 6, and 7 in DAC Control Register 1, the mode can be changed to RJ, DSP, LJ, or Packed Mode 256. The word width defaults to 24 bits but can be changed by reprogramming Bits 3 and 4 in DAC Control Register 1. PACKED MODES The AD1839A has a packed mode that allows a DSP or other controller to write to all DACs and read all ADCs using one input data pin and one output data pin. Packed Mode 256 refers to the number of BCLKs in each frame. The LRCLK is low while data from a left-channel DAC or ADC is on the data pin; LRCLK is high while data from a right-channel DAC or ADC is on the data pin. DAC data is applied on the DSDATA1 pin, and ADC data is available on the ASDATA pin. Figure 19 to Figure 24 show the timing for the packed mode. Packed mode is available for 48 kHz and 96 kHz. AUXILIARY TIME DIVISION MULTIPLEXING (TDM) MODE A special auxiliary mode is provided to allow three external stereo ADCs and one external stereo DAC to be interfaced to the AD1839A to provide 8-in/8-out operation. In addition, this mode supports a glueless interface to a single SHARC DSP serial port, allowing a SHARC DSP to access all eight channels of analog I/O. In this special mode, many pins are redefined; see Table 9 for a list of redefined pins. The auxiliary and TDM interfaces are independently configurable to operate as masters or slaves. When the auxiliary interface is set as a master, by programming the auxiliary mode bit in ADC Control Register 2, AUXLRCLK and AUXBCLK are generated by the AD1839A. When the auxiliary interface is set as a slave, AUXLRCLK and AUXBCLK need to be generated by an external ADC, as shown in Figure 27. The TDM interface can be set to operate as a master or slave by connecting the M/S pin to DGND or ODVDD, respectively. In master mode, the FSTDM and BCLK signals are outputs and are generated by the AD1839A. In slave mode, the FSTDM and BCLK are inputs and should be generated by the SHARC. Both 48 kHz and 96 kHz operations are available (based on a 12.288 MHz or 24.576 MHz MCLK) in this mode. Table 9. Pin Function Changes in Auxiliary Mode Pin Name ASDATA (O) DSDATA1 (I) DSDATA2 (I)/AAUXDATA1 (I) DSDATA3 (I)/AAUXDATA2 (I) AAUXDATA3 (I) ALRCLK (O) ABCLK (O) DLRCLK (I)/AUXLRCLK (I/O) I2S Mode I2S Data Out, Internal ADC I2S Data In, Internal DAC1 I2S Data In, Internal DAC2 I2S Data In, Internal DAC3 Not Connected LRCLK for ADC BCLK for ADC LRCLK In/Out Internal DACs DBCLK (I)/AUXBCLK (I/O) BCLK In/Out Internal DACs DAUXDATA (O) Not Connected Auxiliary Mode TDM Data Out to SHARC. TDM Data In from SHARC. AUX-I2S Data In 1 (from external ADC). AUX-I2S Data In 2 (from external ADC). AUX-I2S Data In 3 (from external ADC). TDM Frame Sync Out to SHARC (FSTDM). TDM BCLK Out to SHARC. AUX LRCLK In/Out. Driven by external LRCLK from ADC in slave mode. In master mode, driven by MCLK/512. AUX BCLK In/Out. Driven by external BCLK from ADC in slave mode. In master mode, driven by MCLK/8. AUX-I2S Data Out (to external DAC). Rev. B | Page 14 of 24 AD1839A LRCLK LEFT CHANNEL RIGHT CHANNEL BCLK SDATA LSB MSB LSB MSB LEFT-JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL LEFT CHANNEL LRCLK RIGHT CHANNEL BCLK LSB MSB SDATA LSB MSB I2S MODE—16 BITS TO 24 BITS PER CHANNEL LEFT CHANNEL LRCLK RIGHT CHANNEL BCLK LSB MSB SDATA LSB MSB RIGHT-JUSTIFIED MODE—SELECT NUMBER OF BITS PER CHANNEL LRCLK BCLK LSB MSB SDATA MSB LSB DSP MODE—16 BITS TO 24 BITS PER CHANNEL 1/fS 03627-B-016 NOTES 1. DSP MODE DOES NOT IDENTIFY CHANNEL. 2. LRCLK NORMALLY OPERATES AT fS EXCEPT FOR DSP MODE, WHICH IS 2 × fS. 3. BCLK FREQUENCY IS NORMALLY 64 × LRCLK BUT MAY BE OPERATED IN BURST MODE. Figure 16. Stereo Serial Modes tABH ABCLK tABL tALS tABDD ALRCLK ASDATA I2S COMPATIBLE MODE ASDATA RIGHT-JUSTIFIED MODE MSB MSB – 1 MSB MSB Figure 17. ADC Serial Mode Timing Rev. B | Page 15 of 24 LSB 03627-B-017 ASDATA LEFT-JUSTIFIED MODE AD1839A tDBH DBCLK tDBL tDLS tDLH DLRCLK DSDATA LEFT-JUSTIFIED MODE tDDS MSB MSB – 1 tDDH tDDS DSDATA I2S COMPATIBLE MODE MSB tDDH tDDS LSB MSB tDDH tDDH Figure 18. DAC Serial Mode Timing LRCLK 128 BCLKs BCLK 16 BCLKs SLOT 1 LEFT 1 SLOT 2 LEFT 2 MSB SLOT 3 LEFT 3 SLOT 4 SLOT 5 SLOT 6 SLOT 7 SLOT 8 LEFT 4 RIGHT 1 RIGHT 2 RIGHT 3 RIGHT 4 MSB – 1 MSB – 2 03627-B-019 ADC DATA Figure 19. ADC Packed Mode 128 LRCLK 256 BCLKs BCLK 32 BCLKs SLOT 1 LEFT 1 SLOT 2 LEFT 2 MSB SLOT 3 LEFT 3 SLOT 4 SLOT 5 SLOT 6 SLOT 7 SLOT 8 LEFT 4 RIGHT 1 RIGHT 2 RIGHT 3 RIGHT 4 MSB – 1 MSB – 2 Figure 20. ADC Packed Mode 256 Rev. B | Page 16 of 24 03627-B-020 ADC DATA 03627-B-018 tDDS DSDATA RIGHT-JUSTIFIED MODE AD1839A LRCLK 128 BCLKs BCLK 16 BCLKs SLOT 1 LEFT 1 SLOT 2 LEFT 2 MSB SLOT 3 LEFT 3 SLOT 4 SLOT 5 SLOT 6 SLOT 7 SLOT 8 LEFT 4 RIGHT 1 RIGHT 2 RIGHT 3 RIGHT 4 MSB – 1 03627-B-021 DAC DATA MSB – 2 Figure 21. DAC Packed Mode 128 LRCLK 256 BCLKs BCLK 32 BCLKs SLOT 1 LEFT 1 SLOT 2 LEFT 2 MSB SLOT 3 LEFT 3 SLOT 4 SLOT 5 SLOT 6 SLOT 7 SLOT 8 LEFT 4 RIGHT 1 RIGHT 2 RIGHT 3 RIGHT 4 MSB – 1 03627-B-022 DAC DATA MSB – 2 Figure 22. DAC Packed Mode 256 tABH ABCLK tABL tABH ALRCLK tALH MSB 03627-B-024 ASDATA tABDD MSB – 1 Figure 23. ADC Packed Mode Timing tDBH DBCLK tDBL tDLS DLRCLK tDLH MSB MSB – 1 tDDH Figure 24. DAC Packed Mode Timing Rev. B | Page 17 of 24 03627-B-025 tDDS DSDATA AD1839A FSTDM TDM INTERFACE BCLK TDM ASDATA1 TDM (OUT) MSB TDM MSB TDM 1ST CH 8TH CH INTERNAL ADC L1 ASDATA AUX_ADC L2 AUX_ADC L3 AUX_ADC L4 INTERNAL ADC R1 AUX_ADC R2 AUX_ADC R3 AUX_ADC R4 32 MSB TDM MSB TDM DSDATA1 TDM (IN) 1ST CH 8TH CH DSDATA1 INTERNAL DAC L1 INTERNAL DAC L2 INTERNAL DAC L3 INTERNAL DAC L4 INTERNAL DAC R1 INTERNAL DAC R2 INTERNAL DAC R3 INTERNAL DAC R4 32 RIGHT LEFT AAUXDATA1 (IN) (FROM AUX ADC NO. 1) I2S - MSB LEFT I2S - MSB RIGHT AAUXDATA2 (IN) (FROM AUX ADC NO. 2) I2S - MSB LEFT I2S - MSB RIGHT AAUXDATA3 (IN) (FROM AUX ADC NO. 3) I2S - MSB LEFT I2S - MSB RIGHT 03627-B-026 AUX BCLK I2S (FROM AUX ADC NO. 1) AUXBCLK FREQUENCY IS 64 × FRAME RATE; TDM BCLK FREQUENCY IS 256 × FRAME RATE. TxCLK TxDATA LRCLK TFS (NC) 12.288MHz SHARC IS ALWAYS RUNNING IN SLAVE MODE (INTERRUPT DRIVEN). SHARC RxDATA 30MHz FSYNC-TDM (RFS) Figure 25. Auxiliary Mode Timing RxCLK BCLK DSDATA1 ADC NO. 1 BCLK SLAVE DATA MCLK LRCLK ADC NO. 2 BCLK SLAVE DATA MCLK ASDATA FSTDM DBCLK/AUXBCLK LRCLK DLRCLK/AUXLRCLK LRCLK DSDATA2/AAUXDATA1 ADC NO. 3 BCLK SLAVE DATA DSDATA3/AAUXDATA2 MCLK AAUXDATA3 MCLK BCLK DAUXDATA DATA DAC NO. 1 SLAVE MCLK AD1839A MASTER Figure 26. Auxiliary Mode Connection (Master Mode) to SHARC Rev. B | Page 18 of 24 03627-B-027 AUX - I2S INTERFACE AUX LRCLK I2S (FROM AUX ADC NO. 1) TxCLK TxDATA TFS (NC) LRCLK RxDATA 12.288MHz SHARC IS ALWAYS RUNNING IN SLAVE MODE (INTERRUPT DRIVEN). SHARC RxCLK 30MHz FSYNC-TDM (RFS) AD1839A BCLK DSDATA1 ADC NO. 1 BCLK SLAVE DATA MCLK LRCLK MCLK ASDATA FSTDM DBCLK/AUXBCLK LRCLK DLRCLK/AUXLRCLK LRCLK DSDATA2/AAUXDATA1 ADC NO. 3 BCLK SLAVE DATA DSDATA3/AAUXDATA2 MCLK AAUXDATA3 BCLK DAUXDATA DATA DAC NO. 1 SLAVE MCLK AD1839A MCLK SLAVE 03627-B-028 ADC NO. 2 BCLK SLAVE DATA Figure 27. Auxiliary Mode Connection (Slave Mode) to SHARC CONTROL/STATUS REGISTERS The AD1839A has 13 control registers, 11 of which are used to set the operating mode of the part. The other two registers, ADC Peak 0 and ADC Peak 1, are read-only and should not be programmed. Each of the registers is 10 bits wide with the exception of the ADC peak reading registers, which are 6 bits wide. Writing to a control register requires a 16-bit data frame to be transmitted. Bits 15 to 12 are the address bits of the required register. Bit 11 is a read/write bit. Bit 10 is reserved and should always be programmed to 0. Bits 9 to 0 contain the 10-bit value that is to be written to the register, or, in the case of a read operation, the 10-bit register contents. Figure 15 shows the format of the SPI read and write operation. DAC Control Registers The AD1839A register map has eight registers that are used to control the functionality of the DAC section of the part. The function of the bits in these registers is discussed next. Sample Rate These bits control the sample rate of the DACs. Based on a 24.576 MHz IMCLK, sample rates of 48 kHz, 96 kHz, and 192 kHz are available. The MCLK scaling bits in ADC Control 3 should be programmed appropriately, based on the master clock frequency. Power-Down/Reset This bit controls the power-down status of the DAC section. By default, normal mode is selected; by setting this bit, the digital section of the DAC stage can be put into a low power mode, thus reducing the digital current. The analog output section of the DAC stage is not powered down. DAC Data-Word Width These two bits set the word width of the DAC data. Compact disk (CD) compatibility may require 16 bits, but many modern digital audio formats require 24-bit sample resolution. DAC Data Format The AD1839A serial data interface can be configured to be compatible with a choice of popular interface formats, including I2S, LJ, RJ, or DSP modes. Details on these interface modes are provided in the Serial Data Ports—Data Format section. De-emphasis The AD1839A provides built-in de-emphasis filtering for the three standard sample rates of 32.0 kHz, 44.1 kHz, and 48 kHz. Mute DAC Each of the six DACs in the AD1839A has its own independent mute control. Setting the appropriate bit mutes the DAC output. The AD1839A uses a clickless mute function that attenuates the output to approximately −100 dB over a number of cycles. Stereo Replicate Setting this bit copies the digital data sent to the stereo pair DAC1 to the three other stereo DACs in the system. This allows all three stereo DACs to be driven by one digital data stream. Note that in this mode, DAC data sent to the other DACs is ignored. DAC Volume Control Each DAC in the AD1839A has its own independent volume control. The volume of each DAC can be adjusted in 1,024 linear steps by programming the appropriate register. The default value for this register is 1023, which provides no attenuation, that is, full volume. Rev. B | Page 19 of 24 AD1839A ADC Control Registers The AD1839A register map has five registers that are used to control the functionality and read the status of the ADCs. The function of the bits in each of these registers is discussed below. ADC Peak Level These two registers store the peak ADC result from each channel when the ADC peak readback function is enabled. The peak result is stored as a 6-bit number from 0 dB to −63 dB in 1 dB steps. The value contained in the register is reset once it has been read, allowing for continuous level adjustment as required. Note that the ADC peak level registers use the six most significant bits in the register to store the results. Sample Rate This bit controls the sample rate of the ADCs. Based on a 24.576 MHz IMCLK, sample rates of 48 kHz and 96 kHz are available. The MCLK scaling bits in ADC Control 3 should be programmed appropriately, based on the master clock frequency. ADC Power-Down This bit controls the power-down status of the ADC section and operates in a manner similar to the DAC power-down. High-Pass Filter The ADC signal path has a digital high-pass filter. Enabling this filter removes the effect of any dc offset in the analog input signal from the digital output codes. ADC Data-Word Width These two bits set the word width of the ADC data. ADC Data Format The AD1839A serial data interface can be configured to be compatible with a choice of popular interface formats, including I2S, LJ, RJ, or DSP modes. Master/Slave Auxiliary Mode When the AD1839A is operating in the auxiliary mode, the auxiliary ADC control pins, AUXBCLK and AUXLRCLK, which connect to the external ADCs, can be set to operate as a master or slave. If the pins are set in slave mode, one of the external ADCs should provide the LRCLK and BCLK signals. ADC Peak Readback Setting this bit enables ADC peak reading. See the ADCs section for more information. Table 10. Control Register Map Register Address 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Register Name DACCTRL1 DACCTRL2 DACVOL1 DACVOL2 DACVOL3 DACVOL4 DACVOL5 DACVOL6 DACVOL7 DACVOL8 ADCPeak0 ADCPeak1 ADCCTRL1 ADCCTRL2 ADCCTRL3 Reserved Description DAC Control 1 DAC Control 2 DAC Volume—Left 1 DAC Volume—Right 1 DAC Volume—Left 2 DAC Volume—Right 2 DAC Volume—Left 3 DAC Volume—Right 3 DAC Volume—Left 4 DAC Volume—Right 4 ADC Left Peak ADC Right Peak ADC Control 1 ADC Control 2 ADC Control 3 Reserved Rev. B | Page 20 of 24 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W Width 10 10 10 10 10 10 10 10 10 10 6 6 10 10 10 10 Reset Setting (Hex) 000 000 3FF 3FF 3FF 3FF 3FF 3FF 3FF 3FF 000 000 000 000 000 Reserved AD1839A Table 11. DAC Control 1 Address R/W RES De-emphasis DAC Data Format 15, 14, 13, 12 0000 11 0 10 0 9, 8 00 = None 01 = 44.1 kHz 10 = 32.0 kHz 11 = 48.0 kHz 7, 6, 5 000 = I2S 001 = RJ 010 = DSP 011 = LJ 100 = Packed 256 101 = Packed128 110 = Reserved 111 = Reserved Function DAC Data-Word Width 4, 3 00 = 24 Bits 01 = 20 Bits 10 = 16 Bits 11 = Reserved Power-Down Reset Sample Rate 2 0 = Normal 1 = Power-Down 1, 0 00 = 8 × (48 kHz) 01 = 4 × (96 kHz) 10 = 2 × (192 kHz) 11 = 8 × (48 kHz) Table 12. DAC Control 2 Address 15, 14, 13, 12 0001 R/W 11 RES 10 Reserved 9 0 0 0 Stereo Replicate Function MUTE DAC 8 Reserved 7 Reserved 6 OUTR3 5 OUTL3 4 OUTR2 3 OUTL2 2 OUTR1 1 OUTL1 0 0 = Off 1 = Replicate 0 = On 1 = Mute 0 = On 1 = Mute 0 = On 1 = Mute 0 = On 1 = Mute 0 = On 1 = Mute 0 = On 1 = Mute 0 = On 1 = Mute 0 = On 1 = Mute Table 13. DAC Volume Control Function R/W Address 15, 14, 13, 12 0010 = DACL1 0011 = DACR1 0100 = DACL2 0101 = DACR2 0110 = DACL3 0111 = DACR3 11 0 RES 10 0 DAC Volume 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 0000000000 = Mute 0000000001 = 1/1023 0000000010 = 2/1023 1111111110 = 1022/1023 1111111111 = 1023/1023 Table 14. ADC Peak Function R/W Address 15, 14, 13, 12 1010 = Left ADC 1011 = Right ADC 11 1 RES 10 0 Six Data Bits 9, 8, 7, 6, 5, 4 000000 = 0.0 dBFS 000001 = –1.0 dBFS 000010 = –2.0 dBFS Four Fixed Bits 3, 2, 1, 0 0000 These four bits are always 0. 111111 = –63.0 dBFS Table 15. ADC Control 1 Address 15, 14, 13, 12 1100 R/W 11 0 RES 10 0 Reserved 9 0 Filter 8 0 = All Pass 1 = High-Pass Rev. B | Page 21 of 24 Function ADC PowerDown 7 0 = Normal 1 = Power-Down Sample Rate 6 0 = 48 kHz 1 = 96 kHz Reserved 5, 4, 3, 2, 1, 0 0, 0, 0, 0, 0, 0 0, 0, 0, 0, 0, 0 AD1839A Table 16. ADC Control 2 Address 15, 14, 13, 12 1101 R/W 11 0 RES 10 0 Master/Slave Aux Mode 9 0 = Slave 1 = Master ADC Data Format 8, 7, 6 000 = I2S 001 = RJ 010 = DSP 011 = LJ 100 = Packed 256 101 = Packed 128 110 = Auxiliary 256 111 = Auxiliary 512 Function ADC DataWord Width 5, 4 00 = 24 Bits 01 = 20 Bits 10 = 16 Bits 11 = Reserved ADC MUTE AUXDATA 3 0 = Off 1 = On RES 2 0 Right 1 0 = On 1 = Mute Left 0 0 = On 1 = Mute Table 17. ADC Control 3 Function Address 15, 14, 13, 12 1110 R/W RES 11 RES 10 Reserved 9, 8 IMCLK Clocking Scaling 7, 6 ADC Peak Readback 5 DAC Test Mode 4, 3, 2 ADC Test Mode 1, 0 0 0 0, 0 00 = MCLK × 2 01 = MCLK 10 = MCLK × 2/3 11 = MCLK × 2 0 = Disabled Peak Readback 1 = Enabled Peak Readback 000 = Normal Mode All Others Reserved 00 = Normal Mode All Others Reserved CASCADE MODE Dual AD1839A Cascade The AD1839A can be cascaded to an additional AD1839A that, in addition to six external stereo ADCs and two external stereo DACs, can be used to create a 32-channel audio system with 16 inputs and 16 outputs. The cascade is designed to connect to a SHARC DSP and operates in a time division multiplexing (TDM) format. Figure 28 shows the connection diagram for cascade operation. The digital interface for both parts must be set to operate in Auxiliary 512 mode by programming ADC Control Register 2. AD1839A Device 1 is set as the master device by connecting the M/S pin to DGND; AD1839A Device 2 is set as a slave device by connecting the M/S to ODVDD. Both devices should be run from the same MCLK and PD/RST signals to ensure that they are synchronized. With Device 1 set as a master, it generates the frame-sync and bit clock signals. These signals are sent to the SHARC and Device 2, ensuring that both know when to send and receive data. The cascade can be thought of as two 256-bit shift registers, one for each device. At the beginning of a sample interval, the shift registers contain the ADC results from the previous sample interval. The first shift register (Device 1) clocks data into the SHARC and clocks in data from the second shift register (Device 2). While this is happening, the SHARC is sending DAC data to the second shift register. By the end of the sample interval, all 512 bits of ADC data in the shift registers have been clocked into the SHARC and replaced by DAC data, which is subsequently written to the DACs. Figure 29 shows the timing diagram for the cascade operation. Rev. B | Page 22 of 24 AD1839A AD1839A NO. 1 (SLAVE) DOUT LRCLK BCLK DSDATA AD1839A NO. 2 (MASTER) SHARC AUXDATA3 DOUT ASDATA ALRCLK ABCLK DSDATA AUX ADC (SLAVE) AUXDATA2 LRCLK AUXDATA1 BCLK AUXBCLK AUXLRCLK AUX ADC (SLAVE) DOUT LRCLK BCLK DOUT LRCLK AUX ADC (SLAVE) AUXDATA3 BCLK DOUT ASDATA ALRCLK ABCLK DRx RFSx RCLKx AUX ADC (SLAVE) AUXDATA2 LRCLK AUXDATA1 BCLK AUXBCLK AUXLRCLK AUX ADC (SLAVE) DOUT BCLK LRCLK AUX ADC (SLAVE) (SLAVE) 03627-B-029 TFSx TCLKx DTx Figure 28. Dual AD1839A Cascade 256 ABCLKs 256 ABCLKs TFSx/ RFSx AD1839A NO. 1 DACs AD1839A NO. 2 DACs DTx L1 L2 DRx L1 L2 L3 DTx MSB MSB – 1 LSB DRx MSB MSB – 1 LSB L3 L4 R1 R2 R3 R4 L1 L2 R3 R4 L1 L2 AD1839A NO. 1 ADCs L4 R1 L3 L4 R1 R2 R3 R4 R3 R4 AD1839A NO. 2 ADCs R2 L3 L4 R1 R2 BCLK 03627-B-030 DON’T CARE 32 ABCLKs Figure 29. Dual AD1839A Cascade Timing 47µF 5.76kΩ + 100pF NPO 5.76kΩ 120pF NPO OP275 VBIAS (2.25V) 237Ω 11kΩ 3.01kΩ 11kΩ ADCxN 270pF NPO VREF OP275 1nF NPO 5.76kΩ 68pF NPO 560pF NPO OUTx 100pF NPO 5.76kΩ OP275 237Ω VREF ADCxP AUDIO OUTPUT 2.2nF NPO 1.5kΩ 5.62kΩ 1nF NPO 750kΩ 5.62kΩ 604Ω 150pF NPO Figure 31. Typical DAC Output Filter Circuit Figure 30. Typical ADC Input Filter Circuit Rev. B | Page 23 of 24 03627-B-032 600Z 03627-B-031 AUDIO INPUT AD1839A OUTLINE DIMENSIONS 1.03 0.88 0.73 13.45 13.20 SQ 12.95 2.45 MAX 39 SEATING PLANE 10° 6° 2° 2.20 2.00 1.80 26 7.80 REF 10.20 10.00 SQ 9.80 TOP VIEW (PINS DOWN) 0.23 0.11 VIEW A 7° 0° 0.13 MIN COPLANARITY 0.25 MAX 27 40 VIEW A PIN 1 52 14 1 0.65 BSC ROTATED 90° CCW 13 0.40 0.22 COMPLIANT TO JEDEC STANDARDS MS-022-AC. Figure 32. 52-Lead Metric Quad Flat Package [MQFP] (S-52-1) Dimensions shown in millimeters ORDERING GUIDE Model AD1839AAS AD1839AAS-REEL AD1839AASZ1 AD1839AASZ-REEL1 EVAL-AD1839AEB 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 52-Lead MQFP 52-Lead MQFP 52-Lead MQFP 52-Lead MQFP 52-Lead MQFP Z = Pb-free part. © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03627–0–6/04(B) Rev. B | Page 24 of 24 Package Option S-52-1 S-52-1 S-52-1 S-52-1 S-52-1