AZ DISPLAYS, INC. SPECIFICATIONS FOR LIQUID CRYSTAL DISPLAY PART NUMBER: AGM2416B DATE: September 13, 2005 Page 1 of 12 AZ DISPLAYS, INC. AGM2412B 1 General Specifications Item Standard Value Unit Dot-Graphic Display Pattern Color Mono. Character with ICON Grayscale Digits Dots FSTN Module Dimension 92.0 X 71.8 X 2.0 mm Viewing Area 67.0 X 46.8 mm Active Area 62.38 X 42.38 mm Character Size / mm Character Pitch / mm DOT Size 0.245 X 0.24 mm DOT Pitch 0.265 X 0.26 mm LCD Type TN, Positive HTN, Positive STN, Yellow-Green FSTN, Positive Color STN FM LCD Polarizer Type Transflective Anti-Glare View Direction 6H Transmissive ST8016 & ST8024 LCD Driving Method 1/160duty, 1/14bias I2C 6800 Backlight Type / Backlight Color / EL/CCFL Driver type / DC-DC Converter Build-in o Reflective 12H LCD Controller & Driver Interface Type TN, Negative HTN, Negative STN, Gray STN, Blue FSTN, Negative 4-wire Serial 8080 4-bit 3-wire Serial External Operation Temperature ( C) -10 ~ 60 (TOPL – T OPH ) °C Storage Temperature (oC) (TSTL -- T STH ) ° C -20 ~ 70 Page 2 of 12 AZ DISPLAYS, INC. AGM2412B 3.1 Pin Description Segment Pin Pin No. Symbol Function Description 1 V0L 2 V12L 3 V34L 4 V5L Bias power supply pins for LCD drive voltage Normally use the bias voltages set by a resistor divider Ensure that voltages are set such that VSS • • V5 < V43 < V12 < V0. ViL and ViR (i = 0,12, 43, 5) must connect to an external power supply, and supply regular voltage which is assigned by specification for each power pin 5 VSS 6 VSS 7 VDD 8 VDD 9 DBLKB 10 D0 11 D1 12 D2 13 D3 14 XCK Ground Logic power supply Use as contrast control, use PWM signal as input. Connect to VDD for no contrast control. Data bus Clock input pin for taking display data * Data is read at the falling edge of the clock pulse. Control input pin for output of non-select level The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. When set to VSS level "L", the LCD drive output pins (Y1-Y240) are set to level Vss. When set to "L", the contents of the line latch are reset, but the display data are read in the data latch regardless of the condition of DISPOFF. When the DISPOFF function is canceled, the driver outputs non-select level (V 12 or V43), then outputs the contents of the data latch at the next falling edge of the LP. At that time, if DISPOFF removal time does not correspond to what is shown in AC characteristics, it can not output the reading data correctly. Table of truth values is shown in "TRUTH TABLE" in Functional Operations. 15 DOFFB 16 LP Latch pulse input pin for display data Data is latched at the falling edge of the clock pulse. FR AC signal input pin for LCD drive waveform The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. Normally it inputs a frame inversion signal. The LCD drive output pins' output voltage levels can be set using the line latch output signal and the FR signal. Table of truth values is shown in "TRUTH TABLE" in Functional Operations. 18 MD Mode selection pin When set to VSS level "L", 8-bit parallel input mode is set. When set to VDD level "H", 4-bit parallel input mode is set. Refer to "RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS" in Functional Operations. 19 V5R Bias power supply pins for LCD drive voltage 17 Page 3 of 12 AZ DISPLAYS, INC. 20 V34R 21 V12R 22 V0R Common Pin Pin No. Symbol 23 V0L 24 V12L 25 V34L 26 27 28 29 30 31 32 33 34 VSS VSS VSS VDD VDD VDD EIO2 D7 DOFFB 35 LP 36 FR 37 38 39 V34R V12R V0R AGM2412B Normally use the bias voltages set by a resistor divider Ensure that voltages are set such that VSS • • V5 < V43 < V12 < V0. ViL and ViR (i = 0,12, 43, 5) must connect to an external power supply, and supply regular voltage which is assigned by specification for each power pin Function Description Bias power supply pins for LCD drive voltage Normally use the bias voltages set by a resistor divider. Ensure that voltages are set such that VSS < V43 < V12 < V0. ViL and ViR (i = 0,12, 43) must connect to an external power supply, and supply regular voltage that is assigned by specification for each power pin. Ground Logic power supply Shift data input for shift register at common mode Dual mode data input at common mode Control input pin for output of non-select level The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. When set to VSS level "L", the LCD drive output pins (Y 1-Y160) are set to level Vss. When set to "L¡±, the contents of the shift register are reset to not reading data. When the /DISPOFF function is canceled, the driver outputs non-select level (V 12 or V43), and the shift data is read at the next falling edge of the LP. At that time, if /DISPOFF removal time does not correspond to what is shown in AC characteristics, the shift data is not read correctly. Table of truth-values is shown in "TRUTH TABLE" in Functional Operations. Shift clock pulse input pin for bi-directional shift register * Data is shifted at the falling edge of the clock pulse. AC signal input pin for LCD drive waveform The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. Normally it inputs a frame inversion signal. The LCD drive output pins' output voltage levels can be set using the shift register output signal and the FR signal. Table of truth-values is shown in "TRUTH TABLE" in Functional Operations. Bias power supply pins for LCD drive voltage Normally use the bias voltages set by a resistor divider. Ensure that voltages are set such that VSS < V43 < V12 < V0. ViL and ViR (i = 0,12, 43) must connect to an external power supply, and supply regular voltage that is assigned by specification for each power pin. Page 4 of 12 AZ DISPLAYS, INC. AGM2412B 3.2 Block Diagram Page 5 of 12 AZ DISPLAYS, INC. AGM2412B 4. Electrical-optical Specifications 4.1 Absolute Maximum Ratings 4.2 Electrical-Optical Characteristics No 1 Item Symbol Condition Current (all SEG on) o Ta=25 C I o Min. Typ. Max. Unit - 15.0 30.0 • A • 2 Contrast Ratio Cr Ta=25 C VLCD = 19.5V 4.5 5.0 - - 3 Threshold voltage Vth Ta=25oC 4 5 Saturation voltage Response time 2.05 2.10 V - 250 350 ms o - 200 300 ms o - 300 450 ms o - 250 350 ms 45 - - Deg. 25 - - Deg. 45 - - Deg. 45 - - Deg. 32 64 128 Hz Fall time Tf Ta=25 C On time • 1 • 12H • 2 • 3H • 3 • 9H • •4 Frame frequency Ta=25 C T ON 6H 11 - o Ta=25 C 7 10 V Tr T OFF 9 - Rise time Off time Viewing Angle 1.90 Ta=25 C Vsat 6 8 1.85 o Ta=25 C Cr = 2 o Ta=25 C Ta=25oC fM 4.3 Electrical Characteristics No Item Symbol Condition 1 Supply Voltage for Logic VDD -VSS - 2 Supply Voltage for LCD Driver VDD -VO Ta=25 oC (VLCD) 3 Supply Current for Logic IDD Ta=25 C VDD =5.0V 4 Frame Frequency fM Ta=25 C o o Min. Typ. Max. Unit 2.5 - 5.5 V 19.3 19.5 19.7 V - 23 26 mA - 80 - Hz Page 6 of 12 AZ DISPLAYS, INC. AGM2412B 5 Input High Voltage VIH - 0.8X VDD - VDD V 6 Input Low Voltage VIL - GND - 0.2X VDD V 7 Output High Voltage VOH - VDD-0.4 - - V 8 Output Low Voltage VOL - - - +0.4 V 4.3 Timming Characteristics • Segment Page 7 of 12 AZ DISPLAYS, INC. AGM2412B 5 Input High Voltage VIH - 0.8X VDD - VDD V 6 Input Low Voltage VIL - GND - 0.2X VDD V 7 Output High Voltage VOH - VDD-0.4 - - V 8 Output Low Voltage VOL - - - +0.4 V 4.3 Timming Characteristics • Segment Page 8 of 12 AZ DISPLAYS, INC. AGM2412B Page 9 of 12 AZ DISPLAYS, INC. AGM2412B Page 10 of 12 AZ DISPLAYS, INC. • AGM2412B Common Page 11 of 12 Page 12 of 12 AZ DISPLAYS, INC. AGM2416B