TI CDCR61A

CDCR61A
DIRECT RAMBUS CLOCK GENERATOR – LITE
SCAS626 – FEBRUARY 2000
D
D
D
D
PW PACKAGE
(TOP VIEW)
400-MHz Differential Clock Source for
Direct Rambus Memory Systems for an
800-MHz Data Transfer Rate
Operates From Two (3.3-V and 1.80-V)
Power Supplies With 180 mW (Typ) at 400
MHz Total
Packaged in a Thin Shrink Small-Outline
Package (PW)
External Crystal Required for Input
VDDP
GNDP
XOUT
XIN
VDDL
LCLK
GNDL
S1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
S0
VDD
GND
CLK
CLKB
GND
VDD
S2
description
The Direct Rambus clock generator – lite (DRCG-Lite) is an independent crystal clock generator. It performs
clock multiplication using PLL, sourced by an internal crystal oscillator. It provides one differential, high-speed
Rambus channel compatible output pair. Also, one single-ended output is available to deliver 1/2 of the crystal
frequency. The Rambus channel operates at up to 400 MHz with an option to select 300 MHz as well. The
desired crystal is a 18.75-MHz crystal in a series resonance fundamental application.
The CDCR61A is characterized for operation over free-air temperatures of 0°C to 85°C.
functional block diagram
S0
VDDP
S1
XTAL
OSC
S2
PLL
XIN
2
DIV
XOUT
BUSCLK
LCLK
/2
BUSCLK FREQUENCY SETTINGS
S0
M (PLL MULTIPLIER)
0
16
1 or Open
64/3
FUNCTION TABLE
VDDP
ON
S1
S2
MODE
CLK
CLKB
LCLK
0
0
Normal
CLK
CLKB
XIN divided by 2
ON
1
1
Normal
CLK
CLKB
XIN divided by 2
ON
0
1
Test
Divided by 2
Divided by 2
XIN divided by 2
ON
1
0
Test
Divided by 4
Divided by 4
XIN divided by 2
0V
0
0
Test
XIN
XIN (invert)
XIN divided by 2
0V
1
1
Test
XIN
XIN (invert)
XIN divided by 2
0V
0
1
Test
XIN divided by 2
XIN (invert) divided by 2
XIN divided by 2
0V
1
0
Test
XIN divided by 4
XIN (invert) divided by 4
XIN divided by 2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Direct Rambus and Rambus are trademarks of Rambus Inc.
Copyright  2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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CDCR61A
DIRECT RAMBUS CLOCK GENERATOR – LITE
SCAS626 – FEBRUARY 2000
Terminal Functions
TERMINAL
NAME
CLK
CLKB
GNDP, GNDL,
GND
LCLK
NO.
I/O
DESCRIPTION
13
O
Output clock, connect to Rambus channel
12
O
Output clock (complement), connect to Rambus channel
2, 7,
11, 14
Ground
6
O
LVCMOS output, 1/2 of crystal frequency
S0, S1, S2
16, 8, 9
I
LVTTL level logic select terminal for function selection
VDD
VDDP
10, 15
VDDL
XIN
5
4
I
Reference crystal input
XOUT
3
O
Reference crystal feedback
Power supply, 3.3 V
1
Power supply for PLL, 3.3 V (0 V for Test mode)
Power supply for LCLK, 1.8 V
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, VDD or VDDP (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V
Supply voltage range, VDDL (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V
Input voltage range,VI, at any input terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Output voltage range, VO, at any output terminal (CLK, CLKB) . . . . . . . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Output voltage range, VO, at any output terminal (LCLK) . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VDDL + 0.5 V
ESD rating (MIL-STD 883C, Method 3015) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . > 2 kV, Machine Model >200 V
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see Dissipation Rating Table
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to the GND terminals.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C‡
TA = 85°C
POWER RATING
PW
1400 mW
11 mW/°C
740 mW
‡ This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with
no air flow.
2
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CDCR61A
DIRECT RAMBUS CLOCK GENERATOR – LITE
SCAS626 – FEBRUARY 2000
recommended operating conditions
Supply voltage, VDD
LCLK supply voltage, VDDL
MIN
NOM
MAX
3
3.3
3.6
V
1.7
1.8
2.1
V
0.35×VDD
0.35×VDD
V
S0
Low level input voltage,
Low-level
voltage VIL
S1, S2
S0
High level input voltage,
High-level
voltage VIH
S1, S2
Internal pullup resistance
Low level output current
Low-level
current, IOL
High level output current,
High-level
current IOH
0.65×VDD
0.65×VDD
10
55
100
S1, S2
90
145
250
CLK, CLKB
16
LCLK
10
CLK, CLKB
–16
LCLK
–10
14.0625
Input capacitance (CMOS),
(CMOS) CI†
V
S0
Input frequency at crystal input
kΩ
mA
mA
18.75
MHz
S0, S1, S2
2.5
XIN, XOUT
20
Operating free-air temperature, TA
† Capacitance measured at f = 1 MHz, dc bias = 0.9 V, and VAC < 100 mV
UNIT
0
pF
°C
85
timing requirements
MIN
MAX
Clock cycle time, t(cycle)
2.5
3.7
Input slew rate, SR
0.5
4
V/ns
3
ms
State transition latency (VDDX or S0 to CLKs – normal mode), t(STL)
UNIT
ns
crystal specifications
Frequency
Frequency tolerance (at 25°C ± 3°C)
MIN
MAX
UNIT
14.0625
18.75
MHz
15
ppm
–15
Equivalent resistance (CL = 10 pF)
100
Ω
Temperature drift (–10°C to 75°C)
10
ppm
Drive level
0.01
1500
µW
Motional inductance
20.7
25.3
mH
Insulation resistance
500
MΩ
Spurious attenuation ratio (at frequency ± 500 kHz)
3
dB
Overtone spurious
8
dB
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CDCR61A
DIRECT RAMBUS CLOCK GENERATOR – LITE
SCAS626 – FEBRUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TEST CONDITIONS†
PARAMETER
MIN
TYP‡
MAX
UNIT
1.25
1.85
V
0.4
0.7
V
VO(X)
Differential crossing-point output voltage
See Figures 1 and 7
VO(PP)
Peak-to-peak output voltage swing,
single ended
VOH – VOL,
See Figure 1
VDD = 3 V,
VDD = 3.3 V,
II = –18 mA
VI = VO
VDD = 3.3 V,
VDD = 3.6 V,
VO = 2 V
VI = VDD
27
VDD = 3.6 V,
VDD = 3.3 V,
VI = VDD
VO = 0 V
10
VDD = 3.6 V,
VDD = 3.6 V,
VI = 0 V
VI = 0 V
VIK
RI
Input clamp voltage
Input resistance
XIN, XOUT
XOUT
IIH
High-level input current
S0
S1, S2
XOUT
IIL
Low-level input current
S0
S1, S2
–1.2
>50
10
–5.7
–30
–100
–10
–50
See Figure 1
CLK, CLKB
VOH
High level output voltage
High-level
LCLK
IOH
Low level output voltage
Low-level
CLK, CLKB
IOH = –1 mA
VDD = 3 V,
IOH = –16 mA
2.2
VDDL = min to max,
IOH = – 10 mA
VDDL –
0.45 V
LCLK
VDDL = min to max,
VDD = 3.135 V,
IOL = 10 mA
VO = 1 V
CLK, CLKB
VDD = 3.3 V,
VDD = 3.465 V,
VO = 1.65 V
VO = 3.135 V
VDDL = 1.7 V,
VDDL = 1.8 V,
VO = 0.5 V
VO = 0.9 V
VDDL = 2.1 V,
VDD = 3.135 V,
VO = 1.6 V
VO = 1.95 V
VDD = 3.3 V,
VDD = 3.465 V,
VO = 1.65 V
VO = 0.4 V
VDDL = 1.7 V,
VDDL = 1.8 V,
VO = 1.2 V
VO = 0.9 V
CLK, CLKB
IOL
Low level output current
Low-level
LCLK
rOL
High-level dynamic output resistance§
Low-level dynamic output resistance§
CO
Output capacitance
rOH
mA
µA
V
VDDL
0.1
0.5
0
–32
V
0.45
–52
–51
–14.5
–11
–21
–26
mA
–28
–24.5
43
–35
61.5
65
25.5
11
36
27
mA
30
VDDL = 2.1 V,
VO = 0.5 V
∆IO – 14.5 mA to ∆IO – 16.5 mA
28
38
12
25
40
Ω
∆IO + 14.5 mA to ∆IO + 16.5 mA
12
17
40
Ω
CLK, CLKB
3
LCLK
3
† VDD refers to any of the following; VDD, VDDL, and VDDP
‡ All typical values are at VDD = 3.3 V, VDDL = 1.8 V, TA = 25°C.
§ rO = ∆VO/∆IO. This is defined at the output terminals, not at the measurement point of Figure 1.
4
µA
1
IOL = 1 mA
IOL = 16 mA
LCLK
VDD–
0.1 V
VDD = min to max,
VDD = min to max,
VDD = 3 V,
High level output current
High-level
mA
2.1
See Figure 1
VOL
V
kΩ
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CDCR61A
DIRECT RAMBUS CLOCK GENERATOR – LITE
SCAS626 – FEBRUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
TEST CONDITIONS†
PARAMETER
IDD
IDDL
MIN
TYP‡
MAX
UNIT
Static supply current
Outputs high or low (VDDP = 0 V)
6.5
Static supply current (LVCMOS)
Outputs high or low (VDDP = 0 V)
50
µA
300 MHz
39
mA
400 MHz
50
mA
400 MHz
8
mA
IDD(NORMAL)
Supply current in normal state
IDDL(NORMAL)
Supply current in normal state
(LVCMOS)
mA
† VDD refers to any of the following; VDD, VDDL, and VDDP
‡ All typical values are at VDD = 3.3 V, VDDL = 1.8 V, TA = 25°C.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
t(cycle)
Clock cycle time (CLK, CLKB)
tcjj
Total jitter
j
over 1,, 2,, 3,, 4,, 5,, or 6
clock cycles‡
tjL
Long term jitter
Long-term
tDC
Output duty cycle over 10,000 cycles
tDC,ERR
DC ERR
Output cycle-to-cycle
cycle to cycle duty cycle error
tr, tf
Output rise and fall times (measured
at 20%-80% of output voltage)#
∆t
Difference between rise and fall times on a single
device (20%–80%) |tf – tr|#
tc(LCLK)
t(cj)
Clock cycle time (LCLK)
LCLK cycle jitter§
See Figure 11
t(cj10)
tDC
LCLK 10-cycle jitter§¶
See Figure 11
tr, tf
TYP†
2.5
300 MHz
400 MHz
300 MHz
400 MHz
300 MHz
400 MHz
CLK, CLKB
LCLK
Output rise and fall times (measured
at 20%-80% of output voltage)
LCLK
400
300
45%
55
160
UNIT
ns
ps
ps
55%
70
See Figure 6
ps
400
ps
100
ps
106.6
142.2
ns
–0.2
0.2
ns
–1.3 t(cj)
1.3 t(cj)
ns
40%
60%
See Figure 9,
See Figure 9
fmod = 50 kHz
fmod = 8 MHz
3.7
100
See Figure 4
See Figure 9,
MAX
140
See Figure 3
See Figure 5
Output duty cycle
PLL loop bandwidth
MIN
1
–3
–20
ns
dB
† All typical values are at VDD = 3.3 V, TA = 25°C.
‡ Output short-term jitter specification is peak-to-peak (see Figure 9).
§ LCLK cycle jitter and 10-cycle jitter are defined as the difference between the measured period and the nominal period.
¶ LCLK 10-cycle jitter specification is based on the measured value of LCLK cycle jitter.
# VDD= 3.3 V
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CDCR61A
DIRECT RAMBUS CLOCK GENERATOR – LITE
SCAS626 – FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
68 Ω, ±5%
3 pF
See Note A
39 Ω, ±5%
RT = 28 Ω
(CLK)
Measurement
Node
39 Ω, ±5%
68 Ω, ±5%
100 pF
RT = 28 Ω
(CLKB)
3 pF
See Note A
NOTE A: These capacitors represent parasitic capacitance. No discrete capacitors are used on the test
board during device characterization.
Figure 1. Test Load and Voltage Definitions (VO(STOP), VO(X), VO, VOH, VOL)
CLK
CLKB
tc1
tc2
Cycle-to-cycle jitter = | tc1 – tc2| over 10000 consecutive cycles
Figure 2. Cycle-to-Cycle Jitter
CLK
CLKB
tc(i)
tc(i+1)
tc(i) = nominal expected time
Cycle-to-cycle jitter = | tc(i) – tc(i+1)| over 10000 consecutive cycles
Figure 3. Short-Term Cycle-to-Cycle Jitter over 2, 3, 4, or 6 Cycles
CLK
CLKB
t(cycle)
tjL = | t(cycle), max– t(cycle), min| over 10000 consecutive cycles
Figure 4. Long-Term Jitter
6
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CDCR61A
DIRECT RAMBUS CLOCK GENERATOR – LITE
SCAS626 – FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
CLK
CLKB
tpW+
t(cycle)
Duty cycle (tDC) = (tpW+/t(cycle))
Figure 5. Output Duty Cycle
CLK
CLKB
tpW+(i)
t(cycle)
tpW+(i+1)
t(cycle)
Duty cycle error (tDC,ERR) = tpW+(i) – tpW+(i+1)
Figure 6. Duty Cycle Error (Cycle-to-Cycle)
CLK
VO(X)+
VO(X), nom
VO(X)–
CLKB
Figure 7. Crossing-Point Voltage
1.8 V
120 Ω
LCLK
10 pF
120 Ω
VOH
80%
20%
tr
VOL
tf
Figure 8. LCLK Test Load Circuit and Voltage Waveform for CLK/CLKB and LCLK
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CDCR61A
DIRECT RAMBUS CLOCK GENERATOR – LITE
SCAS626 – FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VDD, VDDP, or
S0
CLK/CLKB
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
t(STL)
Figure 9. PLL Frequency Transition Timing
LCLK
t(cj)
t(cj10)
Figure 10. LCLK Jitter
8
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CDCR61A
DIRECT RAMBUS CLOCK GENERATOR – LITE
SCAS626 – FEBRUARY 2000
MECHANICAL DATA
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
0,75
0,50
A
Seating Plane
0,15
0,05
1,20 MAX
0,10
PINS **
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064 / E 08/96
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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Copyright  2000, Texas Instruments Incorporated