Revised January 1999 CD4503BC Hex Non-Inverting 3-STATE Buffer General Description Features The CD4503BC is a hex non-inverting 3-STATE buffer with high output current sink and source capability. 3-STATE outputs make it useful in bus-oriented applications. Two separate disable inputs are provided. Buffers 1 through 4 are controlled by the disable 4 input. Buffers 5 and 6 are controlled by the disable 2 input. A high level on either disable input will cause those gates on its control line to go into a high impedance state. ■ Wide supply voltage range: 3.0 VDC to 18 VDC ■ 3-STATE outputs ■ Symmetrical turn on/turn off delays ■ Symmetrical output rise and fall times ■ Pin-for-pin replacement for MM80C97 and MC14503 Ordering Code: Package Number Package Description CD4503BCM Order Number M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body CD4503BCSJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide CD4503BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Schematic Diagram Pin Assignments for DIP, SOIC and SOP Truth Table In Disable Out Input Top View © 1999 Fairchild Semiconductor Corporation 0 0 1 0 0 1 X 1 3-STATE X = Don't Care DS005989.prf www.fairchildsemi.com CD4503BC Hex Non-Inverting 3-STATE Buffer October 1987 CD4503BC Absolute Maximum Ratings(Note 1) Recommended Operating Conditions (Note 2) (Note 2) Supply Voltage (VDD) −0.5V to +18V Supply Voltage (VDD) Input Voltage (VIN) −0.5V to +0.5V Operating Temperature Range (TA) −65°C to +150°C Storage Temperature Range (TS) Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The tables of “Recommended Operating Conditions” and “Electrical Characteristics” provide conditions for actual device operation. Power Dissipation (PD) Dual-In-Line 700 mW Small Outline 500 mW +3V to +15V −40°C to +85°C Note 2: VSS = 0V unless otherwise specified. Lead Temperature (TL) (Soldering, 10 seconds) 260°C DC Electrical Characteristics (Note 2) Symbol IDD Parameter −40°C Conditions Quiescent Device VDD = 5V, Current VIN = VDD or VSS Min VDD = 10V, +25°C Max Min Typ +85°C Max Min Max Units 4 4 30 µA 8 8 60 µA 16 16 120 µA VIN = VDD or VSS VDD = 15V, VIN = VDD or VSS VOL VOH LOW Level VIN = VDD or 0 Output Voltage VDD = 5V 0.05 0 0.05 0.05 V VDD = 10V 0.05 0 0.05 0.05 V VDD = 15V 0.05 0 0.05 0.05 V HIGH Level Output Voltage VIL VIN = V DD or 0 VDD = 5V 4.95 4.95 4.95 V VDD = 10V 9.95 9.95 9.95 V VDD = 15V 14.95 LOW Level VDD = 5V, Input Voltage VO = 4.5V or 0.5V VDD = 10V, 14.95 14.95 V 1.5 2.25 1.5 1.5 V 3.0 4.50 3.0 3.0 V 4.0 6.75 4.0 4.0 V VO = 9.0V or 1.0V VDD = 15V, VO = 13.5V or 1.5V VIH HIGH Level VDD = 5V, Input Voltage VO = 0.5V or 4.5V VDD = 10V, 3.5 3.5 2.75 3.5 V 7.0 7.0 5.5 7.0 V 11.0 11.0 8.25 11.0 V VO = 1.0V or 9.0V VDD = 15V, VO = 1.5V or 13.5V IOL IOH LOW Level Output VDD = 4.5V, VOL = 0.4V 2.30 1.95 2.65 1.60 mA Current VDD = 5.0V, VOL = 0.4V 2.5 2.10 2.75 1.75 mA mA VDD = 10V, V OL = 0.5V 6.5 5.45 7.0 4.45 VDD = 15V, VOL = 1.5V 16.50 13.80 25.00 11.30 mA HIGH Level Output VDD = 5V, VOH = 4.6V −1.04 −0.88 −1.76 −0.7 mA Current VDD = 10V, VOH = 9.5V −2.60 −2.2 −4.50 −1.8 mA VDD = 15V, VOH = 13.5V −7.2 −6.0 −17.6 −4.8 mA ITL 3-STATE Leakage Current VDD = 15V ±0.3 ±10−4 ±0.3 ±1.0 µA IIN Input Current VDD = 15V ±0.3 ±10−5 ±0.3 ±1.0 µA Note 3: IOH and IOL are tested one output at a time. www.fairchildsemi.com 2 (Note 4) TA = 25°C, CL = 50 pF, RL = 200 kΩ, Input tr = tf = 20 ns, unless otherwise specified Symbol tPHL, tPLH tPLZ, tPHZ tPZL, tPZH tTLH tTHL Parameter Propagation Delay Time Typ Max Units VDD = 5V Conditions Min 75 100 ns VDD = 10V 35 40 ns VDD = 15V 25 30 ns Propagation Delay Time, VDD = 5V 80 125 ns Logical Level to HIGH VDD = 10V 40 90 ns Impedance State VDD = 15V 35 70 ns Propagation Delay Time, VDD = 5V 95 175 ns High Impedance State to VDD = 10V 40 80 ns Logical Level VDD = 15V 35 70 ns Output Rise Time VDD = 5V 45 80 ns VDD = 10V 23 40 ns VDD = 15V 18 35 ns VDD = 5V 45 80 ns VDD = 10V 23 40 ns VDD = 15V 18 35 ns Output Fall Time Note 4: AC Parameters are guaranteed by DC correlated testing. 3 www.fairchildsemi.com CD4503BC AC Electrical Characteristics CD4503BC AC Test Circuits and Switching Time Waveforms tPHL , tPLH CMOS to CMOS tPHZ and tPZH tPLZ and tPZL tPHZ tPLZ tPZH tPZL Note: Delays measured with input tr, tf ≤ 20 ns. www.fairchildsemi.com 4 CD4503BC Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Package Number M16A 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D 5 www.fairchildsemi.com CD4503BC Hex Non-Inverting 3-STATE Buffer Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.