500MHz Video Front End: 4-1 MUX, VGA & DC-Restore Features General Description • • • • • • The EL4102C VFE (Video Front End) is designed to perform all of the input processing functions in an analog video system as well as provide analog input processing for digital video systems. The EL4102C VFE contains a 4:1 MUX input, a DC-restore amplifier and a variable gain amplifier. The MUX input can be used to select which input to use. In a digital system, the DC-restore and variable gain amplifiers allow the input signal to be positioned and scaled to give optimum A-to-D conversions results. In an analog system these perform the brightness and contrast operations. A buffered output of the MUX selection is also available for use as a monitor output. 4:1 multiplexer with monitor out 18dB variable gain amplifier DC-restore amplifier Digital control serial interface ±5V operation 500MHz bandwidth Applications • • • • • • HDTV/DTV Analog Inputs Video Projectors Computer Monitors Set Top Boxes Security Video Broadcast Video Equipment With a 500MHz bandwidth and only 50mA supply current, the EL4102C is ideal for use in portable and fixed projectors, as well as HDTV, DTV and other high performance video applications. A 3-wire digital interface enables full control of the input selection, as well as 0 to -18dB of gain and blanking operations. The EL4102C is available in the QSOP24 package and is specified for operation over the -40°C to +85°C temperature range. Ordering Information Part No. EL4102CU Package 24-Pin QSOP Tape & Reel EL4102C - Preliminary EL4102C - Preliminary Outline # MDP0040 Connection Diagram SAMPLE PULSE 1 HOLD 2 GNDL2 CAP 24 DCREF 23 CH 0.33nF DCV VI/P0 3 IN0 DCFDBK 22 RGV +5V 4 VS1+ VFDBK 21 VI/P1 RFV 0V 5 IN1 VOUT 20 6 GNDI VS2+ 19 +5V VS- 18 -5V Video Out RL=150Ω VI/P2 7 IN2 Monitor Out RL=150Ω RFM -5V 8 VS- MOUT 17 9 IN3 MFDBK 16 10 ENB GNDL 15 11 SDI PDWN 14 VI/P3 SCLK 12 SCLK SDO 13 PDWN DATAOUT Note: All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication; however, this data sheet cannot be a “controlled document”. Current revisions, if any, to these specifications are maintained at the factory and are available upon your request. We recommend checking the revision level before finalization of your design documentation. © 2001 Elantec Semiconductor, Inc. August 30, 2001 ENB SDI RGM EL4102C - Preliminary EL4102C - Preliminary 500MHz Video Front End: 4-1 MUX, VGA & DC-Restore Absolute Maximum Ratings (T A = 25°C) Values beyond absolute maximum ratings can cause the device to be prematurely damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. 11V Supply Voltage (VS+ to VS-) Input Voltage VS- - 0.3V, VS+ +0.3V Storage Temperature Range Ambient operating Temperature Operating Junction Temperature Power Dissipation -65°C to +150°C -40°C to +85°C 125°C See Curves Important Note: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA. Electrical Characteristics VS1+ = VS2+ = 5V, VS1- = VS2- = -5V, RFV = RFG = 750, RGV = RGM = O.C., AV = 1, RLV = RLM = 150Ω, CLV = CLM = 3p, CH = 0.33n, GAIN = 1. Parameter Description Conditions Min Typ Max Unit Supply IS1+ Positive Supply Current 1 IS - Negative Supply Current IS2+ Positive Supply Current 2 VIN = 0, IL = 0 14 15 20 mA IS1S+ Positive Supply Current 1 in Standby Standby 3.8 5 7.3 mA VIN = 0, IL = 0 35 mA 45 mA ISS- Negative Supply Current in Standby Standby 0.57 1 1.3 mA IS2S+ Positive Supply Current 2 in Standby Standby -10 - 10 µA VS1+, VS2+ Positive Supply Voltage 4.5 5.0 5.5 V VS - Negative Supply Voltage -4.5 -5.0 -5.5 V -2.2 6.1 Input Ib Input Bias Current VIN = 0V Ibo Input Bias Current Drift with Temp. VIN = 0V VIH Input High Voltage VIL Input Low Voltage VIP Input Voltage Swing, Pos. Saturated Input, Att. code = 01010 VIN Input Voltage Swing, Neg. Saturated Input, Att. code = 01010 IIDL Low Input Current for SCLK and ENB VIN = 0V IIDH High Input Current for SCLK and ENB IIL Low Input Current for SDI, PDWN, HOLD IIH High Input Current for SDI, PDWN, HOLD tsh Sample and Hold Delay Time tsu Data Set Up Time TBD 10 TBD th Data Hold Time TBD 10 TBD ns fclk Serial Clock Rate TBD 5 MHz -22.4 TBD 2 V 0.8 3.35 µA nA/°C 3.5 V V -3.5 -3.39 V 50 85 150 µA VIN =5V 0 0.1 10 µA VIN = 0V 15 48 75 µA VIN =5V 0 0.1 10 µA 15 ns ns tsue Enable Set Up Time TBD 10 ns the Enable Hold Time TBD 10 ns tpd Clock to Data Output Delay CL = 10pF TBD 21 ns -400 30 420 -5 - 5 Output VOSM Output Offset Voltage - Monitor VIN = 0V VOS DC-restore Offset Voltage auto-zero on, DCREF = 0 TCVOS Output Offset Voltage Drift - Video auto-zero on VO + Output Voltage Swing, Pos. Attenuator = 0dB, Monitor & Video Outputs VO - Output Voltage Swing, Neg. Attenuator = 0dB, Monitor & Video Outputs VSDO high Serial Data Output High IL = +1mA 4.7 V VSDO low Serial Data Output Low IL = -1mA 0.25 V 15 2 3.44 mV µV/°C 3.5 -3.5 mV V -3.43 V Electrical Characteristics VS1+ = VS2+ = 5V, VS1- = VS2- = -5V, RFV = RFG = 750, RGV = RGM = O.C., AV = 1, RLV = RLM = 150Ω, CLV = CLM = 3p, CH = 0.33n, GAIN = 1. Parameter ISC Description Output Short Circuit Current Conditions RL = 10Ω, Source or Sink Min Typ 65 100 Max Unit mA AC Performance SR Slew Rate - Video Out (20%-80%) VOUT = 4VP-P 1000 2100 4500 V/µS SRM Slew Rate - Monitor Out (20%-80%) VOUT = 4VP-P 1250 2100 3900 V/µS OS Output Overshoot, Video VOUT = 1VP-P TBD OSM Output Overshoot, Monitor VOUT = 1VP-P TBD % ts Settling Time to 1%, Video Hold Mode TBD ns tsm Settling Time to 1%, Monitor VREF DC-restore Reference Voltage Range VIN = -2V to +2V tsd DC-restore - Settling Time to 1% Sample Mode On VOHS DC-restore - Video Output Hold Step S - H Transition VOSB DC-restore - Offset vs. Black Level Sample Mode On % TBD ICCL DC-restore - Charge Current Limit, ICAP Sample Mode On IDC DC-restore - Droop Current, ICAP Hold Mode On BW 3dB Bandwidth, Video Out Attenuator = 00000 BWM 3dB Bandwidth, Monitor Out 0.1BW ±0.1dB Flat Bandwidth, Video Out 0.1BWM -2 - ns 2 1.2 -1.1 -1 -0.6 mV 1 260 -30 - V µS mV/V µA 30 nA TBD MHz TBD MHz TBD MHz ±0.1dB Flat Bandwidth, Monitor Out TBD MHz Vp Peaking, Video TBD dB Vpm Peaking, Monitor TBD dB dP Diff. Phase @3.58MHz, Video TBD ° dG Diff. Gain @3.58MHz, Video TBD % dPM Diff. Phase @3.58MHz, Monitor TBD ° dPG Diff. Gain @3.58MHz, Monitor TBD % en Noise Voltage at Input for VOUT TBD nV/√Hz enm Noise Voltage at Input for MOUT TBD nV/√Hz Attenuator = 00000 Crosstalk  @10MHz 3 channel hostile -45 dB Crosstalk  @100MHz 3 channel hostile -20 dB Attenuator Range - 18.2 - Attenuator Step Size 31 Steps - 0.58 - dB Relative Attenuation Error Between any 2 levels 0 - ±0.2 dB 1. Total unwanted output normalized by wanted (or expected) output; add -10dB to get channel-to-channel isolation 3 dB EL4102C - Preliminary EL4102C - Preliminary 500MHz Video Front End: 4-1 MUX, VGA & DC-Restore EL4102C - Preliminary EL4102C - Preliminary 500MHz Video Front End: 4-1 MUX, VGA & DC-Restore Serial Programming Truth Table Inputs (X = Don’t Care) Standby Input Selection Attenuation MSB LSB Attenuation B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 0 0 0 X X 0dB = 1.000 0 0 0 0 0 1 X X -0.6dB = 0.94 0 0 0 0 1 0 X X -1.2dB = 0.88 0 0 0 0 1 1 X X -1.7dB = 0.82 0 0 0 1 0 0 X X -2.3dB = 0.77 0 0 0 1 0 1 X X -2.9dB = 0.7 0 0 0 1 1 0 X X -3.5dB = 0.67 0 0 0 1 1 1 X X -4.1dB = 0.63 0 0 1 0 0 0 X X -4.6dB = 0.59 0 0 1 0 0 1 X X -5.2dB = 0.55 0 0 1 0 1 0 X X -5.8dB = 0.51 0 0 1 0 1 1 X X -6.4B = 0.48 0 0 1 1 0 0 X X -7.0dB = 0.45 0 0 1 1 0 1 X X -7.5dB = 0.42 0 0 1 1 1 0 X X -8.1dB = 0.39 0 0 1 1 1 1 X X -8.7dB = 0.37 0 1 0 0 0 0 X X -9.3dB = 0.34 0 1 0 0 0 1 X X -9.9dB = 0.32 0 1 0 0 1 0 X X -10.5dB = 0.30 0 1 0 0 1 1 X X -11.0dB = 0.28 0 1 0 1 0 0 X X -11.6dB = 0.26 0 1 0 1 0 1 X X -12.2dB = 0.25 0 1 0 1 1 0 X X -12.8dB = 0.23 0 1 0 1 1 1 X X -13.4dB = 0.22 0 1 1 0 0 0 X X -13.9dB = 0.20 0 1 1 0 0 1 X X -14.5dB = 0.19 0 1 1 0 1 0 X X -15.1dB = 0.18 0 1 1 0 1 1 X X -15.7dB = 0.17 0 1 1 1 0 0 X X -15.3dB = 0.15 0 1 1 1 0 1 X X -16.8dB = 0.14 0 1 1 1 1 0 X X -17.4dB = 0.13 0 1 1 1 1 1 X X -18.0dB = 0.12 0 X X X X X 1 1 IN3 Selected 0 X X X X X 1 0 IN2 Selected 0 X X X X X 0 1 IN1 Selected 0 X X X X X 0 0 IN0 Selected 1 X X X X X X X Standby Mode - Powered Down 1 1 1 1 1 1 1 1 Wake-up Condition (-18.0dB, IN3, Powered Down) 4 Control Bits Logic Table Bit Function B7 Standby - Power Down B6 Gain Bit 4 B5 Gain Bit 3 B4 Gain Bit 2 B3 Gain Bit 1 B2 Gain Bit 0 B1 Input Select Bit 1 B0 Input Select Bit 0 Serial Timing Diagram ENB tHE tSE T tr tf tHE tSE SCLK tSD SDI tHD B7 tw B6 B5 B4-B2 B1 B0 t MSB Load MSB first, LSB last LSB Serial Timing Parameters Parameter Example T ≥100 ns Description Clock Period tr/tf 0.05 x T tHE ≥40ns ENB Hold Time Clock Rise/Fall Time tSE ≥40ns ENB Setup Time tHD ≥40ns Data Hold Time tSD ≥40ns tw 0.50 x T Data Setup Time Clock Pulse Width 5 EL4102C - Preliminary EL4102C - Preliminary 500MHz Video Front End: 4-1 MUX, VGA & DC-Restore EL4102C - Preliminary EL4102C - Preliminary 500MHz Video Front End: 4-1 MUX, VGA & DC-Restore Pin Descriptions Pin Number Pin Name Pin Type 1 HOLD Logic Input 2 GNDL2 Logic Ground 3 IN0 High Frequency Signal 4 VS1+ Power 5 IN1 High Frequency Signal 6 GNDI Analog Signal 7 IN2 High Frequency Signal Pin Description Hold pulse for DC-restore function Logic ground for “hold” buffer Video input #0 Positive power pin for quiet supply currents Video input #1 Intermediate reference for attenuation function Video input #2 8 VS - Power 0 IN3 High Frequency Signal 10 ENB Logic Input Enable (negative true) input for loading serial data stream 11 SDI Logic Input Serial input data stream 12 SCLK Logic Input 13 SDO Logic Output Negative power pin Video input #3 Serial data stream clock Serial output data stream for connection to cascaded chip 14 PDWN Logic Input 15 GNDL Logic Ground 16 MFDBK High Frequency Signal Monitor amplifier feedback 17 MOUT High Frequency Signal Monitor amplifier output Power down input to put chip in low current standby mode Logic ground for logic buffers 18 VS - Power Negative power pin 19 VS2+ Power Positive power pin for heavy, pulsatile supply currents 20 VOUT High Frequency Signal 21 VFDBK High Frequency Signal 22 DCFDBK Analog Signal Input to sample circuit 23 DCREF Analog Signal Reference DC voltage representing black level 24 CAP Analog Signal Sample storage capacitor for DC-restore circuit Video amplifier output Video amplifier feedback 6 Block Diagram (Gain of 1) VS+ Input Video MFDBK 750 + IN0 MOUT X Input Video + - IN1 VOUT 750 VFDBK Input Video Input Video IN2 + - DCFDBK DCREF HOLD IN3 CAP ENB SDI CH SD0 SCLK GNDL GNDI GNDL2 VS- 7 PDWN EL4102C - Preliminary EL4102C - Preliminary 500MHz Video Front End: 4-1 MUX, VGA & DC-Restore EL4102C - Preliminary EL4102C - Preliminary 500MHz Video Front End: 4-1 MUX, VGA & DC-Restore Applications Information Using the Serial Data Output Connection for a Multi-chip Design The serial data out (SDO) of chip one is connected to the serial data in (SDI) of chip two, similarly, chip two SDO is connected to SDI on chip three. The clock (SCLK) and enable (/ENB) signals are connected in parallel to all three chips. See figure yy for suggested interconnect of the control signals. In a system design that uses three chips, (i.e. RGB, YUV, YPrPb systems) the control signal may be "daisy chained" through the three chips. This gives an advantage in that the control will be updated simultaneously on the three channels. Figure xx shows the control signal waveforms when using this configuration. Note, that the last data bit clocked into the three chips occurs on the last positive clock edge that is within the enabled period. This will be D0 in the first chip, D8 and D16 on the second two chips. The rising edge of /ENB will then simultaneously transfer the data internally to the chip. Typically the data for each chip is held as an image in the micro-controller system; the load operation would prepare the update information as a 24-bit word ready for shifting into the three chips. 8 EL4102C - Preliminary EL4102C - Preliminary 500MHz Video Front End: 4-1 MUX, VGA & DC-Restore General Disclaimer Specifications contained in this data sheet are in effect as of the publication date shown. Elantec, Inc. reserves the right to make changes in the circuitry or specifications contained herein at any time without notice. Elantec, Inc. assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. August 30, 2001 WARNING - Life Support Policy Elantec, Inc. products are not authorized for and should not be used within Life Support Systems without the specific written consent of Elantec, Inc. Life Support systems are equipment intended to support or sustain life and whose failure to perform when properly used in accordance with instructions provided can be reasonably expected to result in significant personal injury or death. Users contemplating application of Elantec, Inc. Products in Life Support Systems are requested to contact Elantec, Inc. factory headquarters to establish suitable terms & conditions for these applications. Elantec, Inc.’s warranty is limited to replacement of defective components and does not cover injury to persons or property or other consequential damages. Elantec Semiconductor, Inc. 675 Trade Zone Blvd. Milpitas, CA 95035 Telephone: (408) 945-1323 (888) ELANTEC Fax: (408) 945-9305 European Office: 44-118-977-6020 Japan Technical Center: 81-45-682-5820 9 Printed in U.S.A.