OKI MS82V48540

FEDS82V48540-01
OKI Semiconductor
MS82V48540
Issue Date:Nov. 8, 2002
393,216-Word × 32-Bit × 4-Bank FIFO-SGRAM
GENERAL DESCRIPTION
The MS82V48540 is a 48-Mbit system clock synchronous dynamic random access memory. In addition to the
conventional random read/write access function, the MS82V48540 provides the automatic row address increment
function and automatic bank switching function. Therefore, if once the row and column addresses are set,
continuous serial accesses are possible while banks are automatically switched till input of the Precharge
command. The MS82V48540 is ideal for digital camera and TV buffer memory applications.
FEATURES
•
•
•
•
•
•
•
•
•
•
393,216 words × 32 bits × 4 banks memory (1,536 rows × 256 columns × 32 bits × 4 banks)
Single 3.3 V ±0.3 V power supply
LVTTL compatible inputs and outputs
Programmable burst length (1, 2, 4, 8 and full page)
Programmable CAS latency (2, 3)
Automatic row address increment function and automatic bank switching function
Power Down operation and Clock Suspend operation
3,072 refresh cycles/64 ms
Auto refresh and self refresh capability
Package:
86-pin 400 mil plastic TSOP (II) (TSOPII86-P-400-0.50-K) (Product : MS82V48540-xTA)
x indicates speed rank.
PRODUCT FAMILY
Family
Max. Operating Frequency
Access Time
MS82V48540-7
143 MHz
5 ns
MS82V48540-8
125 MHz
6 ns
Package
86-pin Plastic TSOP (II) (400 mil)
1/44
FEDS82V48540-01
OKI Semiconductor
MS82V48540
PIN CONFIGURATION (TOP VIEW)
VCC
DQ0
VCCQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VCCQ
DQ5
DQ6
VSSQ
DQ7
NC
VCC
DQM0
WE
CAS
RAS
CS
NC
BA0
BA1
A10/AP
A0
A1
A2
DQM2
VCC
NC
DQ16
VSSQ
DQ17
DQ18
VCCQ
DQ19
DQ20
VSSQ
DQ21
DQ22
VCCQ
DQ23
VCC
1
86
2
85
3
84
4
83
5
82
6
81
7
80
8
79
9
78
10
77
11
76
12
75
13
74
14
73
15
72
16
71
17
70
18
69
19
68
20
67
21
66
22
65
23
64
24
63
25
62
26
61
27
60
28
59
29
58
30
57
31
56
32
55
33
54
34
53
35
52
36
51
37
50
38
49
39
48
40
47
41
46
42
45
43
44
VSS
DQ15
VSSQ
DQ14
DQ13
VCCQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VCCQ
DQ8
NC
VSS
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
VSS
NC
DQ31
VCCQ
DQ30
DQ29
VSSQ
DQ28
DQ27
VCCQ
DQ26
DQ25
VSSQ
DQ24
VSS
86-Pin Plastic TSOP (II)
(Type K)
Pin Name
Function
A0 – A10
Row Address Inputs
A0 – A7
Column Address Inputs
BA0, BA1
Bank Address
Pin Name
WE
DQM0 – DQM3
DQ0 – DQ31
Function
Write Enable
DQ Mask Enable
Data Inputs/outputs
CLK
System Clock Input
VCC
Supply Voltage
CKE
Clock Enable
VSS
Ground
CS
Chip Select
VCCQ
Supply Voltage for DQ
RAS
Row Address Strobe
VSSQ
Ground for DQ
CAS
Column Address Strobe
NC
No Connection
Note: The same power supply voltage must be provided to every VCC pin and VCCQ pin.
The same GND voltage level must be provided to every VSS pin and VSSQ pin.
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FEDS82V48540-01
OKI Semiconductor
MS82V48540
BLOCK DIAGRAM
CKE
CLK
CS
RAS
CAS
WE
DQM0
to
DQM3
I/O
Timing
Controller
Register
Bank
Controller
BA0, BA1
Internal
Column
Address
Counter
Column
8
Address
Buffers
Internal
Input
Row
Data
Address
Counter
Register
Column Decoders
Input
32 Buffers
32
11
Address
Buffers
Word Drivers
Sense Amplifiers
Row
Row Decoders
A0 to
A10
BA0,
BA1
12Mb
Memory
Cells
Bank A
Bank B
Bank C
Bank D
Read
32
Data
Register
32
Output
Buffers
32
DQ0
to
DQ31
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FEDS82V48540-01
OKI Semiconductor
MS82V48540
PIN DESCRIPTION
CLK
Fetches all inputs at the "H" edge.
CS
Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE,
DQM0, DQM1, DQM2 and DQM3.
CKE
Masks system clock to deactivate the subsequent CLK operation.
If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is
deactivated. CKE should be asserted at least one cycle prior to a new command.
Address
Row & column multiplexed.
Row address: RA0 – RA10
Column address: CA0 – CA7
BA0, BA1
Selects bank to be activated during row address latch time and selects bank for precharge and
read/write during column address latch time.
BA0 = “L”, BA1 = “L”: Bank A
BA0 = “H”, BA1 = “L”: Bank B
BA0 = “L”, BA1 = “H”: Bank C
BA0 = “H”, BA1 = “H”: Bank D
RAS
CAS
WE
Functionality depends on the combination. For details, see the function truth table.
DQM0 –
DQM3
Masks the read data of two clocks later when DQM0 - DQM3 are set "H" at the "H" edge of the
clock signal.
Masks the write data of the same clock when DQM0 - DQM3 are set "H" at the "H" edge of the
clock signal.
DQM0 controls DQ0 to DQ7, DQM1 controls DQ8 to DQ15, DQM2 controls DQ16 to DQ23, and
DQM3 controls DQ24 to DQ31.
DQ0 – DQ31
Data inputs/outputs are multiplexed on the same pin.
*Notes: 1. When CS is set "High" at a clock transition from "Low" to "High", all inputs except CLK, CKE,
DQM0, DQM1, DQM2, and DQM3 are invalid.
2. When issuing an active, read or write command, the bank is selected by BA0 and BA1.
BA0
BA1
Active, read or write
0
0
Bank A
1
0
Bank B
0
1
Bank C
1
1
Bank D
3. The auto precharge function is enabled or disabled by the A10/AP input when the read or
write command is issued.
A10/AP
BA0
BA1
0
0
0
After the end of burst, bank A holds the active status.
Operation
1
0
0
After the end of burst, bank A is precharged automatically.
0
1
0
After the end of burst, bank B holds the active status.
1
1
0
After the end of burst, bank B is precharged automatically.
0
0
1
After the end of burst, bank C holds the active status.
1
0
1
After the end of burst, bank C is precharged automatically.
0
1
1
After the end of burst, bank D holds the active status.
1
1
1
After the end of burst, bank D is precharged automatically.
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FEDS82V48540-01
OKI Semiconductor
MS82V48540
4. When issuing a precharge command, the bank to be precharged is selected by the A10/AP,
BA0 and BA1 inputs.
A10/AP
BA0
BA1
0
0
0
Bank A is precharged.
Operation
0
1
0
Bank B is precharged.
0
0
1
Bank C is precharged.
0
1
1
Bank D is precharged.
1
×
×
All banks are precharged.
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FEDS82V48540-01
OKI Semiconductor
MS82V48540
COMMAND OPERATION
Mode Register Set Command (CS, RAS, CAS, WE = “Low”)
The MS82V48540 has the mode register that defines the operation mode “CAS Latency, Burst Length, Burst
Sequence”. The Mode Register Set command should be executed just after the MS82V48540 is powered on.
Before entering this command, all banks must be precharged. Next command can be issued after tRSC.
Auto Refresh Command (CS, RAS, CAS = “Low”, WE = “High”)
The Auto Refresh command performs refresh automatically by the address counter. The refresh operation must be
performed 3,072 times within 64 ms and the next command can be issued after tRC from last Auto Refresh
command. Before entering this command, all banks must be precharged.
Self Refresh Entry/Exit Command (CS, RAS, CAS, CKE = “Low”, WE = “High”)
The self refresh operation continues after the Self Refresh Entry command is entered, with CKE level left “low”.
This operation terminates by making CKE level “high”. The self refresh operation is performed automatically by
the internal address counter on the MS82V48540 chip.
In self refresh mode, no external refresh control is required. Before entering self refresh mode, all banks must be
precharged. Next command can be issued after tRC.
Single Bank Precharge Command (CS, RAS, WE, A10/AP = “Low”, CAS = “High”)
The Single Bank Precharge command triggers bank precharge operation. Precharge bank is selected by BA0 and
BA1.
All Banks Precharge Command (CS, RAS, WE = “Low”, CAS, A10/AP = “High”)
The All Bank Precharge command triggers precharge of all banks.
If this command is executed during special bank active mode, the special bank active mode is terminated.
Bank Active Command (CS, RAS = “Low”, CAS, WE = ”High”)
The Bank Active command activates the bank selected by BA0 and BA1. The Bank Active command corresponds
to conventional DRAM's RAS falling operation. Row addresses “A0 – A10, BA0 and BA1” are strobed.
Write Command (CS, CAS, WE, A10/AP = “Low”, RAS = “High”)
The Write command is required to begin burst write operation. Then burst access initial bit column address is
strobed.
Write with Auto Precharge Command (CS, CAS, WE = “Low”, RAS, A10/AP = “High”)
The Write with Auto Precharge command is required to begin burst write operation with automatic precharge after
the burst write. Any command that interrupts this operation cannot be issued.
Read Command (CS, CAS, A10/AP = “Low”, RAS, WE = “High”)
The Read command is required to begin burst read operation. Then burst access initial bit column address is
strobed.
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FEDS82V48540-01
OKI Semiconductor
MS82V48540
Read with Auto Prechaege Command (CS, CAS = “Low”, RAS, WE, A10/AP = “High”)
The Read with Auto Precharge command is required to begin burst read operation with auto precharge after the
burst read. Any command that interrupts this operation cannot be issued.
No Operation Command (CS = “Low”, RAS, CAS, WE = “High”)
The No Operation command does not trigger any operation.
Device Deselect Command (CS = “High”)
The Device Deselect command disables the RAS, CAS, WE and Address input. This command does not trigger
any operation.
Data Write/Output Enable Command (DQMi = “Low”)
The Data Write/Output Enable command enables DQ0 - DQ31 in read or write.
The each DQM0, 1, 2 and 3 corresponds to DQ0 - DQ7, DQ8 - DQ15, DQ16 - DQ23 and DQ24 - DQ31
respectively.
Data Mask/Output Disable Command (DQMi = “High”)
The Data Mask/Output Disable command disables DQ0 - DQ31 in read or write. In read cycle output buffers are
disabled after 2 clocks . In write cycle input buffers are disabled at the same clock. The each DQM0, 1, 2 and 3
corresponds to DQ0 - DQ7, DQ8 - DQ15, DQ16 - DQ23 and DQ24 - DQ31
respectively.
Burst Stop Command (CS, WE = “Low”, RAS, CAS = “High”)
The Burst Stop command stops burst access. After the Burst Stop command is entered, the output buffer goes into
high impedance state.
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FEDS82V48540-01
OKI Semiconductor
MS82V48540
SPECIAL READ/WRITE OPERATION
The special read or write operation is activated by executing the Read or Write command after selecting the special
page mode with the Mode Register command.
The automatic bank switching and automatic row address increment operations are activated by executing the
Bank Active command during Special Page mode, and the serial access starts from the address fetched with the
Read or Write command. The burst operation starts from the start address toward the column. When the last
column address is reached, the bank is automatically switched and the row address is also automatically
incremented and the serial access continues from the start column address. The automatic bank switching and
automatic row address increment operations continue until the All Bank Precharge command is executed each time
the last column address is reached.
Since the bank switching and row address increment are automatically made during the special read or write
operation, the row address proceeds as shown in the following figure.
0
1535
256
1535
256
0
Bank B
BA0 = “H”, BA1 = “L”
0
3073 3075 3077 3079
Start
address
6143
Bank A
BA0 = “L”, BA1 = “L”
Row
6144
1535
256
0
Bank C
BA0 = “L”, BA1 = “H”
Column
➀ ➂ ➄ ➆
0
3174 3076 3078 3080
1535
256
0
Operation is ended by input of
All Bank Precharge command.
Bank D
BA0 = “H”, BA1 = “H”
0
3071
➁ ➃ ➅ ➇
0
3072
Note) The circled numbers indicate the orders of row address increment.
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FEDS82V48540-01
OKI Semiconductor
MS82V48540
TRUTH TABLE
Command Truth Table
Address
CS
RAS
CAS
WE
BA0, 1
A10/AP
A9 – A0
Device Deselect
H
×
×
×
×
×
×
No Operation
L
H
H
H
×
×
×
Mode Register Set
L
L
L
L
Auto Refresh
L
L
L
H
×
Bank Activate
L
L
H
H
BA
Read
L
H
L
H
BA
L
CA (A7 – A0)
Read with Auto Precharge
L
H
L
H
BA
H
CA (A7 – A0)
Function
OP. CODE
×
×
RA
Write
L
H
L
L
BA
L
CA (A7 – A0)
Write with Auto Precharge
L
H
L
L
BA
H
CA (A7 – A0)
Precharge Select Bank
L
L
H
L
BA
L
×
Precharge All Banks
L
L
H
L
×
H
×
Burst Stop
L
H
H
L
×
×
×
DQM Truth Table
Function
DQMi
Data Write/Output Enable
L
Data Mask/Output Disable
H
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FEDS82V48540-01
OKI Semiconductor
MS82V48540
Function Truth Table (1/3)
Note 1
Current State
Idle
Active (ACT)
CS
WE
BA
Address
H
RAS CAS
×
×
×
×
×
NOP
L
H
H
H
×
×
NOP
L
H
H
L
BA
×
ILLEGAL
2
L
H
L
×
BA
CA, A10
ILLEGAL
2
L
L
H
H
BA
L
L
L
L
L
L
L
H
L
BA
RA
Action
Row Active
Op-Code Mode Register Write
A10
NOP
4
5
L
L
L
H
×
×
Auto Refresh/Self refresh
H
×
×
×
×
×
NOP
L
H
H
×
×
×
NOP
L
H
L
H
BA
CA, A10
Read
L
H
L
L
BA
CA, A10
Write
L
L
H
H
BA
RA
ILLEGAL
L
L
H
L
BA
A10
Precharge
L
L
L
×
×
×
ILLEGAL
Active (Special
Page Mode)
H
×
×
×
×
×
NOP
L
H
H
×
×
×
NOP
(SACT)
L
H
L
H
BA
CA
Serial Read
L
H
L
L
BA
CA
Serial Write
L
L
H
H
BA
RA
ILLEGAL
Read (RD)
Write (WT)
Note
L
L
H
L
BA
A10: L
ILLEGAL
L
L
H
L
BA
A10: H
Precharge
L
L
L
×
×
×
ILLEGAL
2
H
×
×
×
×
×
NOP (Continue Row Active after Burst ends)
L
H
H
H
×
×
NOP (Continue Row Active after Burst ends)
L
H
H
L
×
×
Burst Stop → Row Active
L
H
L
H
BA
CA, A10
Term Burst, new Read
3
L
H
L
L
BA
CA, A10
Term Burst, start Write
3
L
L
H
H
BA
RA
ILLEGAL
2
L
L
H
L
BA
A10
Term Burst, execute Precharge
L
L
L
×
×
×
ILLEGAL
H
×
×
×
×
×
NOP (Continue Row Active after Burst ends)
L
H
H
H
×
×
NOP (Continue Row Active after Burst ends)
L
H
H
L
×
×
Burst Stop → Row Active
L
H
L
H
BA
CA, A10
Term Burst, start Read
3
L
H
L
L
BA
CA, A10
Term Burst, new Write
3
L
L
H
H
BA
RA
ILLEGAL
2
L
L
H
L
BA
A10
Term Burst, execute Precharge
3
L
L
L
×
×
×
ILLEGAL
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FEDS82V48540-01
OKI Semiconductor
MS82V48540
Function Truth Table (2/3)
Note 1
Current State
CS
Read with Auto
Precharge
(RAP)
H
Write with Auto
Precharge
(WAP)
RAS CAS
×
WE
BA
Address
Action
×
×
×
×
NOP (Continue Burst to End and enter Precharge)
L
H
H
H
×
×
NOP (Continue Burst to End and enter Precharge)
L
H
H
L
×
×
ILLEGAL
L
H
L
H
BA
CA, A10
ILLEGAL
L
H
L
L
BA
CA, A10
ILLEGAL
L
L
H
H
BA
RA
ILLEGAL
2
L
L
H
L
BA
A10
ILLEGAL
2
L
L
L
×
×
×
ILLEGAL
H
×
×
×
×
×
NOP (Continue Burst to End and enter Precharge)
L
H
H
H
×
×
NOP (Continue Burst to End and enter Precharge)
L
H
H
L
×
×
ILLEGAL
L
H
L
H
BA
CA, A10
ILLEGAL
L
H
L
L
BA
CA, A10
ILLEGAL
L
L
H
H
BA
RA
ILLEGAL
2
L
L
H
L
BA
A10
ILLEGAL
2
L
L
L
×
×
×
ILLEGAL
Read (Special
Page Mode)
H
×
×
×
×
×
NOP (Continue serial read)
L
H
H
H
×
×
NOP (Continue serial read)
(SRD)
L
H
H
L
×
×
ILLEGAL
L
H
L
×
BA
CA
ILLEGAL
L
L
H
H
BA
RA
ILLEGAL
L
L
H
L
BA
A10: L
ILLEGAL
L
L
H
L
BA
A10: H
Precharging
Write (Special
Page Mode)
(SWT)
Precharging
(PRE)
Note
L
L
L
×
×
×
ILLEGAL
H
×
×
×
×
×
NOP (Continue serial write)
L
H
H
H
×
×
NOP (Continue serial write)
L
H
H
L
×
×
ILLEGAL
L
H
L
×
BA
CA
ILLEGAL
L
L
H
H
BA
RA
ILLEGAL
L
L
H
L
BA
A10: L
ILLEGAL
L
L
H
L
BA
A10: H
Precharging
L
L
L
×
×
×
ILLEGAL
H
×
×
×
×
×
NOP → Idle after tRP
L
H
H
H
×
×
NOP → Idle after tRP
L
H
H
L
BA
×
ILLEGAL
2
L
H
L
×
BA
CA
ILLEGAL
2
L
L
H
H
BA
RA
ILLEGAL
2
L
L
H
L
BA
A10
NOP
4
L
L
L
×
×
×
ILLEGAL
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FEDS82V48540-01
OKI Semiconductor
MS82V48540
Function Truth Table (3/3)
Note 1
Current State
Refreshing
(REF)
CS
WE
BA
Address
H
RAS CAS
×
×
×
×
×
NOP → Idle after tRC
L
H
H
H
×
×
NOP → Idle after tRC
L
H
H
L
BA
×
ILLEGAL
L
H
L
×
BA
CA
ILLEGAL
Action
L
L
H
H
BA
RA
ILLEGAL
L
L
H
L
BA
A10
ILLEGAL
L
L
L
×
×
×
ILLEGAL
ABBREVIATIONS
BA = Bank Address
NOP = No Operation command
RA = Row Address
Note
CA = Column Address
Notes: 1. All inputs are enabled when CKE is set high for at least 1 cycle prior to the inputs.
2. Illegal to bank in specified state, but may be legal in some cases depending on the state of
bank selection.
3. To avoid bus contention, satisfy tCCD and tDPL.
4. NOP to bank precharging or in idle state. Precharges activated bank by BA or A10/AP.
5. Illegal if any bank is not idle.
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OKI Semiconductor
MS82V48540
Function Truth Table for CKE
Current State (n)
Self Refresh
(SREF)
Power Down (PD)
All Banks Idle
(ABI)
Any State Other
than Listed Above
Note:
CKEn-1 CKEn CS
RAS CAS
WE
Address
Action
H
×
×
×
×
×
×
INVALID
L
H
H
×
×
×
×
Exit Self Refresh → ABI
L
H
L
H
H
H
×
Exit Self Refresh → ABI
L
H
L
H
H
L
×
ILLEGAL
L
H
L
H
L
×
×
ILLEGAL
L
H
L
L
×
×
×
ILLEGAL
L
L
×
×
×
×
×
NOP (Maintain Self Refresh)
H
×
×
×
×
×
×
INVALID
L
H
H
×
×
×
×
Exit Self Refresh → ABI
L
H
L
H
H
H
×
Exit Self Refresh → ABI
L
H
L
H
H
L
×
ILLEGAL
L
H
L
H
L
×
×
ILLEGAL
L
H
L
L
×
×
×
ILLEGAL
Note
L
L
×
×
×
×
×
NOP (Continue power down mode)
H
H
×
×
×
×
×
Refer to Truth Table
6
H
L
H
×
×
×
×
Enter Power Down
6
H
L
L
H
H
H
×
Enter Power Down
6
H
L
L
H
H
L
×
ILLEGAL
6
H
L
L
H
L
×
×
ILLEGAL
6
H
L
L
L
H
L
×
ILLEGAL
6
H
L
L
L
L
H
×
Enter Self Refresh
6
H
L
L
L
L
L
×
ILLEGAL
6
L
L
×
×
×
×
×
NOP
6
H
H
×
×
×
×
×
Refer to Truth Table
H
L
×
×
×
×
×
Begin Clock Suspend Next Cycle
L
H
×
×
×
×
×
Enable Clock of Next Cycle
L
L
×
×
×
×
×
Continue Clock Suspension
6. Power-down and self refresh can be entered only when all the banks are in an idle state.
13/44
FEDS82V48540-01
OKI Semiconductor
MS82V48540
Mode Set Address Keys
CAS Latency
Operation Code
A8 A7
0
TM
A6 A5 A4
CL
A3
BT
BT = 0
BT = 1
Reserved
0
Sequential
0
0
0
1
Reserved
0
1
Reserved
1
Interleave
0
0
1
2
Reserved
1
0
2
0
1
0
4
4
1
3
0
1
1
8
8
Mode Setting
0
0
1
0
0
1
1
Vender
Use
Only
0
1
0
1
Write Burst Length
Burst Length
0
0
*Note 1
Burst Type
0
A2 A1 A0
1
0
0
Reserved
1
0
0
Reserved
Reserved
A9
Length
1
0
1
Reserved
1
0
1
Reserved
Reserved
0
Burst
1
1
0
Reserved
1
1
0
Special page
Reserved
1
Single Bit
1
1
1
Reserved
1
1
1
Full Page
Reserved
*Note 1: To select Special Page mode, set A9 to “L”.
The write burst length during Special Page mode is set only for Burst.
POWER ON SEQUENCE
1. With CKE = "H", DQM = "H" and the other inputs in NOP state, turn on the power supply and
start the system clock.
2. After the VCC voltage has reached the specified level, pause for 200 µs or more with the input
kept in NOP state.
3. Issue the precharge all bank command.
4. Apply an Auto-refresh 8 or more times.
5. Enter the mode register command.
14/44
FEDS82V48540-01
OKI Semiconductor
MS82V48540
Burst Length and Sequence
BL = 2
Starting Address
(column address A0, binary)
Sequential Type
Interleave Type
0
0, 1
Not supported
1
1, 0
Not supported
Starting Address
(column address A1, A0, binary)
Sequential Type
Interleave Type
00
0, 1, 2, 3
0, 1, 2, 3
01
1, 2, 3, 0
1, 0, 3, 2
10
2, 3, 0, 1
2, 3, 0, 1
11
3, 0, 1, 2
3, 2, 1, 0
Starting Address
(column address A2 - A0, binary)
Sequential Type
Interleave Type
000
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
001
1, 2, 3, 4, 5, 6, 7, 0
1, 0, 3, 2, 5, 4, 7, 6
010
2, 3, 4, 5, 6, 7, 0, 1
2, 3, 0, 1, 6, 7, 4, 5
011
3, 4, 5, 6, 7, 0, 1, 2
3, 2, 1, 0, 7, 6, 5, 4
100
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
101
5, 6, 7, 0, 1, 2, 3, 4
5, 4, 7, 6, 1, 0, 3, 2
110
6, 7, 0, 1, 2, 3, 4, 5
6, 7, 4, 5, 2, 3, 0, 1
111
7, 0, 1, 2, 3, 4, 5, 6
7, 6, 5, 4, 3, 2, 1, 0
BL = 4
BL = 8
BL = Special, Full : Sequential only
15/44
FEDS82V48540-01
OKI Semiconductor
MS82V48540
READ/WRITE COMMAND INTERVAL
Read to Read Command Interval
BL = 4, CL = 2
0
1
2
3
4
5
6
7
8
CLK
RD-A RD-B
QA1
DQ
QB1
QB2
QB3
Hi-Z
QB4
1cycle
Write to Write Command Interval
BL = 4, CL = 2
0
1
2
3
4
5
6
7
8
CLK
WT-A WT-B
DB1
DA1
DQ
DB3
DB2
Hi-Z
DB4
1cycle
Write to Read Command Interval
BL = 4
0
1
2
3
4
5
6
7
8
CLK
CL = 2
DQ
CL = 3
DQ
WT-A RD-B
DA1
Hi-Z
QB1
QB2
QB3
QB4
QB1
QB2
QB3
WT-A RD-B
DA1
Hi-Z
QB4
1cycle
16/44
FEDS82V48540-01
OKI Semiconductor
MS82V48540
Read to Write Command Interval
BL = 4, CL = 2, 3
0
1
2
3
4
5
6
5
6
7
8
CLK
CL = 2, 3
RD-A WT-B
DQM
DQ
Hi-Z
DB1
DB2
DB3
DB4
1cycle
BL = 4, CL = 2, 3
0
1
2
3
4
7
8
CLK
CL = 2
WT-B
RD-A
DQM
DQ
CL = 3
Hi-Z
QA1
QA2
QA3
DB1 DB2
Hi-Z is
necessary
WT-B
QA1
QA2
RD-A
DQM
DQ
Hi-Z
DB1
DB2
Hi-Z is
necessary
17/44
FEDS82V48540-01
OKI Semiconductor
MS82V48540
BURST TERMINATION
Burst Read Termination by Precharging in READ Cycle
BL = 2, 4, 8, Full
0
1
2
3
4
5
6
7
8
CLK
tRP
RD
CL = 2
PRE
Q1
DQ
Q2
Q3
ACT
Hi-Z
Q4
tRP
RD
CL = 3
PRE
Q1
DQ
Q2
ACT
Q3
Hi-Z
Q4
Burst Read Termination by Precharging in WRITE Cycle
BL = 2, 4, 8, Full
0
1
2
3
4
5
6
7
8
CLK
tRP
CL = 2
WT
DQ
D1
PRE
D2
D3
D4
D5
ACT
Hi-Z
tRP
CL = 3
WT
DQ
D1
PRE
D2
D3
D4
D5
ACT
Hi-Z
Note: D5 data will not be written
18/44
FEDS82V48540-01
OKI Semiconductor
MS82V48540
Read Burst Stop Command
BL = 2, 4, 8, Full
0
1
2
3
4
5
6
7
8
CLK
RD
BST
CL = 2
DQ
Q1
CL = 3
DQ
Q2
Q3
Q4
Q1
Q2
Q3
Hi-Z
Hi-Z
Q4
Write Burst Stop Command
BL = 2, 4, 8, Full
0
1
2
3
4
5
6
7
8
CLK
WT
CL = 2, 3
DQ
D1
BST
D2
D3
D4
Hi-Z
19/44
FEDS82V48540-01
OKI Semiconductor
MS82V48540
AUTO PRECHARGE
Read with Auto Precharge
BL = 4
0
1
2
3
4
5
6
7
8
CLK
RAP
CL = 2
Auto precharge starts
Q1
DQ
RAP
CL = 3
Q2
Q3
Hi-Z
Q4
Auto precharge starts
Q1
DQ
Q2
Q3
Hi-Z
Q4
(tRAS is satisfied)
Write with Auto Precharge
BL = 4
0
1
2
3
4
5
6
7
8
CLK
CL = 2
DQ
CL = 3
DQ
WAP
D1
Auto precharge starts
D2
D3
Hi-Z
Auto precharge starts
WAP
D1
D4
D2
D3
D4
Hi-Z
(tRAS is satisfied)
20/44
FEDS82V48540-01
OKI Semiconductor
MS82V48540
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Symbol
Voltage on Power Supply Pin Relative to GND
Rating
Unit
VCC
–0.5 to 4.6
V
VIN, VOUT
–0.5 to VCC + 0.5 ≤ 4.6
V
Short Circuit Output Current
IOS
50
mA
Power Dissipation
PD*
1
W
Operating Temperature
Topr
0 to 70
°C
Storage Temperature
Tstg
–55 to 150
°C
Voltage on Input Pin Relative to GND
*: Ta = 25 °C
Recommended Operating Conditions
(Ta = 0 to 70°C)
Parameter
Power Supply Voltage
Symbol
Min.
Typ.
Max.
Unit
VCC
3.0
3.3
3.6
V
VSS
0
0
0
V
Input High Voltage
VIH
2.0
—
VCC + 0.3
V
Input Low Voltage
VIL
–0.3
—
0.8
V
Capacitance
(VCC = 3.3 V ±0.3 V, Ta = 25°C, f = 1 MHz)
Symbol
Min.
Max.
Unit
Input Capacitance (A0 – A10, BA0, BA1)
Parameter
CIN1
—
5
pF
Input Capacitance
(CLK, CKE, CS, RAS, CAS, WE DQM 0 – DQM3)
CIN2
—
5
pF
Output Capacitance
(DQ0 – DQ31)
COUT
—
6
pF
21/44
FEDS82V48540-01
OKI Semiconductor
MS82V48540
DC Characteristics
Parameter
Symbol
Test Condition
MS82V48540-7 MS82V48540-8
CKE
Other
Min.
Max.
Min.
Max.
2.4
—
2.4
—
Output High Voltage
VOH
—
IOH= –2.0 mA
Output Low Voltage
Unit
V
VOL
—
IOL= 2.0 mA
—
0.4
—
0.4
V
Input Leakage Current
ILI
—
—
–10
10
–10
10
µA
Output Leakage Current
ILO
—
—
–10
10
–10
10
µA
Operating Current
(1 Bank)
ICC1
tCK = tCK min.
CKE ≥ VIH tRC = tRC min.
No Burst
—
200
—
180
mA
ICC2P
CKE ≤ VIL tCK = tCK min.
—
2
—
2
mA
ICC2PS
CKE ≤ VIL
CLK ≤ VIL
tCK = ∞
—
2
—
2
mA
ICC2N
CKE ≥ VIH
CS ≥ VIH
tCK = tCK min.
—
40
—
40
mA
CLK ≤ VIL
tCK = ∞
—
20
—
20
mA
Precharge Standby Current
in Power Down Mode
Precharge Standby Current
in Non Power Down Mode
Active Standby Current in
Power Down Mode
Active Standby Current in
Non Power Down Mode
ICC2NS CKE ≥ VIH
ICC3P
CKE ≤ VIL tCK = tCK min.
—
3
—
3
mA
—
3
—
3
mA
ICC3PS
CKE ≤ VIL
CLK ≤ VIL
tCK = ∞
ICC3N
CKE ≥ VIH
CS ≥ VIH
tCK = tCK min.
—
50
—
50
mA
CLK ≤ VIL
tCK = ∞
—
30
—
30
mA
ICC3NS CKE ≥ VIH
Operating Current
(Burst Mode)
ICC4
CKE ≥ VIH tCK = tCK min.
—
240
—
200
mA
Refresh Current
ICC5
CKE ≥ VIH tRC ≥ tRC min.
—
200
—
180
mA
Self Refresh Current
ICC6
CKE ≤ 0.2V
—
3
—
3
mA
—
Note
1, 2
1, 2
Notes 1. The maximum value of power supply current is obtained with the output open.
2. Address and data are changed only one time during one cycle.
22/44
FEDS82V48540-01
OKI Semiconductor
MS82V48540
AC Characteristics
Test conditions
• AC measurements assume tT = 1 ns.
• Reference level for measuring timing of input signals is 1.4 V. Transition times are measured between VIH and
VIL.
• If tT is longer than 1 ns, reference level for measuring timing of input signals is VIH (MIN.) and VIL (MAX).
• An access time is measured at 1.4 V.
• Input levels at the AC testing are 2.4 V/0.4 V.
tCK
tCH
tCL
2.4 V
CLK 1.4 V
0.4 V
tSetup tHold
2.4 V
Input 1.4 V
0.4 V
tAC
tOH
Output
1.4 V
1.4 V
23/44
FEDS82V48540-01
OKI Semiconductor
MS82V48540
Synchronous Characteristics
Parameter
Clock Cycle Time
Access Time from CLK
Symbol
MS82V48540-7
MS82V48540-8
Min.
Max.
Min.
Max.
Unit
Note
CAS Latency = 3
tCK3
7
—
8
—
CAS Latency = 2
tCK2
12
—
12
—
ns
CAS Latency = 3
tAC3
—
5
—
6
ns
1
CAS Latency = 2
tAC2
—
8
—
8
ns
1
ns
CLK High Level Width
tCH
2.5
—
3
—
ns
CLK Low Level Width
tCL
2.5
—
3
—
ns
Data-out Hold Time
tOH
2
—
2
—
ns
Data-out Low-impedance Time
tLZ
0
—
0
—
ns
Data-out High-impedance Time
tHZ
—
5
—
6
ns
Data-in Setup Time
tDS
2
—
2
—
ns
Data-in Hold Time
tDH
1
—
1
—
ns
Address Setup Time
tAS
2
—
2
—
ns
Address Hold Time
tAH
1
—
1
—
ns
CKE Setup Time
tCKS
2
—
2
—
ns
CKE Hold Time
tCKH
1
—
1
—
ns
Command (CS, RAS, CAS, WE, DQM) Setup Time
tCMS
2
—
2
—
ns
Command (CS, RAS, CAS, WE, DQM) Hold Time
tCMH
1
—
1
—
ns
Note 1. Output load.
1.4 V
Z = 50Ω
50Ω
Output
30 pF
24/44
FEDS82V48540-01
OKI Semiconductor
MS82V48540
Asynchronous Characteristics
Parameter
MS82V48540-7
MS82V48540-8
Min.
Max.
Min.
Max.
tRC
63
—
72
—
ACT to PRE Command Period
tRAS
42
120k
48
120k
ns
SACT to PRE Command Period
tRASS
6
—
6
—
CLK
tRP
21
—
24
—
ns
REF to REF/ACT/SACT Command Period
PRE to ACT Command Period
Symbol
Unit
ns
PRE-ALL (Special Page) to SACT Command Period
tRPS
9
—
9
—
CLK
Delay Time ACT/SACT to READ/WRITE Command
tRCD
21
—
24
—
ns
ACT (0) to ACT (1) Command Period
tRRD
14
—
16
—
ns
READ/WRITE to READ/WRITE Command Period
tCCD
7
—
8
—
ns
Data-in to PRE Command Period
tDPL
7
—
8
—
ns
Data Output to WRITE Command Input Time
tOWD
14
—
16
—
ns
Mode Register Set Cycle Time
tRSC
14
—
16
—
ns
tT
1
30
1
30
ns
tREF
—
64
—
64
ms
Transition Time
Refresh Time
Note
25/44
FEDS82V48540-01
OKI Semiconductor
MS82V48540
TIMING WAVEFORM
READ/WRITE CYCLE (BL = 2, CL = 3)
0
CLK
1
2
tCK
tCKS tCH
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
tCKH
tCL
CKE
tCMS tCMH
CS
RAS
CAS
WE
tAS tAH
BA0
BA1
A10
/AP
RAa
ADD
RAa
RDa
CAa
tCMS
DQM
0-3
DQ
CAb
tAC tOH
Hi-Z
tHZ
tDS tDH
DAb1 DAb2
QAa1 QAa2
tRCD
RDa
tCMH
tLZ
tOWD
tDPL
tRAS
tRP
tRC
ACT-A
RD-A
WT-A
PRE-A
ACT-D
26/44
FEDS82V48540-01
OKI Semiconductor
MS82V48540
Special READ CYCLE (BL = Special Page, CL = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
CKE
H
CS
RAS
CAS
WE
BA0
BA1
A10
/AP
RAa
ADD
RAa
DQM
0-3
DQ
RDa
CAa
RDa
L
Hi-Z
QAa1 QAa2 QAa3 QAa4
tRCD
SACT-A
Qn-1
Qn Qn+1 Qn+2
tRASS
SRD-A
Special Read Start
tRPS
PRE-ALL
SACT-D
27/44
FEDS82V48540-01
OKI Semiconductor
MS82V48540
Special WRITE CYCLE (BL = Special Page, CL = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
CKE
H
CS
RAS
CAS
WE
BA0
BA1
A10
/AP
RAa
ADD
RAa
DQM
0-3
DQ
RBa
CAa
RBa
L
Hi-Z
DAa1 DAa2 DAa3 DAa4 DAa5
tRCD
SACT-A
tRASS
SWT-A
Special Write Start
Dn-2 Dn-1 Dn
tDPL
PRE-ALL
tRPS
SACT-B
28/44
FEDS82V48540-01
OKI Semiconductor
MS82V48540
Mode Register Set
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
CKE
H
CS
RAS
CAS
WE
BA
A10
/AP
ADD
DQM
0-3
DQ
Hi-Z
MRA
PRE-ALL
tRP
ACT
tRSC
29/44
FEDS82V48540-01
OKI Semiconductor
MS82V48540
Auto Reflesh
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
CKE
H
CS
RAS
CAS
WE
BA
A10
/AP
ADD
DQM
0-3
L
DQ
Hi-Z
REF
PRE-ALL
tRP
REF
tRC
ACT
tRC
30/44
FEDS82V48540-01
OKI Semiconductor
MS82V48540
Self Reflesh (Entry and Exit)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
CKE
H
CS
RAS
CAS
WE
BA
A10
/AP
ADD
DQM
0-3
DQ
L
Hi-Z
PRE-ALL
tRP
SELF
Entry
SELF
Exit
tRC
SELF
Entry
SELF
Exit
ACT
tRC
31/44
FEDS82V48540-01
OKI Semiconductor
MS82V48540
Burst Termination by Precharging (BL = 8, CL = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
CKE
H
CS
RAS
CAS
WE
BA0
BA1
A10
/AP
RAa
ADD
RAa
DQM
0-3
DQ
RAb
CAa
RAb
CAb
L
Hi-Z
ACT-A
DAa1 DAa2
WT-A
QAb1 QAb2 QAb3 QAb4
PRE-A
ACT-A
PRE Command
Termination
RD-A
PRE-A
PRE Command
Termination
32/44
FEDS82V48540-01
OKI Semiconductor
MS82V48540
Auto Precharging (BL = 4, CL = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
CKE
H
CS
RAS
CAS
WE
BA0
BA1
A10
/AP
RAa
RBa
ADD
RAa
CAa RBa
DQM
0-3
DQ
CBa
L
Hi-Z
ACT-A
QAa1 QAa2 QAa3 QAa4
RAP-A
ACT-B
DBa1 DBa2 DBa3 DBa4
WAP-B
AP-A
AP-B
33/44
FEDS82V48540-01
OKI Semiconductor
MS82V48540
Power Down Mode and Clock Suspension (BL = 4, CL = 2)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
tCKS
CKE
CS
RAS
CAS
WE
BA0
BA1
A10
/AP
RAa
ADD
RAa
DQM
0-3
DQ
CAa
L
Hi-Z
QAa1 QAa2
ACT-A
PD
Entry
RD-A
PD
Exit
ACTIVE STANDBY
QAa3
QAa4
PRE-A
Clock
Mask Start
Clock
Mask End
PD
Entry
PD
Exit
PRECHARGE STANDBY
34/44
FEDS82V48540-01
OKI Semiconductor
MS82V48540
CLOCK Suspend Exit & Power Down Exit
1) Clock Suspend (= Active Power Down) Exit
2) Power Down (= Precharge Power Down) Exit
CLK
CLK
CKE
CKE
Note 3
Internal
CLK
Command
tCKS
Internal
CLK
Note 1
RD
tCKS
Note 2
Command
NOP ACT
Notes: 1. Active power down: one or both bank active state.
2. Precharge power down: both bank precharge state.
3. NOP should be issued. And new command can be issued after 1 Clock.
35/44
FEDS82V48540-01
OKI Semiconductor
MS82V48540
Byte Read/Write Operation (by DQM) (BL = 4, CL = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
CKE
H
CS
RAS
CAS
WE
BA0
BA1
A10
/AP
RBa
ADD
RBa
CBa
CBb
DQM0
DQM1
DQM2
DQM3
DQ
0-7
QBa1 QBa2 QBa3
DQ
8 - 15
DBb2 DBb3 DBb4
QBa2 QBa3 QBa4
DQ
16 - 23
QBa1
DQ
24 - 31
QBa1 QBa2
ACT-B
RD-B
QBa3 QBa4
QBa4
DBb1
DBb3 DBb4
DBb1 DBb2
DBb4
DBb1 DBb2 DBb3
WT-B
Byte of
Byte of
Byte of
Byte of
DQ8-15 DQ24-31
DQ0-7 DQ16-23
not Read not Read
not Write not Write
Byte of
Byte of
Byte of
Byte of
DQ16-23
DQ0-7
DQ8-15 DQ24-31
not Read not Read
not Write not Write
36/44
FEDS82V48540-01
OKI Semiconductor
MS82V48540
Burst Read and Single Write (BL = 4, CL = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
CKE
H
CS
RAS
CAS
WE
BA0
BA1
A10
/AP
RAa
ADD
RAa
DQM
0-3
L
DQ
Hi-Z
ACT-B
CAa
QAa1 QAa2 QAa3 QAa4
RD-B
CBb
CBb
DBb
DBc
Single
WT-B
Single
WT-B
PRE-B
37/44
FEDS82V48540-01
OKI Semiconductor
MS82V48540
Random Column Read (Continuous Read of Same Bank) (BL = 4, CL = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
CKE
H
CS
RAS
CAS
WE
BA0
BA1
A10
/AP
RAa
ADD
RAa
DQM
0-3
RAi
CAa
CAb
CAc
RAi
L
DQ
QAa1 QAa2 QAa3 QAa4 QAb1 QAb2 QAc1 QAc2 QAc3 QAc4
ACT-A
RD-A
RD-A
RD-A
PRE-A
ACT-A
38/44
FEDS82V48540-01
OKI Semiconductor
MS82V48540
Random Column Write (Continuous Write of Same Bank) (BL = 4, CL = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
CKE
H
CS
RAS
CAS
WE
BA0
BA1
A10
/AP
RBa
ADD
RBa
DQM
0-3
RBi
CBa
CBb
CBc
RBi
L
DQ
DBa1 DBa2 DBa3 DBa4 DBb1 DBb2 DBc1 DBc2 DBc3 DBc4
ACT-B
WT-B
WT-B
WT-B
PRE-B
ACT-B
39/44
FEDS82V48540-01
OKI Semiconductor
MS82V48540
Interleaved Column Read (BL = 4, CL = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
CKE
H
CS
RAS
CAS
WE
BA0
BA1
A10
/AP
RAa
RBa
ADD
RAa
CAa RBa
DQM
0-3
CBa
CBb
CAb
L
DQ
QAa1 QAa2 QAa3 QAa4 QBa1 QBa2 QBb1 QBc2 QAb1 QAb2 QAb3 QAb4
ACT-A
RD-A ACT-B
RD-B
RD-B
RD-A
PRE-B
PRE-A
tRCD
tRRD
40/44
FEDS82V48540-01
OKI Semiconductor
MS82V48540
Interleaved Column Write (BL = 4, CL = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
CKE
H
CS
RAS
CAS
WE
BA0
BA1
A10
/AP
RCa
RDa
ADD
RCa
CCa RDa
DQM
0-3
CDa
CDb
CCb
L
DQ
DCa1 DCa2 DCa3 DCa4 DDa1 DDa2 DDb1 DDb2 DCb1 DCb2 DCb3 DCb4
ACT-C
WT-C ACT-D
WT-D
WT-D
WT-C
PRE-D
PRE-C
tRCD
tRRD
41/44
FEDS82V48540-01
OKI Semiconductor
MS82V48540
PACKAGE DIMENSIONS
(Unit: mm)
TSOP(2)86-P-400-0.50-K
Mirror finish
5
Package material
Lead frame material
Pin treatment
Package weight (g)
Rev. No./Last Revised
Epoxy resin
42 alloy
Solder plating (≥5µm)
0.53 TYP.
1/Jul. 14, 1998
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity
absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product
name, package name, pin number, package code and desired mounting conditions (reflow method,
temperature and times).
42/44
FEDS82V48540-01
OKI Semiconductor
MS82V48540
REVISION HISTORY
Document
No.
Date
Page
Previous Current
Edition
Edition
–
–
Description
First edition
Changed the speed rank indication in
“Package” of the FEATURES Section
from “XX to “x”.
1
1
Changed the device names in the Family
column in the table of the PRODUCT
FAMILY Section.
FEDS82V48540-01
22
22
Changed the names of the family
devices in the table of the DC
Characteristics Section.
24
24
Changed the names of the family
devices in the table of the Synchronous
Characteristics Section.
25
Changed the names of the family
devices in the table of the Asynchronous
Characteristics Section.
Nov. 8, 2002
25
43/44
FEDS82V48540-01
OKI Semiconductor
MS82V48540
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements.
Before using the product, please make sure that the information being referred to is up-to-date.
2.
The outline of action and examples for application circuits described herein have been chosen as an
explanation for the standard action and performance of the product. When planning to use the product, please
ensure that the external conditions are reflected in the actual circuit, assembly, and program designs.
3.
When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.
4.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation
resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or
unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified
maximum ratings or operation outside the specified operating range.
5.
Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is
granted by us in connection with the use of the product and/or the information and drawings contained herein.
No responsibility is assumed by us for any infringement of a third party’s right which may result from the use
thereof.
6.
The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not authorized for use in any system or application that requires special
or enhanced quality and reliability characteristics nor in any system or application where the failure of such
system or application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace
equipment, nuclear power control, medical equipment, and life-support systems.
7.
Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products
and will take appropriate and necessary steps at their own expense for these.
8.
No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2002 Oki Electric Industry Co., Ltd.
44/44