Gigabit Ethernet Transceiver Chip with Dual Serial I/O and Differential PECL Clock Inputs Technical Data HDMP-1638 Transceiver Features Description • IEEE 802.3z Gigabit Ethernet compatible, Supports 1250 MBd Gigabit Ethernet • Based on X3T11 “10-Bit Specification” • Low Power Consumption • Transmitter and Receiver Functions Incorporated Onto a Single IC • 10 mm, 64-Pin Plastic Package • 5 Volt Tolerant I/Os • 10-Bit Wide Parallel TTL Compatible I/Os • Single +3.3 V Power Supply • Differential PECL Clock Inputs • Dual Serial I/O With Receive Select • 2kV ESD Protection on All Pins The HDMP-1638 transceiver is a single silicon bipolar integrated circuit packaged in a plastic QFP package. It provides a low-cost, low-power physical layer solution for 1250 MBd Gigabit Ethernet or proprietary link interfaces. It provides complete Serialize/ Deserialize (“SerDes”) for copper transmission, incorporating both the Gigabit Ethernet transmit and receive functions into a single device. Applications • 1250 MBd Gigabit Ethernet Interface • High Speed Proprietary Interface • Backplane Serialization/Bus Extender This chip is used to build a high speed interface (as shown in Figure 1) while minimizing board space, power and cost. It is compatible with the IEEE 802.3z specification. The transmitter section accepts 10-bit wide parallel TTL data and serializes this data into two high speed serial data streams. The parallel data is expected to be “8B/10B” encoded data, or equivalent. This parallel data is latched into the input register of the transmitter section on the rising edge of the 125 MHz reference clock (used as the transmit byte clock). The transmitter section’s PLL locks to this user supplied 125 MHz byte clock. This clock is then multiplied by 10, to generate the 1250 MHz serial signal clock used to generate the high speed outputs. The high speed outputs are capable of interfacing directly to copper cables for electrical transmission or to a separate fiber optic module for optical transmission. The receiver section allows for the selection of one of two serial electrical data streams at 1250 MBd and recovers the original 10-bit wide parallel data. The receiver PLL locks onto the incoming serial signal and recovers the high speed serial clock and data. The serial data is converted back into 10-bit parallel data, recognizing the 8B/10B comma character to establish byte alignment. CAUTION: As with all semiconductor IC’s, it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by electrostatic discharge (ESD). 2 The recovered parallel data is presented to the user at TTL compatible outputs. The receiver section also recovers two 62.5 MHz receiver byte clocks which are 180 degrees out of phase with each other. The parallel data is properly aligned with the rising edge of alternating clocks. For test purposes, the transceiver provides for on-chip local loopback functionality controlled through an external input pin. Additionally, the byte synchronization feature may be disabled. This may be useful in proprietary applications which use alternative methods to align the parallel data. HDMP-1638 TRANSMITTER SECTION SERIAL DATA OUT PLL PROTOCOL DEVICE PLL SERIAL DATA IN RECEIVER SECTION BYTSYNC REFCLK RXSEL ENBYTSYNC Figure 1. Typical Application Using the HDMP-1638. • TTL Parallel I/O’s • High Speed Phase Locked Loops • Parallel to Serial Converter • Serial Clock and Data Recovery • Comma Character Recognition • Byte Alignment Circuitry • Serial to Parallel Converter DATA BYTE TX[0-9] FRAME MUX OUTPUT SELECT INTERNAL LOOPBACK TXCAP0 TXCAP1 TX PLL/CLOCK GENERATOR INTERNAL TX CLOCKS INPUT SELECT RX PLL/CLOCK RECOVERY RXCAP0 RXCAP1 RBC0 RBC1 DATA BYTE RX[0-9] FRAME DEMUX AND BYTE SYNC BYTSYNC INTERNAL RX CLOCKS INPUT SAMPLER ENBYTSYNC Figure 2. HDMP-1638 Transceiver Block Diagram. ± DOUTA ± DOUTB LOOPEN ± REFCLK OUTPUT DRIVER The HDMP-1638 was designed to transmit and receive 10-bit wide parallel data over highspeed serial lines. The parallel data applied to the transmitter is expected to be encoded per the Gigabit Ethernet specification, which uses an 8B/10B encoding scheme with special reserve characters for link management purposes. In order to accomplish this task, the HDMP-1638 incorporates the following: INPUT LATCH HDMP-1638 Block Diagram RXSEL ± DINA ± DINB 3 Input Latch Output Select The transmitter accepts 10-bit wide TTL parallel data at inputs TX[0..9]. REFCLK (from this point forward, REFCLK is defined as the difference between the userprovided PECL reference clocks, ± REFCLK) is used as the transmit byte clock. The TX[0..9] and REFCLK signals must be properly aligned, as shown in Figure 3. The OUTPUT SELECT block provides for an optional internal loopback of the high speed serial signal for testing purposes. TX PLL/Clock Generator The transmitter Phase Locked Loop and Clock Generator (TX PLL/CLOCK GENERATOR) block is responsible for generating all internal clocks needed by the transmitter section to perform its functions. These clocks are based on the supplied reference byte clock. REFCLK is used as both the frequency reference clock for the PLL and the transmit byte clock for the incoming data latches. It is expected to be 125 MHz and properly aligned to the incoming parallel data (see Figure 3). This clock is then multiplied by 10 to generate the 1250 MHz clock necessary for the high speed serial outputs. Frame MUX The FRAME MUX accepts the 10-bit wide parallel data from the INPUT LATCH. Using internally generated high speed clocks, this parallel data is multiplexed into the 1250 MBd serial data stream. The data bits are transmitted sequentially, from the least significant bit (TX[0]) to the most significant bit (TX[9]). In normal operation, LOOPEN is set low and the serial data stream is placed at both ± DOUTA and B. When wrap-mode is activated by setting LOOPEN high, the ± DOUTA, B pins are held static at logic 1 and the serial output signal is internally wrapped to the INPUT SELECT box of the receiver section. Input Select The INPUT SELECT block determines whether one of two pairs of signals ± DINA, B or the internal loop-back serial signal is used. In normal operation, LOOPEN is set low and the serial data is accepted at ± DINA or B. RXSEL selects if serial data at ± DINA or B will be parallelized. If RXSEL is low then ± DINA will be selected. If RXSEL is high then ± DINB will be selected. When LOOPEN is set high, the high speed serial signal is internally looped-back from the transmitter section to the receiver section. This feature allows for loop back testing exclusive of the transmission medium. RX PLL/Clock Recovery The RX PLL/CLOCK RECOVERY block is responsible for frequency and phase locking onto the incoming serial data stream and recovering the bit and byte clocks. An automatic locking feature allows the Rx PLL to lock onto the input data stream without external PLL training controls. It does this by continually frequency locking onto the 125 MHz reference clock, and then phase locking onto the input data stream. An internal signal detection circuit monitors the presence of the input, and invokes the phase detection as the data stream appears. Once bit locked, the receiver generates the high speed sampling clock at 1250 MHz for the input sampler, and recovers the two 62.5 MHz receiver byte clocks (RBC1/RBC0). These clocks are 180 degrees out of phase with each other, and are alternately used to clock the 10-bit parallel output data. Input Sampler The INPUT SAMPLER is responsible for converting the serial input signal into a retimed serial bit stream. In order to accomplish this, it uses the high speed serial clock recovered from the RX PLL/CLOCK RECOVERY block. This serial bit stream is sent to the FRAME DEMUX and BYTE SYNC block. 4 Frame Demux and Byte Sync The FRAME DEMUX AND BYTE SYNC block is responsible for restoring the 10-bit parallel data from the high speed serial bit stream. This block is also responsible for recognizing the comma character (or a K28.5 character) of positive disparity (0011111xxx). When recognized, the FRAME DEMUX AND BYTE SYNC block works with the RX PLL/CLOCK RECOVERY block to properly align the receive byte clocks to the parallel data. When a comma character is detected and realignment of the receiver byte clocks (RBC1/RBC0) is necessary, these clocks are stretched, not slivered, to the next possible correct alignment position. These clocks will be fully aligned by the start of the second 2-byte ordered set. The second comma character received shall be aligned with the rising edge of RBC1. As per the 8B/10B encoding scheme, comma characters must not be transmitted in consecutive bytes to allow the receiver byte clocks to maintain their proper recovered frequencies. Output Drivers The OUTPUT DRIVERS present the 10-bit parallel recovered data byte properly aligned to the receive byte clocks (RBC1/RBC0), as shown in Figure 5. These output data buffers provide TTL compatible signals. Signal Detect The SIGNAL DETECT block examines the differential amplitude of the inputs ± DINB. When this input signal is too small, it outputs a logic 0 at SIG_DET (refer to SIG_DET pin definition for detection thresholds). When the signal at ± DINB is of a valid amplitude, SIG_DET is set to logic 1. HDMP-1638 (Transmitter Section) Timing Characteristics TA = 0 °C to +70 °C, VCC = 3.15 V to 3.45 V Symbol Parameter Units Min. Typ. t setup Setup Time nsec 1.5 thold Hold Time nsec 1.0 Transmitter Latency nsec 3.5 bits 4.4 t _txlat[1] Max. Note: 1. The transmitter latency, as shown in Figure 4, is defined as the time between the latching in of the parallel data word (as triggered by the rising edge of the transmit byte clock, REFCLK) and the transmission of the first serial bit of that parallel word at either output pair (defined by the rising edge of the first bit transmitted). 5 0.0 V AC REFCLK 2.0 V TX[0]-TX[9] DATA DATA DATA DATA DATA 0.8 V tSETUP tHOLD Figure 3: Transmitter Section Timing. DATA BYTE A ± DOUTA,B T6 T7 T8 T9 T0 T1 T2 T3 T4 T5 DATA BYTE B T6 T7 T8 T9 T0 T1 T2 T3 T4 T5 t_TXLAT TX[0]-TX[9] REFCLK Figure 4: Transmitter Latency. DATA BYTE B DATA BYTE C 0.0 V AC 6 HDMP-1638 (Receiver Section) Timing Characteristics TA = 0 °C to +70 °C, VCC = 3.15 V to 3.45 V Symbol Parameter Units Min. Typ. Max. Frequency Lock at Powerup µs 500 b_sync[1,2] Bit Sync Time bits 2500 t valid_before Time Data Valid Before Rising Edge of RBC nsec 2.5 Time Data Valid After Rising Edge of RBC nsec 1.5 % 40 60 Rising Edge Time Difference Between RBC0 and RBC1 nsec 7.5 8.5 Receiver Latency nsec 22.4 bits 28.0 f_lock tvalid_after t duty RBC Duty Cycle tA-B[4] t _rxlat[3] Notes: 1. This is the recovery time for input phase jumps, per the Fibre Channel Specification X3.230-1994 FC-PH Standard, Sec 5.3. 2. Tested using CPLL=0.1 µF. 3. The receiver latency, as shown in Figure 6, is defined as the time between receiving the first serial bit of a parallel data word (defined as the first edge of the first serial bit) and the clocking out of that parallel word (defined by the rising edge of the receive byte clock, either RBC1 or RBC0). 4. Guaranteed at room temperature. tvalid_before tvalid_after RBC1 1.4 V 2.0 V RX[0]-RX[9] K28.5 DATA DATA DATA DATA 0.8 V 2.0 V BYTSYNC 0.8 V 1.4 V RBC0 tA-B Figure 5: Receiver Section Timing DATA BYTE C ± DINA,B R5 R6 R7 R8 DATA BYTE D R9 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R2 R3 R4 R5 t_rxlat RX[0]-RX[9] RBC1/0 Figure 6: Receiver Latency DATA BYTE A DATA BYTE D 1.4 V 7 HDMP-1638 (TRx) Absolute Maximum Ratings TA = 25 °C, except as specified. Operation in excess of any one of these conditions may result in permanent damage to this device. Symbol VCC VIN,TTL VIN,HS_IN IO,TTL Parameter Units Min. Max. Supply Voltage V -0.5 5.0 TTL Input Voltage V -0.7 VCC +2.8 HS_IN Input Voltage V 2.0 VCC TTL Output Source Current mA 13 Tstg Storage Temperature °C -65 +150 Tj Junction Temperature °C 0 +150 HDMP-1638 (TRx) Guaranteed Operating Rates TA = 0 °C to +70 °C, VCC = 3.15 V to 3.45 V Parallel Clock Rate (MHz) Min. Max. 124.0 126.0 Serial Baud Rate (MBaud) Min. Max. 1240 1260 HDMP-1638 (TRx) Transceiver Reference Clock Requirements TA = 0 °C to +70 °C, VCC = 3.15 V to 3.45 V Symbol f Ftol Symm Parameter Units Min. Typ. Max. Nominal Frequency (for Gigabit Ethernet Compliance) MHz Frequency Tolerance ppm -100 +100 % 40 60 Symmetry (Duty Cycle) 125 8 HDMP-1638 (TRx) DC Electrical Specifications TA = 0 °C to +70 °C, VCC = 3.15 V to 3.45 V Symbol Parameter Units Min. Typ. Max. VIH,TTL TTL Input High Voltage Level, Guaranteed High Signal For All Inputs V 2 5.5 VIL,TTL TTL Input Low Voltage Level, Guaranteed Low Signal For All Inputs V 0 0.8 VOH,TTL TTL Output High Voltage Level, IOH = -400 µA V 2.2 VCC VOL,TTL TTL Output Low Voltage Level, IOL = 1 mA V 0 0.6 IIH,TTL Input High Current (Magnitude), VIN = 2.4 V, V CC = 3.45 V µA 40 IIL,TTL Input Low Current (Magnitude), VIN = 0.4 V, VCC = 3.45 V µA -600 Transceiver VCC Supply Current, TA = 25 °C ma ICC,TRx[1,2] 270 Notes: 1. Masurement Conditions: Tested sending 1250 MBd PRBS 2^7-1 sequence from a serial BERT with both DOUT outputs biased with 150 Ω resistors. 2. Typical specified with VCC = 3.3 volts, maximum specified with V CC = 3.45 volts. HDMP-1638 (TRx) PECL DC Electrical Specifications TA = 0 °C to +70 °C, VCC = 3.15 V to 3.45 V Symbol Parameter Units Min. Typ. Max. VIH,PECL PECL Input High Voltage Level V 2.14 2.42 VIL,PECL PECL Input Low Voltage Level V 1.49 1.82 9 HDMP-1638 (TRx) AC Electrical Specifications TA = 0 °C to +70 °C, VCC = 3.15 V to 3.45 V Symbol Parameter Units Min. Typ. Max. tr,TTLin Input TTL Rise Time, 0.8 to 2.0 Volts nsec 2 tf,TTLin Input TTL Fall Time, 2.0 to 0.8 Volts nsec 2 tr,TTLout Output TTL Rise Time, 0.8 to 2.0 Volts, 10 pF Load nsec 1.5 2.4 tf,TTLout Output TTL Fall Time, 2.0 to 0.8 Volts, 10 pF Load nsec 1.1 2.4 trs,HS_OUT HS_OUT Single-Ended (+DOUT) Rise Time psec 85 225 327 tfs,HS_OUT HS_OUT Single-Ended (+DOUT) Fall Time psec 85 200 327 trd,HS_OUT HS_OUT Differential Rise Time psec 85 327 tfd,HS_OUT HS_OUT Differential Fall Time psec 85 327 VIP,HS_IN HS_IN Input Peak-To-Peak Differential Voltage mV 200 1200 2000 HS_OUT Output Pk-Pk Diff. Voltage (Z0=50 Ω, Fig. 10) mV 1200 1600 2200 VOP,HS_OUT[1] Note: 1.Output Peak-to-Peak Differential Voltage specified as DOUT+ minus DOUT-. 22.0680 ns Yaxis = 400 mV/DIV A. DIFFERENTIAL HS_OUT OUTPUT (DOUT+ MINUS DOUT–) 22.0680 ns B. SINGLE-ENDED HS_OUT OUTPUT (DOUT+) Eye Diagrams of the High-Speed Serial Outputs from the HDMP-1638 as Captured on the 83480A Digital Communications Analyzer. Tested with PRBS=2 7-1. Figure 7: Transmitter DOUT Eye Diagrams. Yaxis = 200 mV/DIV 10 HDMP-1638 (Transmitter Section) Output Jitter Characteristics (Measured with equivalent parts which have TTL REFCLK input) TA = 0 °C to +70 °C, VCC = 3.15 V to 3.45 V Symbol Parameter Units Typ. RJ[1] Random Jitter at DOUT, the High Speed Electrical Data Port, Specified as 1 Sigma Deviation of the 50% Crossing Point (RMS) ps 8 DJ[1] Deterministic Jitter at DOUT, the High Speed Electrical Data Port (pk-pk) ps TBD Note: 1. Defined by Fibre Channel Specification X3.230-1994 FC-PH Standard, Annex A, Section A.4 and tested using measurement method shown in Figure 8. 70311A CLOCK SOURCE 70841B PATTERN GENERATOR* 0000011111 + DATA - DATA 1.25 GHz 83480A OSCILLOSCOPE 125 MHz TRIGGER CH1 1.25 GHz CH2 70841B PATTERN GENERATOR +K28.5, -K28.5 + DATA - DATA 83480A OSCILLOSCOPE DIVIDE BY 10 CIRCUIT (DUAL OUTPUT) DIVIDE BY 2 CIRCUIT TRIGGER CH1 CH2 +DOUT -DOUT 70311A CLOCK SOURCE +DOUT BIAS TEE -DOUT HDMP-1638 VARIABLE DELAY REFCLK LOOPEN Tx[0..9] * PATTERN GENERATOR PROVIDES A DIVIDE BY 10 FUNCTION. TTL 125 MHz REFCLK Tx[0..9] 1.4 V -DIN +DIN HDMP-1638 ENBYTSYNC LOOPEN Rx[0..9] 0011111000 (STATIC K28.7) A. BLOCK DIAGRAM OF RJ MEASUREMENT METHOD Figure 8: Transmitter Jitter Measurement Method. B. BLOCK DIAGRAM OF DJ MEASUREMENT METHOD 11 HDMP-1638 (TRx) Thermal and Power Temperature Characteristics TA = 0 °C to +70 °C, VCC = 3.15 V to 3.45 V Symbol Parameter Units Typ. Max. P D, TRx[1,2] Transceiver Power Dissipation, one Output Pair Open, Parallel Data Has 5 Ones and 5 Zeroes. mW 840 TBD PD, TRx[1,2,3] Transceiver Power Dissipation, Outputs Connected Per Recommended Bias Terminations with Idle Pattern mW 890 TBD Thermal Resistance, Junction to Case °C/W 10 Qjc[4] Notes: 1. PD is obtained by multiplying VCC by ICC and subtracting the power dissipated outside the chip at the high speed bias resistors. 2. Typical specified with V CC = 3.3 volts, maximum value specified with VCC = 3.45 volts. 3. Specified with high speed outputs biased with 150 Ω resistors and receiver TTL outputs driving 10 pF loads. 4. Based on independent package testing by Agilent Technologies. Q ja for these devices is 48°C/W for the HDMP-1638. Qja is measured on a standard 3x3” FR4 PCB in a still air environment. To determine the actual junction temperature in a given application, use the following: T J = T C +(Qjc x Pd), where TC is the case temperature measured on the top center of the package and P D is the power being dissipated. I/O Type Definitions I/O Type Definition I-TTL Input TTL, floats high when left open O-TTL Output TTL HS_OUT HS_IN High Speed Output, ECL Compatible High Speed Input C External circuit node S Power supply or ground PECL Positive ECL HDMP-1638 (TRx) Pin Input Capacitance Symbol Parameter CINPUT Input Capacitance on TTL Input Pins Units Typ. Max. pF 1.6 12 O_TTL I_TTL VCC_TTL R VCC_TTL VCC_TTL or VCC_RX R R R VBB 1.4 V R GND ESD PROTECTION ESD PROTECTION GND_TTL GND_TTL Figure 9: O-TTL and I-TTL Simplified Circuit Schematic. HS OUT HS IN VCC VCC_TXHS VCC_TXECL + A – + – VCC VCC R R 0.01 µF +DOUT Zo +DIN RPAD 150 -DOUT 2 * Z0 RPAD Zo 0.01 µF GND ESD PROTECTION -DIN GND ESD 150 PROTECTION GND_TXHS GND NOTES: 1. HS_IN INPUTS SHOULD NEVER BE CONNECTED TO GROUND AS PERMANENT DAMAGE TO THE DEVICE MAY RESULT. 2. THE OPTIONAL SERIES PADDING RESISTORS (RPAD) HELP DAMPEN LOAD REFLECTIONS. TYPICAL RPAD VALUES FOR MISMATCHED LOADS RANGE BETWEEN 25-Z0 Ω. 3. FOR PECL REFCLK INPUT PAIR, THE CONSTANT VOLTAGE SUPPLIES (SHOWN AS A) AND RESISTORS R ARE OMITTED. Figure 10: HS_OUT and HS_IN Simplified Circuit Schematic. VCC_RXA RXCAP1 DINAGND_RXA DINA+ DINBVCC_RXHS VCC_RX GND_RXHS DINB+ VCC_TXHS DOUTB+ DOUTBVCC_TXECL DOUTA+ DOUTA- 13 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 48 TX[1] 2 3 47 46 TX[2] 4 TX[3] TX[4] 5 6 45 44 43 TX[5] TX[6] 7 8 9 GND_TXHS TX[0] TX[7] TX[8] TX[9] NC RXSEL GND_TXTTL GND_TXA TXCAP1 10 11 12 42 41 40 HDMP-1638 xxxx-x Rz.zz S 39 38 37 YYWW 36 35 34 13 14 15 33 16 RBC0 GND_RXTTL VCC_RX VCC_RXTTL RBC1 SIG_DET NC -REFCLK ENBYTSYNC GND TXCAP0 VCC_TXA LOOPEN VCC_TX GND +REFCLK 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 xxxx-x = WAFER LOT NUMBER–BUILD NUMBER Rz.zz = DIE REVISION S = SUPPLIER CODE YYWW = DATE CODE (YY = YEAR, WW = WORK WEEK) COUNTRY = COUNTRY OF MANUFACTURE (MARKED ON BACK OF DEVICE) *NOTE: PINS 12 AND 27 ARE DESIGNATED AS "NO CONNECT" PINS AND ARE NORMALLY UNCONNECTED. HDMP-1638 fig 11 Figure 11: HDMP-1638 (TRx) Package Layout and Marking, Top View. RXCAP0 BYTSYNC GND_RXTTL RX[0] RX[1] RX[2] VCC_RXTTL RX[3] RX[4] RX[5] RX[6] VCC_RXTTL RX[7] RX[8] RX[9] GND_RXTTL 14 TRx I/O Definition NAME PIN TYPE SIGNAL BYTSYNC 47 O-TTL Byte Sync Output: An active high output. Used to indicate detection of either a comma character (0011111XXX). It is only active when ENBYTSYNC is enabled. -DINA +DINA 52 53 HS_IN Serial Data Inputs: High speed inputs. Serial data is accepted from the ± DINA inputs when LOOPEN and RXSEL are both low. -DINB +DINB 55 56 HS_IN Serial Data Inputs: High speed inputs. Serial data is accepted from the ± DINB inputs when LOOPEN is low and RXSEL high. RXSEL 13 I-TTL Serial Input Select: If this pin is held low then ± DINA inputs are parallelized. If this pin is held high then ± DINB inputs are parallelized. -DOUTA +DOUTA 59 60 HS_OUT Serial Data Outputs: High speed outputs. These lines are active when LOOPEN is set low. When LOOPEN is set high, these outputs are held static at logic 1. If unused, remove the 150 Ω pulldown resistors to save power. -DOUTB +DOUTB 62 63 HS_OUT Serial Data Outputs: High speed outputs. These lines are active when LOOPEN is set low. When LOOPEN is set high, these outputs are held static at logic 1. If unused, remove the 150 Ohm pulldown resistors to save power. ENBYTSYNC 24 I-TTL Enable Byte Sync Input: When high, turns on the internal byte sync function to allow clock synchronization to a comma character (0011111XXX). When the line is low, the function is disabled and will not reset registers and clocks, or strobe the BYTSYNC line. GND 21 S Logic Ground: Normally 0 volts. This ground is used for internal PECL logic. It should be isolated from the noisy TTL ground as well as possible. 25 GND_RXA 51 S Analog Ground: Normally 0 volts. Used to provide a clean ground plane for the receiver PLL and high-speed analog cells. GND_RXHS 57 S Ground: Normally 0 volts. GND_RXTTL 32 33 46 S TTL Receiver Ground: Normally 0 volts. Used for the TTL output cells of the receiver section. GND_TXA 15 S Analog Ground: Normally 0 volts. Used to provide a clean ground plane for the PLL and high-speed analog cells. 15 NAME PIN TYPE SIGNAL GND_TXHS 1 S Ground: Normally 0 volts. GND_TXTTL 14 S TTL Transmitter Ground: Normally 0 volts. Used for the TTL input cells of the transmitter section. N/C 27,12 LOOPEN 19 I-TTL Loopback Enable Input: When set high, the high speed serial signal is internally wrapped from the transmitter’s serial loopback outputs back to the receiver’s loopback inputs. Also when in loopback mode, the ± DOUT outputs are held static at logic 1. When set low, ± DOUT outputs and ± DIN inputs are active. RBC1 RBC0 30 31 O-TTL Receiver Byte Clocks: The receiver section recovers two 62.5 MHz receive byte clocks. These two clocks are 180 degrees out of phase. The receiver parallel data outputs are alternately clocked on the rising edge of these clocks. The rising edge of RBC1 aligns with the output of the comma character (for byte alignment) when detected. +REFCLK -REFCLK 22 23 PECL Reference Clock and Transmit Byte Clock: A 125 MHz clock supplied by the host system. The transmitter section accepts this signal as the frequency reference clock. It is multiplied by 10 to generate the serial bit clock and other internal clocks. The transmit side also uses this clock as the transmit byte clock for the incoming parallel data TX[0]..TX[9]. It also serves as the reference clock for the receive portion of the transceiver. RX[0] RX[1] RX[2] RX[3] RX[4] RX[5] RX[6] RX[7] RX[8] RX[9] 45 44 43 41 40 39 38 36 35 34 O-TTL Data Outputs: One 10 bit data byte. RX[0] is the first bit received. RX[0] is the least significant bit. When there is a loss of input signal at ± DINB and RXSEL is high, these outputs are held static at logic 1. Refer to SIG_DET (pin 26) pin definition for more details. RXCAP0 RXCAP1 48 49 C These pins are connected to an isolated pad and have no functionality. They may be left open, however, TTL levels may also be applied to these pins. Loop Filter Capacitor: A loop filter capacitor for the internal PLL must be connected across the RXCAP0 and RXCAP1 pins. (typical value = 0.1 µF) 16 NAME PIN TYPE SIGNAL TX[0] TX[1] TX[2] TX[3] TX[4] TX[5] TX[6] TX[7] TX[8] TX[9] 2 3 4 5 6 7 8 9 10 11 I-TTL Data Inputs: One 10 bit, 8B/10B encoded data byte. TX[0] is the first bit transmitted. TX[0] is the least significant bit. TXCAP0 TXCAP1 17 16 C SIG_DET 26 O-TTL VCC_RX 28 58 S Logic Power Supply: Normally 3.3 volts. Used for internal receiver PECL logic. It should be isolated from the noisy TTL supply as well as possible. VCC _RXA 50 S Analog Power Supply: Normally 3.3 volts. Used to provide a clean supply line for the PLL and high speed analog cells. VCC _RXHS 54 S High Speed Supply: Normally 3.3 volts. Used only for the high speed receiver cell (HS_IN). Noise on this line should be minimized for best operation. VCC _RXTTL 29 37 42 S TTL Power Supply: Normally 3.3 volts. Used for all TTL receiver output buffer cells. VCC_TX 20 S Logic Power Supply: Normally 3.3 volts. Used for internal transmitter PECL logic. Also used for all transmitter TTL input buffer cells. VCC_TXA 18 S Analog Power Supply: Normally 3.3 volts. Used to provide a clean supply line for the PLL and high speed analog cells. VCC _TXECL 61 S High Speed ECL Supply: Normally 3.3 volts. Used only for the last stage of the high speed transmitter output cell (HS_OUT) as shown in Figure 10. Due to high current transitions, this VCC should be well bypassed to a ground plane. VCC_TXHS 64 S High Speed Supply: Normally 3.3 volts. Used by the transmitter side for the high speed circuitry. Noise on this line should be minimized for best operation. Loop Filter Capacitor: A loop filter capacitor must be connected across the TXCAP1 and TXCAP0 pins (typical value=0.1 µF). Signal Detect: Indicates a loss of signal on the high-speed differential inputs, ± DINB, as in the case where the transmission cable becomes disconnected. If ± DIN>=200 mV peak-to-peak, SIG_DET=logic 1. If ± DIN<200 mV and ± DIN>50 mV, SIG_DET=undefined. If ± DIN<=50 mV, SIG_DET=logic 0. 17 Transceiver Power Supply Bypass and Loop Filter Capacitors VCC* VCC RXCAP1 VCC_RXA GND_RXA VCC_RXHS VCC_RX GND_RXHS GND_TXHS VCC_TXECL VCC_TXHS CPLLR RXCAP0 GND_RXTTL VCC_RXTTL VCC HDMP-1638 TOP VIEW CPLLT GND_RXTTL VCC_RX VCC_RXTTL GND TXCAP1 VCC_TX GND GND_TXTTL GND_TXA TXCAP0 VCC_TXA VCC_RXTTL GND_RXTTL VCC VCC* * SUPPLY VOLTAGE INTO VCC_RXA AND VCC_TXA SHOULD BE FROM A LOW NOISE SOURCE. ALL BYPASS CAPACITORS AND PLL FILTER CAPACITORS ARE 0.1 µF. Figure 12: Power Supply Bypass. Start Up Procedure: The transceiver startup procedure(s) and the following conditions: VCC = +3.3 V ± 5 % and REFCLK = 125 MHz ± 100 ppm. After the above conditions have been met, apply valid data using a balanced code such as 8B/10B. Frequency lock occurs within 500 µs. After frequency lock, phase lock occurs within 2500 bit times. If desired, bypass capacitors may be used on the power supply pins of the HDMP-1638. All bypass chip capacitors are 0.1 µF. The VCC_RXA and VCC _TXA pins are the analog power supply pins for the PLL sections. The supply into these pins should be clean with minimum noise. Use of capacitors as shown in Figure 12 is mandatory for these pins. The PLL loop filter capacitors and their pin locations are also shown on Figure 12. Notice that only two capacitors are required; CPLLT for the transmitter and CPLLR for the receiver. Nominal capacitance is 0.1 µF. The maximum voltage across the capacitors is on the order of 1 volt, so the capacitor can be a low voltage type and physically small. The PLL capacitors are to be placed physically close to the appropriate pins on the HDMP-1638. Keeping the lines short will prevent them from picking up any stray noise from surrounding lines or components. 18 Package Information Item Details Package Material Plastic Lead Finish Material 85% Tin, 15% Lead Lead Finish Thickness 300–800 µm Lead Coplanarity 0.08 mm max Mechanical Dimensions PIN #1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 2 3 4 5 6 7 8 9 48 47 46 45 44 43 42 41 40 HDMP-1638 A1 A2 10 39 TOP VIEW 11 38 12 37 13 36 14 35 15 34 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 B4 B1 A1 B5 B2 B3 A2 C1 C3 C2 ALL DIMENSIONS ARE IN MILLIMETERS. PART NUMBER A1 A2 B1 B2 B3 B4 B5 C1 C2 C3 HDMP-1638 10.00 13.20 0.22 0.50 0.88 0.17 0.25 2.00 0.25 MIN. 2.45 TOLERANCE ± 0.10 ± 0.25 ± 0.05 BASIC + 0.15/ MAX. – 0.10 Figure 13: Mechanical Dimensions of HDMP-1638. + 0.10/ – 0.05 MAX. www.semiconductor.agilent.com Data subject to change. Copyright © 1999 Agilent Technologies, Inc. 5968-5120E (11/99)