AD SSM2302CPZ-R2

Filterless High Efficiency
Class-D Stereo Audio Amplifier
SSM2302
5.0 V supply and has a signal-to-noise ratio (SNR) that is better
than 98 dB. PDM modulation is used to provide lower EMIradiated emissions compared with other Class-D architectures.
FEATURES
Filterless Class-D amplifier with built-in output stage
1.4 W into 8 Ω at 5.0 V supply with less than 1% THD
85% efficiency at 5.0 V, 1.4 W into 8 Ω speaker
Better than 98 dB SNR (signal-to-noise ratio)
Single-supply operation from 2.5 V to 5.0 V
20 nA ultralow shutdown current
Short-circuit and thermal protection
Available in 16-lead, 3 mm × 3 mm LFCSP
Pop-and-click suppression
Built-in resistors reduce board component count
Fixed and user-adjustable gain configurations
The SSM2302 has a micropower shutdown mode with a typical
shutdown current of 20 nA. Shutdown is enabled by applying a
logic low to the SD pin.
The architecture of the device allows it to achieve a very low level
of pop and click. This minimizes voltage glitches at the output
during turn-on and turn-off, thus reducing audible noise on
activation and deactivation.
APPLICATIONS
The fully differential input of the SSM2302 provides excellent
rejection of common-mode noise on the input. Input coupling
capacitors can be omitted if the dc input common-mode voltage
is approximately VDD/2.
Mobile phones
MP3 players
Portable gaming
Portable electronics
Educational toys
The SSM2302 also has excellent rejection of power supply noise,
including noise caused by GSM transmission bursts and RF
rectification. PSRR is typically 63 dB at 217 Hz.
GENERAL DESCRIPTION
The SSM2302 is a fully integrated, high efficiency, Class-D stereo
audio amplifier. It is designed to maximize performance for
mobile phone applications. The application circuit requires a
minimum of external components and operates from a single
2.5 V to 5.0 V supply. It is capable of delivering 1.4 W of continuous output power with less than 1% THD + N driving an
8 Ω load from a 5.0 V supply.
The gain can be set to 6 dB or 12 dB utilizing the gain control
select pin connected respectively to ground or VDD. Gain can
also be adjusted externally by using an external resistor.
The SSM2302 is specified over the commercial temperature range
(−40°C to +85°C). It has built-in thermal shutdown and output
short-circuit protection. It is available in a 16-lead, 3 mm × 3 mm
lead-frame chip scale package (LFCSP).
The SSM2302 features a high efficiency, low noise modulation
scheme. It operates with 85% efficiency at 1.4 W into 8 Ω from a
FUNCTIONAL BLOCK DIAGRAM
0.1µF
10µF
SSM2302
0.01µF1
RIGHT IN+
VDD
OUTR+
INR+
INR–
RIGHT IN–
VDD
VBATT
2.5V TO 5.0V
GAIN
CONTROL
MODULATOR
FET
DRIVER
OUTR–
0.01µF 1
SD
GAIN
GAIN
0.01µF1
LEFT IN+
INTERNAL
OSCILLATOR
OUTL+
INL+
INL–
LEFT IN–
BIAS
GAIN
CONTROL
MODULATOR
0.01µF1
GND
1 INPUT
CAPS ARE OPTIONAL IF INPUT DC COMMON-MODE
VOLTAGE IS APPROXIMATELY VDD/2.
FET
DRIVER
OUTL–
GND
06051-001
SHUTDOWN
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
SSM2302
TABLE OF CONTENTS
Features .............................................................................................. 1
Pop-and-Click Suppression ...................................................... 12
Applications....................................................................................... 1
EMI Noise.................................................................................... 12
General Description ......................................................................... 1
Layout .......................................................................................... 13
Functional Block Diagram .............................................................. 1
Input Capacitor Selection.......................................................... 13
Revision History ............................................................................... 2
Proper Power Supply Decoupling ............................................ 13
Specifications..................................................................................... 3
Evaluation Board Information...................................................... 14
Absolute Maximum Ratings............................................................ 4
Introduction................................................................................ 14
Thermal Resistance ...................................................................... 4
Operation .................................................................................... 14
ESD Caution.................................................................................. 4
SSM2302 Application Board Schematic.................................. 15
Pin Configuration and Function Descriptions............................. 5
SSM2302 Stereo Class-D Amplifier Evaluation Module
Component List.......................................................................... 16
Typical Performance Characteristics ............................................. 6
Typical Application Circuits............................................................ 9
Application Notes ........................................................................... 12
Overview...................................................................................... 12
SSM2302 Application Board Layout........................................ 17
Outline Dimensions ....................................................................... 18
Ordering Guide .......................................................................... 18
Gain Selection ............................................................................. 12
REVISION HISTORY
6/06—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
SSM2302
SPECIFICATIONS
VDD = 5.0 V, TA = 25oC, RL = 8 Ω, unless otherwise noted
Table 1.
Parameter
DEVICE CHARACTERISTICS
Output Power
Symbol
Conditions
PO
RL = 8 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V
RL = 8 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V
RL = 8 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 2.5 V
RL = 8 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V
RL = 8 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V
RL = 8 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 2.5 V
POUT =1.4 W, 8 Ω, VDD = 5.0 V
1.4
0.615
0.275
1.53
0.77
0.35
85
W
W
W
W
W
W
%
PO = 1 W into 8 Ω each channel, f = 1 kHz, VDD = 5.0 V
PO = 0.5 W into 8 Ω each channel, f = 1 kHz, VDD = 3.6 V
0.1
0.04
%
%
V
dB
dB
MHz
mV
Efficiency
η
Total Harmonic Distortion + Noise
THD + N
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
Channel Separation
Average Switching Frequency
Differential Output Offset Voltage
POWER SUPPLY
Supply Voltage Range
Power Supply Rejection Ratio
VCM
CMRRGSM
XTALK
fSW
VOOS
VDD
PSRR
PSRRGSM
Supply Current
ISY
Shutdown Current
ISD
GAIN CONTROL
Closed-Loop Gain
Min
Typ
1.0
VCM = 2.5 V ± 100 mV at 217 Hz
PO = 100 mW , f = 1 kHz
VDD − 1
55
98
1.8
2.0
G = 6 dB; G = 12 dB
Guaranteed from PSRR test
VDD = 2.5 V to 5.0 V, 50 Hz, input floating/ground
VRIPPLE = 100 mV at 217 Hz, inputs ac GND,
CIN = 0.01 μF, input referred
VIN = 0 V, no load, VDD = 5.0 V
VIN = 0 V, no load, VDD = 3.6 V
VIN = 0 V, no load, VDD = 2.5 V
SD = GND
Max
2.5
70
5.0
Unit
85
63
V
dB
dB
8.0
6.6
5.3
20
mA
mA
mA
nA
Av0
Av1
ZIN
GAIN pin = 0 V
GAIN pin = VDD
SD = VDD,
SD = GND
6
12
150
210
dB
dB
KΩ
KΩ
SHUTDOWN CONTROL
Input Voltage High
Input Voltage Low
Turn-On Time
Turn-Off Time
Output Impedance
VIH
VIL
tWU
tSD
ZOUT
ISY ≥ 1 mA
ISY ≤ 300 nA
SD rising edge from GND to VDD
SD falling edge from VDD to GND
SD = GND
1.2
0.5
30
5
>100
V
V
ms
μs
KΩ
NOISE PERFORMANCE
Output Voltage Noise
en
VDD = 2.5 V to 5.0 V, f = 20 Hz to 20 kHz, inputs are
ac grounded, sine wave, AV = 6 dB, A weighting
POUT = 1.4 W, RL = 8 Ω
35
μV
98
dB
Differential Input Impedance
Signal-to-Noise Ratio
SNR
Rev. 0 | Page 3 of 20
SSM2302
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings apply at 25°C, unless otherwise noted.
Table 2.
Parameter
Supply Voltage
Input Voltage
Common-Mode Input Voltage
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
Lead Temperature Range
(Soldering, 60 sec)
Rating
6V
VDD
VDD
−65°C to +150°C
−40°C to +85°C
−65°C to +165°C
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type
16-lead, 3 mm × 3 mm LFCSP
θJA
44
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 4 of 20
θJC
31.5
Unit
°C/W
SSM2302
12 OUTR+
11 OUTR–
10 GAIN
14 VDD
NC = NO CONNECT
06051-002
9 INR+
INR– 8
NC 7
TOP VIEW
(Not to Scale)
INL– 5
INL+ 4
SSM2302
NC 6
SD 3
13 GND
PIN 1
INDICATOR
OUTL+ 1
OUTL– 2
15 VDD
16 GND
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 2. SSM2302 LFCSP Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Mnemonic
OUTL+
OUTL−
SD
INL+
INL−
NC
NC
INR−
INR+
GAIN
OUTR−
OUTR+
GND
VDD
VDD
GND
Description
Inverting Output for Left Channel.
Noninverting Output for Left Channel.
Shutdown Input. Active low digital input.
Noninverting Input for Left Channel.
Inverting Input for Left Channel.
No Connect.
No Connect.
Inverting Input for Right Channel.
Noninverting Input for Right Channel.
Gain Selection. Digital input.
Noninverting Output for Right Channel.
Inverting Output for Right Channel.
Ground for Output Amplifiers.
Power Supply for Output Amplifiers.
Power Supply for Output Amplifiers.
Ground for Output Amplifiers.
Rev. 0 | Page 5 of 20
SSM2302
TYPICAL PERFORMANCE CHARACTERISTICS
100
100
RL = 8Ω, 33µH
GAIN = 12dB
VDD = 3.6V
RL = 8Ω, 33µH
10
VDD = 2.5V
10
THD + N (%)
THD + N (%)
1
1
VDD = 3.6V
500mW
0.1
0.01
125mW
250mW
0.1
0.001
0.001
0.0001
0.01
0.1
1
10
OUTPUT POWER (W)
0.0001
10
06051-003
0.01
0.000001 0.00001
100
Figure 3. THD + N vs. Output Power into 8 Ω, AV = 12 dB
100
1k
10k
100k
FREQUENCY (Hz)
06051-006
VDD = 5V
Figure 6. THD + N vs. Frequency, VDD = 3.6 V
100
RL = 8Ω, 33µH
GAIN = 6dB
VDD = 2.5V
RL = 8Ω, 33µH
10
VDD = 2.5V
10
THD + N (%)
THD + N (%)
1
1
VDD = 3.6V
250mW
0.1
75mW
125mW
0.01
0.1
0.01
0.1
1
10
OUTPUT POWER (W)
0.0001
10
06051-004
0.000001
0.0001
0.0000001
0.00001
0.001
5.5
8
7
SUPPLY CURRENT (mA)
THD + N (%)
100k
9
VDD = 5V
RL = 8Ω, 33µH
1
0.1
1W
0.25W
0.5W
6
5
4
3
2
0.001
1
100
1k
10k
FREQUENCY (Hz)
100k
06051-005
0.0001
10
10k
Figure 7. THD + N vs. Frequency, VDD = 2.5 V
10
0.01
1k
FREQUENCY (Hz)
Figure 4. THD + N vs. Output Power into 8 Ω, AV = 6 dB
100
100
06051-007
VDD = 5V
0.01
06051-008
0.001
Figure 5. THD + N vs. Frequency, VDD = 5.0 V
Rev. 0 | Page 6 of 20
0
2.5
3.0
3.5
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
Figure 8. Supply Current vs. Supply Voltage, No Load
SSM2302
12
1.0
VDD = 3.6V
RL = 8Ω, 33µH
0.9
0.8
POWER DISSIPATION (W)
SHUTDOWN CURRENT (µA)
10
8
VDD = 5V
6
VDD = 2.5V
4
VDD = 3.6V
0.7
0.6
0.5
0.4
0.3
0.2
2
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
SHUTDOWN VOLTAGE (V)
0
06051-009
0
1.8
GAIN = 2
RL = 8Ω, 33µH
POWER DISSIPATION (W)
0.4
0.5
0.6
0.7
0.8
1.0
10%
0.8
1%
0.6
0.4
0.2
1.4
1.2
1.0
0.8
0.6
0.4
3.0
3.5
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
0
06051-010
0
2.5
90
VDD = 2.5V
VDD = 3.6V
80
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3
OUTPUT POWER (W)
Figure 10. Maximum Output Power vs. Supply Voltage
100
0
06051-013
0.2
Figure 13. Power Dissipation vs. Output Power at VDD = 5.0 V
400
RL = 8Ω, 33µH
RL = 8Ω, 33µH
350
VDD = 5V
SUPPLY CURRENT (mA)
VDD = 5V
70
60
50
40
30
300
VDD = 3.6V
250
200
VDD = 2.5V
150
100
20
50
10
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4
OUTPUT POWER (W)
0
06051-011
0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
OUTPUT POWER (W)
Figure 14. Output Power vs. Supply Current, One Channel
Figure 11. Efficiency vs. Output Power into 8 Ω
Rev. 0 | Page 7 of 20
1.6
06051-014
OUTPUT POWER (W)
0.3
VDD = 5V
RL = 8Ω, 33µH
1.6
1.2
EFFICIENCY (%)
0.2
Figure 12. Power Dissipation vs. Output Power at VDD = 3.6 V
f = 1kHz
1.4
0.1
OUTPUT POWER (W)
Figure 9. Supply Current vs. Shutdown Voltage
1.6
0
06051-012
0.1
0
SSM2302
0
7
–10
6
–20
5
4
–40
VOLTAGE
–50
–60
SD INPUT
3
2
1
–70
OUTPUT
0
–80
–1
–90
100
1k
10k
100k
FREQUENCY (Hz)
–2
–10 –5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90
06051-015
–100
10
TIME (ms)
Figure 15. Power Supply Rejection Ratio vs. Frequency
0
–10
Figure 18. Turn-On Response
7
RL = 8Ω, 33µH
GAIN = 6dB
OUTPUT
6
5
–20
SD INPUT
4
–30
VOLTAGE
CMRR (dB)
06051-018
PSRR (dB)
–30
–40
–50
3
2
1
–60
0
–70
1k
10k
100k
FREQUENCY (Hz)
Figure 16. Common-Mode Rejection Ratio vs. Frequency
VDD = 3.6V
VRIPPLE = 1V rms
RL = 8Ω, 33µH
–60
–80
–100
–120
100
1k
10k
FREQUENCY (Hz)
100k
06051-017
CROSSTALK (dB)
–40
–140
10
0
20
40
60
80
100
120
TIME (ms)
Figure 19. Turn-Off Response
0
–20
–2
–20
Figure 17. Crosstalk vs. Frequency
Rev. 0 | Page 8 of 20
140
160
180
06051-019
100
06051-016
–80
10
–1
SSM2302
TYPICAL APPLICATION CIRCUITS
10µF
0.1µF
SSM2302
0.01µF1
RIGHT IN+
VDD
OUTR+
INR+
INR–
RIGHT IN–
VDD
VBATT
2.5V TO 5.0V
GAIN
CONTROL
MODULATOR
FET
DRIVER
OUTR–
0.01µF 1
SD
SHUTDOWN
VDD
GAIN
0.01µF1
LEFT IN+
INTERNAL
OSCILLATOR
OUTL+
INL+
INL–
LEFT IN–
BIAS
GAIN
GAIN
CONTROL
MODULATOR
FET
DRIVER
OUTL–
0.01µF1
GND
06051-030
GND
1 INPUT CAPS ARE OPTIONAL IF INPUT DC COMMON-MODE
VOLTAGE IS APPROXIMATELY VDD/2.
Figure 20. Stereo Differential Input Configuration, Gain = 12 dB
10µF
0.1µF
SSM2302
0.01µF
RIGHT IN
VDD
VBATT
2.5V TO 5.0V
VDD
OUTR+
INR+
INR–
GAIN
CONTROL
MODULATOR
FET
DRIVER
OUTR–
0.01µF
SD
SHUTDOWN
GAIN
0.01µF
LEFT IN
BIAS
GAIN
INTERNAL
OSCILLATOR
OUTL+
INL+
INL–
GAIN
CONTROL
MODULATOR
FET
DRIVER
OUTL–
0.01µF
GND
06051-031
GND
Figure 21. Stereo Single-Ended Input Configuration, Gain = 6 dB
Rev. 0 | Page 9 of 20
SSM2302
EXTERNAL GAIN SETTINGS = 20 log[4/(1 + R/150kΩ)]
0.1µF
10µF
SSM2302
0.01µF1
RIGHT IN+
R
0.01µF1
VDD
OUTR+
INR+
INR–
RIGHT IN–
VDD
VBATT
2.5V TO 5.0V
GAIN
CONTROL
MODULATOR
FET
DRIVER
OUTR–
R
SD
SHUTDOWN
0.01µF1
LEFT IN+
GAIN
GAIN
R
INL+
INL–
LEFT IN–
0.01µF1
BIAS
INTERNAL
OSCILLATOR
POP/CLICK
SUPPRESSION
OUTL+
GAIN
CONTROL
MODULATOR
FET
DRIVER
OUTL–
R
GND
GND
06051-036
VDD
1 INPUT CAPS ARE OPTIONAL IF INPUT DC COMMON-MODE
VOLTAGE IS APPROXIMATELY VDD/2.
Figure 22. Stereo Differential Input Configuration, User-Adjustable Gain
EXTERNAL GAIN SETTINGS = 20 log[4/(1 + R/150kΩ)]
0.1µF
10µF
SSM2302
RIGHT IN
0.01µF1 R
VDD
VBATT
2.5V TO 5.0V
VDD
OUTR+
INR+
INR–
GAIN
CONTROL
MODULATOR
FET
DRIVER
OUTR–
0.01µF1 R
SD
SHUTDOWN
VDD
0.01µF1 R
BIAS
GAIN
INTERNAL
OSCILLATOR
POP/CLICK
SUPPRESSION
OUTL+
INL+
INL–
GAIN
CONTROL
MODULATOR
FET
DRIVER
OUTL–
0.01µF1 R
GND
GND
1 INPUT CAPS ARE OPTIONAL IF INPUT DC COMMON-MODE
VOLTAGE IS APPROXIMATELY VDD/2.
Figure 23. Stereo Single-Ended Input Configuration, User-Adjustable Gain
Rev. 0 | Page 10 of 20
06051-037
LEFT IN
GAIN
SSM2302
EXTERNAL GAIN SETTINGS = 20 log[2/(1 + R/150kΩ)]
0.1µF
10µF
SSM2302
0.01µF1
RIGHT IN+
R
0.01µF1
VDD
OUTR+
INR+
INR–
RIGHT IN–
VDD
VBATT
2.5V TO 5.0V
GAIN
CONTROL
MODULATOR
FET
DRIVER
OUTR–
R
SD
SHUTDOWN
GAIN
R
0.01µF1
POP/CLICK
SUPPRESSION
OUTL+
INL+
INL–
LEFT IN–
INTERNAL
OSCILLATOR
GAIN
CONTROL
MODULATOR
FET
DRIVER
OUTL–
R
GND
GND
06051-038
0.01µF1
LEFT IN+
BIAS
GAIN
1 INPUT CAPS ARE OPTIONAL IF INPUT DC COMMON-MODE
VOLTAGE IS APPROXIMATELY VDD/2.
Figure 24. Stereo Differential Input Configuration, User-Adjustable Gain
EXTERNAL GAIN SETTINGS = 20 log[2/(1 + R/150kΩ)]
0.1µF
10µF
SSM2302
RIGHT IN
0.01µF1 R
VDD
VBATT
2.5V TO 5.0V
VDD
OUTR+
INR+
INR–
GAIN
CONTROL
MODULATOR
FET
DRIVER
OUTR–
0.01µF1 R
SD
SHUTDOWN
GAIN
0.01µF1 R
INTERNAL
OSCILLATOR
POP/CLICK
SUPPRESSION
OUTL+
INL+
INL–
GAIN
CONTROL
MODULATOR
FET
DRIVER
OUTL–
0.01µF1 R
GND
GND
1 INPUT CAPS ARE OPTIONAL IF INPUT DC COMMON-MODE
VOLTAGE IS APPROXIMATELY VDD/2.
Figure 25. Stereo Single-Ended Input Configuration, User-Adjustable Gain
Rev. 0 | Page 11 of 20
06051-039
LEFT IN
BIAS
GAIN
SSM2302
APPLICATION NOTES
OVERVIEW
EMI NOISE
The SSM2302 stereo Class-D audio amplifier features a filterless
modulation scheme that greatly reduces the external components
count, conserving board space and thus reducing systems cost.
The SSM2302 does not require an output filter, but instead relies
on the inherent inductance of the speaker coil and the natural
filtering of the speaker and human ear to fully recover the audio
component of the square-wave output. While most Class-D amplifiers use some variation of pulse-width modulation (PWM), the
SSM2302 uses a Σ-Δ modulation to determine the switching
pattern of the output devices. This provides a number of important
benefits. Σ-Δ modulators do not produces a sharp peak with
many harmonics in the AM frequency band, as pulse-width
modulators often do. Σ-Δ modulation provides the benefits of
reducing the amplitude of spectral components at high frequencies;
that is, reducing EMI emission that might otherwise be radiated
by speakers and long cable traces. The SSM2302 also offers
protection circuits for overcurrent and temperature protection.
The SSM2302 uses a proprietary modulation and spreadspectrum technology to minimize EMI emissions from the
device. Figure 26 shows SSM2302 EMI emission starting from
100 kHz to 30 MHz. Figure 27 shows SSM2302 EMI emission
from 30 kHz to 2 GHz. These figures clearly describe the SSM2302
EMI behavior as being well below the FCC regulation values,
starting from 100 kHz and passing beyond 1 GHz of frequency.
Although the overall EMI noise floor is slightly higher, frequency
spurs from the SSM2302 are greatly reduced.
60
= HORIZONTAL
= VERTICAL
= REGULATION VALUE
50
LEVEL (dB(µV/m))
GAIN SELECTION
70
40
30
20
Pulling the GAIN pin high of the SSM2302 sets the gain of the
speaker amplifier to 12 dB; pulling it low sets the gain of the
speaker amplifier to 6 dB.
It is possible to adjust the SSM2302 gain by using external resistors
at the input. To set a gain lower than 12 dB refer to Figure 22 for
differential input configuration and Figure 23 for single-ended
configuration. For external gain configuration from a fixed 12 dB
gain, please use the following formula:
1
10
100
06051-032
0
0.1
10k
06051-033
10
FREQUENCY (MHz)
Figure 26. EMI Emissions from SSM2302
70
60
External Gain Settings = 20 log[4/(1 + R/150 kΩ)]
= HORIZONTAL
= VERTICAL
= REGULATION VALUE
To set a gain lower than 6 dB refer to Figure 24 for differential
input configuration and Figure 25 for single-ended configuration.
For external gain configuration from a fixed 6 dB gain, use the
following formula:
LEVEL (dB(µV/m))
50
40
30
20
External Gain Settings = 20 log[2/(1 + R/150 kΩ)]
10
POP-AND-CLICK SUPPRESSION
Voltage transients at the output of audio amplifiers can occur when
shutdown is activated or deactivated. Voltage transients as low
as 10 mV can be heard as an audio pop in the speaker. Clicks
and pops can also be classified as undesirable audible transients
generated by the amplifier system, therefore as not coming from
the system input signal. Such transients can be generated when
the amplifier system changes its operating mode. For example, the
following can be sources of audible transients: system power-up/
power-down, mute/unmute, input source change, and sample rate
change. The SSM2302 has a pop-and-click suppression architecture
that reduces this output transients, resulting in noiseless activation
and deactivation.
0
10
100
1k
FREQUENCY (MHz)
Figure 27. EMI Emissions from SSM2302
The measurements for Figure 26 and Figure 27 were taken with
a 1 kHz input signal, producing 0.5 W output power into an 8 Ω
load from a 3.6 V supply. Cable length was approximately 5 cm.
The EMI was detected using a magnetic probe touching the 2”
output trace to the load.
Rev. 0 | Page 12 of 20
SSM2302
LAYOUT
INPUT CAPACITOR SELECTION
As output power continues to increase, care needs to be taken to
lay out PCB traces and wires properly between the amplifier,
load, and power supply. A good practice is to use short, wide
PCB tracks to decrease voltage drops and minimize inductance.
Make track widths at least 200 mil for every inch of track length
for lowest DCR, and use 1 oz or 2 oz of copper PCB traces to
further reduce IR drops and inductance. A poor layout
increases voltage drops, consequently affecting efficiency. Use
large traces for the power supply inputs and amplifier outputs to
minimize losses due to parasitic trace resistance. Proper
grounding guidelines helps to improve audio performance,
minimize crosstalk between channels, and prevent switching
noise from coupling into the audio signal. To maintain high
output swing and high peak output power, the PCB traces that
connect the output pins to the load and supply pins should be as
wide as possible to maintain the minimum trace resistances. It
is also recommended to use a large-area ground plane for
minimum impedances. Good PCB layouts also isolate critical
analog paths from sources of high interference. High frequency
circuits (analog and digital) should be separated from low
frequency ones. Properly designed multilayer printed circuit
boards can reduce EMI emission and increase immunity to RF
field by a factor of 10 or more compared with double-sided
boards. A multilayer board allows a complete layer to be used
for ground plane, whereas the ground plane side of a doubleside board is often disrupted with signal crossover. If the system
has separate analog and digital ground and power planes, the
analog ground plane should be underneath the analog power
plane, and, similarly, the digital ground plane should be
underneath the digital power plane. There should be no overlap
between analog and digital ground planes nor analog and
digital power planes.
The SSM2302 will not require input coupling capacitors if the
input signal is biased from 1.0 V to VDD − 1.0 V. Input
capacitors are required if the input signal is not biased within
this recommended input dc common-mode voltage range, if
high-pass filtering is needed (Figure 20), or if using a singleended source (Figure 21). If high-pass filtering is needed at the
input, the input capacitor along with the input resistor of the
SSM2302 will form a high-pass filter whose corner frequency is
determined by the following equation:
fC = 1/(2π × RIN × CIN)
Input capacitor can have very important effects on the circuit
performance. Not using input capacitors degrades the output
offset of the amplifier as well as the PSRR performance.
PROPER POWER SUPPLY DECOUPLING
To ensure high efficiency, low total harmonic distortion (THD),
and high PSRR, proper power supply decoupling is necessary.
Noise transients on the power supply lines are short-duration
voltage spikes. Although the actual switching frequency can
range from 10 kHz to 100 kHz, these spikes can contain
frequency components that extend into the hundreds of
megahertz. The power supply input needs to be decoupled with
a good quality low ESL and low ESR capacitor—usually around
4.7 μF. This capacitor bypasses low frequency noises to the
ground plane. For high frequency transients noises, use a 0.1 μF
capacitor as close as possible to the VDD pin of the device.
Placing the decoupling capacitor as close as possible to the
SSM2302 helps maintain efficiency performance.
Rev. 0 | Page 13 of 20
SSM2302
EVALUATION BOARD INFORMATION
INTRODUCTION
Gain Control
The SSM2302 audio power amplifier is a complete low power,
Class-D, stereo audio amplifier capable of delivering 1.4 W/channel
into 8 Ω load. In addition to the minimal parts required for the
application circuit, measurement filters are provided on the
evaluation board so that conventional audio measurements can
be made without additional components.
The gain select header controls the gain setting of the SSM2302.
This section provides an overview of Analog Devices SSM2302
evaluation board. It includes a brief description of the board as
well as a list of the board specifications.
Table 5. SSM2302 Evaluation Board Specifications
Parameter
Supply Voltage Range, VDD
Power Supply Current Rating
Continuous Output Power, PO
(RL = 8 Ω, f = 1 kHz, 22 kHz BW)
Minimum Load Impedance
Specification
2.5 V to 5.0 V
1.5 A
1.4 W
1.
Select jumper to LG for 6 dB gain.
2.
Select jumper to HG for 12 dB gain.
External Gain Settings
It is possible to adjust the SSM2302 gain using external resistors
at the input. To set a gain lower than 12 dB refer to Figure 22
and Figure 23 on the product data sheet for proper circuit configuration. For external gain configuration from a fixed 12 dB
gain, use the following formula:
External Gain Settings = 20 log[4/(1 + R/150 kΩ)]
To set a gain lower than 6 dB refer to Figure 24 and Figure 25
on the product data sheet for proper circuit configuration. For
external gain configuration from a fixed 6 dB gain, use the
following formula:
8Ω
External Gain Settings = 20 log[2/(1 + R/150 kΩ)]
OPERATION
Shutdown Control
Use the following steps when operating the SSM2302
evaluation board.
Power and Ground
1.
Set the power supply voltage between 2.5 V and 5.0 V. When
connecting the power supply to the SSM2302 evaluation
board, make sure to attach the ground connection to the
GND header pin first and then connect the positive supply
to the VDD header pin.
Inputs and Outputs
1.
Ensure that the audio source is set to the minimum level.
2.
Connect the audio source to Inputs INL± and INR±.
3.
Connect the speakers to Outputs OUTL± and OUTR±.
The shutdown select header controls the shutdown function of
the SSM2302. The shutdown pin on the SSM2302 is active low,
meaning that a low voltage (GND) on this pin places the SSM2302
into shutdown mode.
1.
Select jumper to 1-2 position. Shutdown pulled to VDD.
2.
Select jumper to 2-3 position. Shutdown pulled to GND.
Input Configurations
1.
For differential input configuration with input capacitors
do not place a jumper on JP8, JP9, JP10, and JP11.
2.
For differential input configuration without input capacitors
place a jumper on JP8, JP9, JP10, and JP11.
Rev. 0 | Page 14 of 20
SSM2302
SSM2302 APPLICATION BOARD SCHEMATIC
JP2
POWER
JP8
HEADER 2
C7
0.1µF
1 2
C8
INL+
L2
FERRITE BEAD
SD
C9
C1
1nF
JP3
1
2
OUT LEFT
C2
1nF
OUTL– 1
VDD
NC
VDD
1 2
GND
C10
16
15
14
U1
SSM2302
L1
FERRITE BEAD
GAIN
0.01µF
2 1
JP11
HEADER 2
GAIN
1
2
OUT RIGHT
C4
1nF
VDD
R3
100kΩ
C3
1nF
L2
FERRITE BEAD
C11
0.01µF
VDD
13
VDD
JP12
1
3
5
2
4
6
HEADER 13C
SD
R4
100kΩ
Figure 28. SSM2302 Application Board Schematic
Rev. 0 | Page 15 of 20
06051-034
INR–
OUTR–
8
GND
NC
OUTR+
7
INL–
12
JP10
HEADER 2
6
11
JP9
HEADER 2
5
OUTL+ 2
0.01µF
2 1
RIN+
3
RIN–
2
1
RIGHT IN
C5
10µF
0.01µF
INL+ 4
SD 3
3
2
1
LEFT IN
LIN+
LIN–
C6
0.1µF
L1
FERRITE BEAD
9
INR+
10 GAIN
JP1
1 2
VDD
SSM2302
SSM2302 STEREO CLASS-D AMPLIFIER EVALUATION MODULE COMPONENT LIST
Table 6.
Reference
C8, C9, C10, C11
C6, C7
C5
C1, C2, C3, C4
R3, R4
L1, L2, L3, L4
U1
EVAL BOARD
Description
Capacitors, 0.01 μF
Capacitor, 0.1 μF
Capacitor, 10 μF
Capacitor, 1 nF
Resistor, 100 kΩ
Ferrite bead
IC, SSM2302
PCB evaluation board
Footprint
0402
0603
0805
0402
0603
0402
3.0 mm × 3.0 mm
Quantity
4
2
1
4
2
4
1
1
Rev. 0 | Page 16 of 20
Manufacturer/Part Number
Murata Manufacturing Co., Ltd./GRM15
Murata Manufacturing Co., Ltd./GRM18
Murata Manufacturing Co., Ltd./GRM21
Murata Manufacturing Co., Ltd./GRM15
Vishay/CRCW06031003F
Murata Manufacturing Co., Ltd./BLM15EG121
SSM2302CSPZ
SSM2302
06051-035
SSM2302 APPLICATION BOARD LAYOUT
Figure 29. SSM2302 Application Board Layout
Rev. 0 | Page 17 of 20
SSM2302
OUTLINE DIMENSIONS
3.00
BSC SQ
0.60 MAX
0.45
PIN 1
INDICATOR
TOP
VIEW
13
12
2.75
BSC SQ
0.80 MAX
0.65 TYP
12° MAX
16
1
EXPOSED
PAD
0.50
BSC
0.90
0.85
0.80
0.50
0.40
0.30
PIN 1
INDICATOR
*1.65
1.50 SQ
1.35
9 (BOTTOM VIEW) 4
8
5
0.25 MIN
1.50 REF
0.05 MAX
0.02 NOM
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
*COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2
EXCEPT FOR EXPOSED PAD DIMENSION.
Figure 30. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
3 mm × 3 mm Body, Very Thin Quad
(CP-16-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model
SSM2302CPZ-R2 1
SSM2302CPZ-REEL1
SSM2302CPZ-REEL71
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Z = Pb-free part.
Rev. 0 | Page 18 of 20
Package Option
CP-16-3
CP-16-3
CP-16-3
Branding
A15
A15
A15
SSM2302
NOTES
Rev. 0 | Page 19 of 20
SSM2302
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06051-0-6/06(0)
Rev. 0 | Page 20 of 20