Single-Channel, 1024-Position, Digital Rheostat with I2C Interface and 50-TP Memory AD5175 FEATURES FUNCTIONAL BLOCK DIAGRAM VDD POWER-ON RESET RDAC REGISTER SCL SDA I2C SERIAL INTERFACE A 10 W 50-TP MEMORY BLOCK ADDR RESET VSS APPLICATIONS AD5175 EXT_CAP GND 08719-001 Single-channel, 1024-position resolution 10 kΩ nominal resistance 50-times programmable (50-TP) wiper memory Rheostat mode temperature coefficient: 35 ppm/°C 2.7 V to 5.5 V single-supply operation ±2.5 V to ±2.75 V dual-supply operation for ac or bipolar operations I2C-compatible interface Wiper setting and memory readback Power on refreshed from memory Resistor tolerance stored in memory Thin LFCSP, 10-lead, 3 mm × 3 mm × 0.8 mm package Compact MSOP, 10-lead 3 mm × 4.9 mm × 1.1 mm package Figure 1. Mechanical rheostat replacements Op-amp: variable gain control Instrumentation: gain, offset adjustment Programmable voltage to current conversions Programmable filters, delays, time constants Programmable power supply Sensor calibration GENERAL DESCRIPTION The AD5175 is a single-channel, 1024-position digital rheostat that combines industry leading variable resistor performance with nonvolatile memory (NVM) in a compact package. This device supports both dual-supply operation at ±2.5 V to ±2.75 V and single-supply operation at 2.7 V to 5.5 V, and offers 50-times programmable (50-TP) memory. The AD5175 device wiper settings are controllable through the I2C–compatible digital interface. Unlimited adjustments are allowed before programming the resistance value into the 50-TP memory. The AD5175 does not require any external voltage supply to facilitate fuse blow and there are 50 opportunities for permanent programming. During 50-TP activation, a permanent blow fuse command freezes the resistance position (analogous to placing epoxy on a mechanical rheostat). The AD5175 is available in a 3 mm × 3mm 10-lead LFCSP package and in a 10-lead MSOP package. The part is guaranteed to operate over the extended industrial temperature range of −40°C to +125°C. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved. AD5175 TABLE OF CONTENTS Features .............................................................................................. 1 Shift Register ............................................................................... 12 Applications ....................................................................................... 1 Write Operation.......................................................................... 13 Functional Block Diagram .............................................................. 1 Read Operation........................................................................... 15 General Description ......................................................................... 1 RDAC Register............................................................................ 16 Revision History ............................................................................... 2 50-TP Memory Block ................................................................ 16 Specifications..................................................................................... 3 Write Protection ......................................................................... 16 Electrical Characteristics ............................................................. 3 50-TP Memory Write-Acknowledge Polling .......................... 18 Interface Timing Specifications .................................................. 4 Reset ............................................................................................. 18 Absolute Maximum Ratings............................................................ 6 Shutdown Mode ......................................................................... 18 Thermal Resistance ...................................................................... 6 RDAC Architecture .................................................................... 18 ESD Caution .................................................................................. 6 Programming the Variable Resistor ......................................... 18 Pin Configuration and Function Descriptions ............................. 7 EXT_CAP Capacitor.................................................................. 19 Typical Performance Characteristics ............................................. 8 Terminal Voltage Operating Range ......................................... 19 Test Circuits ..................................................................................... 11 Power-Up Sequence ................................................................... 19 Theory of Operation ...................................................................... 12 Outline Dimensions ....................................................................... 20 Serial Data Interface ................................................................... 12 Ordering Guide .......................................................................... 20 REVISION HISTORY 3/10—Revision 0: Initial Version Rev. 0 | Page 2 of 20 AD5175 SPECIFICATIONS ELECTRICAL CHARACTERISTICS VDD = 2.7 V to 5.5 V, VSS = 0 V; VDD = 2.5 V to 2.75 V, VSS = −2.5 V to −2.75 V; −40°C < TA < +125°C, unless otherwise noted. Table 1. Parameter DC CHARACTERISTICS—RHEOSTAT MODE Resolution Resistor Integral Nonlinearity 2, 3 Symbol Test Conditions/Comments Min R-INL |VDD − VSS| = 3.6 V to 5.5 V |VDD − VSS| = 3.3 V to 3.6 V |VDD − VSS| = 2.7 V to 3.3 V Resistor Differential Nonlinearity2 Nominal Resistor Tolerance Resistance Temperature Coefficient 4, 5 Wiper Resistance RESISTOR TERMINALS Terminal Voltage Range4, 6 Capacitance A4 Capacitance W4 Common-Mode Leakage Current4 DIGITAL INPUTS Input Logic4 High Low Input Current Input Capacitance4 DIGITAL OUTPUT Output Voltage4 High Low R-DNL 10 −1 −1 −2.5 −1 Tristate Leakage Current Output Capacitance4 POWER SUPPLIES Single-Supply Power Range Dual-Supply Power Range Supply Current Positive Negative 50-TP Store Current4, 7 Positive Negative 50-TP Read Current4, 8 Positive Negative Power Dissipation 9 Power Supply Rejection Ratio4 VSS f = 1 MHz, measured to GND, code = half scale f = 1 MHz, measured to GND, code = half scale V A = VW VINH VINL IIN CIN VOH VOL Max +1 +1.5 +2.5 +1 ±15 35 35 Code = full scale Code = zero scale VTERM Typ 1 70 VDD 90 40 50 2.0 0.8 ±1 5 RPULL_UP = 2.2 kΩ to VDD RPULL_UP = 2.2 kΩ to VDD VDD = 2.7 V to 5.5 V, VSS = 0 V VDD = 2.5 V to 2.75 V, VSS = −2.5 V to −2.75 V VDD − 0.1 2.7 ±2.5 IDD_OTP_READ ISS_OTP_READ PDISS PSRR 5.5 ±2.75 V V 1 μA μA 4 −4 mA mA 500 −500 VIH = VDD or VIL = GND ΔVDD/ΔVSS = ±5 V ± 10% Rev. 0 | Page 3 of 20 5.5 −50 V V μA pF V V μA pF −1 IDD_OTP_STORE ISS_OTP_STORE V pF pF nA 0.4 0.6 +1 5 IDD ISS Bits LSB LSB LSB LSB % ppm/°C Ω V −1 VSS = 0 V Unit −55 μA μA μW dB AD5175 Parameter DYNAMIC CHARACTERISTICS4, 10 Bandwidth Total Harmonic Distortion Resistor Noise Density Symbol Test Conditions/Comments −3 dB, RAW = 5 kΩ, Terminal W, see Figure 23 VA = 1 V rms, f = 1 kHz, RAW = 5 kΩ RWB = 5 kΩ, TA = 25°C, f = 10 kHz Min Typ 1 700 −90 13 Max Unit kHz dB nV/√Hz 1 Typical specifications represent average readings at 25°C, VDD = 5 V, and VSS = 0 V. Resistor position nonlinearity error (R-INL) is the deviation from the ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. 3 The maximum current in each code is defined by IAW = (VDD − 1)/RAW. 4 Guaranteed by design and not subject to production test. 5 See Figure 8 for more details. 6 Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground referenced bipolar signal adjustment. 7 Different from operating current; the supply current for the fuse program lasts approximately 55 ms. 8 Different from operating current; the supply current for the fuse read lasts approximately 500 ns. 9 PDISS is calculated from (IDD × VDD) + (ISS × VSS). 10 All dynamic characteristics use VDD = +2.5 V, VSS = −2.5 V. 2 INTERFACE TIMING SPECIFICATIONS VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter fSCL 2 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t11A t12 t13 tSP 3 tEXEC 4, 5 Conditions 1 Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode High speed mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Limit at TMIN, TMAX Min Max 100 400 4 0.6 4.7 1.3 250 100 0 3.45 0 0.9 4.7 0.6 4 0.6 160 4.7 1.3 4 0.6 1000 300 300 300 1000 300 1000 Unit kHz kHz μs μs μs μs ns ns μs μs μs μs μs μs ns μs μs μs μs ns ns ns ns ns ns ns Fast mode 300 ns Standard mode Fast mode RESET pulse time Fast mode 300 300 ns ns ns ns ns 20 0 500 50 Description Serial clock frequency Serial clock frequency tHIGH, SCL high time tHIGH, SCL high time tLOW, SCL low time tLOW, SCL low time tSU;DAT, data setup time tSU;DAT, data setup time tHD;DAT, data hold time tHD;DAT, data hold time tSU;STA, set-up time for a repeated start condition tSU;STA, set-up time for a repeated start condition tHD;STA, hold time (repeated) start condition tHD;STA, hold time (repeated) start condition tHD;STA, hold time (repeated) start condition tBUF, bus free time between a stop and a start condition tBUF, bus free time between a stop and a start condition tSU;STO, setup time for a stop condition tSU;STO, setup time for a stop condition tRDA, rise time of the SDA signal tRDA, rise time of the SDA signal tFDA, fall time of the SDA signal tFDA, fall time of the SDA signal tRCL, rise time of the SCL signal tRCL, rise time of the SCL signal tRCL1, rise time of the SCL signal after a repeated start condition and after an acknowledge bit tRCL1, rise time of the SCL signal after a repeated start condition and after an acknowledge bit tFCL, fall time of the SCL signal tFCL, fall time of the SCL signal Minimum RESET low time Pulse width of the spike is suppressed Command execute time Rev. 0 | Page 4 of 20 AD5175 Parameter tRDAC_R-PERF tRDAC_NORMAL tMEMORY_READ tMEMORY_PROGRAM tRESET tPOWER-UP 6 Limit at TMIN, TMAX Min Max 2 600 6 350 600 2 Conditions 1 Unit μs ns μs ms μs ms Description RDAC register write command execute time (R-Perf mode) RDAC register write command execute time (normal mode) Memory readback execute time Memory program time Reset 50-TP restore time Power-on 50-TP restore time 1 Maximum bus capacitance is limited to 400 pF. The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on EMC behavior of the part. 3 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode. 4 Refer to tRDAC_R-PERF and tRDAC_NORMAL for RDAC register write operations. 5 Refer to tMEMORY_READ and tMEMORY_PROGRAM for memory commands operations. 6 Maximum time after VDD − VSS is equal to 2.5 V. 2 Shift Register and Timing Diagrams DB9 (MSB) 0 C3 0 C1 C2 C0 D9 D8 DB0 (LSB) D7 D6 D4 D5 D3 D2 D1 D0 08719-003 DATA BITS CONTROL BITS Figure 2. Shift Register Content t11 t12 t6 t8 t2 SCL t6 t4 t5 t1 t10 t3 t9 SDA t7 S S t13 P 08719-002 P RESET Figure 3. 2-Wire I2C Timing Diagram Rev. 0 | Page 5 of 20 AD5175 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter VDD to GND VSS to GND VDD to VSS VA, VW to GND Digital Input and Output Voltage to GND EXT_CAP to VSS IA, IW Pulsed 1 Frequency > 10 kHz Frequency ≤ 10 kHz Continuous Operating Temperature Range 3 Maximum Junction Temperature (TJ Maximum) Storage Temperature Range Reflow Soldering Peak Temperature Time at Peak Temperature Package Power Dissipation Rating –0.3 V to +7.0 V +0.3 V to −7.0 V 7V VSS − 0.3 V, VDD + 0.3 V −0.3 V to VDD + 0.3 V 7V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θJA is defined by JEDEC specification JESD-51 and the value is dependent on the test board and test environment. Table 4. Thermal Resistance ±6 mA/d 2 ±6 mA/√d2 ±6 mA −40°C to +125°C 150°C Package Type 10-Lead LFCSP 10-Lead MSOP 1 JEDEC 2S2P test board, still air (0 m/sec airflow). −65°C to +150°C ESD CAUTION 260°C 20 sec to 40 sec (TJ max − TA)/θJA θJA 50 1351 1 Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A and W terminals at a given resistance. 2 Pulse duty factor. 3 Includes programming of 50-TP memory. Rev. 0 | Page 6 of 20 θJC 3 N/A Unit °C/W °C/W AD5175 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 10 ADDR VDD 1 A 2 W 3 VSS 4 10 ADDR 9 SCL 8 SDA 7 RESET 6 GND AD5175 TOP VIEW (Not to Scale) EXT_CAP 5 EXT_CAP 5 9 SCL 8 SDA W 3 VSS 4 08719-004 VDD 1 AD5175 (EXPOSED PAD)* 7 RESET 6 GND *LEAVE FLOATING OR CONNECTED TO VSS. Figure 4. MSOP Pin Configuration 08719-103 A 2 Figure 5. LFCSP Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 2 3 4 Mnemonic VDD A W VSS 5 EXT_CAP 6 7 GND RESET 8 SDA 9 SCL 10 EPAD ADDR Exposed Pad Description Positive Power Supply. Decouple this pin with 0.1 μF ceramic capacitors and 10 μF capacitors. Terminal A of RDAC. VSS ≤ VA ≤ VDD. Wiper Terminal of RDAC. VSS ≤ VW ≤ VDD. Negative Supply. Connect to 0 V for single-supply applications. Decouple this pin with 0.1 μF ceramic capacitors and 10 μF capacitors. External Capacitor. Connect a 1 μF capacitor between EXT_CAP and VSS. This capacitor must have a voltage rating of ≥7 V. Ground Pin, Logic Ground Reference. Hardware Reset Pin. Refreshes the RDAC register with the contents of the 50-TP memory register. Factory default loads midscale until the first 50-TP wiper memory location is programmed. RESET is active low. Tie RESET to VDD if not used. Serial Data Line. This pin is used in conjunction with the SCL line to clock data into or out of the 16-bit input registers. It is a bidirectional, open-drain data line that should be pulled to the supply with an external pull-up resistor. Serial Clock Line. This pin is used in conjunction with the SDA line to clock data into or out of the 16-bit input registers. Tristate Address Input. Sets the two least significant bits (Bit A1, Bit A0) of the 7-bit slave address (see Table 6). Leave floating or connected to VSS Rev. 0 | Page 7 of 20 AD5175 TYPICAL PERFORMANCE CHARACTERISTICS 0.8 0.7 +25°C –40°C +125°C 0.6 0.5 CURRENT (mA) 0.2 0 –0.2 0.4 0.3 0.2 0.1 –0.4 0 128 256 384 512 640 768 896 1023 CODE (Decimal) –0.1 08719-014 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VOLTAGE (V) 08719-038 INL (LSB) 0.4 –0.6 VDD/VSS = 5V/0V 0.6 Figure 9. Supply Current (IDD) vs. Digital Input Voltage Figure 6. R-INL in Normal Mode vs. Code vs. Temperature 500 0.4 +25°C –40°C +125°C 0.3 400 IDD = 5V 300 200 CURRENT (nA) 0.1 0 IDD = 3V 100 ISS = 3V 0 –100 –200 –0.1 ISS = 5V –300 –0.2 128 256 384 512 640 768 896 1023 CODE (Decimal) –500 –40 –30 –20 –10 0 TEMPERATURE (°C) Figure 7. R-DNL in Normal Mode vs. Code vs. Temperature Figure 10. Supply Current (IDD, ISS) vs. Temperature 7 VDD/VSS = 5V/0V VDD/VSS = 5V/0V 6 THEORETICAL lWA_MAX (mA) 600 500 400 300 200 100 5 4 3 2 1 0 128 256 384 512 640 768 CODE (Decimal) 896 1023 08719-019 RHEOSTAT MODE TEMPCO (ppm/°C) 700 0 10 20 30 40 50 60 70 80 90 100 110 08719-018 0 08719-015 –0.3 –400 Figure 8. Tempco ΔRWA/ΔT vs. Code 0 0 85 170 255 340 425 510 595 680 765 850 935 1023 CODE (Decimal) Figure 11. Theoretical Maximum Current vs. Code Rev. 0 | Page 8 of 20 08719-028 DNL (LSB) 0.2 AD5175 0 –20 –10 0x100 –15 PSRR (dB) –35 0x040 –25 0x020 –30 0x010 –40 –45 –50 –45 –50 0x004 0x002 –55 0x001 1 –40 0x008 VDD/VSS = 5V/0V 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) –60 10 08719-031 –35 VDD/VSS = 5V/0V CODE = HALF SCALE –30 0x080 –20 GAIN (dB) –25 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 12. Bandwidth vs. Frequency vs. Code 08719-024 –5 0x200 Figure 15. PSRR vs. Frequency 8 0 VDD/VSS = ±2.5V CODE = HALF SCALE fIN = 1V rms –20 NOISE BW = 22kHz 7 VOLTAGE (V) THD + N (dB) –40 –60 6 –80 5 –100 1k 10k 1M 100k FREQUENCY (Hz) 0.07 0.11 0.13 20 10kΩ GLITCH AMPLITUDE (mV) –40 –60 VDD/VSS = ±2.5V CODE = HALF SCALE fIN = 1kHz NOISE BW = 22kHz VDD/VSS = ±2.5V IAW = 200µA 0.01 0 –10 –20 –30 –40 –50 –60 0.1 AMPLITUDE (V rms) 1 –70 –2 08719-026 THD + N (dB) –20 –100 0.001 0.17 Figure 16. VEXT_CAP Waveform While Writing Fuse 10 –80 0.15 TIME (Seconds) Figure 13. THD + N vs. Frequency 0 0.09 0 2 TIME (µs) Figure 17. Maximum Glitch Energy Figure 14. THD + N vs. Amplitude Rev. 0 | Page 9 of 20 4 08719-102 100 08719-029 4 10 08719-039 –120 AD5175 1.0 0.006 VDD/VSS = 5V/0V IAW = 10µA CODE = HALF SCALE 0.005 ΔRAW RESISTANCE (%) 0 –0.5 0.004 0.003 0.002 0.001 0 –1.0 0 10 20 30 40 TIME (µs) 50 60 Figure 18. Digital Feedthrough –0.002 0 100 200 300 400 500 600 700 800 900 1000 OPERATION AT 150°C (Hours) Figure 19. Long-Term Drift Accelerated Average by Burn-In Rev. 0 | Page 10 of 20 08719-101 –1.5 –10 –0.001 VDD/VSS = ±2.5V IAW = 200µA 08719-100 VOLTAGE (mV) 0.5 AD5175 TEST CIRCUITS Figure 20 to Figure 24 define the test conditions used in the Specifications section. DUT IW A A VMS 08719-033 Figure 23. Gain vs. Frequency Figure 20. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL) RWA = CODE = 0x00 IW W RW = DUT VMS IW GND 08719-034 +2.75V V+ = VDD ±10% V+ PSS (%/%) = NC = NO CONNECT –2.75V Figure 24. Common Leakage Current PSRR (dB) = 20 log IW GND NC Figure 21. Wiper Resistance W +2.75V –2.75V A 2 A VDD GND ICM W RWA VMS V VMS VDD ΔVMS% ΔVDD% VMS 08719-035 A Figure 22. Power Supply Sensitivity (PSS, PSRR) Rev. 0 | Page 11 of 20 08719-037 VMS DUT 1GΩ W W 08719-036 DUT AD5175 THEORY OF OPERATION The AD5175 is designed to operate as a true variable resistor for analog signals within the terminal voltage range of VSS < VTERM < VDD. The RDAC register contents determine the resistor wiper position. The RDAC register acts as a scratchpad register, which allows unlimited changes of resistance settings. The RDAC register can be programmed with any position setting using the I2C interface. When a desirable wiper position is found, this value can be stored in a 50-TP memory register. Thereafter, the wiper position is always restored to that position for subsequent power-up. The storing of 50-TP data takes approximately 350 ms; during this time, the AD5175 is locked and does not acknowledge any new command thereby preventing any changes from taking place. The acknowledge bit can be polled to verify that the fuse program command is complete. SERIAL DATA INTERFACE The AD5175 has a 2-wire I2C-compatible serial interface. It can be connected to an I2C bus as a slave device under the control of a master device; see Figure 3 for a timing diagram of a typical write sequence. The AD5175 supports standard (100 kHz) and fast (400 kHz) data transfer modes. Support is not provided for 10-bit addressing and general call addressing. The AD5175 has a 7-bit slave address. The five MSBs are 01011 and the two LSBs are determined by the state of the ADDR pin. The facility to make hardwired changes to ADDR allows the user to incorporate up to three of these devices on one bus, as outlined in Table 6. The 2-wire serial bus protocol operates as follows: The master initiates a data transfer by establishing a start condition, which is when a high-to-low transition on the SDA line occurs while SCL is high. The next byte is the address byte, which consists of the 7-bit slave address and a R/W bit. The slave device corresponding to the transmitted address responds by pulling SDA low during the ninth clock pulse (this is termed the acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to, or read from, its shift register. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL. When all data bits have been read or written, a stop condition is established. In write mode, the master pulls the SDA line high during the 10th clock pulse to establish a stop condition. In read mode, the master issues a no acknowledge for the ninth clock pulse, that is, the SDA line remains high. The master then brings the SDA line low before the 10th clock pulse, and then high during the 10th clock pulse to establish a stop condition. SHIFT REGISTER For the AD5175, the shift register is 16 bits wide, as shown in Figure 2. The 16-bit word consists of two unused bits, which should be set to 0, followed by four control bits and 10 RDAC data bits, and data is loaded MSB first (Bit D9). The four control bits determine the function of the software command (Table 7). Figure 25 shows a timing diagram of a typical AD5175 write sequence. The command bits (Cx) control the operation of the digital potentiometer and the internal 50-TP memory. The data bits (Dx) are the values that are loaded into the decoded register. Table 6. Device Address Selection ADDR Pin GND VDD NC (No Connection) 1 1 A1 1 0 1 A0 1 0 0 Not available in bipolar mode. VSS < 0 V. Rev. 0 | Page 12 of 20 7-Bit I2C Device Address 0101111 0101100 0101110 AD5175 Two bytes of data are then written to the RDAC, the most significant byte followed by the least significant byte; both of these data bytes are acknowledged by the AD5175. A stop condition follows. The write operations for the AD5175 are shown in Figure 25. WRITE OPERATION It is possible to write data for the RDAC register or the control register. When writing to the AD5175, the user must begin with a start command followed by an address byte (R/W = 0), after which the AD5175 acknowledges that it is prepared to receive data by pulling SDA low. A repeated write function gives the user flexibility to update the device a number of times after addressing the part only once, as shown in Figure 26. 1 9 1 9 SCL 0 1 0 1 1 A1 A0 R/W 0 0 C3 C2 C1 C0 D9 D8 ACK. BY AD5175 START BY MASTER ACK. BY AD5175 FRAME 2 MOST SIGNIFICANT DATA BYTE FRAME 1 SERIAL BUS ADDRESS BYTE 9 9 1 SCL (CONTINUED) SDA (CONTINUED) D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY AD5175 FRAME 3 LEAST SIGNIFICANT DATA BYTE Figure 25. Write Command Rev. 0 | Page 13 of 20 STOP BY MASTER 08719-005 SDA AD5175 1 9 1 9 SCL 0 1 0 1 1 A1 A0 R/W START BY MASTER 0 0 C3 C2 C1 C0 D9 D8 ACK. BY AD5175 ACK. BY AD5175 FRAME 1 SERIAL BUS ADDRESS BYTE FRAME 2 MOST SIGNIFICANT DATA BYTE 9 9 1 SCL (CONTINUED) SDA (CONTINUED) D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY AD5175 FRAME 3 LEAST SIGNIFICANT DATA BYTE 9 1 9 SCL (CONTINUED) 0 SDA (CONTINUED) 0 C3 C2 C1 C0 D9 D8 ACK. BY AD5175 FRAME 4 MOST SIGNIFICANT DATA BYTE 9 1 9 SCL (CONTINUED) SDA (CONTINUED) D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY AD5175 FRAME 5 LEAST SIGNIFICANT DATA BYTE Figure 26. Multiple Write Rev. 0 | Page 14 of 20 STOP BY MASTER 08719-006 SDA AD5175 READ OPERATION which enables readback of the RDAC register, 50-TP memory, or the control register. The user can then read back the data beginning with a start command followed by an address byte (R/W = 1), after which the device acknowledges that it is prepared to transmit data by pulling SDA low. Two bytes of data are then read from the device, as shown in Figure 27. A stop condition follows. If the master does not acknowledge the first byte, the second byte is not transmitted by the AD5175. When reading data back from the AD5175, the user must first issue a readback command to the device, this begins with a start command followed by an address byte (R/W = 0), after which the AD5175 acknowledges that it is prepared to receive data by pulling SDA low. Two bytes of data are then written to the AD5175, the most significant byte followed by the least significant byte; both of these data bytes are acknowledged by the AD5175. A stop condition follows. These bytes contain the read instruction, 1 9 1 9 SCL SDA 0 1 0 1 1 A1 A0 R/W 0 0 C3 C2 C1 C0 D9 D8 ACK. BY AD5175 START BY MASTER ACK. BY AD5175 FRAME 1 SERIAL BUS ADDRESS BYTE FRAME 2 MOST SIGNIFICANT DATA BYTE 1 9 9 SCL (CONTINUED) SDA (CONTINUED) D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY AD5175 STOP BY MASTER FRAME 3 LEAST SIGNIFICANT DATA BYTE 1 9 1 9 SCL 0 1 0 1 1 A1 A0 R/W 0 0 X X X X D9 D8 ACK. BY AD5175 START BY MASTER ACK. BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE FRAME 2 MOST SIGNIFICANT DATA BYTE 9 9 1 SCL (CONTINUED) SDA (CONTINUED) D7 D6 D5 D4 D3 D2 D1 D0 NO ACK. BY STOP BY MASTER MASTER FRAME 3 LEAST SIGNIFICANT DATA BYTE Figure 27. Read Command Rev. 0 | Page 15 of 20 08719-007 SDA AD5175 Prior to 50-TP activation, the AD5175 presets to midscale on power-up. It is possible to read back the contents of any of the 50-TP memory registers through the I2C interface by using Command 5 in Table 7. The lower six LSB bits, D0 to D5 of the data byte, select which memory location is to be read back. A binary encoded version address of the most recently programmed wiper memory location can be read back using Command 6 in Table 7. This can be used to monitor the spare memory status of the 50-TP memory block. RDAC REGISTER The RDAC register directly controls the position of the digital rheostat wiper. For example, when the RDAC register is loaded with all 0s, the wiper is connected to Terminal A of the variable resistor. It is possible to both write to and read from the RDAC register using the I2C interface. The RDAC register is a standard logic register; there is no restriction on the number of changes allowed. 50-TP MEMORY BLOCK WRITE PROTECTION The AD5175 contains an array of 50-TP programmable memory registers, which allow the wiper position to be programmed up to 50 times. Table 11 shows the memory map. Command 3 in Table 7 programs the contents of the RDAC register to memory. The first address to be programmed is Location 0x01, see Table 11, and the AD5175 increments the 50-TP memory address for each subsequent program until the memory is full. Programming data to 50-TP consumes approximately 4 mA for 55 ms, and takes approximately 350 ms to complete, during which time the shift register is locked preventing any changes from taking place. Bit C2 of the control register in Table 10 can be polled to verify that the fuse program command was successful. No change in supply voltage is required to program the 50-TP memory; however, a 1 μF capacitor on the EXT_CAP pin is required as shown in Figure 29. On power-up, serial data input register write commands for both the RDAC register and the 50-TP memory registers are disabled. The RDAC write protect bit (Bit C1) of the control register (see Table 9 and Table 10), is set to 0 by default. This disables any change of the RDAC register content regardless of the software commands, except that the RDAC register can be refreshed from the 50-TP memory using the software reset, Command 4, or through the hardware by the RESET pin. To enable programming of the variable resistor wiper position (programming the RDAC register), the write protect bit (Bit C1) of the control register must first be programmed. This is accomplished by loading the serial data input register with Command 7 (see Table 7). To enable programming of the 50-TP memory block, Bit C0 of the control register, which is set to 0 by default, must first be set to 1. Table 7. Command Operation Truth Table D7 X D7 Data[DB9:DB0] 1 D6 D5 D4 D3 X X X X D6 D5 D4 D3 D2 X D2 D1 X D1 D0 X D X X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 X X X X D5 D4 D3 D2 D1 D0 1 0 X X X X X X X X X X 1 1 1 X X X X X X X X D1 D0 0 0 0 0 0 1 X X X X X X X X X X X X X X X X X X X D0 Command Number 0 1 Command[DB13:DB10] C3 C2 C1 C0 0 0 0 0 0 0 0 1 D9 X D9 D8 X D8 2 3 0 0 0 0 1 1 0 1 X X 4 0 1 0 0 52 0 1 0 6 0 1 73 0 8 9 1 1 1 2 3 X is don’t care. See Table 11 for the 50-TP memory map. See Table 10 for bit details. Rev. 0 | Page 16 of 20 Operation NOP: do nothing. Write contents of serial register data to RDAC. Read contents of RDAC wiper register. Store wiper setting: store RDAC setting to 50-TP. Software reset: refresh RDAC with the last 50-TP memory stored value. Read contents of 50-TP from the SDO output in the next frame. Read address of the last 50-TP programmed memory location. Write contents of the serial register data to the control register. Read contents of the control register. Software shutdown. D0 = 0; normal mode. D0 = 1; shutdown mode. AD5175 Table 8. Write and Read to RDAC and 50-TP Memory DIN 0x1C03 0x0500 0x0800 0x0C00 SDO1 0xXXXX 0x1C03 0x0500 0x100 0x1800 0x0000 0x0C00 0xXX19 0x1419 0x2000 0x0000 0x0100 0x0000 0xXXXX 1 Action Enable update of wiper position and 50-TP memory contents through digital interface. Write 0x100 to the RDAC register, wiper moves to ¼ full-scale position. Prepare data read from RDAC register. Stores RDAC register content into 50-TP memory. 16-bit word appears out of SDO, where the last 10-bits contain the contents of the RDAC Register 0x100. Prepare data read of the last programmed 50-TP memory monitor location. NOP Instruction 0 sends a 16-bit word out of SDO, where the six LSBs (that is, the last 6 bits) contain the binary address of the last programmed 50-TP memory location, for example, 0x19 (see Table 11). Prepares data read from Memory Location 0x19. Prepare data read from the control register. Sends a 16-bit word out of SDO, where the last 10-bits contain the contents of Memory Location 0x19. NOP Instruction 0 sends a 16-bit word out of SDO, where the last four bits contain the contents of the control register. If Bit C2 = 1, fuse program command successful. X is don’t care. Table 9. Control Register Bit Map DB9 0 DB8 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 C2 DB2 0 DB1 C1 DB0 C0 Table 10. Control Register Description Bit Name C0 C1 C2 1 Description 50-TP program enable 0 = 50-TP program disabled (default) 1 = enable device for 50-TP program RDAC register write protect 0 = wiper position frozen to value in OTP memory (default)1 1 = allow update of wiper position through a digital interface 50-TP memory program success bit 0 = fuse program command unsuccessful (default) 1 = fuse program command successful Wiper position is frozen to the last value programmed in the 50-TP memory. Wiper freezes to midscale if 50-TP memory has not been previously programmed. Table 11. Memory Map Command Number 5 1 D9 X X X X X … X … X … X … X … X … X X D8 X X X X X … X … X … X … X … X … X X D7 X X X X X … X … X … X … X … X … X X Data Byte[DB9:DB0]1 D6 D5 D4 D3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 … … … … 0 0 0 1 … … … … 0 0 1 0 … … … … 0 0 1 1 … … … … 0 1 0 1 … … … … 0 1 1 0 … … … … 0 1 1 1 0 1 1 1 D2 0 0 0 0 1 … 0 … 1 … 1 … 0 … 0 … 0 0 X is don’t care. Rev. 0 | Page 17 of 20 D1 0 0 1 1 0 … 1 … 0 … 1 … 0 … 1 … 0 1 D0 0 1 0 1 0 … 0 … 0 … 0 … 0 … 0 … 1 0 Register Contents Reserved 1st programmed wiper location (0x01) 2nd programmed wiper location (0x02) 3rd programmed wiper location (0x03) 4th programmed wiper location (0x04) … 10th programmed wiper location (0xA) … 20th programmed wiper location (0x14) … 30th programmed wiper location (0x1E) … 40th programmed wiper location (0x28) … 50th programmed wiper location (0x32) … MSB resistance tolerance (0x39) LSB resistance tolerance (0x3A) AD5175 50-TP MEMORY WRITE-ACKNOWLEDGE POLLING RDAC ARCHITECTURE After each write operation to the 50-TP registers, an internal write cycle begins. The I2C interface of the device is disabled. To determine if the internal write cycle is complete and the I2C interface is enabled, interface polling can be executed. I2C interface polling can be conducted by sending a start condition followed by the slave address and the write bit. If the I2C interface responds with an acknowledge (ACK), the write cycle is complete and the interface is ready to proceed with further operations. Otherwise, I2C interface polling can be repeated until it completes. To achieve optimum performance, Analog Devices, Inc., has patented the RDAC segmentation architecture for all the digital potentiometers. In particular, the AD5175 employs a three-stage segmentation approach, as shown in Figure 28. The AD5175 wiper switch is designed with the transmission gate CMOS topology. A RL RESET RL The AD5175 can be reset through software by executing Command 4 (see Table 7) or through hardware on the low pulse of the RESET pin. The reset command loads the RDAC register with the contents of the most recently programmed 50-TP memory location. The RDAC register loads with midscale if no 50-TP memory location has been previously programmed. Tie RESET to VDD if the RESET pin is not used. RM RM 10-BIT ADDRESS DECODER SW RW W 08719-008 RW SHUTDOWN MODE Figure 28. Simplified RDAC Circuit The AD5175 can be shut down by executing the software shutdown command, Command 9 (see Table 7), and setting the LSB to 1. This feature places the RDAC in a zero-powerconsumption state where Terminal A is disconnected from the wiper terminal. It is possible to execute any command from Table 7 while the AD5175 is in shutdown mode. The part can be taken out of shutdown mode by executing Command 9 and setting the LSB to 0, or by issuing a software or hardware reset. PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation The nominal resistance between Terminal W and Terminal A, RWA, is available in 10 kΩ and has 1024-tap points accessed by the wiper terminal. The 10-bit data in the RDAC latch is decoded to select one of the 1024 possible wiper settings. As a result, the general equation for determining the digitally programmed output resistance between the W terminal and A terminal is D (1) RWA (D) = × RWA 1024 where: D is the decimal equivalent of the binary code loaded in the 10-bit RDAC register. RWA is the end-to-end resistance. In the zero-scale condition, a finite total wiper resistance of 120 Ω is present. Regardless of which setting the part is operating in, take care to limit the current between the A terminal to W terminal, and W terminal to B terminal, to the maximum continuous current of ±6 mA, or the pulse current specified in Table 3. Otherwise, degradation or possible destruction of the internal switch contact can occur. Rev. 0 | Page 18 of 20 AD5175 Calculate the Actual End-to-End Resistance TERMINAL VOLTAGE OPERATING RANGE The resistance tolerance is stored in the internal memory during factory testing. The actual end-to-end resistance can, therefore, be calculated (which is valuable for calibration, tolerance matching, and precision applications). The positive VDD and negative VSS power supplies of the AD5175 define the boundary conditions for proper 2-terminal digital resistor operation. Supply signals present on Terminal A and Terminal W that exceed VDD or VSS are clamped by the internal forward-biased diodes (see Figure 30). The resistance tolerance in percentage is stored in fixed-point format, using a 16-bit sign magnitude binary. The sign bit(0 = negative and 1 = positive) and the integer part is located in Address 0x39, as shown in Table 11. Address 0x3A contains the fractional part, as shown in Table 12. VDD A That is, if the data readback from Address 0x39 is 0000001010 and data from Address 0x3A is 0010110000, then the end-to-end resistance can be calculated as follows. W DB[9:8]: XX = don’t care VSS DB[7]: 0 = negative Figure 30. Maximum Terminal Voltages Set by VDD and VSS DB[6:0]: 0001010 = 10 The ground pin of the AD5175 is primarily used as a digital ground reference. To minimize the digital ground bounce, join the AD5175 ground terminal remotely to the common ground. The digital input control signals to the AD5175 must be referenced to the device ground pin (GND) and satisfy the logic level defined in the Specifications section. An internal level shift circuit ensures that the common-mode voltage range of the three terminals extends from VSS to VDD, regardless of the digital input level. For Memory Location 0x3A, DB[9:8]: XX = don’t care DB[7:0]: 10110000 = 176 × 2−8 = 0.6875 Therefore, tolerance = −10.6875% and RWA (1023)= 8.931 kΩ. EXT_CAP CAPACITOR A 1 μF capacitor to VSS must be connected to the EXT_CAP pin (see Figure 29) on power-up and throughout the operation of the AD5175. POWER-UP SEQUENCE Because there are diodes to limit the voltage compliance at Terminal A and Terminal W (see Figure 30), it is important to power VDD/VSS first before applying any voltage to Terminal A and Terminal W; otherwise, the diode is forward-biased such that VDD/VSS are powered unintentionally. The ideal power-up sequence is VSS, GND, VDD, digital inputs, VA, and VW. The order of powering VA, VW, and digital inputs is not important as long as they are powered after VDD/VSS. AD5175 EXT_CAP C1 1µF 08719-109 For Memory Location 0x39, 50-TP MEMORY BLOCK VSS 08719-009 VSS Figure 29. EXT_CAP Hardware Setup As soon as VDD is powered, the power-on preset activates, which first sets the RDAC to midscale and then restores the last programmed 50-TP value to the RDAC register. Table 12. End-to-End Resistance Tolerance Bytes Memory Map Address 0x39 0x3A 1 DB9 X X DB8 X X DB7 Sign 2−1 DB6 26 2−2 X is don’t care. Rev. 0 | Page 19 of 20 Data Byte 1 DB5 DB4 25 24 2−3 2−4 DB3 23 2−5 DB2 22 2−6 DB1 21 2−7 DB0 20 2−8 AD5175 OUTLINE DIMENSIONS 2.48 2.38 2.23 3.10 3.00 SQ 2.90 0.50 BSC 6 PIN 1 INDEX AREA 10 1.74 1.64 1.49 EXPOSED PAD 0.50 0.40 0.30 5 TOP VIEW 0.80 0.75 0.70 PIN 1 INDICATOR (R 0.15) FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.05 MAX 0.02 NOM 0.30 0.25 0.20 0.20 REF 121009-A SEATING PLANE 1 BOTTOM VIEW Figure 31. 10-Lead Frame Chip Scale Package [LFCSP_WD] 3 mm × 3 mm Body, Very Thin, Dual Lead (CP-10-9) Dimensions shown in millimeters 3.10 3.00 2.90 10 3.10 3.00 2.90 5.15 4.90 4.65 6 1 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.30 0.15 6° 0° 0.23 0.13 0.70 0.55 0.40 COMPLIANT TO JEDEC STANDARDS MO-187-BA 091709-A 0.15 0.05 COPLANARITY 0.10 Figure 32. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD5175BRMZ-10 AD5175BRMZ-10-RL7 AD5175BCPZ-10-R2 AD5175BCPZ-10-RL7 1 RAB (kΩ) 10 10 10 10 Resolution 1,024 1,024 1,024 1,024 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 10-Lead MSOP 10-Lead MSOP 10-Lead LFCSP_WD 10-Lead LFCSP_WD Z = RoHS Compliant Part. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08719-0-3/10(0) Rev. 0 | Page 20 of 20 Package Option RM-10 RM-10 CP-10-9 CP-10-9 Branding DDR DDR DEG DEG