TC9325F TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC9325F Single-Chip DTS Microcontroller (DTS-20) The TC9325F is a single-chip digital tuning system (DTS) microcontroller incorporating a 230 MHz prescaler, PLL, and LCD driver. In addition to a 20-bit IF counter, an 8-channel, 8-bit AD converter, two types of serial interface, and buzzer function, the TC9325F offers a range of functions required for DTS, including an interrupt function, an 8-bit timer-counter, and an 8-bit pulse counter. In addition, the LCD driver features six modes combining 1/4, 1/3, and 1/2 duty and 1/2 and 1/3 bias. This product is suitable for use in a wide variety of DTS systems, from automobile to home audio, including compact stereo systems. Weight: 1.6 g (typ.) Features • • • • • • • • • • • • • • • • • • CMOS DTS microcontroller LSI with built-in 230 MHz prescaler, PLL, and LCD driver Operating voltage: PLL operating: VDD = 3.0 to 3.6 V (typ. 3.3 V) PLL off: VDD = 3.0 to 3.6 V (when CPU only operating) Crystal oscillator frequency: 4.5 MHz, 75 kHz Current dissipation: PLL operating: IDD = 3.5 mA (typ.) (crystal oscillator frequency 4.5 MHz, VHF mode) PLL off: IDD = 1 mA (typ.) (crystal oscillator frequency 4.5 MHz, CPU only operating) PLL off: IDD = 0.25 mA (typ.) (crystal oscillator frequency 75 kHz, CPU only operating) Operating temperature range: Ta = ï40 to 85°C Program memory (ROM): 16 bits × 16,384 steps Data memory (RAM): 4 bits × 1,024 words Instruction execution time: 1.78 µs (crystal oscillator frequency 4.5 MHz) 40 µs (crystal oscillator frequency 75 kHz) Stack levels: 16 General-purpose IF counter: 20-bit (CMOS input supported) AD converter: 8 bits × 8 channels LCD driver: 1/4, 1/3, 1/2 duty, 1/2, 1/3 bias modes selectable, 136 segments maximum I/O ports: CMOS I/O ports: 40 Output-only ports: Up to 31, input-only ports: Up to 5 Timer-counter: 8-bit (as timer clock: INTR1, INTR2, instruction cycle, or 1 kHz selectable) Pulse counter: 8-bit up/down counter (input from INTR2 pin) Buzzer: 0.625 to 3 kHz (8 settings) Four modes: Continuous, Single-Shot, 10-Hz Intermittent, 10-Hz Intermittent at 1-Hz Intervals Interrupts: 2 external, 4 internal (three types of serial interface, 8-bit timer) Package: QFP-100 (0.65-mm pitch) 1 2002-05-14 TC9325F P3-0 (ADIN5) P3-1 (ADIN6) P3-2 (ADIN7) P3-3 (ADIN8) GND VDD2 P4-0 P4-1 (SI1/SI2) P4-2 (SO1/SO2) P4-3 (SCK1/SCK2) P5-0 (BUZR) P5-1 (SI3/SI4) P5-2 (SO3/SO4) P5-3 (SCK3/SCK4) MUTE TEST HOLD INTR1 INTR2 (CTRIN) IFIN1 (IN1) IFIN2 (IN2) GND FMIN AMIN VDD NC DO1 DO2 (OUT) TEST2 P6-0 Pin Assignment 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P6-1 81 P6-2 82 P6-3 83 P7-0 84 P7-1 85 P7-2 86 P7-3 87 P8-0 88 P8-1 89 P8-2 90 P8-3 91 PLL Interrupt input SIO SIO I/O ports I/O ports AD converter (8 channels) I/O ports 50 P2-3 (ADIN4) 49 P2-2 (ADIN3) 58 P2-1 (ADIN2) 47 P2-0 (ADIN1) 46 DCREF 45 P1-3 44 P1-2 43 P1-1 42 P1-0 41 GND 40 RESET I/O ports QFP-100 (0.65-mm pitch) NC 92 39 VDD1 GND 93 38 P10-3 (S34) XOUT2 94 37 P10-2 (S33) XIN2 95 36 P10-1 (S32) 35 P10-0 (S31) 34 P9-3 (S30) 33 P9-2 (S29) 32 P9-1 (S28) 31 P9-0 (S27) 2 OT30 (S26) OT29 (S25) OT28 (S24) OT27 (S23) OT26 (S22) OT7 (S3) OT25 (S21) OT6 (S2) OT24 (S20) OT5 (S1) OT23 (S19) OT4 (COM4/S35) OT22 (S18) OT3 (COM3/S36) OT21 (S17) 7 OT20 (S16) 6 OT19 (S15) 5 OT18 (S14) 4 OT17 (S13) 3 OT16 (S12) 2 OT15 (S11) 1 OT2 (COM2) 100 OT1 (COM1) VEE LCD driver (1/4, 1/3, 1/2 duty, 1/2, 1/3 bias, 136 segments max) 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 OT14 (S10) 99 OT13 (S9) GND1 OT12 (S8) 98 OT11 (S7) XIN1 I/O ports Oscillator 1 (4.5 MHz) OT10 (S6) 97 OT9 (S5) 96 OT8 (S4) VDD XOUT1 Oscillator 2 (75 kHz) 2002-05-14 TC9325F Block Diagram Serial interface-2 Mute MUTE TEST R/W buf. G-reg. Timer P5-3 (SCK3/SCK4) P5-2 (SO3/SO4) HOLD Port5 INTR1 INTR2 (PCTRIN) P5-1 (SI3/SI4) Interrupt control ALU RAM (4 × 1024 word) Up/down counter IFIN1 (IN1) IF counter IFIN2 (IN2) Buzzer Serial interface-1 Data register (16 bit) GND FMIN P5-0 (BUZR) P4-3 (SCK1/SCK2) PLL P4-2 (SO1/SO2) AMIN Port4 P4-1 (SI1/SI2) NC P4-0 VDD Phase comp. DO2 (OUT) VDD2 Instruction decoder ROM DO1 GND (16 × 16384 step) P3-3 (ADIN8) Port3 TEST2 P3-0 (ADIN5) P6-0 P2-3 (ADIN4) Port6 Port2 P6-3 P7-0 Program counter Port7 P7-3 P8-0 A/D conv. Stack register (16 level) Port8 P8-3 P2-0 (ADIN1) DCref P1-3 Port1 P1-0 GND NC Reset RESET GND XOUT2 XIN2 75 kHz oscilator XIN1 P10-3 (S34) Port10 OSC cont. VDD XOUT1 VDD1 CPU P10-0 (S31) Peripheral P9-3 (S30) 4.5 MHz oscilator Port9 P9-0 (S27) GND1 LCD driver VEE 3 OT30 (S26) OT29 (S25) OT28 (S24) OT27 (S23) OT26 (S22) OT25 (S21) OT24 (S20) OT23 (S19) OT22 (S18) OT21 (S17) OT20 (S16) OT19 (S15) OT12 (S8) OT11 (S7) OT10 (S6) OT9 (S5) OT8 (S4) OT7 (S3) OT6 (S2) OT5 (S1) OT4 (COM4/S35) COM2 (OT2) OT3 (COM3/S36) COM1 (OT1) Output port 2002-05-14 TC9325F Pin No. Symbol 1 OT1/COM1 Pin Name Output port /LCD common output 2 3 4 OT2/COM2 OT3/COM3 /S36 OT4/COM4 /S35 OT5/S1 ~ 5~30 OT30/S26 P9-0/S27 ~ 31~34 P9-3/S30 P10-0/S31 ~ 35~38 P10-3/S34 40 RESET Output port /LCD common output /LCD segment output Output port /LCD segment output Function and Operation Remarks Output ports. Pins OT1 to OT20 can be incremented by software, allowing easy data access to external RAM/ROM. Can be set to LCD driver output by software. At 1/4 duty, controller can display up to 136 segments using a matrix consisting of COM1 to 4 and SEG1 to 34. At 1/3 duty, can display up to 105 segments using a matrix consisting of COM1 to 3 and SEG1 to 35. At 1/2 duty, can display up to 72 segments using a matrix consisting of COM1 to 2 and SEG1 to 36. Set to output ports after a system reset or clock stop. VDD1 VEEH /VEEM /VEEL 4-bit CMOS I/O ports. Input and output can be programmed I/O port 9 /LCD segment output in 1-bit units. These can be set bit by bit to LCD driver output by software. After a system reset, set to I/O port input. When a clock stop is executed, the I/O port 10 Input pins used as the LCD driver must be /LCD segment output set to output Low level (function as an instruction I/O port). Reset input Device’s system reset signal input pin. Setting RESET to Low level triggers a reset. When the pin is set to High, the program starts from address 0. Since system reset will start if the voltage beyond 0 V to 3.5 V is supplied to VDD pin, this pin is used by fixed to “H” level. VDD1 VEEH /VEEL VDD 4-bit CMOS I/O port. Input and output can be programmed in 1-bit unit. VDD P1-0 ~ 42~45 I/O port 1 P1-3 Input instruction 4 2002-05-14 TC9325F Pin No. Symbol Pin Name 46 DCREF AD converter reference voltage input P2-0 /ADIN1 ~ 47~50 P2-3 /ADIN4 P3-0 /ADIN5 ~ 51~54 P3-3 /ADIN8 I/O port 2 /A/D analog voltage input I/O port 3 /A/D analog voltage input 57 P4-0 I/O port 4 58 P4-1 /SI1 /SI2 Serial data input 1 /Serial data input 2 59 P4-2 /SO1 /SO2 Serial data input/output 1 /Serial data input 2 60 P4-3 /SCK1 /SCK2 Serial clock input/output 1 /Serial clock input 2 Function and Operation Remarks AD converter reference voltage input pin. Normally apply VDD. 4-bit CMOS I/O ports. Input and output can be programmed in 1-bit unit. Pins P2-0 to P3-3 are also used for the built-in 8-bit, 8-channel AD converter analog input. A built-in AD converter is a comparison system one by one. When using a 4.5 MHz oscillator, the conversion clock can be selected among 900 kHz, 100 kHz, and 50 kHz. When using a 75 kHz oscillator, the conversion clock is set to 75 kHz. The conversion times are respectively 23, 192, 382, and 294 µs. The necessary pins can be programmed to A/D analog input in 1-bit units. Voltage up to the VDD can be input as the AD converter analog input voltage. Settings for the AD converter and its associated control can be performed by software. 4-bit CMOS I/O ports. Input and output can be programmed in 1-bit unit. Pins P4-1 to P4-3 also input/output the two serial interface circuits (SIO1, SIO2). On the clock edge of the SCK1 pin, SIO1 can input 4-bit or 8-bit serial data to pin SI1 or input/output data to pin SO1. The clock (SCK1) of serial operation can perform selection of an inside (SCK = 37.5 kHz) /exterior, and can perform control of various LSI, and communication between controllers easily. Enabling the SIO1 interrupt jumps the program to address 4 when SIO1 execution completes. On the falling edge of the SCK2 pin, SIO2 can input 26-bit serial data to the SI2 pin. SIO2 incorporates a data detector. Enabling the SIO2 interrupt triggers the interrupt on the falling edge of the SCK2 pin and jumps the program to address 6. The SIO1 and SIO2 inputs all incorporate Schmitt circuits. SIO1 and SIO2 and their associated controls can be used and set by software. 5 To AD converter VDD To AD converter Input instruction VDD Input instruction (P4-0) VDD Input instruction + SIOon (P4-1~P4-3) 2002-05-14 TC9325F Pin No. Symbol Pin Name I/O port 5 /buzzer output 61 P5-0/BUZR 62 P5-1 /SI3 /Serial data input 3 63 P5-2 /SO3 /SO4 /Serial data input/output 3 /Serial data input/output 4 64 P5-3 /SCK3 /SCK4 /Serial clock input/output 3 /Serial clock input/output 4 65 66 MUTE TEST Muting output port Test mode control input Function and Operation Remarks 4-bit CMOS I/O ports. Input and output can be programmed in 1-bit unit. Pin 5-0 is also used to output a buzzer signal. Pins P5-1 to P5-3 are also VDD used to input/output the two serial interface circuits (SIO3, SIO4). The buzzer output can be selected between eight frequency settings (0.625 to 3 kHz), which can be output in four modes: Continuous, Single-Shot, 10 Hz-Intermittent, and 10-Hz Intermittent at 1-Hz Intervals. SIO3 is a serial interface supporting Input instruction three lines, while the SIO4 serial (P5-0) interface supports two lines. On the clock edge of the SCK3/SCK4 pin, SIO3/SIO4 can input 4- or 8-bit serial data to pin SI3 or output data to the SO3/SO4 pin. As the serial operating clock (SCK3/SCK4), an internal (450/225/150/75 kHz) clock or VDD external clock can be selected. Rising and falling shift can also be selected. The clock data output is N-channel open drain. This design facilitates LSI control and communication between controllers. Enabling the SIO3 or SIO4 interrupts triggers the interrupt and jumps the program to address 3 when interface Input instruction + SIOon SIO3 or SIO4 completes execution. (P5-1~P5-3) This is effective for high-speed serial communications. All of the input of SIO3 and SIO4 built-in the Schmitt circuits. SIO3, SIO4, and their associated controls can be used and set by software. 1-bit output port. Normally used as a muting control signal output. This pin can set the internal MUTE bit to 1 according to changes in the I/O port 8 input and HOLD input. The MUTE bit output logic can be changed. VDD Input pin for controlling Test mode. When the pins are at High level, the device is in Test mode; at Low level, in normal operation. Normally, set the pins to Low level or NC (pull-down resistors are incorporated). VDD RIN2 6 2002-05-14 TC9325F Pin No. 67 68 69 Symbol HOLD INTR1 INTR2 /PCTRin Pin Name Function and Operation Hold mode control input Input pin for requesting and releasing Hold mode. Normally used to input radio mode selection or battery detection signals. Hold mode includes Clock Stop mode (crystal oscillator stopped) and Wait mode (CPU stopped), which can be set by the CKSTP and WAIT instructions respectively. Clock Stop mode can be entered by software in one of two ways: forcibly or when Low level is detected on the HOLD pin. Clock Stop mode can be released when High level is detected on the HOLD pin or when the input changes. Executing the CKSTP instruction stops the clock generator and CPU, entering memory backup mode. In this state the device is set to low current dissipation (10 µA max). Wait mode is executed, regardless of the HOLD pin input state, and the device is set to low current dissipation. To set wait mode, specify by software either crystal oscillator only operating or CPU suspended. Wait mode is released when the HOLD pin input changes. External interrupt input /pulse count input External interrupt input pins. Enabling the interrupt function and inputting a pulse (of at least 1.11 to 3.33 µs when the 4.5 MHz clock is in use, or at least 13.3 to 40 µs when the 75 kHz clock used) to these input pins generates an interrupt (INTR1/2) and jumps the program to address 1/2. The input logic and the clock edge (rising/falling) can be individually selected for each interrupt input. The internal 8-bit timer clock can be selected as input to the pins. At the pulse count or when the count reaches a specified value, an interrupt can be generated (to address 5). These pins are also used to input an 8-bit pulse counter. This counter can be selected between rising and falling edge input and between an up-counter and a down-counter. These pins are Schmitt inputs and can also be used as input ports. The pins can also be utilized as ports for inputting remote control signals or tape counts. 7 Remarks VDD VDD 2002-05-14 TC9325F Pin No. 70 71 73 74 Symbol IFIN1/IN1 IFIN2/IN2 FMIN AMIN Pin Name Function and Operation IF signal inputs /input port IF signal input pins for the IF counter to count the IF signals of the FM and AM bands and detect the automatic stop position. The input frequency is in the range 0.3 to 20 MHz. A built-in input amp and capacitive coupling support low-amplitude operation. The IF counter is a 20-bit counter with selectable gate times of 1, 4, 16, and 64 ms. 20 bits of data can be easily stored in memory. In Manual mode, the gates can be switched on and off by instruction. These input pins can also be programmed as an input port (IN port). At that time, they become CMOS inputs and the clocks of those inputs can be counted using the IF counter. Note: Pins set as IF input go Low in PLL Off mode. FM local oscillation signal input AM local oscillation signal input Programmable counter input pins for the FM/AM band. Their input mode can be switched by software among 1/2 + pulse swallow (VHF/FM) mode for FM input, and pulse swallow (HF) or direct division (LF) mode for AM input. The local oscillation output (voltage-controlled oscillator or VCO output) is normally input at the following frequencies: 50 to 230 MHz in VHF mode, 50 to 140 MHz in FM1 mode, 10 to 60 MHz in FM2 mode, 1 to 30 MHz in HF mode, and 0.5 to 20 MHz in LF mode. A built-in input amp and capacitive coupling support low-amplitude operation. Note: In PLL Off mode or when the pins are not set for input, the input goes to high impedance. 8 Remarks RFIN VDD RFIN VDD RFIN VDD 2002-05-14 TC9325F Pin No. 77 78 79 Symbol DO1 DO2/OUT TEST2 Pin Name Function and Operation Phase comparator output /output port PLL phase comparator output pins. In tri-state output, when the programmable counter divider output is higher than the reference frequency, the pins output High level; when the output is lower than the reference frequency, the pins output Low level. When the outputs match, the pins go to high impedance. Because DO1 and DO2 are output in parallel, optimal filter constants can be designed for both the AM and FM bands. The DO2 pin can be programmed to high impedance or set as an output port (OUT). Therefore, lockup time can be improved using the DO1 and DO2 pins or the pins can be effectively used as output ports. Lock-up time can also be improved by using DO1 and DO2 together by setting the pins to High-Speed Lock mode when using a 4.5 MHz oscillator. When the phase difference equals or exceeds ±1.11 µs, DO1 and DO2 output the phase difference pulse. When the phase difference is less than ±1.11 µs, the DO2 output goes to high impedance and only DO1 outputs the phase difference pulse. Test mode control input 2 Remarks VDD Input pin for controlling Test mode. When the pins are at High level, the device is in Test mode; at Low level, in normal operation. Normally, set the pins to Low level or NC (pull-down resistors are incorporated). VDD RIN2 P6-0 ~ 80~83 I/O port 6 4-bit CMOS I/O ports. Input and output can be programmed in 1-bit units. VDD P6-3 P7-0 ~ 84~87 Input instruction I/O port 7 P7-3 P8-0 ~ 88~91 P8-3 I/O port 8 4-bit CMOS I/O port. Input and output can be programmed in 1-bit unit. As the pins can be pulled up or pulled down by software they can be used as key input pins. When set to an I/O port input, that input can be varied to release Clock Stop or Wait modes or to set the MUTE bit of the MUTE pin to 1. VDD VDD VDD RIN1 9 2002-05-14 TC9325F Pin No. 94 Symbol Pin Name XOUT2 75 kHz crystal oscillator pins 95 97 XIN2 Function and Operation Crystal oscillator pins. Connect a 4.5 MHz crystal (Ci = Co = 30 pF typ.) to XIN1 and XOUT1 and a 75 kHz crystal (Ci = Co = 30 pF typ.) to XIN2 and XOUT2. Two different types of crystal resonators (4.5 MHz and 75 kHz) can be connected, or simply connect one (4.5 MHz or 75 kHz). Note that if a 75 kHz crystal only is connected, XIN1 must be fixed to GND level. If both 4.5 MHz and 75 kHz crystal oscillators are connected, after a reset the CPU operates on the 4.5 MHz crystal oscillator clock. The clock can be readily switched by software between the CPU operating clock and the peripheral clock. Oscillation stops during execution of the CKSTP instruction. Remarks XOUT2 ROUT2 RfXT2 VDD XIN2 XOUT1 XOUT1 ROUT1 RfXT1 VDD 4.5 MHz crystal oscillator pins 98 XIN1 100 VEE 76 96 VDD 41 55 72 93 LCD driver bias voltage output pin This is the bias voltage output pin for the LCD driver. Power supply pins Pins used for supplying power. The pins supply VDD = 3.0 to 3.6 V. In backup state (when execution of the CKSTP instruction), current dissipation becomes low (10 µA max), dropping the power supply voltage to 2.0 V. If 3.0 V or more is applied to these pins when the voltage is 0 V, a system reset is applied to the device and the program starts from address 0 (power-on reset). Note: To operate the power-on reset, allow 10 to 100 ms while the device power supply voltage rises. GND 39 VDD1 99 GND1 XIN1 56 VDD2 Power supply pins For I/O Port4,5 72 93 NC No connection Pins used for supplying power for I/O port 4,5.The pins supply VDD = VDD to 5.5 V. VDD GND VDD2 No connection 10 2002-05-14 TC9325F Description of Operations ż CPU The CPU consists of a program counter, a stack register, an ALU, program memory, data memory, a G-register, a data register, a DAL address register, a carry flip-flop (F/F), a judge circuit, and an interrupt circuit. . Program Counter (PC) The program counter is a 14-bit binary up counter used to address program memory (ROM). The program counter is cleared by a system reset and starts from address 0. The PC is normally incremented by 1 at the execution of each instruction. However, executing a Jump or Call instruction loads the address specified in the instruction’s operand to the PC. When an instruction with a skip function (for example, the AIS, SLTI, TMT, and RNS instructions) is executed and the result matches the skip condition, the PC is incremented by 2 and the next instruction is skipped. When an interrupt is received, the system loads the vector address corresponding to the interrupt. Note: Program memory (ROM) uses the address range 0000H to 3FFFH. Access to addresses outside this range is prohibited. Contents of Program Counter (PC) Instruction PC13 PC12 PC11 PC10 PC9 PC8 JUMP ADDR1 CALL ADDR2 PC7 PC6 PC5 PC4 PC3 PC1 PC0 Instruction operand (ADDR1) 0 0 0 0 Instruction operand (ADDR2) DAL ADDR3, (r) (DAL bit = 0) PC2 0 0 Contents of general register (r) Instruction operand (ADDR3) DAL (DA) DAL address register (DA) (DAL bit = 1) RN, RNS, RNI Contents of stack register When interrupt received Power-on reset, reset by RESET pin Vector address for interrupt 0 0 0 0 0 0 0 0 Priority Interrupt Source Vector Address 1 INTR1 pin 0001H 2 INTR2 pin 0002H 3 Serial interface 1 0003H 4 Serial interface 3/4 0004H 5 Timer-counter 0005H 6 Serial interface 2 0006H 0 0 0 0 0 0 2. Stack Register The stack register consists of 16 × 14 bits. When a subroutine call instruction is executed or an interrupt is processed, this register stores a value equal to the contents of the program counter + 1 (that is, the return address). Executing a return instruction (RN, RNS, RNI) loads the contents of the stack register to the program counter. The stack register can nest to 16 stack levels. 11 2002-05-14 TC9325F 3. ALU The arithmetic and logic unit (ALU) has a binary 4-bit parallel addition-subtraction function, a logical operation function, a compare function, and a multiple bit judge function. The CPU does not include an accumulator; all operations directly use the contents of the data memory. 4. Program Memory (ROM) Program memory, which stores the program, is made up of 16 bits × 16,384 steps. The useable address range is the 16,384 steps of the range 0000H to 3FFFH. The program memory divides the 16,384 steps into 16 pages (pages 0 to 15). The address area available to Jump instructions is from 0000H to 3BFFH (pages 0 to 14). The area for Call instructions is 0000H to 03FFH (page 0). When the DAL bit (located in the I/O map) is set to 0 (DAL ADDR3, (r) instruction), area 3C00H to 3FFFH (page 15) of program memory can be used as data area. When the DAL bit is set to 1 (DAL (DA) instruction) the area 0000H to 3FFFH (pages 0 to 7) is available as data area. At that time the DAL instruction can load any 16 bits within the data area to the data register. Note: Set the data area in program memory to addresses outside the program loop. ROM 16 bits Vector address at interrupt 0000H 0001H 0400H 0002H Page 1 0003H 0800H 0004H Page 2 0005H 0C00H 0006H Page 3 Interrupt vector address 0000H Jump destination address at initialization Page 0 (1-k steps) INTR1 INTR2 Serial interface 3/4 Serial interface 1 8-bit timer Serial interface 2 1000H Page 4 Page 6 1C00H Page 7 2000H Page 8 2400H Page 9 2800H Page 10 Area available to Call instruction 1800H Area available to Jump instruction Page 5 Area available to DAL instruction 1400H *1: Area accessible with the DAL instruction when DAL bit = 0. *2: Area accessible with the DAL instruction when DAL bit = 1. Note: The DAL bit is located on the I/O map. *2 2C00H Page 11 3000H Page 12 3400H Page 13 3800H Page 14 3C00H Page 15 *1 3FFFH 12 2002-05-14 TC9325F 5. Data Memory (RAM) Data memory, which stores the data, is made up of 4 bits x 1,024 words. The 1,024 words are identified by a row address (8 bits) and a column address (4 bits). 1,020 words (row address = 04H to 3FH) are for indirect addressing by the G-register. Accordingly, when processing data in this area be sure to first set the G-register to specify the row address. Data memory area 00H to 0FH is called the general registers and can be used simply by specifying the (4 bits) column address. The 16 general registers can be used in data memory operations and transfers. The general registers can also be used as normal data memory. Note: The (4 bits) column address specifying the general register is used as the general register’s register number. Note: All row addresses (00H to 3FH) can be indirectly specified by the G-register. Note: The LD and ST instructions can directly address 256 words of data memory (row address area 00H to 0FH). COLMUN ADDRESS: DC ROW ADDRESS: DR 0 1 2 3 4 5 6 7 8 9 A B C D E F Row addresses (04H to FFH) indirectly specified by G-register * Row address area 00H to 0FH can be indirectly specified. * General register (any register within 000H to 00FH) 0 1 2 3 4 5 6 7 8 9 A B C D E F 10 11 12 The LD and ST instructions can directly specify row addresses (00H to 0FH). 3C 3D 3F 13 2002-05-14 TC9325F 6. G-register (G-REG) The G-register is an 8-bit register for addressing the 1,024 words of row address in data memory (row address = 04H to 3FH). The MVGD or MVGS instruction validates the contents of the G-register. Other instructions have no effect. The G-register is treated as a port. OUT1, an I/O instruction, sets the contents of the G-register. (See the section on register ports.) The STIG instruction can also be used to directly set 8-bit content in the G-register. 7. Data Register (DATA REG) This register, which consists of 1 × 16 bits, is loaded with 16 bits of data from anywhere in program memory on execution of the DAL instruction. The data register is treated as a port. Executing I/O instruction IN1 reads the contents of the register to data memory using four bits. (See the section on register ports.) This register, which can also be written from data memory, can be used for saving and restoring data when an interrupt occurs. 8. DAL Address Register (DA) This register consists of 1 × 14 bits. Executing the DAL instruction with the DAL bit set to 1 loads 16 bits of data from any program memory address specified by the DAL address register. Setting the (DATA) → DA bit to 1 transfers the contents of the data register (DATA REG) to the DAL address register (DA). This register and its control bit are treated as a port and can be accessed by the IN3/OUT3 I/O instruction. (See the section on register ports.) 9. Carry F/F (Ca Flag) This F/F is set when a Carry or Borrow occurs as the result of an arithmetic instruction. When a Carry or Borrow does not occur the F/F is reset. The contents of the Carry F/F change only on execution of an addition/subtraction, CLT, or CLTC instruction. The contents are not affected by the execution of any other instruction. The Carry F/F can also be accessed by the IN1/OUT1 I/O instruction. Accordingly, an I/O instruction is used to save and restore data in data memory at an interrupt. (See the section on register ports.) 0. Judge Circuit (J) This circuit is used to determine the skip condition when an instruction with a skip function is executed. If the skip condition is satisfied, the program counter is incremented by 2 and the next instruction is skipped. A total of 15 instructions have skip functions. (See instructions with the * symbol in the list of instruction functions and operations in 11.) . Interrupt Circuit The interrupt circuit branches to various vector addresses in response to demands from peripheral hardware and handles interrupts. (See the section on interrupt functions.) 14 2002-05-14 TC9325F 2. Instruction Set List The TC9325F has a total of 57 instruction sets, all using one-word instructions. These instructions use 6-bit instruction code. Upper 2 bits Lower 4 bits 00 01 10 11 0 1 2 3 0000 0 AI M, I TMTR r, M SLTI M, I 0001 1 AIC M, I TMFR r, M SGEI M, I 0010 2 SI M, I SEQ r, M SEQI M, I 0011 3 SIB M, I SNE r, M SNEI M, I 0100 4 ORIM M, I TMTN M, N 0101 5 ANIM M, I TMT M, N TMFN M, N TMF M, N IN1 M, C IN2 M, C LD 0110 6 XORIM M, I 0111 7 MVIM M, I 1000 8 AD r, M 1001 9 AC r, M r, M* JUMP ADDR1 ST M*, r 1010 A SU r, M IN3 M, C 1011 B SB r, M OUT1 M, C 1100 C ORR r, M CLT r, M OUT2 M, C 1101 D ANDR r, M CLTC r, M OUT3 M, C 1110 E XORR r, M MVGD r, M DAL ADDR3, r SHRC M RORC M STIG I* SKP, SKPN RN, RNS 1111 F MVSR M1, M2 MVGS M, r CAL ADDR2 WAIT P CKSTP XCH M DI, EI, RNI NOOP 15 2002-05-14 TC9325F 3. List of Instruction Functions and Operations (Description of symbols in list) M ; Data memory address Normally, an address in the data memory range 000H to 01FH. M* ; Data memory address (1,024 words) An address in the data memory range 000H to 3FFH. (Valid only at ST, LD instruction execution) r ; General register An address in the data memory range 000H to 00FH. PC ; Program counter (14 bits) STACK ; Stack register (14 bits) G ; G-register (8 bits) DATA ; Data register (16 bits) I ; Immediate data (4 bits) I* ; Immediate data (6 bits; valid only at execution of STIG instruction) N ; Bit position (4 bits) − ; All 0 C ; Code number of port (4 bits) CN ; Code number of port (4 bits) RN ; General register No. (4 bits) ADDR1 ; Program memory address (14 bits) ADDR2 ; Program memory address in page 0 (10 bits) ADDR3 ; Upper 6 bits of program memory address in page 0 DA ; DAL address register (14 bits, valid only at execution of DAL instruction when DAL bit set to 1) Ca ; Carry CY ; Carry flag P ; Wait condition b ; Borrow IN1~IN3 ; IN1 to IN3: The ports used at IN1 to IN3 instruction execution OUT1 to OUT3 ; The ports used at OUT1 to OUT3 instruction execution () ; Contents of registers or data memory []C ; Contents of the port indicated by code No. C (4 bits) [] ; Contents of data memory indicated by the register or data memory []P ; Contents of program memory (16 bits) IC ; Instruction code (6 bits) * ; Instruction with skip function DC ; Data memory column address (4 bits) DR ; Data memory row address (4 bits) DR* ; Data memory row address (4 bits, valid only at execution of ST or LD instruction) (M) b0 to (M) b3 ; Bit data of data memory contents (1 bit) 16 2002-05-14 TC9325F Compare instruction Subtraction instruction Addition instruction Instruction Set Mnemonic Skip Function Description Operation IC (6 bits) Machine Language (16 bits) A B C (2 bits) (4 bits) (4 bits) AI M, I Add immediate data M ← (M) + I to memory 000000 DR DC I AIC M, I Add immediate data to memory with M ← (M) + I + ca carry 000001 DR DC I AD r, M Add memory to general register 001000 DR DC RN AC r, M Add memory to general register with r ← (r) + (M) + ca carry 001001 DR DC RN SI M, I Subtract immediate data from memory M ← (M) − I 000010 DR DC I SIB M, I Subtract immediate data from memory with borrow M ← (M) − I − b 000011 DR DC I SU r, M Subtract memory from general register r ← (r) − (M) 001010 DR DC RN SB r, M Subtract memory from general register with borrow r ← (r) − (M) − b 001011 DR DC RN SLTI M, I * Skip if memory is less than immediate Skip if (M) < I data 110000 DR DC I SGEI M, I * Skip if memory is greater than or equal to immediate data Skip if (M) > =I 110001 DR DC I SEQI M, I * Skip if memory is equal to immediate data Skip if (M) = I 110010 DR DC I SNEI M, I * Skip if memory is not equal to immediate data Skip if (M) ≠ I 110011 DR DC I SEQ r, M * Skip if general register is equal to memory Skip if (r) = (M) 010010 DR DC RN SNE r, M * Skip if general register is not equal to memory Skip if (r) ≠ (M) 010011 DR DC RN r, M Set carry flag if general register is less than memory, or reset if not (CY) ← 1 if (r) < (M) or (CY) ← 0 if (r) > = (M) 011100 DR DC RN r, M Set carry flag if general register is less than memory with carry or reset if not (CY) ← 1 if (r) < (M) + (ca) or (CY) ← 0 if (r) > = (M) + (Ca) 011101 DR DC RN CLT CLTC r ← (r) + (M) 17 2002-05-14 TC9325F Logical operation instruction I/O instruction Transfer instruction Instruction Set Mnemonic Skip Function Description Operation IC (6 bits) Machine Language (16 bits) A B C (2 bits) (4 bits) (4 bits) LD r, M* Load memory to general register r ← (M*) 0101 DR* (4 bits) DC RN ST M*, r Store memory to general register M* ← (r) 0110 DR* (4 bits) DC RN MVSR M1, M2 Move memory to memory in same row (DR, DC1) ← (DR, DC2) 001111 DR DC1 DC2 MVIM Move immediate data to memory M←I 000111 DR DC I MVGD r, M Move memory to destination memory referring to G-register and general register [(G), (r)] ← (M) 011110 DR DC RN MVGS M, r Move source memory referring to G-register and (M) ← [(G), (r)] general register to memory (Note) 011111 DR DC RN STIG I* Move immediate data to G-register G ← I* 111111 IN1 M, C Input IN1 port data to memory M ← [IN1] C 111000 DR DC CN OUT1 M, C Output contents of memory to OUT1 port [OUT1] C ← (M) 111011 DR DC CN IN2 M, C Input IN2 port data to memory M ← [IN2] C 111001 DR DC CN OUT2 M, C Output contents of memory to OUT2 port [OUT2] C ← (M) 111100 DR DC CN IN3 M, C Input IN3 port data to memory M ← [IN3] C 111010 DR DC CN OUT3 M, C Output contents of memory to OUT3 port [OUT3] C ← (M) 111101 DR DC CN ORR r, M Logical OR of general register and r ← (r) ∨ (M) memory 001100 DR DC RN ANDR r, M Logical AND of general register and r ← (r) ∧ (M) memory 001101 DR DC RN ORIM M, I Logical OR of memory and immediate data M ← (M) ∨ I 000100 DR DC I ANIM M, I Logical AND of memory and immediate data M ← (M) ∧ I 000101 DR DC I XORIM M, I Logical exclusive OR of memory and immediate data M ← (M) ∀ I 000110 DR DC I XORR r, M Logical exclusive OR of general r ← (r) ∀ (M) register and memory 001110 DR DC RN M, I I* 0010 Note: The MVGS instruction execution time is two machine cycles. 18 2002-05-14 TC9325F Instruction Set Mnemonic Interrupt instruction Jump instruction Subroutine instruction Bit judge instruction TMTR r, M Skip Function Description Operation IC (6 bits) Machine Language (16 bits) A B C (2 bits) (4 bits) (4 bits) * Test general register bits by memory bits, Skip if r [N (M)] = all then skip if all bits “1” specified are true 010000 DR DC RN 010001 DR DC RN TMFR r, M * Test general register bits by memory bits, Skip if r [N (M)] = all then skip if all bits “0” specified are false TMT M, N * Test memory bits, then skip if all bits specified are true Skip if M (N) = all “1” 110101 DR DC N Skip if M (N) = all “0” 110111 DR DC N TMF M, N * Test memory bits, then not skip if all bits specified are false TMTN M, N * Test memory bits, then skip if all bits specified are true Skip if M (N) = not all “1” 110100 DR DC N TMFN M, N * Test memory bits, then not skip if all bits specified are false Skip if M (N) = not all “0” 110110 DR DC N SKP * Skip if carry flag is true Skip if (CY) = 1 111111 00 0011 SKPN * Skip if carry flag is false Skip if (CY) = 0 111111 01 0011 CALL ADDR2 Call subroutine STACK ← (PC) + 1 and PC ← ADDR2 101111 RN Return to main routine PC ← (STACK) 111111 10 0011 RNS Return to main routine and skip unconditionally PC ← (STACK) and skip 111111 11 0011 JUMP ADDR1 Jump to address specified PC ← ADDR1 10 DI Reset IMF (Note) IMF ← 0 111111 00 0111 EI Set IMF (Note) IMF ← 1 111111 01 0111 RNI Return to main PC ← (STACK) routine and set IMF (Note) IMF ← 1 111111 11 0111 ADDR2 (10 bits) ADDR1 (14 bits) (excluding 3C00H to 3FFFH) Note: The IMF bit is an interrupt master enable flag located on the I/O map. (See the section on interrupt functions.) 19 2002-05-14 TC9325F Other instructions Instruction Set Mnemonic Skip Function Machine Language (16 bits) A B C (2 bits) (4 bits) (4 bits) Description Operation SHRC M Shift memory bits to right direction with carry 0 → (M) b3 → (M) b2 → (M) b1 → (M) b0→ (CY) 111111 DR DC 0000 RORC M Rotate memory bits to right direction with carry (M) b3 → (M) b2 → (M) b1→ (M) b0 → (CY) 111111 DR DC 0001 XCH Exchange memory bits mutually (M) b3 ↔ (M) b0, (M) b2 ↔ (M) b1 111111 DR DC 0110 IF DAL bit = 0 then load program in page 0 to DATA register. (Note) DATA ← [ADDR3 + (r)] p in page 0 111110 ADDR3 (6 bits) Wait at condition P 111111 P 0100 Stop clock generator to MODE condition 111111 0101 111111 1111 M DAL ADDR3, r IC (6 bits) At P = “0” H, the condition is CPU waiting (soft wait mode) WAIT P At P = “1” H, expect for clock generator, all function is waiting (hard wait mode) CKSTP Clock generator stop NOOP No operation RN Note: The lower 4 bits of the 10 bits of program memory specified by the DAL instruction (DAL ADDR3r) are used for indirectly addressing the contents of the general registers. Note: The DAL instruction execution time is two machine cycles. Note: The DAL bit and the DAL address register (DA) are located on the I/O map. (See the section on register ports.) Note: Executing the DAL instruction with the DAL bit set to 1 invalidates the operand. At this time the DAL address register (DA) is used for all the addresses to reference. To specify 0, 0 to be operand parts as dummy data at this time. 20 2002-05-14 TC9325F ż I/O Map All the ports in the device are accessed by six I/O instructions (OUT1 to 3 and IN1 to 3) and 4-bit code number matrices. The following pages show the port allocations as an I/O map. On the I/O map, the ports used by I/O instructions are in horizontal positions and the port code numbers are in vertical positions. The G-register, data register, DAL address register, and DAL bit are treated as ports. The OUT1 to 3 instructions specify output ports. The IN1 to 3 instructions specify input ports. Note: The diagonal lines on the I/O map indicate ports that do not exist in the device. Executing an output instruction to output data to a non-existent output port has no effect on other ports or on data memory contents. When a non-existent input port is specified by an input instruction, all the content read to the data memory is undefined. Note: Output ports indicated by an asterisk (*) on the I/O map are unused ports. Any data output to these ports are “don’t care”. Note: The contents of the ports are represented by four bits where Y1 corresponds to the lowest bit of the data in data memory, and Y8 to the highest bit. The ports specified by the six input/output instructions and by code No. C are represented in this document by the following notation. φ [K/L] m n (o) (Pp) Pages (1 to 3) Contents of selected port (indirectly specified data, 0 to F (HEX)) I/O instruction operand CN (0 to F (HEX)) The six I/O instructions (IN1 to IN3, OUT1 to OUT3) I/O Instruction OUT1 OUT2 OUT3 IN1 IN2 IN3 m 1 2 3 1 2 3 Indicates input/output ports. K: Input port (instructions IN1 to 3) L: Output port (instructions OUT1 to 3) Example: The G-register is set by the OUT1 instruction with codes C and D. Therefore, the notation is φL1C and φL1D. 21 2002-05-14 TC9325F I/O Map (IN (M, C), IN2 (M, C), IN3 (M, C), OUT (M, C), OUT2 (M, C), OUT3 (M, C)) Page 1 Y1 φL1 φL2 φL3 φK1 φK2 OUT1 OUT2 OUT3 IN1 IN2 Y2 Y4 Y8 Y1 Y2 Y4 Y8 Y1 Y2 Y4 I/O control 1 0 HF PW * Y8 Y1 I/O port 1 Y2 Y4 Y8 Y1 IF monitor Y2 φK3 IN3 Y4 Y8 Y1 Y2 SI02 decode data FM Y4 Y8 -2 -3 -2 -3 -2 -3 -2 -3 -2 -3 -2 -3 -2 -3 -2 -3 -2 -3 I/O port 1 0 -0 Programmable counter 1 -1 -2 -3 -0 -1 -2 I/O control 2 -3 BUSY MANUAL I/O port 2 OVER DCD0 IF data 1 DCD1 DCD2 DCD3 -0 -1 SI02 information data 1 I/O port 2 1 P0 P1 P2 P3 -0 Programmable counter 2 -1 -2 -3 -0 -1 -2 I/O control 3 -3 F0 F1 I/O port 3 F2 F3 INF0 IF data 2 INF1 INF2 INF3 -0 -1 SI02 information data 2 I/O port 3 2 P4 P5 P6 P7 -0 Programmable counter 3 -1 -2 -3 -0 -1 -2 I/O control 4 -3 F4 F5 I/O port 4 F6 F7 INF4 IF data 3 INF5 INF6 INF7 -0 -1 SI02 information data 3 I/O port 4 3 P8 P9 P10 P11 -0 Programmable counter 4 -1 -2 -3 -0 -1 -2 I/O control 5 -3 F8 F9 I/O port 5 F10 F11 INF8 IF data 4 INF9 INF10 INF11 -0 -1 SI02 information data 4 I/O port 5 4 P12 P13 P14 P15 -0 Programmable counter 4 -1 -2 -3 -0 -1 -2 I/O control 6 -3 F12 F13 I/O port 6 F14 F15 * * * -0 Reference select -1 -2 -3 -0 -1 -2 I/O control 7 -3 F16 F17 F18 F19 R1 R2 P3 -0 I/F counter control 1 -1 -2 -3 -0 -1 -2 I/O control 8 * IF1/IN1 IF2/IN2 -0 I/F counter control 2 -1 -2 OFS4/ CHK4 -3 I/O port 8 -3 -0 -2 OFS8/ CHK8 -3 HOLD MANUAL G0 G1 -0 Mute control 9 -2 -3 -0 I/O control 10 OFS2/ CHK2 OFS5/ CHK5 OFS6/ CHK6 OFS9/ CHK9 -2 -0 -1 I/O port 6 OFS3/ CHK3 -0 -1 I/O port 7 OFS7/ CHK7 -0 -1 INTR1 I/O port 8 0 0 INTR2 STOP F/F -3 I/O port 10 -0 -1 I/O port 9 -0 -1 Mute control I/O port 10 MUTE Unlock detect POL HOLD -0 D02 control -1 -2 -3 -0 -1 -2 -3 DAL (DATA) → DA OT Count Up I/O port 8 pulled up I/O port 8 pulled down RESET PN M0 M1 CA flag * * * -0 -1 S1 S2 -2 -3 Data selection B -1 MUTE I/O-8 A -1 OFS1/ CHK1 I/O port 9 8 STA/ STP INF15 SI02 offset/check data 2 -1 I/O control 9 INF14 SI02 offset/check data 2 7 IF1/IF2 OFS0/ CHK0 I/O port 7 6 R0 INF13 SI02 offset/check data 1 5 P16 INF12 IF data 5 G-register 1 C G0 G1 G2 G3 IO1 S8 General-purpose output data/serial interface output data/segment I/O control OT/SO OT/SO OT/SO OT/SO /SEG /SEG /SEG /SEG G-register 2 F/F ENA S1 S2 DAL address/pulse counter control DA0 DA1 DA2 0 d0 d1 d2 0 -0 -1 -2 -3 IN1 DAL 0 0 0 DA0 DA1 IN2 DAL address 0 DA3 Data register 1 Segment data 1 HOLD Input port Data selection CA flag S4 POL Unlock detect S4 S8 G-register 1 d3 G0 G1 Data register 2 DA2 DA3 Data register 1 G2 G3 d0 G-register 2 d1 d2 d3 Data register 2 D G4 G5 G6 G7 COM1 Test port 1 COM2 COM3 COM4 d4 Segment data 2 d5 d6 d7 G4 G5 G6 G7 d4 Data register 3 d5 d6 d7 Data register 3 E #0 #1 #2 Page #3 COM1 Test port 2 F COM2 COM3 COM4 d8 Segment data 3/LCD driver control d9 d10 d11 d8 Data register 4 Page Timer 0 * Page 2 Page 3 #4 COM1 COM2 COM3 COM4 d12 d13 d14 d15 22 Page 2 Page 3 d9 d10 d11 Data register 4 0 2 Hz F/F 10 Hz 100 Hz 500 Hz d12 d13 d14 d15 2002-05-14 TC9325F Page 2 Y1 φL1 φL2 φL3 φK1 φK2 OUT1 OUT2 OUT3 IN1 IN2 Y2 Y4 Y8 Y1 Interrupt control 0 POL1 (INTR1) POL2 (INTR2) EF1 (INTR1) EF2 (INTR2) * IE EF3 (SIO-3/4) -0 EF5 (timer) EF6 (SIO-2) EF4 (SIO-1) -0 ILR1 (INTR1) ILR2 (INTR2) * ILR3 (SIO-3/4) * -0 ILR5 (timer) ILR6 (SIO-2) Y2 Y4 -1 -2 -1 -2 -1 -2 ILR4 (SIO-1) -0 -1 -2 -3 -0 * -0 Timer-counter interrupt detect data 1 -1 -2 Y1 Y2 -2 -3 POL1 (INTR1) POL2 (INTR2) I/O port 2 -3 -0 -0 -1 -2 -3 EF1 (INTR1) EF2 (INTR2) -0 -1 -2 -3 EF5 (timer) -0 EF3 (SIO-3/4) 0 -2 -3 IL1 (INTR1) IL2 (INTR2) IL3 (SIO-3/4) IMF -2 -3 IL5 (timer) IL6 (SIO-2) I/O port 6 0 ID1 ID2 ID3 -0 Timer-counter interrupt detect data 2 -1 -2 -3 -0 EF4 (SIO-1) -2 -3 CT0 CT1 I/O port 7 CT2 ID5 ID6 ID7 -0 Timer-counter control 7 CK SEL0 CK SEL1 Timer reset 8 9 2 Hz F/F Reset Counter Reset HOLD PLL off control IF counter sprit GT -2 -3 -0 0 Counter Reset -0 -1 -2 * * Prescaller IN IL4 (SIO-1) -3 -0 CPU CK SEL TIMER/RE F CK SEL CA flag * * * G-register 1 C G0 G1 G2 G3 CT4 CT5 CT6 -1 -2 -3 -0 DCD1 DCD2 DCD3 -0 -1 INF1 INF2 INF5 INF6 INF9 INF3 -0 -1 INF12 INF10 INF13 INF7 -0 -1 OFS0/ CHK0 INF14 OFS1/ CHK1 INF11 -0 -1 OFS4/ CHK4 OFS2/ CHK2 OFS5/ CHK5 -2 OFS8/ CHK8 -3 OFS6/ CHK6 OFS9/ CHK9 -1 -2 INTR1 INF15 -2 -3 -2 -3 -2 -3 -0 -1 -2 -3 -2 -3 -2 -3 -2 -3 -2 -3 I/O port 6 OFS3/ CHK3 -0 -1 I/O port 7 OFS7/ CHK7 -0 -1 I/O port 8 0 0 INTR2 STOP F/F -3 I/O port 10 -3 I/O port 5 SI02 offset/check data 2 CT7 -2 I/O port 4 SI02 offset/check data 1 CT3 Y8 I/O port 3 SI02 information data 4 0 Y4 I/O port 2 SI02 offset/check data 2 -1 I/O control 10 Y2 I/O port 1 I/O port 9 -0 -1 I/O port 9 -0 -1 Mute control I/O port 10 MUTE -0 -1 -2 -3 -0 -1 -2 -3 DAL (DATA) → DA OT Count Up I/O port 8 pulled up I/O port 8 pulled-down OSC2 ON (4.5 MHz) INF8 HOLD -0 OSC1 ON (4.5 MHz) -3 Y1 SI02 information data 3 I/O port 8 -0 -1 S1 S2 -2 -3 Data selection B -2 I/O control 9 CKSTP モード INF4 Timer-counter data 2 -1 I/O control 8 Oscillation control A -1 Y8 SI02 information data 2 6 ID4 INF0 Timer-counter data 1 -1 I/O control 7 IN3 Y4 SI02 information data 1 5 ID0 DCD0 Interrupt latch 2 -1 Y2 SI02 decode data Interrupt latch 1 -1 I/O control 6 IE EF6 (SIO-2) I/O port 5 -3 Y1 Interrupt enable flag 2 I/O port 4 -3 Y8 Interrupt enable flag 1 I/O port 3 -3 Y4 Interrupt control -1 I/O control 5 * Y8 I/O port 1 I/O control 4 Interrupt latch reset 2 4 Y1 I/O control 3 Interrupt latch reset 1 3 Y8 I/O control 2 Interrupt enable flag 2 2 Y4 I/O control 1 Interrupt enable flag 1 1 Y2 φK3 IO1 S8 General-purpose output data/serial interface output data/segment I/O control OT/SO OT/SO OT/SO OT/SO /SEG /SEG /SEG /SEG G-register 2 F/F ENA S1 S2 DAL address/pulse counter control DA0 DA1 DA2 0 d0 d1 d2 0 -0 -1 -2 -3 IN1 DAL 0 0 0 DA0 DA1 IN2 DAL address 0 DA3 Data register 1 Segment data 1 HOLD Input port Data selection CA flag S4 POL Unlock detect S4 S8 G-register 1 d3 G0 G1 Data register 2 DA2 DA3 Data register 1 G2 G3 d0 G-register 2 d1 d2 d3 Data register 2 D G4 G5 G6 G7 COM1 Test port 1 COM2 COM3 COM4 d4 Segment data 2 d5 d6 d7 G4 G5 G6 G7 d4 Data register 3 d5 d6 d7 Data register 3 E #0 #1 #2 Page #3 COM1 Test port 2 F COM2 COM3 COM4 d8 Segment data 3/LCD driver control d9 d10 d11 d8 Data register 4 Page Timer 0 * Page 2 Page 3 #4 COM1 COM2 COM3 COM4 d12 d13 d14 d15 23 Page 2 Page 3 d9 d10 d11 Data register 4 0 2 Hz F/F 10 Hz 100 Hz 500 Hz d12 d13 d14 d15 2002-05-14 TC9325F Page 3 Y1 φL1 φL2 φL3 φK1 φK2 OUT1 OUT2 OUT3 IN1 IN2 Y2 Y4 Y8 Y1 A/D control 1 Y2 Y4 Y8 Y1 Y2 Y4 I/O control 1 Y8 Y1 Y2 I/O port 1 Y4 Y8 Y1 A/D data Y2 φK3 IN3 Y4 Y8 Y1 Y2 SI02 decode data Y4 Y8 -2 -3 -2 -3 -2 -3 -2 -3 -2 -3 -2 -3 -2 -3 -2 -3 -2 -3 I/O port 1 0 AD SEL0 AD SEL1 AD SEL2 STA -0 A/D control 2 -1 -2 -3 -0 -1 -2 I/O control 2 -3 AD0 AD1 I/O port 2 AD2 AD3 DCD0 A/D data DCD1 DCD2 DCD3 -0 -1 SI02 information data 1 I/O port 2 1 CK SEL1 CK SEL2 * * -0 Serial I/F-3/4 control 1 -1 -2 -3 -0 -1 -2 I/O control 3 -3 AD4 AD5 I/O port 3 AD6 AD7 INF0 A/D data INF1 INF2 INF3 -0 -1 SI02 information data 2 I/O port 3 2 edge SCK INV SCK0 SIO ON -0 Serial I/F-3/4 control 2 -1 -2 -3 -0 -1 -2 I/O control 4 -3 BUSY I/O port 4 0 0 3 STA SI1S 8 bit Nch -0 Serial I/F-3/4 control 3 4 SCK3 /SCK4 SO3/SO4 ENA -1 -2 -3 -0 -1 -2 I/O control 5 MOD -0 Serial I/F-3/4 control 4 -1 -2 -3 BUSY I/O port 5 -3 -0 COUNT SIO F/F -2 -3 SO/SDA I/O port 6 SCK/SCL ENA CK1 F/F Reset MSB -0 Serial I/F-3/4 control 5 -1 -2 -3 -0 SO-NG F/F -2 -3 STA F/F STP F/F I/O port 7 BUSY2 * * * -0 Serial I/F-1/2 control 1 -1 -2 -3 -0 0 -2 I/O control 8 -3 BUSY I/O port 8 COUNT SIO F/F SCK INV SCK0 SIO ON -0 Serial I/F-1/2 control 2 -1 -2 -3 -0 ACK -2 -3 SI0 I/O port 9 SI1 SI2 0 OFS4/ CHK4 SOI 8 BIT/CHK MOD -0 Buzzer output control 1 -1 -2 -3 -0 I/O control 10 INF9 INF10 INF13 INF14 OFS1/ CHK1 OFS2/ CHK2 OFS5/ CHK5 OFS6/ CHK6 SI3 OFS8/ CHK8 OFS9/ CHK9 -2 -3 SI4 I/O port 10 SI5 SI6 I/O port 4 INF11 -0 -1 I/O port 5 INF15 -0 -1 I/O port 6 OFS3/ CHK3 -0 -1 I/O port 7 OFS7/ CHK7 -0 -1 INTR1 0 INTR2 STOP F/F SI7 Serial I/F-1 input data 1 I/O port 8 0 Serial I/F-3/4 input data 2 -1 -1 SI02 offset/check data 2 HOLD STA -0 SI02 offset/check data 2 8 -0 -1 I/O port 9 -0 -1 Mute control 9 I/O port 10 MUTE BF0 BF1 BF2 BEN -0 Buzzer output control 2 -1 -2 -3 BM0 BM1 ON POL CA flag * * * -0 -1 S1 S2 -2 G-register 1 C G1 G2 -1 -2 -3 DAL (DATA) → DA OT Count Up I/O port 8 pulled up -3 Data selection G0 -0 I/O port 8 pulled down A B OFS0/ CHK0 Serial I/F-3/4 input data 1 -1 I/O control 9 INF7 SI02 offset/check data 1 7 edge INF12 Serial I/F-1/2 monitor -1 INF6 SI02 information data 4 6 STP INF8 Serial I/F-3/4 monitor 3 -1 I/O control 7 INF5 SI02 information data 3 5 CK0 INF4 Serial I/F-3/4 monitor 2 -1 I/O control 6 0 Serial I/F-3/4 monitor 1 G3 S4 SI1 SI2 SI3 Serial I/F-1 input data 2 IO1 DA0 DA1 DA2 SI4 SI5 SI6 SI7 CA flag 0 0 0 F/F ENA S1 S2 d0 d1 d2 HOLD -0 -1 -2 -3 DAL 0 0 0 DA0 DA1 Input port IN1 IN2 Data selection DA3 Data register 1 Segment data 1 POL Unlock detect DAL address/pulse counter control S8 General-purpose output data/serial interface output data/segment I/O control OT/SO OT/SO OT/SO OT/SO /SEG /SEG /SEG /SEG G-register 2 SI0 S4 DAL address S8 G-register 1 d3 G0 G1 Data register 2 DA2 DA3 Data register 1 G2 G3 d0 G-register 2 d1 d2 d3 Data register 2 D G4 G5 G6 G7 COM1 Test port 1 COM2 COM3 COM4 d4 Segment data 2 d5 d6 d7 G4 G5 G6 G7 d4 Data register 3 d5 d6 d7 Data register 3 E #0 #1 #2 Page #3 COM1 Test port 2 F COM2 COM3 COM4 d8 Segment data 3/LCD driver control d9 d10 d11 d8 Data register 4 Page Timer 0 * Page 2 Page 3 #4 COM1 COM2 COM3 COM4 d12 d13 d14 d15 24 Page 2 Page 3 d9 d10 d11 Data register 4 0 2 Hz F/F 10 Hz 100 Hz 500 Hz d12 d13 d14 d15 2002-05-14 TC9325F φL2B Data selection S1 S2 S4 I/O S8 φL2B Y1 Y2 φL2C φL2D φL2E φL2F OUT2 OUT2 OUT2 OUT2 Y4 Y8 Y1 Y2 General-purpose output port data 1 Y4 Y8 Y1 Y2 S1 Y4 Y8 Y1 Y2 S17 Y4 Y8 COM3 COM4 COM3 COM4 COM3 * * * S33 0 OT1 OT2 OT3 OT4 COM1 COM2 General-purpose output port data 2 COM3 COM4 COM1 COM2 S2 COM3 COM4 COM1 COM2 S18 S34 1 OT5 OT6 OT7 OT8 COM1 COM2 General-purpose output port data 3 COM3 COM4 COM1 COM2 S3 COM3 COM4 COM1 COM2 S19 S35 2 OT9 OT10 OT11 OT12 COM1 COM2 General-purpose output port data 4 COM3 COM4 COM1 COM2 S4 COM3 COM4 COM1 COM2 S20 S36 3 OT13 OT14 OT15 OT16 COM1 COM2 General-purpose output port data 5 COM3 COM4 COM1 COM2 S5 COM3 COM4 COM3 COM4 COM3 COM4 COM3 COM4 COM3 COM4 COM3 COM4 COM3 COM4 COM3 COM4 COM3 COM4 COM3 COM4 COM3 COM4 COM3 COM4 COM1 COM2 DUTY0 DUTY1 S21 4 OT17 OT18 OT19 OT20 COM1 COM2 General-purpose output port data 6 COM3 COM4 COM1 COM2 S6 S22 5 OT21 OT22 OT23 OT24 COM1 COM2 COM3 COM4 COM1 COM2 S7 General-purpose output port data 7 S23 6 OT25 OT26 OT27 OT28 COM1 COM2 General-purpose output port data 8 COM3 COM4 COM1 COM2 S8 S24 7 OT29 OT30 * * COM1 COM2 Serial I/F-3/4 output data 1 COM3 COM4 COM1 COM2 S9 S25 8 SO0 SO1 SO2 SO3 COM1 COM2 Serial I/F-3/4 output data 2 COM3 COM4 COM1 COM2 S10 S26 9 SO4 SO5 SO6 SO7 COM1 COM2 Serial I/F-1/2 output data 1 COM3 COM4 COM1 COM2 S11 S27 A SO0 SO1 SO2 SO3 COM1 COM2 Serial I/F-1/2 output data 2 COM3 COM4 COM1 COM2 S12 S28 B SO4 SO5 SO6 SO7 COM1 COM2 COM3 COM4 COM1 COM2 S13 S29 C COM1 COM2 COM3 COM4 COM1 COM2 S14 S30 D COM1 COM2 Segment I/O control 1 COM3 COM4 COM1 COM2 S15 S31 LCD control 1 E SEG27 SEG28 SEG29 SEG30 COM1 COM2 Segment I/O control 2 COM3 COM4 COM1 COM2 S16 S32 BIAS FRAME LCD control 2 F SEG31 SEG32 SEG33 SEG34 COM1 COM2 25 COM3 COM4 COM1 COM2 COM3 COM4 DISP OFF LCD OFF * * 2002-05-14 TC9325F φL2B φL2B Data selection S1 S2 S4 φL3B I/O S8 Data selection S1 OUT3 φL2B Y1 Y2 Y4 S2 S4 IN3 φL2B Y8 φK3B I/O S8 Y1 DAL address 1 Y4 Y8 DAL address 1 0 0 DA0 DA1 DA2 DA0 DA3 DAL address 2 DA1 DA2 DA3 DAL address 2 1 1 DA4 DA5 DA6 DA4 DA7 DAL address 3 DA5 DA6 DA7 DAL address 3 2 2 DA8 DA9 DA10 DA8 DA11 DAL address 4 DA9 DA10 DA11 DAL address 4 3 3 DA12 DA13 * DA12 * Pulse counter control 1 DA13 0 0 Pulse counter data 1 4 4 DOWN POL * * PC0 Pulse counter control 2 5 Y2 CTR RESET OVER RESET PC1 PC2 PC3 Pulse counter data 2 5 * * PC4 PC5 PC6 PC7 Pulse counter data 3 6 6 OVER 7 7 8 8 9 9 A A B B C C D D E E F F 26 0 0 0 2002-05-14 TC9325F ż System Clock Control Circuit The system clock control circuitry consists of a clock generator, an oscillation detector, an oscillation control port, a timing generator, and a backup mode control circuit. Clock generator CO Ｒ 94 XOUT2 75 kHz CI Oscillation control port (φL1AP2) 75 kHz oscillator 95 XIN2 Oscillation detector CO 97 XOUT1 4.5 MHz CI Backup mode control circuit 4.5 MHz oscillator Timing generator 98 XIN1 CPU clock Peripheral clock 4.5 MHz oscillator: CI = 30 pF, CO = 30 pF (typ.) 75 kHz oscillator: CI = 30 pF, CO = 30 pF, R = 0 Ω (typ.) Note: Select a crystal oscillator with a low CI value and good startup characteristics. Note: Determine the constants for external resistors and capacitors in accordance with the crystal oscillator actually used. Note: Fix to GND level the input pin (XIN1 or XIN2) of any oscillator that is not connected to a crystal oscillator. Note: The 4.5 MHz and 75 kHz oscillators incorporate Schmitt trigger circuits. . Clock Generator and Oscillation Detector The clock generator is a circuit to generate a reference clock supplied to the CPU core and peripheral hardware. The TC9325F incorporates both 4.5 MHz and 75 kHz oscillators. Connect the 4.5 MHz oscillator to the XIN1 and XOUT1 pins and the 75 kHz oscillator to the XIN2 and XOUT2 pins. The oscillation detector detects the clocks for the 4.5 MHz and 75 kHz oscillators and selects which to use as the reference clock. If clocks for both oscillators are detected, the clock for the 4.5 MHz oscillator is selected as the reference clock. Accordingly, either one or both oscillators (4.5 MHz and 75 kHz) can be connected. Note that an input pin (XIN1 or XIN2) that is not connected to an oscillator must be fixed to GND level. If both the 75 kHz and 4.5 MHz oscillators are connected, after a reset the CPU operates on the 4.5 MHz crystal oscillator clock. The clock can be readily switched by software between the CPU operating clock and the peripheral clock. 27 2002-05-14 TC9325F 2. Oscillation Control Port The oscillation control port controls the 4.5 MHz and 75 kHz oscillators. φ L1AP2 Y1 Y2 Y4 Y8 OSC1 ON (4.5 MHz) OSC2 ON (75 kHz) CPU CK SEL TIMER/REF CK SEL Peripheral clock selection 0: 4.5 MHz 1: 75 kHz CPU clock selection 0: 4.5 MHz 1: 75 kHz 75 kHz oscillator control 0: Halts oscillation. 1: Oscillates. 4.5 MHz oscillator control 0: Halts oscillation. 1: Oscillates. Note: Before switching to the clock for a halted oscillator, wait at least 100 ms after oscillation starts, then switch. 3. Timing Generator The timing generator is a circuit for generating various system clocks supplied from the selected reference clock to the CPU core or peripheral hardware. The reference clock is selected by the oscillation detector and oscillation control port. 28 2002-05-14 TC9325F ż System Reset A system reset on the device occurs when an L signal is applied to the RESET pin, or when the voltage supplied to the VDD pin goes from 0 V to more than 3.5 V (a power-on reset). Following a system reset, the program starts from address 0 after a standby period of 100 ms. Because the power-on reset function is typically used, fix the RESET pin to the H level. Note: The power-on reset function can be disabled by using the Al switch. Please clearly specify whether you want the power-on reset function disabled or not in your ES order sheet. If the power-on reset function is disabled, use the RESET pin to trigger resets. Note: During a system reset and during the standby period following the reset, the LCD common signal and segment outputs are fixed at the L level. Note: After a system reset, the non-initialized internal ports shown in the previous I/O map must be initialized by software. After a reset, the ports and bits on the I/O map indicated by the symbol are fixed to 0 and the ports and bits indicated by the symbol are fixed to 1. Ports and bits with no symbol are undefined. φL2 I/O φL1 I/O OUT2 Code Y1 Y2 OUT1 Y4 Code Y8 Y1 I/O port 1 control Y2 Y4 Y8 Reference select 0 6 -0 -1 -2 -3 R0 After a system reset, these ports are all reset to 1. After a system reset, the ports with no symbols are undefined. (Note) R1 R2 R3 After a system reset, ports and bits with no symbol are undefined. (Note) VDD pin GND RESET pin GND A reset from the RESET pin halts the crystal oscillator. XOUT1/2 pin Standby (approx. 100 ms) Internal reset signal CPU operating Reset CPU operating Standby (approx. 100 ms) CPU operating Standby (approx. 100 ms) <Operation Timing Example> Note: If there is a possibility of the supply voltage falling below 3.5 V, set to Clock Stop mode or trigger a reset. Re-applying the power supply voltage after it has dropped to below 0.3 V to 0.6 V triggers a power-on reset. 29 2002-05-14 TC9325F . Reset Control Port The CPU can be reset using the RESET pin or by a power-on reset. If the power supply falls to 2.4 V or below, the STOP F/F bit is set to 1. This bit can be used for such purposes as detecting a fall in the supply voltage from a momentary interruption or during Backup mode. When such a drop in supply voltage is detected, set Clock Stop mode to prevent CPU malfunction then back up the memory. Setting the 2-Hz reset bit to 1 resets the STOP F/F bit. The reset control data are read to data memory by the IN1 instruction with the operand [CN = 7H]. Y1 φL18P2 Y2 Y4 Y8 2 Hz F/F RESET Setting the port to 1 resets the 2-Hz F/F and the STOP F/F. Y1 φK2F Y2 Y4 Y8 Y1 2 Hz F/F Y2 Y4 Y8 STOP F/F φK28 Supply voltage detection port 0: Supply voltage above 2.4 V 1: Supply voltage 2.4 V or below Note: For information on the 2-Hz F/F bit, see the timer port section. 2. Reset Circuit Structure and Operation Timing Power-on reset circuit GND VDD CPU reset signal 40 Voltage detection signal for VDD = 2.4 V S F/F R STOP F/F 2-Hz F/F reset signal Note: When the supply voltage falls to 2.4 V or below, set Backup mode. Note: Reswitching on the power supply when the supply voltage falls to or below the range 0.3 to 0.6 V triggers a reset. Note: When Backup mode is not set, be sure to turn the power supply on from the GND level. Note: If necessary, use the RESET pin to trigger a reset. Supply voltage VDD ∼ − 2.4 V GND Execute 2-Hz F/F reset STOP F/F bit Example of Supply Voltage Detection Bit Operation 30 2002-05-14 TC9325F ż Backup Modes To access the three Backup modes, execute the CKSTP or WAIT instruction. . Clock Stop Mode Clock Stop mode halts the system and maintains the internal state of the system immediately prior to halting at low current consumption (1 µA or below). In Clock Stop mode, the crystal oscillator halts and the LCD display output pins and CMOS output ports are all automatically fixed to the L level. The supply voltage can be reduced to 2.0 V. When the CKSTP instruction is executed, execution halts at the address of the CKSTP instruction. Therefore, execution starts again from the next address when Clock Stop mode is released (after a standby period of around 100ms). (1) Setting Clock Stop Mode Clock Stop mode can be set to one of two modes. The CKSTP MODE bit determines which of the two modes are set. This bit is accessed by the OUT1 instruction with the operand [CN = 8H] on I/O map page 2. Y1 φL18P2 Y2 Y4 Y8 CKSTP mode 0: MODE-0 1: MODE-1 1) MODE-0 In mode 0, executing the CKSTP instruction when the HOLD pin is L sets Clock Stop mode. Executing the CKSTP instruction when the HOLD pin is H is equivalent to executing a NOOP instruction. 2) MODE-1 In mode 1, executing the Clock Stop instruction sets Clock Stop mode regardless of the level of the HOLD pin. Note: The PLL is off during execution of the CKSTP instruction. Note: Prior to executing the CKSTP instruction, be sure to access the HOLD input and I/O port 8 input ports to reset the 2-Hz F/F. Attempting to set Clock Stop mode without resetting the 2-Hz F/F may result in a failure to set the mode. (2) Releasing Clock Stop Mode 1) MODE-0 In mode 0, Clock Stop mode is released when the HOLD pin goes to H, or by a change in the input state of any I/O port (P8-0 to 3) pin set to input mode. 2) MODE-1 In mode 1, Clock Stop mode is released by a change in the input state of the HOLD pin or of any I/O port (P8-0 to 3) pin set to input mode. 31 2002-05-14 TC9325F (3) Clock Stop Mode Timing 1) MODE-0 HOLD pin High impedance XOUT1/2 pin CPU operation Clock stop CKSTP instruction NOOP operation CPU operation Standby (approx. 100 ms) CKSTP instruction execution NOOP operation (Executing the CKSTP instruction while the HOLD pin input is Low sets the device to Clock Stop mode.) 2) MODE-1 HOLD pin High impedance XOUT1/2 pin CPU operation Clock stop CPU operation Standby (approx. 100 ms) CKSTP instruction CKSTP instruction execution Clock stop CKSTP instruction execution (Executing the CKSTP instruction always sets the device to Clock Stop mode.) POWER 4700 µF 1 kΩ 1 MΩ 1 kΩ VDD POWER 67 0.1 µF HOLD 0.1 µF 1 MΩ 470 µF VDD 67 0.1 µF HOLD Backup Circuit Example (Mode 0) 0.1 µF (4) Example of Backup Circuit Using Battery Example of Backup Circuit Using Capacitor 32 2002-05-14 TC9325F 2. Wait Mode Wait mode halts the system and maintains, with reduced current consumption, the internal state of the system immediately prior to halting. Two Wait modes are supported: soft wait and hard wait. When the Wait instruction is executed, execution halts at the address of the WAIT instruction. Therefore, when Wait mode is released, execution starts again from the next address (without delaying for the standby time). (1) Soft Wait Mode Executing the WAIT instruction with the operand [P = 0H] stops the device’s internal CPU only. In this mode, the crystal oscillator and other circuitry continue to operate normally. Using Soft Wait mode in the software for clock functions reduces the current consumed during clock operation. Note: The current consumption varies according to the software because the current consumed is dependent on the time for executing CPU operations. (2) Hard Wait Mode Executing a WAIT instruction with the operand [P = 1H] stops all operation other than the crystal oscillator. This reduces current consumption still further than Soft Wait mode. In this state, CPU operation is halted. Note: During Hard Wait mode, the output ports are retained and the LCD output pins are all fixed to L. (3) Setting Wait Mode Executing the WAIT instruction always sets Wait mode. Note: In Wait mode, the PLL is automatically turned off. (4) 3. Wait Mode Release Conditions Wait mode is released by the following conditions. 1) At a change in the input state of the HOLD pin. 2) At a change in the input state of an I/O port (P8-0 to 3) set as an input port. 3) When the 2-Hz timer F/F is set to 1. (In Soft Wait mode only) HOLD Input Port Y1 φK28 Y2 Y4 Y8 Y1 φL19P2 HOLD 0: Input L level 1: Input H level Y2 Y4 Y8 HOLD PLL off control 0: No PLL off control by the HOLD pin 1: PLL set to Off mode by HOLD pin (L level input) The HOLD pin can be used as an input port. Executing the IN2 instruction with the operand [CN = 8H] reads the data input from this bit to data memory. When setting Clock Stop or Wait mode, always access this port prior to executing the backup instruction. Note that if the instruction is executed without first accessing this port, the device may not enter Clock Stop or Wait mode. When the HOLD PLL off control bit is set to 1, inputting L level to the HOLD pin sets PLL Off mode. PLL OFF mode can be quickly set when changing the batteries. This bit is accessed by the OUT1 instruction with the operand [CN = 9H] on I/O map page 2. PLL Off mode can also be set by setting all the reference ports to 1. (See the section on the reference frequency divider.) 33 2002-05-14 TC9325F ż Interrupt Function Peripheral hardware that can use interrupts is the INTR1 and INTR2 pins, serial interfaces 1 to 4, and the timer-counter. When the peripheral hardware satisfies the conditions, the hardware outputs an interrupt request signal and issues an interrupt request. When the interrupt is accepted, processing branches to the vector address determined by the interrupt source and the interrupt handling routine commences. At the start and end of normal interrupt handling in an interrupt routine, prior processing and post processing are needed to restore the state that prevailed when the interrupt occurred. The registers used by the ALU and any data memory that was not corrupted must be saved and restored to the interrupt data memory. When the interrupt handling is complete, the program is restored by an interrupt return instruction. . Interrupt Control Circuit The interrupt control circuit consists of an interrupt enable flag, an interrupt latch, and an interrupt priority circuit block. These are controlled and set by the OUT1/IN1 instructions on page 2 of the I/O map. (1) Interrupt Enable Flag The interrupt enable flags include the master enable flag and individual enable flags for each interrupt source. The individual enable flags enable or disable interrupts in accordance with the interrupt source. The master enable flag can enable or disable any interrupt. Setting the enable register to 1 enables an interrupt while 0 disables the interrupt. The individual enable flags are accessed by the OUT1/IN1 instruction with the operand [CN = 1H, 2H] on I/O map page 2. The master enable flag enables/disables an interrupt on execution of the EI/DI instruction. To disable an interrupt during program execution use the DI instruction. To enable an interrupt, use the EI instruction. Interrupts are enabled while the program between the EI and DI instructions is executing. The master enable flag is reset to 0 when an interrupt request is received and all interrupts are disabled. An interrupt return instruction sets the flag to 1. The master enable flag can be read by the IN1 instruction with the operand [CN = 0H] on I/O map page 2 to data memory. φL11P2 φK11P2 Y1 Y2 Y4 Y8 EF1 EF2 EF3 EF4 Y1 Y2 Y4 Y8 EF1 EF2 EF3 EF4 φL12P2 φK12P2 Y1 Y2 Y4 Y8 EF5 EF6 * * Y1 Y2 Y4 Y8 EF5 EF6 0 0 Individual enable flag EF1･･･INTR1 pin EF2･･･INTR2 pin EF3･･･Serial interface 3/4 EF4･･･Serial interface 1 EF5･･･8-bit timer-counter EF6･･･Serial interface 2 Y1 φK10P2 Y2 Y4 “0”･･･Disabled “1”･･･Enabled Y8 MF Master enable flag 34 Reset to 0 when an interrupt is accepted or when a DI instruction is executed. Set to 1 when an interrupt return or EI instruction is executed. 2002-05-14 TC9325F (2) Interrupt Latch When an interrupt request is issued the interrupt latch is set to 1. If the interrupt is enabled, the interrupt latch passes the request to accept the interrupt to the CPU and branches to the interrupt routine. If the interrupt is accepted, the interrupt latch is automatically reset to 0. The interrupt latch data can be read by software, allowing each application to check whether an interrupt has been generated or not. In addition, an interrupt latch set to 1 by an interrupt request can be reset to 0 and the interrupt request can be cleared or initialized. φL13P2 Y1 Y2 Y4 Y8 ILR1 ILR2 ILR3 ILR4 Reset interrupt latch φK13P2 Y2 Y4 Y8 ILR5 ILR6 * * Setting 1 resets the interrupt latch to 0. Y1 Y2 Y4 Y8 ILR1 ILR2 ILR3 ILR4 Interrupt latch data φL14P2 Y1 φK14P2 Y1 Y2 Y4 Y8 ILR5 ILR6 0 0 0: No interrupt generated 1: Interrupt generated When an interrupt request is issued, set to 1. When an interrupt request is accepted, reset to 0. ILR1･･･INTR1 pin ILR2･･･INTR2 pin ILR3･･･Serial interface 3/4 ILR4･･･Serial interface 1 ILR5･･･8-bit timer-counter ILR6･･･Serial interface 2 (3) Interrupt Priority Circuit Block The interrupt priority circuit determines the interrupt handling priority when more than one interrupt is generated at the same time or when an interrupt is enabled after several are generated. This block also generates the vector address for the interrupt routine. Priority Interrupt Source Vector Address 1 INTR1 pin 0001H 2 INTR2 pin 0002H 3 Serial interface 3/4 0003H 4 Serial interface 1 0004H 5 Timer-counter 0005H 6 Serial interface 2 0006H 35 2002-05-14 TC9325F 2. Interrupt Acceptance Procedure An interrupt request is held until either the interrupt is accepted or the interrupt latch is reset to 0 by a system reset or by software. The following describes the interrupt acceptance operation. 1) The peripheral hardware outputs an interrupt request signal if the interrupt conditions are satisfied and sets the interrupt latch to 1. 2) When the interrupt enable flag for the interrupt source and the master enable flag are set to 1, the interrupt latch for the accepted interrupt source is reset to 0. 3) The interrupt master enable flag is reset to 0 and the interrupt is disabled. 4) The contents of the stack pointer are decremented by 1. 5) The contents of the program counter are saved to the stack register. At that time, the contents of the program counter have the address following the address when the interrupt was accepted or enabled. 6) The contents of the vector address corresponding to the accepted interrupt are loaded to the program counter. 7) The vector address contents are executed. Steps (1) to (6) above are executed in one instruction cycle. This instruction cycle is called an interrupt cycle. Note: The stack pointer can specify up to 16 stack register levels. The contents of the stack pointer cannot be refered. With an interrupt enable period Individual enable EI instruction flag set to 1 Instruction Interrupt cycle IMF (master enable flag) interrupt signal Interrupt signal IL (interrupt latch) EF (individual enable flag) One instruction cycle Interrupt enable period Interrupt handling routine Interrupt accepted With an interrupt hold period Instruction Individual enable flag set to 1 EI instruction Interrupt cycle IMF (master enable flag) interrupt signal Interrupt signal IL (interrupt latch) EF (individual enable flag) Interrupt hold period 36 Interrupt handling routine Interrupt accepted 2002-05-14 TC9325F 3. Return from Interrupt Handling Routine To recover from an interrupt handling routine and return to the processing taking place before the interrupt, a special instruction is used. This is the RNI instruction. When the RNI instruction is issued, the following processing is automatically performed in the order shown. 1) 2) 3) The contents of the address stack specified by the stack pointer are restored to the program counter. The interrupt master enable flag is set to 1 (enabled). The stack pointer contents are incremented by 1. The RNI instruction completes the above processing in one instruction cycle. 4. Interrupt Handling Routine If the interrupt occurs in an interrupt-enabled area of the program, the interrupt is accepted at the point the interrupt request is issued regardless of the program being executed at that time. Accordingly, when returning to the original program after the interrupt handling is completed, it is necessary to recover as if no interrupt handling had taken place. Therefore, at the very least, any registers or data memory that might be processed during the interrupt handling routine must be saved before and restored after the interrupt handling routine. (1) Saving In save processing, the carry flag must be saved. If an interrupt is accepted during an arithmetic operation, the contents of the carry flag (CY) and other data change, causing the program to make errors of judgment after restoration. This is why it is necessary to use the IN1 instruction to save the contents of the carry flag in the I/O map to data memory. If necessary, also save the contents of the data memory and general registers used by the interrupt handling routine. When using such instructions as MVGD, MVGS, and DAL in the interrupt routine, also save the G-register, DAL address register, and other contents. (2) Restoring The restoration process is simply an inversion of the above saving process. Because the interrupt master enable flag is reset to 0 when an interrupt is accepted, naturally enough, before the interrupt was accepted the flag must have been set to 1. Therefore, use the RNI instruction to return the master enable flag to its original state. 5. Multiple Interrupts Multiple interrupt processing allows an interrupt to be handled at the same time another interrupt is being handled. As in the diagram, during handling of an interrupt for interrupt source A or B, another interrupt with source C or D can be handled. The interrupt depth at such a time is known as the interrupt level. Main routine Interrupt level 1 Interrupt level 2 MAIN B D A B Interrupt level 3 Interrupt level 4 C D C Example of Multiple Interrupts 37 2002-05-14 TC9325F When using multiple interrupts, note the following. 1) 2) 3) Priority of interrupt sources Restrictions on the address stack levels used when an interrupt request is issued Saving the carry flag and data memory (1) Priority of interrupt sources The priority of multiple interrupts is: A < B < C < D as shown in the diagram. Under this priority, a C interrupt must be given preference even though interrupt A or B is being processed. And a D interrupt must be given priority even though a C interrupt is being processed. A priority for handling multiple interrupts must be determined because of the following hypothetical situation. There are two interrupt sources, A and B. Source A issues a request every 10 ms and the time for handling interrupt A is 4 ms. While source B issues a request every 2 ms and the time for handling interrupt B is 1 ms. If no priority were established for A and B, while interrupt B was being processed, interrupt A would be accepted and processed as a result of an interrupt A request, and interrupt B processing would be repeatedly held up. To prevent this situation, set a priority (A < B) to disable other interrupts during processing of interrupt B and write a program to allow interrupt B to be accepted even during processing of interrupt A. When all the individual enable flags are set to 1 (interrupts enabled), the priority is determined by the hardware described in the interrupt priority circuit block section. However, by manipulating the individual enable flags by software, the hardware priority can be changed. Normally, in the interrupt handling routine, accepted interrupts and low-priority interrupts are disabled and high-priority interrupts are enabled. (2) Restrictions on address stack levels When an interrupt request is issued, the return address is automatically saved to the address stack, as described in the section on interrupt acceptance procedure. The address stack consists of 16 levels, as mentioned in the stack register section, and the address stack can be used even while subroutine call instructions are being executed. Therefore, take care not to exceed the 16 interrupt and subroutine call levels. If these exceed 16, the recorded return addresses are corrupted from the first stack. (3) Saving When using multiple interrupts, be sure to secure separate saving areas for each interrupt source. 38 2002-05-14 TC9325F ż External Interrupt and Timer-Counter Functions Two types of external interrupts are supported using the INTR1 and INTR2 pins. The rising or falling edges of the signals to these pins are used to issue the interrupt requests. The timer-counter is an 8-bit binary counter with timer and external clock timer functions. The external clock timer function input pins can also be used as external interrupt pins (INTR1, INTR2). . External Interrupt Function The external interrupts have two input pins: INTR1 and INTR2. Interrupt requests are issued by detecting the rising and falling edges of these pins. The inputs (INTR1 and INTR2) have a Schmitt trigger circuit and noise canceller. When using the CPU operating clock for the noise suppression clock, use a 900 kHz frequency; when using a 75 kHz clock, use a 75 kHz frequency. Pulses that fall below these frequencies are rejected as noise. The input edge can be selected between a rising/falling edge for each pin. The IE bit enables 8-bit timer-counter operations/interrupts and external interrupt requests. This bit is normally set to 1. This bit is controlled by the OUT1 instruction with the operand [CN = 0H] on I/O map page 2. When an INTR1 pin interrupt is accepted, the program branches to address 0001H. When an INTR2 pin interrupt is accepted, the program branches to 0002H. The INTR1 and INTR2 pins can also be used as input ports. When set to input ports, the input state can be read to data memory by the IN2 instruction with the operand [CN = 8H]. Y1 φL10P2 Y2 POL1 POL2 Y4 Y8 IE * INTR1 INTR2 8-bit timer and external interrupt operation enable control Edge selection 1: Rising edge 0: Falling edge 0: Disable 1: Enable Normally, set this bit to 1. Rejects pulses less than 1.11 µs at 4.5 MHz or 13.3 µs at 75 kHz. Pulses over 3.33 µs at 4.5 MHz or 40 µs at 75 kHz are regarded as a signal. Note: Edge selection also controls the timer-counter external clock edge. Input to the timer-counter does not use the noise canceller function. Care is needed because even when an external interrupt does not occur, clock pulses less than those above are input to the counter. Timer-counter edge selection Y1 φK28 Y2 Y4 1: Count on rising edge 0: Count on falling edge Y8 INTR1 INTR2 Pin input states 0: Input L level 1: Input H level Note: When the edge is switched by the POL bit, an interrupt request may be issued. Accordingly, when switching the edge, first disable interrupts. To return to normal operation, reset the interrupt latch. 39 2002-05-14 TC9325F 2. Timer-Counter Function The timer-counter consists of an 8-bit binary counter, a counter match register, a digital comparator, and the control circuits to run these. The timer-counter inputs a timer clock to an 8-bit binary counter. When the count of the 8-bit binary counter matches the contents of the counter match register, the timer-counter outputs a match signal pulse and generates an interrupt request. The timer-counter can be reset by the match pulse or by software. The reset by match pulse can be enabled or disabled. INTR1/2 input, an instruction cycle, or a frequency of 1 kHz can be selected as a timer clock. (1) Timer-counter register structure The timer-counter registers consist of the counter data, a match register, and a control register. φL15P2 φL16P2 Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8 ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 Timer-counter match data φK15P2 Outputs a match pulse at a match with the timer-counter φK16P2 Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8 CT0 CT1 CT2 CT3 CT4 CT5 CT6 CT7 Timer-counter data φL17P2 Y1 Y2 Y4 Y8 CK0 CK1 GT CR Timer clock selection The timer-counter data are read in binary to the data memory as-are. Timer-counter reset Resets counter whenever 1 is set. Enables counter reset by match pulse CK0 CK1 CPU clock 0 0 * 0 1 4.5 MHz 75 kHz 0: Enabled 1: Disabled Timer clock INTR1 pin input Instruction cycle clock 1 0 * 25 kHz 1 1 * 1 kHz 562.5 kHz The clock edge can be selected by the POL bit 0: Counts on rising edge. 1: Counts on falling edge. 25 kHz Note: When using the timer-counter, the IE bit must be set to 1. 40 2002-05-14 TC9325F (2) Timer mode Timer mode is used for detecting a specified period of time. Whenever a specified period is detected, the timer issues an interrupt request and resets the counter. At this time, the control bit is set as a timer clock to 1 kHz or one instruction cycle, the GT bit is set to 0, and the CR bit to 0 (not reset). Set the timer match data corresponding to the period to be set: Timer period = IDn (match data) × timer clock cycle An external pin can be used for the timer clock. Use a clock frequency that is no longer than one instruction cycle. Setting the GT bit to 1 adds up the external clock count. Input at least one instruction cycle for the external clock input. Timer clock Timer data IDn 00H 01H 02H 03H ID (N − 1) IDn 00H 01H 02H 03H Match pulse Request interrupt and reset timer-counter. 41 2002-05-14 TC9325F ż Internal Interrupts and their Functions The internal interrupts include one timer-counter interrupt and three serial interface interrupts. . Timer-Counter Interrupt The timer-counter interrupt is triggered at a match between the timer-counter value and the match register value. For details, see the section on the timer-counter function. 2. Serial Interface Interrupt A serial interface interrupt is triggered at the completion of a serial operation. For details, see the section on serial interface functions. 3. Interrupt Block Structure Serial interface 3/4 interrupt Serial interface 1 interrupt Serial interface 2 interrupt 4.5 MHz/75 kHz ILR1 68 ILR2 ILR3 ILR4 ILR5 ILR6 Noise canceller INTR1 CK0 CK1 R IL2 EF1 POL2 S EF2 S R S IL3 R IL4 EF3 EF4 S R S IL5 EF5 R IL6 EF6 Decoder Interrupt priority circuit/vector address generator Selector CT0~CT7 CR 8-bit binary counter R EI instruction S IMF R DI instruction Match pulse RNI instruction Match register (D0 to D7) GT 42 La Vector address INTR2 INTR1 R IL1 Noise canceller 1 kHz Instruction cycle clock INTR2 S Interrupt acceptance signal POL1 69 2002-05-14 TC9325F ○ Programmable Counter The programmable counter block consists of a 2-modulus prescaler, 4-bit and 13-bit programmable counters, and the ports used to control the block. The programmable counters can be turned on and off by the contents of the reference ports or the HOLD input state. 1. Programmable Counter Control Ports These ports control the frequency, division method, and the prescaler operating current and gain. φL10P1 Y1 Y2 Y4 Y8 HF PW * FM Power control Division method setting φL12P1 φL11P1 φL13P1 φL14P1 Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8 Y1 Y2 Y4 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 LSB Y8 Y1 Y2 φL15P1 Y4 Y8 Y1 Y2 Y4 Y8 P12 P13 P14 P15 P16 * * * Programmable counter frequency setting MSB The division method and the prescaler power control are accessed using the OUT1 instruction with the operand [CN = 0H] on I/O map page 1. The frequency is accessed using the OUT1 instruction with the operand [CN = 1 to 5H] on I/O map page 1. The frequency is set by writing to bit P16 (φL15P1). When the programmable counter data (P16) are set, all the data from P0 to P16 are updated. Therefore, always access P16 and set it last, even when changing only a portion of the data. Y1 φL19P2 Y2 Y4 Y8 Prescaller IN Sets the prescaler IF counter input. 0: Proper PLL structure 1: Inputs the prescaler divider output to the IF counter. Setting the prescaler IF input: When this bit (Y8) is set to 1 the programmable counter is halted and the prescaler 1/15•16 is fixed to 1/16. Normally when setting a PLL, set 0 to the bit. (See the section on the IF counter.) 43 2002-05-14 TC9325F 2. Setting Division Method The HF and FM bits select the pulse swallow or direct division method. The power control (PW) controls the amp and prescaler (1/2 + 1/15•16) gain. Set the power bit for each mode as in the following table. As the table shows, there are five methods. Reception Operating Frequency Band Example Range Mode HF PW FM Division Method LF 0 * 0 Direct division method HF 1 * 0 FM2 0 1 1 FM1 0 0 1 FM2 1 1 1 FM1 1 0 1 VHF 1 0 MW/LW 0.5~20 MHz SW 1~30 MHz (1/15•16) pulse swallow method Input Pin Frequency (Note) AMin n 10~60 MHz 50~140 MHz FM 10~60 MHz FMin 50~140 MHz (1/2 + 1/15•16) pulse swallow method TV 1 2･n 50~230 MHz (1 ch~12 ch) Note: n indicates the programmed divider value. 3. Setting Frequency The programmable counter frequency is set in bits P0 to P16 using a binary value. • Pulse swallow method (17 bits) MSB LSB P16 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 16 2 0 2 Frequency setting range (n = 210H to 1FFFFH (528 to 131071)) • P0 Direct division method (13 Bits) MSB LSB P16 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 12 2 P5 P4 P3 P2 P1 P0 0 Frequency setting range (n = 10H to 1FFFH (16 to 8191)) 44 2 Don’t care 2002-05-14 TC9325F 4. Programmable Counter Circuit Structure • Pulse Swallow Circuit Structure This circuit is made up of an amp, 1/2 prescaler, 1/15•16 2-modulus prescaler, a 4-bit swallow counter, and a 13-bit binary programmable counter. When using FMin input, a 1/2 divider is inserted before the prescaler. P0~P3 PW HF FM 1/16 FMin 1/2 73 0.01 µF 4-bit swallow counter Preset 1/15･16 1/15 AMin 13-bit programmable counter Amp To phase comparator 74 0.01 µF P4~P16 • Direct division circuit structure This circuit bypasses the prescaler and uses the 13-bit programmable counter. Preset Amp AMin 74 13-bit programmable counter To phase comparator P4~P16 Note: The FMin and AMin pins incorporate amps. Connecting a capacitor permits low-amplitude operation. The input pins not selected by the division method are high impedance. In PLL Off mode the inputs are also high impedance. Therefore, the FMin and AMin pins can be used as a wired OR, as shown below. Note: In PLL Off mode, the entire programmable counter block is halted. At this time, the contents of all the control ports are saved. FM/TV VCO AM VCO 0.001 µF 0.001 µF AM/FM/TV VCO 73 FMin 74 AMin 0.001 µF 73 FMin 74 AMin Example of circuit using VCO in both FM and AM bands. Example of circuit using VCO shared between FM and AM bands. 45 2002-05-14 TC9325F ○ Reference Frequency Divider When the 75-kHz oscillator clock is selected as a peripheral clock, the reference frequency divider divides the frequency of the external 75-kHz crystal oscillator to generate seven PLL reference frequency signals: 1 kHz, 3 kHz, 3.125 kHz, 5 kHz, 6.25 kHz, 12.5 kHz, and 25 kHz. When the 4.5-MHz oscillator clock is selected, the reference frequency divider divides the frequency of the external 4.5-MHz crystal oscillator to generate a further four PLL reference frequency signals: 9 kHz, 10 kHz, 50 kHz, and 100 kHz, making a total of 11 reference frequency signals. The frequency is selected by the reference port data. The selected signal is supplied as the reference frequency for the phase comparator, which is described next. The PLL is turned on and off according to the reference port setting. 1. Reference Port The reference port is an internal port used to select the reference frequency signal, and there are 11 available frequencies. This port is accessed by the OUT1 instruction with the operand [CN = 6H] (øL16P1) on I/O map page 1. When the contents of the reference port are all 1, the programmable counter, IF counter, reference counter, and phase comparator are all halted and the PLL is turned off. When the reference port is set, the frequency setting data of the programmable counter are updated. Therefore, when setting the reference port, be sure to first set the programmable counter frequency, then the reference port. Y1 φL16P1 R0 Y2 R1 Y4 R2 Y8 R3 Reference frequency selection 46 Reference Frequency R3 R2 R1 R0 0 0 0 0 0 1 kHz 0 0 0 1 1 3 kHz 0 0 1 0 2 3.125 kHz 0 0 1 1 3 5 kHz 0 1 0 0 4 6.25 kHz 0 1 0 1 5 12.5 kHz 0 1 1 0 6 25 kHz 0 1 1 1 7 9 kHz 1 0 0 0 8 10 kHz 1 0 0 1 9 50 kHz 1 0 1 0 10 100 kHz 1 0 1 1 11 Prohibited 1 1 0 0 12 Prohibited 1 1 0 1 13 Prohibited 1 1 1 0 14 Prohibited 1 1 1 1 15 PLL off mode 2002-05-14 TC9325F ○ Phase Comparator, Lock Detection Port The phase comparator compares the reference frequency supplied by the reference frequency divider with the output frequency of the programmable counter, and outputs the phase difference. This is used to control the VCO (voltage control oscillator) via the low pass filter so as to match the frequencies and phases between the two signals. The phase comparator outputs in parallel to the tristate buffered DO1 and DO2 pins. This enables the optimal filter constants to be designed for FM, VHF, and AM bands. Also, the DO2 pin can be set as a general-purpose output by the DO2 control port. By using the DO1 and DO2 pins, the PLL lock loop lockup time characteristics can be improved. The unlock detection port can be used to detect the PLL lock state. 1. DO1 Control Port, Unlock Detection Port Y1 φL1AP1 Y2 UNLOCK RESET Y4 Y8 DO2 Control FAST M0 M1 Set DO2 output Set high-speed lock Valid only when 4.5 MHz selected as the peripheral clock FAST M1 M0 DO2 Output State 0 0 0 DO output 0 0 1 L level 0 1 0 H level 0 1 1 “HZ” 1 * * When phase difference 1.11 µs or higher: DO output When phase difference less than 1.11 µs: “HZ” DO1 Output State DO output DO output Setting 1 resets the unlock F/F and unlock enable bit. Y1 φK2A Y2 Y4 Y8 UNLOCK F/F ENA Unlock enable 0: Waiting for PLL unlock detection 1: PLL unlock detectable Unlock detection bit 0: PLL locked 1: PLL unlocked The M0 and M1 bits of the DO2 control port set DO2 as a general-purpose output port and set DO2 to high impedance. The FAST bit sets the high-speed lock. The unlock F/F detects the phase difference between the output frequency of the programmable counter and the reference frequency when the phase is approximately 180°. If the phase does not match, that is, if the PLL is unlocked, the unlock F/F is set. Also, setting the unlock reset bit to 1 resets the unlock F/F. To detect the phase difference at the reference frequency period, reset the unlock F/F, then access the unlock F/F after waiting for an interval longer than the reference frequency period. An enable bit is supplied for this purpose. After confirming that the unlock enable bit is set to 1, access the unlock F/F. Note: When the PLL is off and the DO output is set, the DO output is high impedance. However, when the DO2 pin outputs an L or H level signal, this state is held if PLL Off mode or Clock Stop mode is set. Note: The high-speed lock is effective only when a 4.5-MHz peripheral clock is selected. 47 2002-05-14 TC9325F 2. Phase Comparator, Unlock Port Timing Reference frequency Programmable counter output High impedance H level (Vreg) DO output L level (GND) Phase difference Lock detection strobe Unlock reset execution Unlock F/F Unlock enable 3. Phase Comparator, Unlock Port Circuit Structure Reference frequency Decoder VDD Phase comparator Programmable counter output 77 DO1 “H” level UNLOCK F/F Decoder UNLOCK ENABLE UNLOCK RESET 78 DO2/OT M1, M0, FAST bits 48 2002-05-14 TC9325F C1 R2 DO1 77 FM/VHF/ VCO R1 DO1 77 R1 LPF C2 R4 DO2/OT 78 C1 R3 R3 AM VCO DO2/OT 78 R2 VCO LPF LPF VDD 76 VDD 76 0.1 µF (typ.) 10 µF (typ.) 0.1 µF (typ.) When setting different filter constants for each band 10 µF (typ.) When using the same low pass filter for both bands (High-Speed Lock mode) Note: The filter circuit shown above is an example for your reference. Design your own circuit in accordance with the band structure of your system and the characteristics you require. 49 2002-05-14 TC9325F ○ IF Counter This is a 20-bit general-purpose intermediate frequency (IF) counter used for such purposes as counting the FM or AM intermediate frequency and detecting the auto-stop signal during auto tuning. The FMin/AMin input can be input via the prescaler to the IF counter. The IF counter can also be used for detecting the reception frequency by measuring the analog tuner’s VCO. 1. IF Counter Control Port, Data Port φL17P1 Y1 Y2 Y4 Y8 IF1/ 2 * IF1/IN1 IF2/IN2 IF input/input port selection 0: Input port 1: IF input IF input selection 0: IFin2 input 1: IFin1 input Note: When set as an input port, the frequency can be detected by inputting CMOS input to the IF counter. φL18P1 Y1 Y2 Y4 Y8 STA/ STP MANUAL G0 G1 Time selection for frequency measuring gate (measuring time) G0 G1 Gate time 0 0 1 ms 1 0 4 ms 0 1 16 ms 1 1 64 ms Frequency measuring auto/manual mode selection 0: Auto mode (Auto mode uses the above gate times for measuring.) 1: Manual mode (the STA/ STP bit is used to start and stop measuring.) IF counter start/stop bit 0: Stops counter. 1: Starts counter. Y1 φL19P2 Y2 IF counter split Y4 Y8 Prescaller IN Sets FMin/AMin prescaler input to IF counter 0: IFin pin input 1: FMin/AMin pin input Sets IF counter division operation 0: IF counter 20-bit operation 1: Input from INTR2 pin to upper 8 bits of IF counter Note: If the IF counter input is set to prescaler input, when setting the pulse swallow method, the 1/15•16 prescaler is fixed to 1/16 division and this frequency is input to the IF counter. Note: When the IF counter is set for division operations, the upper 8-bit counter is input from the INTR2 pin. However, gate time (Auto mode) cannot be set for these upper eight bits only. To reset this counter, set the STA/ STP bit to 1. 50 2002-05-14 TC9325F φK10P1 Y1 Y2 Y4 Y8 BUSY MANUAL OVER 0 φK11P1 Overflow detection 20 0: IF counter value < =2 −1 20 1: IF counter value > = 2 (overflow state) Operation mode 0: IF Counter Auto mode 1: IF Counter Manual mode Operation monitor 0: IF counter countup complete 1: IF counter countup in progress φK12P1 φK13P1 φK14P1 Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8 Y1 Y2 Y4 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 Y8 Y1 Y2 φK15P1 Y4 Y8 F12 F13 F14 F15 Y1 Y2 Y4 Y8 F16 F17 F18 F19 20 219 LSB IF counter data MSB Note: With IF input selected, the IF input amp goes off in PLL Off mode. To use the IF counter in PLL Off mode, select as an input port (CMOS input). Note: The input amp not selected by the IF 1/2 bit goes off. When the input amp is off, input is set to high impedance. (1) IF Counter Auto Mode When IF counter Auto mode is selected, the MANUAL bit is set to 0 and the gate time is set based on the IF input frequency band to be measured. Setting the STA/STP bit to 1 starts the IF counter, inputs the clock during the specified gate time, counts the number of input pulses, then completes. To determine when the IF counter has finished counting, check the BUSY bit. Note that the OVER bit is set to 1 if the count equals or exceeds 220 input pulses. To measure the input frequency, load the F0 to F19 IF data when the BUSY and OVER bits are both 0. (2) IF Counter Manual Mode Use Manual mode to measure the frequency by controlling the gate time with an internal time base (e.g., 10 Hz). To enter Manual mode, set the MANUAL bit to 1. At this time the gate time setting is “don’t care”. To start the count, set the STA/ STP bit to 1. Setting the STA/ STP bit to 0 terminates the count and loads the data in binary format. (3) IF Counter Input and Division Setting Intermediate frequency (IF) measuring is normally based on the frequency of a signal input to the IFin1 or IFin2 input pins. These pins incorporate input amps and can be used for low-amplitude operation. In addition, input to the IF counter can be set as below. Use the input in accordance with the specifications. IF Counter Prescaller Split IN IF1/ 2 IF1/IN1 IF2/IN2 IF Input Settings 1 1 * 0 0 IFin1 input (amp operation) * 0 * 0 0 IN1 (IFin1) input (CMOS input) 0 * 1 0 0 IFin2 input (amp operation) * * 0 0 0 IN2 (IFin2) input (CMOS input) VHF mode * * * * * * 0 1 FM1/FM2 mode FMin input (frequency divided by 32/16) HF mode AMin input (frequency divided by 16) LF mode AMin input (input frequency) (Note) 1 * The upper 8 bits only are input from the INTR2 pin. Note: For the input frequency range when setting the prescaler input, see the section on the programmable counter. 51 2002-05-14 TC9325F 2. IF Counter Structure The IF counter block consists of an input amp, a gate time control circuit, and a 12- + 8-bit binary counter. The FMin/AMin prescaler clock can be input to the IF counter. PW FMin 0.001 µF AMin 0.001 µF 1/2 73 To programmable counter 1/15･16 PSC Amp 74 Prescaller IN IFin1 0.001 µF 70 IFin2 0.001 µF IF1/IN1 Prescaller IN IF counter split F0~F11 F12~F19 OVER 8-bit binary counter OVER IF2/IN2 12-bit binary counter 71 Gate IF1/ 2 IN2 IN1 1 kHz Gate time control circuit Manual G0 G1 STA/ STP INTR2 69 Note: All the binary counters of the IF counter operate on the rising edge. Note: The prescaler 1/15•16 division is fixed to 1/16 when the IF counter is input. FMin input division is 1/32; AMin input division is 1/16 or direct input can be used. IF counter input “1” Set data to STA/ STP bit BUSY bit 1 kHz Gate Binary counter input Example of IF Counter Auto Mode Operation Timing 52 2002-05-14 TC9325F ○ LCD Driver The LCD driver consists of 38 pins: 30 pins (OT1/COM1 to OT30/S26) that also function as output ports and eight pins (P9-0/S27 to P10-3/S34) that also operate as I/O ports. The LCD driver has 1/4, 1/3, and 1/2 duty and 1/3 and 1/2 bias drive and can be selected between two frame frequencies. When 1/4 duty is set, up to 136 segments can be displayed using a matrix of COM1 to 4 and S1 to 34. At 1/3 duty, a maximum of 105 segments can be displayed by a matrix of COM1 to 3 and S1 to 35. At 1/2 duty, up to 72 segments can be displayed by a matrix of COM1, 2 and S1 to 36. After a system reset, the pins that also function as output ports are set to output ports, and the pins that are also I/O ports are set to I/O port inputs. The LCD OFF bit is used to switch the output ports and LCD driver, switching 30 ports at a time. The I/O ports and segment outputs are switched individually. 1. LCD Driver Ports The LCD driver control ports consist of a selection port, segment I/O selection ports, segment data ports, and an LCD driver control port. These ports are accessed by the OUT2 instruction with the operand [CN = CH~FH]. Pins S27 to S34 can also operate as an I/O port under the control of the segment I/O selection ports (φL2CE, φL2CF). Setting the port to 1 sets segment output, and setting the port to 0 sets the pins as an I/O port. (See the section on I/O ports.) Set the LCD driver segment data using the segment data ports (φL2D, φL2E, φL2F). Setting the segment data port to 0 turns the LCD display off; setting 1 turns the LCD display on. The LCD drive mode is selected by the LCD driver control port (φL2FE), while the LCD driver control port 2 (φL2FF) is used to switch between the LCD driver and output port (LCD OFF bit) and to turn the LCD display completely off (DISP OFF bit). The DISP OFF bit can turn the whole LCD display off without setting segment data. Setting this bit to 1 outputs the turned off waveforms to all the segments. Setting DISP OFF to 0 outputs the set segment data. The segment data settings are independent of the DISP OFF bit settings. The LCD OFF bit switches the LCD driver on/off. Setting this bit to 1 turns the LCD driver off and sets OT1/COM1 to OT30/S26 pins as output ports (OT1 to OT30). Setting the LCD OFF bit to 0 activates the LCD driver and sets the OT1/COM1 to OT30/S26 pins to LCD driver outputs (COM1 to S26). The segment data settings are independent of the LCD OFF bit settings. These data can be divided/indirectly specified, and set using the data selection port (φL2B). This port is incremented by 1 at each access of segment data port φL2C, segment data ports øL2D to φL2F, and the LCD driver control port. Accordingly, these data can be repeatedly set after the data selection port is set. 53 2002-05-14 TC9325F IO/segment control Y1 φL2B Y2 Y4 SEL1 SEL2 Y8 SEL4 φL2C SEL8 Y1 Y2 Y4 Y8 27Y1 28Y2 29Y4 30Y8 E IO segment selection 1 F IO segment selection 2 Data selection I/O port and segment switching 0: I/0 ports 1: Segment output Segment 1 data Y1 φL2D Y2 Y4 Segment 3 data Y8 Y1 COM2 Y2 COM3 Y4 COM4 Y8 COM1 Y1 Y2 Y4 Y8 0 S1 1 Y1 φL2F S2 2 Y2 Y4 S3 2 S35 3 S36 don’t care COM1 COM2 COM3 COM4 F Y8 Y1 COM2 Y2 COM3 Y4 COM4 Y8 COM1 Y1 Y2 Y4 Y8 0 S33 Y1 Y2 Y4 Y8 1 S34 S16 DUTY0 DUTY1 BIAS FRAME E Segment 2 data Y1 φL2E Y2 Y4 Y1 COM2 Y2 COM3 Y4 COM4 Y8 COM1 Y1 Y2 Y4 Y8 0 S17 1 LCD duty control bit DUTY0 DUTY1 0 1 * S18 2 LCD frame control bit Y8 S19 0 0 1 S32 Duty LCD bias control bit 1/4 1/3 1/2 COM1 COM2 COM3 COM4 F 0: Normal 1: Short F DISP OFF 0: 1/3 bias 1: 1/2 bias LCD OFF * * LCD OFF control bit Segment data 0: LCD output 1: Output port 0: Light off 1: Light on LCD display off control bit 0: Outputs set data. 1: Outputs OFF data. Note: When the DISP OFF bit is set to 1, all segment data are off and the whole display is off. Note: The segment data control whether the segments corresponding to the common and segment outputs are lit or not. Note: During Clock Stop mode and for 100 ms after a system reset, all common and segment outputs are fixed to L. Note: The data selection port is automatically incremented by 1 whenever φLC2, φL2D, φL2E, φL2F, φL3B, or φK3B on the I/O map are accessed. 54 2002-05-14 TC9325F (1/4 duty, 1/3 bias, frame type: normal) COM1 Segment data example Segment data-1 (φL2D) COM2 Y1 0 COM3 (S1) S1 S2 Y2 Y4 Y8 COM1 COM2 COM3 COM4 1 0 1 0 COM4 1 (S2) COM1 COM2 COM3 COM4 1 1 0 1 Data selection (φL2B) DISP OFF 16 ms (62.5 Hz) 2 ms VDD COM1 GND VDD COM2 GND VDD COM3 GND VDD COM4 GND VDD S1 GND VDD S2 GND VDD COM1-S1 (On waveform) GND −VDD VDD COM2-S1 (Off waveform) GND −VDD The LCD driver waveform potential output is GND, 1/3 VDD, 2/3 VDD, and VDD level. The bias voltage is 1/3 VDD and 2/3 VDD at 1/3 bias, and 1/2 VDD at 1/2 bias. (See the following page.) 55 2002-05-14 TC9325F (1/4 duty, 1/2 bias, frame type: normal) COM1 Segment data example Segment data-1 (φL2D) COM2 Y1 0 COM3 (S1) S1 S2 Y2 Y4 Y8 COM1 COM2 COM3 COM4 1 0 1 0 COM4 1 (S2) COM1 COM2 COM3 COM4 1 1 0 1 Data selection (φL2B) DISP OFF 16 ms (62.5 Hz) 2 ms VDD COM1 GND VDD COM2 GND VDD COM3 GND VDD COM4 GND VDD S1 GND VDD S2 GND VDD COM1-S1 (On waveform) GND −VDD VDD COM2-S1 (Off waveform) GND −VDD The LCD driver waveform potential output is GND, 1/2 VDD, and VDD level. 56 2002-05-14 TC9325F (1/3 duty, 1/3 bias, frame type: normal) Segment data example Segment data-1 (φL2D) COM1 Y1 0 COM2 (S1) S1 S2 S3 Y2 Y4 Y8 COM1 COM2 COM3 COM4 0 1 0 * COM3 1 (S2) 2 (S3) COM1 COM2 COM3 COM4 1 1 1 * COM1 COM2 COM3 COM4 1 0 0 * Data selection (φL2B) DISP OFF 12 ms (83.3 Hz) 2 ms VDD COM1 GND VDD COM2 GND VDD COM3 GND VDD S1 GND VDD S2 GND VDD S3 GND VDD COM1-S1 (Off waveform) GND −VDD VDD COM2-S1 (On waveform) GND −VDD The LCD driver waveform potential output is GND, 1/3 VDD, 2/3 VDD, and VDD level. The bias voltage is 1/3 VDD and 2/3 VDD at 1/3 bias, and 1/2 VDD at 1/2 bias. 57 2002-05-14 TC9325F (1/2 duty, 1/3 bias, frame type: normal) S1 Segment data example Segment data-1 (φL2D) S2 Y1 0 S3 (S1) S4 COM1 COM2 1 (S2) 2 (S3) 3 (S4) Y2 Y4 Y8 COM1 COM2 COM3 COM4 1 1 * * COM1 COM2 COM3 COM4 0 1 * * COM1 COM2 COM3 COM4 1 0 * * COM1 COM2 COM3 COM4 0 1 * * Data selection (φL2B) DISP OFF 8 ms (125 Hz) 2 ms VDD COM1 GND VDD COM2 GND VDD S1 GND VDD S2 GND VDD S3 GND VDD S4 GND VDD COM1-S2 (Off waveform) GND −VDD VDD COM2-S2 (On waveform) GND −VDD The LCD driver waveform potential output is GND, 1/3 VDD, 2/3 VDD, and VDD level. The bias voltage is 1/3 VDD and 2/3 VDD at 1/3 bias, and 1/2 VDD at 1/2 bias. 58 2002-05-14 TC9325F (1/4 duty, 1/3 bias, frame type: short) COM1 Segment data example Segment data-1 (φL2D) COM2 Y1 0 COM3 (S1) S1 S2 Y2 Y4 Y8 COM1 COM2 COM3 COM4 1 0 1 0 COM4 1 (S2) COM1 COM2 COM3 COM4 1 1 0 1 Data selection (φL2B) DISP OFF 1 ms 2 ms 8 ms (125 Hz) VDD COM1 GND VDD COM2 GND VDD COM3 GND VDD COM4 GND VDD S1 GND VDD S2 GND VDD COM1-S1 (On waveform) GND −VDD VDD COM2-S1 (Off waveform) GND −VDD The LCD driver waveform potential output is VDD and GND level, and bias voltages are 1/3 and 2/3 VDD and GND level. 59 2002-05-14 TC9325F ○ Serial Interface (SO1 to 4) The TC9325F has four serial interfaces: SIO1, 2, 3, and 4. Serial interfaces 1 and 2 also function as I/O port 4, while interfaces 3 and 4 also operate as I/O port 5. SIO1 and SIO3 are 3-line serial interfaces. SIO1 and SIO3 use pins SI(1/3), SO(1/3), and SCK(1/3) to input or output 4-bit or 8-bit data on an internal or external serial clock. At completion of the serial interface operation an interrupt is generated. SIO2 is a 2-line serial interface. SIO2 uses pins SI2 or SO2 and pin SCK2 to input 26-bit data on an external serial clock. SIO2 has a function for decoding input serial data. An interrupt is generated on each input serial clock edge. SIO4 is a 2-line serial interface. SIO4 uses pins SO4 and SCK4 to input or output 4-bit or 8-bit data on an internal or external serial clock. On completion of the serial interface operation an interrupt is generated. As I/O Port SIO1 P4 SIO2 SIO3 P5 SIO4 Type Data Data Length When Interrupt Generated 3-line Input/output 4/8 bits On completion of serial interrupt operation 2-line Input 26 bits On each serial clock edge 3-line Input/output 4/8 bits On completion of serial interrupt operation 2-line Input/output 4/8 bits On completion of serial interrupt operation Pin Pin I/O port P4-1 P4-2 P4-3 I/O port P5-1 P5-2 P5-3 SIO1 SI1 SO1 SCK1 SIO3 SI3 SO3 SCK3 SIO2 SI2 SO2 SCK2 SIO4 SO4 SCK4 60 2002-05-14 TC9325F 1. Serial Interface 1/2 (SIO1, SIO2) Control Port, Data Port Y1 φL17P3 edge Y2 Y4 SCK-INV SCKO Y8 SIO-ON I/O port 4/serial interface selection 0: I/O port 4 (P4-1 to P4-3) 1: Serial interface 1 or 2 function SCK1 clock external/internal selection 0: External clock input 1: Internal clock output SCK1 clock signal inversion 0: Negative logic output (clock output from H level) 1: Positive logic output (clock output from L level) Serial data shift operation edge selection (for SIO1 and SIO2) 0: Shift on clock rising edge 1: Shift on clock falling edge φL18P3 Y1 Y2 Y4 Y8 STA SOI 8 bit/ CHK MOD Serial interface 1/2 selection 0: SIO1 (generates interrupt on completion of SIO1 serial operation) 1: SIO2 (generates interrupt on SCK2 clock edge) Serial interface 1 data length selection (MOD = 0) 0: 4-bit data 1: 8-bit data Serial interface 2 data (φK25 to φK27) selection (MOD = 1) 0: Offset data (OFS0 to OFS9) 1: Check data (CHK0 to CHK9) Serial data input pin selection 0: SI1/SI2 input 1: SO1/SO2 input Serial operation start and internal port reset 0: Don't care 1: Resets the count and SIO F/F. Sets the serial output data in the shift register. Serial operation starts at the internal SCK clock selection. The SIO2 shift register (26-bit) data reset to 0. 61 2002-05-14 TC9325F φL2B φL2C Y1 Y2 Y4 Y8 SEL1 SEL2 SEL4 SEL8 Y1 Y2 Y4 Y8 Serial interface output data 1 A シリアルインタフ SO1 SO2 SO3 SO0 B SO4 SO5 SO6 SO7 Data selection Serial output data: The data set in this port are output to the serial interface. φK19P3 φK1AP3 Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8 SI0 SI1 SI2 SI3 SI4 SI5 SI6 SI7 Note: The serial interface input data are accessed directly from the shift register. Serial input data: The data input to the serial interface are loaded to data memory. Y1 φK16P3 Y2 BUSY COUNT Y4 Y8 SIO F/F 0 SIO1 start flag 0: Performs SIO operations. 1: Performs no SIO operations. Detect number of SCK clocks 0: Number of clocks normal (the number of SCK clocks is a multiple of 4) 1: Number of clocks abnormal (the number of SCK clocks is not a multiple of 4) SIO1 operation monitor 0: SIO operation complete 1: SIO operation in progress The serial interface pins can also function as I/O port 4 pins P4-1, P4-2, and P4-3. Setting the SIO ON bit to 1 sets these I/O port 4 pins as the SI1/SI2, SO1/SO2, and SCK1/SCK2 pins, respectively. Note: All the serial interface inputs incorporate Schmitt trigger circuits. Note: Even when the serial interface is selected, the SI pin (P4-1) can still be used as an I/O port and therefore can be used for such purposes as inputting/outputting SIO strobe signals. When setting this pin as a serial input pin, set the P4-1 output data to 1 to set the pin as an input. 1) EDGE, SCK-INV, SCKO Bits The EDGE bit sets the shift edge. The SCK-INV bit sets the shift clock input/output waveform. When the EDGE bit is set to 0, serial clock (SCK1) shift operations are performed on the rising edge of the clock. When the EDGE bit is set to 1, serial clock (SCK1) shift operations are performed on the falling edge of the clock. The SCK-INV bit sets whether to start shift operations from the serial clock’s H level output or L level output. When SCK-INV is set to 0, shift operations start from the H output. When SCK-INV is set to 1, shift operations start from the L output. These bits can be used to allow the kind of serial operations shown in the following table. Set those serial operations in accordance with the controlling serial format. The SCKO bit sets the serial clock input/output. When using the TC9325F as the master controller, set SCKO to 1 to output the serial clock. When the TC9325F is the slave, set SCKO to 0 to input the serial clock. 62 2002-05-14 TC9325F SCKINV = 0 SCKINV = 1 STA bit set to 1 edge = 0 STA bit set to 1 SCK1, SCK3 SCK/SOL bit data SO1, SO3 SO/SDA SI1, SI3 1 2 3 SCK1, SCK3 SCK3/SCK4 bit data 4 SO0 SO1 SO2 SO3 SI0 SI1 SI2 SI3 SO1, SO3 SO3/SO4 1 * SI1, SI3 ENA bit ENA bit 2 3 4 SO0 SO1 SO2 SO3 SI0 SI1 SI2 SI3 The ENA bit is not set/reset Interrupt Interrupt BUSY bit BUSY bit Note: The SCK bit must be set to 0. Note: The ENA bit must be set to 0. Note: The settings of this mode can be used for a two-line serial interface. STA bit set to 1 SCK1, SCK3 dge = 1 SO1, SO3 1 * SI1, SI3 ENA bit 2 STA bit set to 1 3 4 SCK1, SCK3 SCK3/SCK4 bit data SO3/SO4 SO0 SO1 SO2 SO3 SO1, SO3 SI0 SI1 SI2 SI3 SI1, SI3 The ENA bit is not set/reset. 1 2 3 4 SO0 SO1 SO2 SO3 SI0 SI1 SI2 SI3 SCK3/SCK4 bit data SO3/SO4 ENA bit Interrupt Interrupt BUSY bit BUSY bit Note: The ENA bit must be set to 0. Note: The SCK bit must be set to 1. 63 2002-05-14 TC9325F 2) 8BIT Bit The 8BIT bit selects the length of the serial data. Setting this bit to 0 selects 4-bit data; setting the bit to 1 selects 8-bit data. When the serial clock is set to the internal clock and SIO operations start, a 4-bit or 8-bit clock is continuously output depending on the setting of this bit. STA bit set to 1 SCK1 pin 1 2 3 SO0 SO1 pin SI1 pin 4 SO1 SI0 5 SO2 SI1 6 SO4 SO3 SI2 SI3 7 SI4 8 SO5 SI5 SO6 SI7 SI6 BUSY SO7 Interrupt Example of Serial Operation When 8-Bit Data Set 3) SOI Bit The SOI bit sets the SOI pin as either a serial data input or output. Setting the SOI bit to 0 sets the SOI pin as a serial data output. Setting 1 sets the pin as a serial data input. This control can be used in serial bus operations where serial data input/output is controlled with a single pin. Edge switching SCK1 pin 1 SO1 pin 2 SO0 STA bit set to 1 SOI bit set to 0 3 SO1 4 SO2 1 (Note) SO3 SI0 2 SI1 3 SI2 4 SI3 STA bit set to 1 SOI bit set to 1 Example of Serial Data Input/Output Operation 4) Monitoring Serial Interface 1 Operation Use the BUSY, COUNT, and SIO F/F bits to check the operating state of the serial interface. The BUSY bit is set to 1 during SIO operations. Therefore, set the control data and access the serial data when the BUSY bit is 0. Interrupt requests are generated on the falling edge of the BUSY bit. Use the COUNT bit to determine whether a 4-bit unit of data has been sent or received. When the number of shift operations is a multiple of 4, the COUNT bit outputs 0. When not a multiple of 4, the bit outputs 1. The SIO F/F bit is set to 1 when the SCK pin starts a shift operation. Setting the STA bit to 1 clears both the COUNT bit and SIO F/F bit to 0. These two bits are mainly used when the SCK pin is set as the external clock (slave). The bits can be used to check whether the external clock was input, whether serial data was sent or received, and whether operations were normal. Because an interrupt normally occurs on completion of a serial interface operation, use interrupt handling for checking whether a serial operation was successful. 5) STA Bit This bit is used to start serial interface operations. Each setting of the STA bit to 1 starts a serial operation. Setting STA to 1 transfers serial output data to the shift register and resets the COUNT bit and the SIO F/F bit. When the SCK clock is set to an internal clock, a serial clock is output. When the SCK clock is set to an external clock, the interface stands by for serial clock input. 64 2002-05-14 TC9325F 2. Serial Interface 1 (SIO1) Structure STA SCKO Interrupt request SCK-INV COUNT Control circuit BUSY 60 SCK1 (P4-3) SIO F/F SOI edge 59 SO1 (P4-2) 8 bit 4-bit shift register 4-bit shift register SO0 SO1 SO2 SO3 SO4 SO5 SO6 SO7 -3 Serial output data SI0~SI3 58 SI1 (P4-1) SI4~SI7 -2 -1 -0 I/O port-4 I/O control data Serial input data -3 -2 -1 -0 I/O port-4 data Serial interface 1 consists of a control circuit, a shift register, and I/O ports. Note: The SI1 pin can be used as I/O port-4 (P4-1). Note: The contents of the shift register are loaded to data memory as the data and serial input data. Accordingly, the data set as the serial output data differ from the serial input data. Note: All the serial input pins (SI1, SO1/SO2, SCK1/SCK2) are Schmitt trigger inputs. 65 2002-05-14 TC9325F 3. SIO1 Circuit Serial Interface Timing When SCK1 is set to an internal clock, the frequency of the clock output from the SCK1 pin is 450 kHz (duty: 50%) with the 4.5-MHz peripheral clock selected, and 37.5 kHz (duty: 50%) with the 75-kHz peripheral clock selected. Note: When SCK1 is set to an external clock, input a clock with a frequency no higher than the above frequencies. SCK1 pin SO1 pin SO0 SI1 pin Serial input data port (φK19P3) STA bit Y8 Y4 Y2 Y1 × × × × SO3 SO2 SO1 SO0 SO1 SO2 SO3 a b c a SO3 SO2 SO1 b a SO3 SO2 c b a SO3 a d d c b a ×: Undefined Set to 1 Set to 1 Interrupt BUSY bit COUNT bit SIO F/F bit 66 2002-05-14 TC9325F 4. Serial Interface 2 (SIO2) Control Port, Data Port Note: ∀ EXOR (exclusive OR) ∀CHK8 1 0 1 1 1 1 0 OFS8 = (INF13 ∀ INF12 ∀ INF11 ∀ INF10 ∀ INF9 ∀ INF4 ∀ INF3 ∀ INF2 ∀ INF1 ∀ INF0) ∀CHK8 1 0 1 0 0 1 1 OFS7 = (INF14 ∀ INF13 ∀ INF9 ∀ INF8 ∀ INF5 ∀ INF4 ∀ INF0) ∀CHK7 0 0 0 1 1 0 1 OFS6 = (INF15 ∀ INF14 ∀ INF11 ∀ INF10 ∀ INF8 ∀ INF7 ∀ INF5 ∀ INF2∀INF1) ∀CHK6 0 0 1 0 1 0 1 OFS5 = (INF15 ∀ INF14 ∀ INF13 ∀ INF10 ∀ INF9 ∀ INF7 ∀ INF6 ∀ INF4 ∀ INF1 ∀ INF0) ∀CHK5 1 0 1 1 0 1 1 OFS4 = (INF15 ∀ INF11 ∀ INF10 ∀ INF9 ∀ INF8 ∀ INF6 ∀ INF4 ∀ INF2 ∀ INF1 ∀ INF0) ∀CHK4 0 0 0 0 1 1 1 OFS3 = (INF13 ∀ INF12 ∀ INF11 ∀ INF9 ∀ INF8 ∀ INF7 ∀ INF4 ∀ INF2 ∀ INF0) ∀CHK3 1 0 1 0 0 0 1 OFS2 = (INF15 ∀ INF14 ∀ INF13 ∀ INF8 ∀ INF7 ∀ INF6 ∀ INF5 ∀ INF4 ∀ INF2) ∀CHK2 0 0 0 0 0 0 0 OFS1 = (INF15 ∀ INF14 ∀ INF13 ∀ INF12 ∀ INF7 ∀ INF6 ∀ INF5 ∀ INF4 ∀ INF3 ∀ INF1) ∀CHK1 0 0 0 0 0 0 0 OFS0 = (INF15 ∀ INF14 ∀ INF13 ∀ INF12 ∀ INF11 ∀ INF6 ∀ INF5 ∀ INF4 ∀ INF3 ∀ INF2 ∀ INF0) ∀CHK0 194h 000h 1B4h 350h 168h 198h 0FCh Other data 0 0 0 1 0 0 0 OFS9 = (INF14 ∀ INF13 ∀ INF12 ∀ INF11 ∀ INF10 ∀ INF5 ∀ INF4 ∀ INF3 ∀ INF2 ∀ INF1) 0 6 5 4 B 3 2 1 Y1 φK20 φK21 φK22 φK23 φK24 φK25 φK26 φK27 φK18P3 Y2 Y4 Y8 SIO2 decode data DCD0 DCD1 DCD2 DCD3 SIO2 information data 1 INF0 INF1 INF2 INF3 SIO2 information data 2 INF4 INF5 INF6 INF7 Information data SIO2 information data 3 INF8 INF9 INF10 INF11 SIO2 information data 4 INF12 INF13 INF14 INF15 SIO2 offset/check data 1 OFS0/ CHK0 OFS1/ CHK1 OFS2/ CHK2 OFS3/ CHK3 SIO2 offset/check data 2 OFS4/ CHK4 OFS5/ CHK5 OFS6/ CHK6 Offset/check data OFS7/ CHK7 SIO2 offset/check data 2 OFS8/ CHK8 OFS9/ CHK9 0 0 Y1 Y2 Y4 Y8 CHK 1 Offset/check data switching 67 0: Reads offset data. 1: Reads check data. 2002-05-14 TC9325F The serial interface 2 (SIO2) data port consists of 16-bit information data (φK21 to φK24), 10-bit check data (φK25 to φK27), 10-bit offset data (φK25 to φK27), and 4-bit decode data (φK20). Of the 26 bits of serial data, 16 bits are information data and 10 bits are check data. When some of the 26 bits of data are exclusive OR-ed, as shown in the previous table, they become offset data. When the offset data are special data (described previously), 1 to 6h and Bh are output as 4-bit decode data. The same port (φK25 to φK27) is used to read both check data and offset data. The SIO2 data selection bit (φL18P3) is used to select the data for reading. Setting the bit to 0 reads offset data; setting the bit to 1 reads check data. To enable a SIO2 operation, set both the SIOon bit (φL17P3) and the MOD bit (φL18P3) to 1. Setting the STA (φL18P3) to 1 resets all 26 bits of shift register. According to the SCK2 pin shift clock, the SI2 pin input states are successively input to the shift register. The shift clock edge can be switched by the EDGE bit (φL17P3). Setting EDGE to 0 shifts the data on the rising edge; setting EDGE to 1 shifts the data on the falling edge. Enabling the SIO2 interrupt at this time triggers the interrupt on the opposite edge to the shift edge. In addition, the SO-I/O bit can be used to switch serial input pins between SI2 and SO2. Setting the SO-I/O bit to 0 sets the SI2 pin to a serial data input. Setting the bit to 1 sets the SO2 pin to a serial data input. Note that when the SI2 pin is selected as a serial input, the SO2 pin becomes a SIO1 serial output pin. Accordingly, Toshiba recommend using the SO2 pin for serial input. Access the serial interface 2 control data using the OUT1 instruction with the operand [CN = 7H, 8H] on I/O map page 3. 5. Serial Interface 2 (SIO2) Structure SIO2 interrupt SCK2 pin SI2 pin SI2 (P4-1) 58 INF14 INF13 CHK3 CHK2 CHK1 CHK0 INF15 Check data Information data 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 26 bits of shift register SO2 (P4-2) 59 edge CHK0 CHK1 CHK2 CHK3 CHK4 CHK5 CHK6 CHK7 CHK8 CHK9 INF0 INF1 INF2 INF3 INF4 INF5 INF6 INF7 INF8 INF9 INF10 INF11 INF12 INF13 INF14 INF15 SCK2 (P4-3) 60 INF15 SOI SIO interrupt EXOR circuit for detecting offset data OFS0 to OFS9 (offset data) Decoder DEC0 to DEC3 (decode data) Note: When using the SI2 pin for serial input, the SO2 pin is used for the SIO1 serial output. When setting the SI2 pin to a serial input, set the P4-1 output data to 1 (input state). Note: Serial input is simultaneously input and shifted to SIO1. 68 2002-05-14 TC9325F 6. Serial Interface 3/4 Control Port, Data Port Y1 φL12P3 edge Y2 Y4 SCK-INV SCKO Y8 SIO-ON I/O port 5 and serial interface selection 0: I/O port 5 (P5-1 to P5-3) selected 1: Serial interface functions selected External/internal clock selection 0: Input external clock (slave) 1: Output internal clock (master) Clock signal inversion 0: Negative logic output (output clock from H level) 1: Positive logic output (output clock from L level) Serial data shift operation logic selection 0: Shift input on clock rising edge, output on rising edge 1: Shift input on clock falling edge, output on falling edge Note: When the P5-2 pin is set as a serial data output (SO3/SO4 set), be sure to set the P5-2 I/O control bit (φL24) to 1 (output state). Setting the P5-2 I/O control bit to 0 sets pin P5-2 to input state. When using pin P5-1 as a serial input (SI3), be sure to set the P5-1 I/O control bit (φL24) to 0 (input). Setting the P5-1 I/O control bit to 1 sets pin P5-1 as an output and outputs the P5-1 output data (φL34) as-are. φL13P3 Y1 Y2 Y4 Y8 STA SI3S 8 bit Nch SIO output format selection (SCK3/SCK4, SO3/SO4 output) 0: CMOS output 1: N-channel open drain output Selecting the number of serial data bits 0: 4 bits 1: 8 bits Starting serial operation and transferring from a serial output data port to a shift register 0: Don’t care 1: Sets serial output data in the shift register and start serial operation. SO3/SO4 pin input/output selection MOD SIS SO3/SO4 Pin SI3/SI4 Pin egde SCKINV SI3S Updating 0 Serial output Serial input 0 1 After STA = 1 set, updates on serial clock falling edge. 1 Serial input P5-1 input/output 1 0 After STA = 1 set, updates on serial clock rising edge. 0 0 0 Serial output 1 1 1 Serial input P5-1 input/output 0 1 Note: The bit is updated under the following conditions. Updates when STA = 1 set. Note: The output data (pin states) are input to the serial interface. 69 2002-05-14 TC9325F φL2C φL2B Y1 Y2 SEL1 SEL2 Y4 Y8 SEL4 SEL8 Y1 Y2 Y4 Y8 Y1interface Y2 3/4 output Y4 dataY8 Serial 1 8 SO0 9 SO4 SO1 SO2 SO5 SO6 SO3 SO7 Data selection Serial output data: The data set in this port are output to the serial interface. φK17P3 φK18P3 Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8 SI0 SI1 SI2 SI3 SI4 SI5 SI6 SI7 Note: The serial interface input data are accessed directly from the shift register. Serial input data: The data input to the serial interface are loaded to data memory. Y1 φL/K14P3 Y2 SO3/ SCK3/ SO4 SCK4 Y4 Y8 ENA MOD/0 Serial interface format selection Output data under software control 0: Selects 3-line serial interface (SIO3). 1: Selects 2-line serial interface (SIO4). 1 Port control and serial interface selection 0: Port output 1: Serial interface φL14 0: Output data 0 (L when N-channel open drain set) 1: Output data 1 (high impedance when N-channel open drain set) φK14 0: Internal data 0 1: Internal data 1 70 2002-05-14 TC9325F φL15P3 Y1 Y2 Y4 Y8 CK0 CK1 F/F reset MSB Serial output data format selection Serial clock output frequency selection 0: Input/output from most significant bit of serial output data 1: Input/output from least significant bit of serial output data SIO operation flag reset 0: Don’t care 1: Resets all flags (STA F/F, STP F/F, SDA_NG F/F, SIO F/F, ACK) Serial Clock Output Frequency CK1 CK0 4.5 MHz 75 kHz 0 0 450 kHz* 37.5 kHz* 0 1 150 kHz 12.5 kHz 1 0 225 kHz 17.75 kHz 1 1 75 kHz 6.25 kHz (Note) Note: The output frequency varies depending on the CPU operation clock used. Note: When TC9325F is set as a slave, CK0 and CK1 are don’t care. When set as a slave, input a shift clock no higher than the frequency indicated by the asterisk (*). φL16P3 Y1 Y2 Y4 Y8 STP * * * Halt serial operations Y1 φL13P3 BUSY Y2 Y4 0: Don’t care 1: Forcibly halts serial operations and cancels start of serial operations. Y8 COUNT SIO F/F SO4-NG Flag for detecting 2-line serial data output state 0: Normal SO4 data transfer 1: Abnormal SO4 data transfer SIO start flag 0: Perform SIO operations 1: Perform no SIO operations Detection of number of clock cycles 0: Number of clocks normal (the number of SCK clocks is a multiple of 4) 1: Number of clocks abnormal (the number of SCK clocks is not a multiple of 4) SIO operation monitor 0: SIO operation complete 1: SIO operation in progress 71 2002-05-14 TC9325F Y1 φK15P3 Y2 Y4 STA F/F STP F/F BUSY4 2-line SIO operation monitor Y8 ACK Two-line SIO acknowledge data detection 0: Normal response 1: Abnormal response STA F/F operation start flag → 1: Start operation STP F/F operation complete flag → 1: Complete operation BUSY4 operation monitor → 1: Operation in progress Access serial interface control and serial data using the OUT1 instruction with the operand [CN = 2H to 6H] and the IN1 instruction with the operand [CN = 3H to 5H] on I/O map page 3. The serial interface pins also function as the I/O port 5 P5-1, P5-2, and P5-3 pins. Setting the SIO ON bit to 1 switches the I/O port 5 pins to SI, SO, and SCK pins, respectively. Note: The serial interface inputs all incorporate Schmitt trigger circuits. Note: Even when the serial interface is selected, the SI pin (P5-1) can still be used as an I/O port. Therefore, the pin can be used for SIO strobe signals. When setting this pin as a serial input, set the P5-1 I/O control bit to input. 72 2002-05-14 TC9325F 1) SIO ON Bit The SIO ON bit switches the P5-2/SO3/SO4 and P5-3/SCK3/SCK4 pins to serial interface function pins SO3/SO4 and SCK3/SCK4. Setting SIO ON to 1 sets the pins to serial interface function pins; setting the bit to 0 sets the pins as I/O port 5. When serial interface functions are set, these pins can all be controlled by the serial interface control bits. Note, however, that the I/O port input data can still be read. Setting pin P5-1/SI3 to serial interface functions allows the pin to be used as a serial input. The I/O port function can be used even when the pin is set to serial interface functions. Input/output can be set using the I/O control port and data can be input/output using the I/O data port. Therefore, when this pin is set to serial input, it must also be set as an I/O port input. 2) MOD Bit The MOD bit selects the serial interface format. Setting MOD to 0 selects 3-line serial interface; setting MOD to 1 selects 2-line serial interface. When two-line serial interface is selected, the EDGE and SCK-INV bits (described below) are set to 0 and the Nch bit to 1. When three-line serial interface is selected, the ACK, BUSY4, STA F/F, and STP F/F bits are invalidated. 3) EDGE, SCK-INV, and ENA Bits The EDGE bit sets the serial clock (SCK3/SCK4) edge. Setting EDGE to 0 inputs serial data on the clock rising edge and outputs serial data on the falling edge. Setting EDGE to 1 inputs serial data on the clock falling edge, and outputs serial data on the rising edge. The SCK-INV bit sets the shift clock’s (SCK3/SCK4) input/output waveform. The bit setting determines whether to start the waveform from the serial clock’s H level output or from L level output. When SCK-INV is set to 0 the shift clock waveform starts from L level output, and when the bit is set to 1 the shift clock waveform starts from H output. The ENA bit switches between serial operations and software control. Setting ENA to 0 selects serial operations. Setting the bit to 1 selects software control. When ENA is set to serial operations, the serial clock (SCK3/SCK4 pin) and serial data (SO3/SO4 pin) are input/output. When ENA is set to software control (ENA = 1), the serial clock is output to the SCK3/SCK4 pin and serial data to the SO3/SO4 pin. When 3-line serial interface is selected with the EDGE and SCK-INV bits both set to 0 or to 1, setting the STA bit to 1 automatically resets ENA to 0, then sets it back to 1 on completion of serial operations. When the EDGE and SCK-INV bits are set to (1, 0) or (0, 1), neither set nor reset occurs. Therefore, with these settings, normally the ENA bit is set to 0. When 2-line serial interface is selected, the ENA bit is set to 1 (forcibly terminate serial operations) under the following conditions. ● On a shift clock (SCK4) rising edge after the SDANG_F/F bit is detected as 1 (data output result flag NG) ● On a shift clock (SCK4) rising edge after the STP F/F bit is detected as 1 (2-line serial interface terminated) ● On a shift clock (SCK4) rising edge after the ACK bit is detected as 1 (acknowledge detection NG) ● On a shift clock (SCK4) falling edge at completion of a shift operation Also, when 2-line serial interface is selected, the ENA bit is reset to 0 (serial operations start) under the following conditions. ● On a shift clock (SCK4) rising edge after the STA bit is detected as 1 (serial operations start) ● On a shift clock (SCK4) rising edge after the STA F/F bit is detected as 1 (2-line serial interface terminated) 73 2002-05-14 TC9325F 4) MSB Bit, 8BIT Bit, Serial Data Port The MSB bit controls the sequence of the serial input/output data. Setting MSB to 0 outputs the serial data from the least significant bit (LSB: SO0 to SO7) and inputs serial data from the least significant bit (LSB: SI0 to SI7). Setting MSB to 1 outputs the serial data from the most significant bit (MSB: SO7 to SO0) and inputs serial data from the most significant bit (MSB: SI7 to SI0). The 8BIT bit selects the length of the serial data. Setting this bit to 0 selects 4-bit data; setting the bit to 1 selects 8-bit data. When 4-bit data is selected, the lower four bits (SO0 to SO3, SI0 to SI3) of the serial data are used. The serial output data of the serial data port (SO0 to SO7) are transferred to the shift register at the start of serial operations, then output to the serial interface. Serial input data (SI0 to SI7) are loaded from the shift register. STA bit set to 1 SCK3 pin SO3 pin 1 SO3/SO4 2 3 5 4 6 7 8 SO0 SO1 SO2 SO3 SO4 SO5 SO6 SO7 SI0 SI1 SI2 SI3 SI4 SI5 SI6 SI7 SI3 pin BUSY SO3/SO4 Interrupt Serial Operation When 8-Bit Data (8BIT = 1), LSB Output (MSB = 0) Set STA bit set to 1 SCK3 pin SO3 pin SI3 pin 1 SO3/SO4 2 3 4 5 6 7 8 SO7 SO6 SO5 SO4 SO3 SO2 SO1 SO0 SI7 SI6 SI5 SI4 SI3 SI2 SI1 SI0 BUSY SO3/SO4 Interrupt Serial Operation When 8-Bit Data (8BIT = 1), MSB Output (MSB = 1) Set 5) SCKO Bit The SCKO bit sets the serial clock (SCK3/SCK4) input/output. When using the TC9325F as the master controller, set SCKO to 1 to output the serial clock. When TC9325F is the slave, set SCKO to 0 to input the serial clock. 74 2002-05-14 TC9325F 6) CK0, CK1 Bits The CK0, CK1 bits select the serial clock frequency when TC9325F is selected as the master. Because the frequency varies according to the CPU clock used, select the frequency in accordance with your specifications. The clock duty is 50%. CK1 CK0 0 Serial clock output frequency 4.5 MHz 75 kHz 0 450 kHz* 37.5 kHz* 0 1 150 kHz 12.5 kHz 1 0 225 kHz 17.75 kHz 1 1 75 kHz 6.25 kHz (Note) Note: The output frequency varies in accordance with the operating clock of the CPU used. When TC9325F is set as a slave, CK0 and CK1 are don’t care. When set as a slave, input a shift clock no higher than the frequency indicated by the asterisk (*). 7) SCK3/SCK4, SO3/SO4 Bits When the ENA bit is set to 1 with the SCK3/SCK4, SO3/SO4 pins set as outputs (by the port 5 I/O control and SCKO/SI1S bits), the SCK3/SCK4 and SO3/SO4 bit data are output as-are. When two-line serial interface is selected, the SCK3/SCK4 and SO3/SO4 bits are set to 1 under the following conditions. ● On a shift clock (SCK4) rising edge after the SDANG_F/F bit is detected as 1 (data output result flag NG) ● On a shift clock (SCK4) rising edge after the STP F/F bit is detected as 1 (two-line serial interface terminated) Also, when two-line serial interface is selected, the SCK3/SCK4 bit is reset to 0 under the following condition. (The SO3/SO4 bits are not reset by a serial operation.) ● On a shift clock (SCK4) falling edge at completion of a shift operation 8) 9) SI3S Bit The SI3S bit switches the serial interface data input/output. Setting SI3S to 1 selects the P5-2/SO3 pin as a serial output and the P5-1/SI3 pin as a serial input. When using the P5-1/SI3 pin as a serial input, the P5-1 I/O control port must be set to input. Setting SI3S to 0 selects the P5-2/SO3 pin as a serial input and the P5-1/SI3 pin as an I/O port input/output (P5-1). The SI3S bit is used to switch the SO3 pin input/output; the input/output switching is updated under the following conditions. Egde SCKINV SI3S Bit Updating 0 1 After STA = 1 set, updates on serial clock (SCK3/SCK4) falling edge. 1 0 After STA = 1 set, updates on serial clock (SCK3/SCK4) rising edge. 0 0 1 1 Updates when STA = 1. Nch Bit The Nch bit selects CMOS output or N-channel open drain output when the SO3/SO4 and SCK3/SCK4 pins are set to output. Setting the Nch bit to 0 sets CMOS output; setting Nch to 1 sets N-channel open drain output. When N-channel open drain is set, the serial clock operation wait function and the serial data output monitor function operate (see the section on the SO-NG F/F). The serial clock wait function pauses the serial clock output when TC9325F is set as a master (serial clock output set) and the serial output clock is set to forcible wait by an external device (which sets the serial clock to L). 75 2002-05-14 TC9325F Maximum tmax SCK3/SCK4 pin tmax = When 4.5-MHz CPU clock used: 1.11 µs When 75-kHz CPU clock used: 13.3 µs Serial clock output Wait period Serial clock output restarted Wait released Forcible wait set by external device (External device outputs L level) 10) BUSY Bit The BUSY bit is used to reference the serial operation state. When a serial operation starts (when the STA bit is set to 1 or the serial operation start conditions are satisfied), BUSY is set to 1. Before attempting to reference serial data, first check that this bit is set to 0. The falling edge of the BUSY bit generates interrupt requests (on completion of a serial operation). 11) COUNT Bit The COUNT bit is used to determine whether data have been sent or received in 4-bit units. When the number of shift operations is a multiple of 4, the COUNT bit outputs 0. When not a multiple of 4, the bit outputs 1. COUNT is reset to 0 whenever the F/F reset bit is set to 1. 12) SIO F/F Bit The SIO F/F bit is set to 1 when the SCK3/SCK4 pin starts a clock operation. When TC9325F is set as a master (serial clock set to external input), this bit can be used to check whether a serial operation has started or is suspended. The SIO F/F bit is reset to 0 whenever the F/F reset bit is set to 1. 13) SO-NG F/F Bit When serial data are output, this bit can be used to check whether the correct data have been output. When the Nch bit is set to 1 (N-channel open drain output), the SO-NG F/F bit is valid. When the SO-NG F/F bit is set to 0, the data output is normal; when the bit is set to 1, the data output is abnormal. When the data output is confirmed as abnormal with 2-line serial interface set, the ENA, SO3/SO4, and SCK3/SCK4 bits are all set to 1, the serial clock and serial data pins are open, and high impedance is set. This overrides the master restrictions when multiple masters are set and simultaneously outputting data. After this, serial operations continue until the completion of 8-bit data serial operations. Then, after checking that the serial operations have completed (BUSY3), the serial data can be referenced. Even though the data output is judged abnormal with 3-line serial interface set, no setting of the ENA, SO3/SO4, and SCK3/SCK4 bits takes place and their status is unchanged. In this case, the SO-NG F/F bit is used to determine whether the data output is normal or abnormal. The SO-GN F/F bit is reset to 0 whenever the F/F reset bit is set to 1. TC9325F serial output (In 2-line serial interface this output pin is open.) SCK3/SCK4 pin L level output by other external device SO3/SO4 pin Serial data abnormal SO-NG F/F bit ENA bit When 2-line serial interface is set, the ENA bit is set to 1 and the serial clock data pin is open. 14) STA Bit This bit is used to start serial interface operations. When 3-line serial interface is set, each setting of the STA bit to 1 starts a serial operation. Setting STA to 1 transfers serial output data to the shift register. When the serial clock is set to an internal clock (master), a serial clock is output. When the serial clock is set to an external clock (slave), the interface stands by for serial clock input. When 2-line serial interface is set, inputting the start conditions to the SCK4 and SO4 pins automatically starts serial operations. When TC9325F is set as the master, a serial clock (SCK4) is output for serial operations. When TC9325F is a slave, an external serial clock is used for serial operations. When receiving or sending data equal to or larger than two bytes, setting STA to 1 on completion of serial operations on the first byte transfers the serial output data to the shift register and starts serial operations on the falling edge of the next serial clock. 76 2002-05-14 TC9325F 15) ACK Bit The ACK bit is the acknowledge bit. This bit is valid when 2-line serial interface is set. After inputting/outputting 8-bit serial data, the status of the SO4 pin is input to the ACK bit on the next rising edge. When 0 is input to ACK with STA already set to 1, the next serial operation begins. When 1 is input to ACK, any serial operations for which the STA bit is already set to 1 are cancelled. ACK is reset to 0 whenever the F/F reset bit is set to 1. 16) STA F/F, STP F/F, BUSY4 Bits These bits are used to detect the 2-line serial interface start and stop conditions and are valid when 2-line serial interface is set. When the 2-line serial interface start conditions are detected, the STA F/F and BUSY4 bits are set to 1. When the 2-line serial interface stop conditions are detected, the STP F/F bit is set to 1 and the BUSY4 bit is reset to 0. The STA F/F and STP F/F bits are reset to 0 whenever the F/F reset bit is set to 1. The 2-line serial interface operation status can be detected by checking these bits. Start conditions Stop conditions SCK4 pin ACK SO4 pin STA F/F bit Acknowledgement from external device STP F/F bit Setting STA to 1 again resumes serial operation. BUSY bit BUSY4 bit Serial operation (hardware control) Software control Software control ENA bit Instruction (when master) SO3/ SO4 = 1 SO3/SO4 = 1 STA = 1 SCK3/SCK4 = 0 SCK3/ SCK4 = 1 (STA = 1) SCK3/ SCK4 = 1 SCK3/ SCK4 = 0 SO3/SO4 = 0 SO3/ SO4 = 1 STA is set to 1 at transfer of data equal to or larger than 2 bytes. SCK3/SCK4 bits are automatically cleared to 0 on completion of a serial operation Example of Two-Line Serial Interface Operation 17) STP Bit The STP bit is used to forcibly terminate serial operations still in progress and to cancel the start of a serial operation. At this time the bit is set to 1. With 2-line serial interface set, when STP is set to 1 to terminate a serial operation in progress, the serial operation terminates at the time the setting is executed. With 3-line serial interface set, when STP is set to 1 to terminate a serial operation in progress, the serial operation is terminated on the falling edge of the serial clock. Also, STP can be used to cancel the commencement of a serial operation where STA is already set to 1. 77 2002-05-14 TC9325F Start condition Interrupt SO4 pin D7 D6 SCK4 pin 1 2 A D5 D1 D0 3 7 8 (ACK) B ACK (WAIT) 9 Interrupt Stop condition D7 D4 D1 D0 1 2 7 8 B C (ACK) ACK (WAIT) 9 C D 2-Line Serial Interface Timing Example First set up the following operating conditions Setting mode conditions ● SIOon = 1: Enables serial interface. ● SCKO = 1: Sets serial clock output (master mode). ● EDGE = 0: Sets rising edge shift. ● SCK-INV = 0: Sets positive logic output. ● 8BIT = 1: Sets 8-bit operations. ● Nch = 1: Sets N-channel open drain output. ● MSB = 1: Sets input/output data from MSB ● CK0/1: Sets by operating frequency. ● MOD = 1: Sets 2-line serial interface operations. When outputting serial data, first set data to the serial output data port (φL2CA, φL2CB). If TC9325F is the master, set SCKO = 1; if the slave, set SCKO = 0; if data output, set SO1 = 0; if data input, set SOI = 1. If TC9325F is the master, control the start conditions output by software. If the slave, set to wait after setting the start conditions. Start conditions (Timing A) For software control when TC9325F is the master, set the SO3/SO4 and SCK3/SCK4 bits to 1 to set software control (ENA = 1) (φL14P3 ← FH). Set bits SO3/SO4 to 0 (φL14P3 ← EH), then set the SCK3/SCK4 bits to 0 (φL14P3 ← CH) to output the start condition waveform. At that time, the serial operation automatically starts on the rising edge of the SCK4 pin, as when STA = 1 is set (no need to set STA = 1). If the serial data input/output (SOI) setting has been changed, the serial data input/output (SOI) is updated on the serial clock’s falling edge. If TC9325F is set as a slave, shift operations start automatically at the start conditions. When serial operations start, the flags are set as follows: BUSY = 1: Serial operation in progress. BUSY4 = 1: Set to 1 at start condition. 2-line serial operation in progress. STA F/F = 1: Set to 1 at start condition. Detects 2-line serial operation start signal. SIO F/F = 1: Set to 1 on SCK4 pin rising edge (1). Detects serial operation clock. ENA = 0: Serial operation input/output state. In serial operations, the SO4 pin state is input to the serial interface on a rising edge; serial data are output on a falling edge. On the falling edges of the eight serial clocks, the following states are set automatically: BUSY = 0: Serial operations complete BUSY4 = 1: Two-line serial operation in progress. Serial operations (Timing B) STA F/F: Flag held SIO F/F: Flag held ENA = 1: Under software control (SO3/SO4, SCK3/SCK4 bits output) SCK3/SCK4 = 0: SCK4 pin set to L and clock wait state set In addition, a serial interface interrupt is generated if the interrupt is enabled. When the TC9325F is the master, even though an H level (pulled-up state) is output to the SCK4 pin during a serial operation, if the pin state is L (waiting for the clock from another device), the serial clock is halted until the clock of the other device is released. Even though an H level is output from the SDA pin during serial data output, if the pin state is L (simultaneous output detected on a multi-master system), the SO3/SO4, SCK3/SCK4, and ENA bits are automatically set to 1 and software control is set on the SCL clock rising edge, then the output is released (Hz). At that time, the SO-NG F/F bit is set to 1. To output an H level from the SO3/SO4 pin after the serial operation completes (set to 0 on the start condition), set the SO3/SO4 bit to 1 (φL14P3 ← 9H or 6H) during a serial operation. Where the stop conditions are satisfied during a serial operation, an interrupt is generated if enabled. 78 2002-05-14 TC9325F Software is used to control the acknowledge detection and output. On completion of a serial operation, ENA = 1, SCK3/SCK4 = 0, the SCK4 pin is automatically set to L, and clock output from other devices is prohibited. This state allows the necessary processing, such as reading serial input data and setting the next data. When that processing is complete, set the necessary conditions, then set the STA bit to 1. Next, if the TC9325F is the master, generate an acknowledge clock by software control. Use software control to set the following: Acknowledge output: SO3/SO4 = 0, SCK3/SCK4 = 0 (φL14P3 ← CH) → SCK3/SCK4 = 1 (φL14P3 ← EH) → SCK3/SCK4 = 0 (φL14P3 ← CH) Acknowledge detection (Timing C) Acknowledge input: SO3/SO4 = 1, SCK3/SCK4 = 0 (φL14P3 ← DH) → SCK3/SCK4 = 1 (φL14P3 ← FH) → SCK3/SCK4 = 0 (φL14P3 ← DH) These states are read to the ACK bit on the rising edge of the SCL pin clock. If the TC9325F is the slave, set the following for during a clock wait state set by completion of a serial operation: Acknowledge output: SO3/SO4 = 0, SCK3/SCK4 = 1 (φL14P3 ← EH) Acknowledge input: SO3/SO4 = 1, SCK3/SCK4 = 1 (φL14P3 ← FH) These states are read to the ACK bit on the rising edge of the SCL pin clock. On the falling edge of the acknowledge clock, the serial operation start (STA = 1) set prior to the reading of the acknowledge is validated and the serial operation commences. Stop condition (Timing D) If the TC9325F is the master, set the output of the stop conditions by software control. If the slave, set the stop conditions, then set to wait state. Set the following software control when the TC9325F is the master: SO3/SO4, SCK3/SCK4 bits = 0 (φL14P3 ← CH), SCK3/SCK4 bits = 1 (φL14P3 ← EH), then set the SO3/SO4 bits to 1 (φL14P3 ← FH). If TC9325F is the slave, the following flags detect the stop condition and terminate the operation. When the stop condition is detected, the flags are: STP F/F = 1: Set to 1 by stop condition. Detects completion of 2-line serial operations. BUSY4 = 0: Reset to 0 by stop condition. 2-line serial operation complete. If completion is detected, the start of serial operations must be forcibly prevented. To do this, set the STP bit to 1 beforehand to terminate the operation. 79 2002-05-14 TC9325F Shift counter 900 kHz 75 kHz SCKINV edge Interrupt request BUSY STA F/F BUSY4 MODE ACK detection Data control SO NG F/F Nch F/F reset F/F reset ENA BUSY MODE SO3/SO4 Output setting 8 BIT 63 SI3S 4-bit shift register 4-bit shift register 62 MSB Selector SO0 SO1 SO2 SO3 SCK3/ SCK4 (P5-3) Shift control 2-line serial interface detection STP F/F 64 SCK3/ SCK4 Shift clock F/F STA STP Output setting Shift clock generator SI3S 8 BIT COUNT Nch SIO F/F Nch CK1 SCKCK2 INV edge STA SCKO 7. Serial Interface Structure SO3/ SO4 (P5-2) SI3 (P5-1) Output setting SO4 SO5 SO6 SO7 Serial output data SI0~SI3 SI4~SI7 -3 Serial input data -2 -1 -0 I/O port 4 data -3 -2 -1 -0 I/O port 4 I/O control data The serial interface consists of a control circuit, shift registers, and I/O ports. Note: The SI pin can also be used as I/O port 5 (P5-1). Note: The contents of the shift registers are loaded to data memory as the data and serial input data. Therefore, the data set as serial output data and the serial input data do not match. Note: The serial input pins all incorporate Schmitt trigger circuits. 80 2002-05-14 TC9325F ○ A/D Converter The 8-channel, 8-bit resolution A/D converter is used for many purposes such as measuring voltages. 1. A/D Converter Control Port, Data Port φL10P3 Y1 Y2 Y4 Y8 AD SEL0 AD SEL1 AD SEL2 STA A/D converter start bit Setting to 1 performs A/D conversion. A/D input pin selection φL11P3 Y1 Y2 Y4 Y8 CK SEL0 CK SEL1 * * SEL0 SEL1 SEL2 A/D Input 0 0 0 ADIN1 1 0 0 ADIN2 0 1 0 ADIN3 1 1 0 ADIN4 0 0 1 ADIN5 1 0 1 ADIN6 0 1 1 ADIN7 1 1 1 ADIN8 AD conversion clock SEL0 φK10P3 SEL1 4.5 MHz Selected 75 kHz Selected 0 0 900 kHz 75 kHz 1 0 100 kHz Prohibited 0 1 50 kHz Prohibited 1 1 900 kHz 75 kHz φK12P3 φK11P3 Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 BUSY 0 0 0 A/D converter operation monitor LSB A/D conversion data MSB 81 0: A/D operation completed 1: A/D conversion in progress 2002-05-14 TC9325F The A/D converter uses 8-bit resolution, successive comparison conversion. The internal power supply (VDD) is used as the AD conversion reference voltage. The A/D converter compares the voltage resulting from dividing the power supply by 256 with the A/D input voltage and outputs the comparison data to the A/D conversion data port. The A/D conversion input is multiplexed to eight channels of external input pins (pins ADIN1 to ADIN8) and selected by the AD SEL0 to SEL2 bits. The A/D converter performs A/D conversion whenever the STA bit is set to 1. When the CPU clock is set to 4.5 MHz, the CK SEL1/2 bits can select the conversion clock among 900-kHz, 100 kHz, and 50 kHz. When the CPU clock is set to 75 kHz, the conversion clock is selected as 75 kHz. The corresponding conversion times are: 23, 192, and 382 µs, and 294 µs. The BUSY bit can be referenced to check whether A/D conversion is complete. After A/D conversion is complete, the controller loads the A/D conversion data to data memory. Use the following formula to calculate the A/D comparison result. VDD × n + 0.5 n − 0.5 >n> (254 > (255 = = 1) < = A/D input voltage < = VDD × =n> = 0) 256 256 (where n is the [decimal] A/D conversion data value) These control bits can be accessed by the OUT2 instruction with the operand [CN = 0H, 1H] and the IN2 instruction with the operand [CN = 0H to 2H] on I/O map page 3. 2. A/D Converter Circuit Structure 54 ADIN8 (P3-3) Sample and hold 53 ADIN7 (P3-2) 52 ADIN6 (P3-1) 51 ADIN5 (P3-0) 50 ADIN4 (P2-3) 49 ADIN3 (P2-2) R Control circuit 48 ADIN2 (P2-1) 47 ADIN1 (P2-0) R STA BUSY SEL0~2 R 3R/2 DCREF Decoder AD0 ~ AD7 A/D conversion latch A/D conversion data Comparator R/2 46 DCREF BUSY The A/D converter consists of a comparator, an A/D conversion latch, and a control circuit. Because the comparator block operates only when the BUSY bit is set to 1, the A/D converter consumes no current when not operating. Note: Set to input ports the I/O ports corresponding to the A/D input pins used. 82 2002-05-14 TC9325F ○ Buzzer Output The buzzer output is used for such purposes as audible alarms or to issue audible confirmation for key-input or Tuning Scan mode. The buzzer frequency can be set from combinations of four output modes and eight frequencies. 1. Buzzer Control Port φL19P3 Y1 Y2 Y4 Y8 BF0 BF1 BF2 BEN Buzzer frequency selection data BF2 BF1 BF0 Buzzer Frequency Duty 0 0 0 0.625 kHz 1/2 0 0 1 0.75 kHz 1/2 0 1 0 1 kHz 2/3 0 1 1 1.25 kHz 1/2 1 0 0 1.5 kHz 1/2 1 0 1 2.08 kHz 2/3 1 1 0 2.5 kHz 1/2 1 1 1 3 kHz 2/3 Buzzer output enable bit 0: Fixes buzzer output (L level when POL = 0; H level when POL = 1). 1: Enables buzzer output. φL1AP3 Y1 Y2 Y4 Y8 BM0 BM1 BUZR ON POL Buzzer output logic setting Buzzer output mode selection 0: Positive logic output (buzzer frequency output from L level on positive logic) 1: Negative logic output (buzzer frequency output from H level on negative I/O port 5 P5-0/buzzer output selection 0: Selects I/O port 5 (P5-0). 1: Selects buzzer output. BM1 BM0 Buzzer Output Mode 0 0 Continuous output (mode A) 0 1 One-shot output (mode B) 1 0 10-Hz intermittent output (mode C) 1 1 10-Hz intermittent output with 1-Hz intervals (mode D) The buzzer output uses the P5-0 I/O port. To switch the port over to buzzer output, set the BUZR ON bit to 1 and set the port to an output using the P5-0 I/O control port. After setting the buzzer frequency, mode, and logic, setting the buzzer enable bit to 1 outputs the buzzer. When setting the buzzer conditions, set the buzzer enable bit to 0. In continuous output (mode A), setting the buzzer enable bit to 1 outputs buzzer frequency continuously. Setting the bit to 0 terminates the buzzer output. In one-shot output (mode B), a 50 ms sound is output every time the buzzer enable bit is set to 1. In this mode, setting the bit to 1 again during the buzzer output (50 ms) lengthens the buzzer output by 50 ms, to 100 ms. The buzzer output time can be easily adjusted. Setting the buzzer enable bit again during the 100 ms of buzzer output lengthens the output to 150 ms, In 10-Hz intermittent output (mode C), setting the buzzer enable bit to 1 sets repetition of output for 50 ms then pause for 50 ms. Setting the bit to 0 terminates the buzzer output. 83 2002-05-14 TC9325F In 10 Hz intermittent output with 1 Hz intervals (mode D), setting the buzzer enable bit to 1 sets repetition of output for 50 ms then pause for 50 ms over a 500 ms period. Then, after a silent period of 500 ms the output/pause is repeated, and so on. Setting the bit to 0 terminates the buzzer output. In modes B, C, and D, when the buzzer enable bit is set to 0 during buzzer output, the buzzer completes output of 50 ms before terminating. The contents of the timer port can be used to determine the buzzer output state. When the timer port 10 Hz bit is set to 0, the buzzer is output; when the bit is 1, the buzzer is paused. Buzzer control is accessed using the OUT1 instruction with the [CN = 9N, AH] operand on I/O map page 3. 2. Buzzer Circuit Structure 10 Hz Multiplexer 0.625 kHz~3 kHz 1 Hz Buzzer output circuit BF0~BF2 61 BUZR (P5-0) BM0~BM2 BEN 3. Buzzer Output Timing Buzzer frequency “1” “1” “0” 10 Hz BUZR output (mode A) Setting the BEN bit to 1 again during buzzer output lengthens the output by 50 ms. BUZR output (mode B) 50 ms BUZR output (mode C) Buzzer frequency output interval 50 ms Pause interval Output state in mode C 500 ms Pause interval BUZR output (mode D) 500 ms Output interval Note: When outputting the buzzer, set P4-0 to output state (set the I/O control port to 1). 84 2002-05-14 TC9325F ○ Pulse Counter The pulse counter is an 8-bit up/down counter. The pulse counter can detect the clock count during CMOS input using the INTR2 pin. This counter is useful for detecting the count when a tape is running. 1. Pulse Counter Control Port, Data Port φL2B Y1 Y2 Y4 Y8 SEL1 SEL2 SEL4 SEL8 Data Selection DAL address data φL3B DAL address data Y1 Y2 Y4 Y8 Y1 DA0 Y2 DA1 Y4 DA2 Y8 DA3 Y1DAL address Y2 Y4 1 0 Y1DAL address Y2 Y4 2 1 2 φK3B Y8 4 Y4 Y8 Y1 DA0 Y2 DA1 Y4 DA2 Y8 DA3 Y1DAL address Y2 Y4 1 Y8 2 CTR OVER RESET RESET 5 DAL address 4 PC0 * Pulse counter control Control * Y8 DAL address 3 3 * Y8 Y1DAL address Y2 Y4 2 1 DAL address 4 DOWN POL Y2 0 DAL address 3 3 Y1 4 PC1 PC3 Pulse counter data PC4 * 5 Pulse counter control PC2 PC5 PC6 PC7 Data Pulse counter data OVER 6 0 0 0 Pulse counter control ● DOWN bit: Sets the up/down for the 8-bit up/down counter. 0: Upcount 1: Downcount ● POL bit: Sets the counter input edge of the input pin (INTR2 pin). 0: Count on input falling edge 1: Count on input rising edge ● CTR RESET bit: Resets the 8-bit up counter whenever set to 1 ● OVER RESET bit: Resets the OVER F/F whenever set to 1. PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 0 2 LSB OVER 7 2 MSB Pulse counter data 85 OVER F/F bit ............. Detects overflow 8 0: The counter value is < =2 −1 8 1: The counter value is > = 2 (overflowed) 2002-05-14 TC9325F The pulse counter counts up the number of pulses input to the INTR2 pin. The POL bit sets the count clock edge of the input pin. When POL is set to 0, the pulses are counted on the falling edge. When POL is set to 1, the pulses are counted on the rising edge. This bit is normally fixed. The DOWN bit sets the up/down of the 8-bit counter. Setting DOWN to 0 specifies upcount; setting the bit to 1 specifies downcount. The bit can be freely switched between up and down counting. However, note that if a clock pulse is input while the bit is being switched, the count is cancelled. When 28 or more pulses are input, the OVER F/F bit is set to 1. To count with 8 bits or higher, use OVER F/F to detect the overflows, adding or subtracting the number of overflows that occur on data memory. After an overflow is detected with OVER F/F, set the OVER RESET bit to 1 to reset OVER F/F. The CTR RESET bit is only used to reset the 8-bit counter. Setting the bit to 1 resets the counter. The counter data are loaded to data memory in binary format. Pulse counter control and data loading are accessed by the OUT3/IN3 instruction with the operand [CN = BH]. These instructions are located in the DAL address register port. This port can be divided/indirectly specified and set using the data selection port (φL2B). Set the data of the desired port first, then access the data port later. The data selection port is incremented by 1 every time the DAL address port (φL3B, φK3B) is accessed. Accordingly, after setting the data selection port, the data can be repeatedly set. Note: Switching the POL bit may input a clock pulse. After switching the bit, reset the counter data using the reset bit. Note: The data selection port is automatically incremented by 1 at each access of φL2C, φL2D, φL2E, φL2F, φL3B, and φK3B. 2. Pulse Counter Circuit Structure OVER RESET CTR RESET To interrupt circuit DOWN F/F 69 PCTRin (INTR2) 8-bit up/down counter POL OVER F/F PC0~PC7 Note: The pulse counter input is a Schmitt trigger input. Note: The pulse counter can be used with an interrupt function (INTR2 pin input) at the same time. 3. Example of Pulse Counter Timing Set data to pulse counter control bit Execute CTR/OVER reset Execute OVER reset Set DOWN bit to 1 Minimum pulse width1 µs DOWN bit CTRin input Counter data 01H 02H 03H FFH 00H 01H 02H N N+1 N−1 N−2 OVER F/F 86 2002-05-14 TC9325F ○ Input/Output Ports (I/O Ports) The 40 I/O ports (derived from I/O P-1 to P-10) are used to input/output control signals. The following table shows the shared functions and the characteristics of each I/O port. I/O Port Shared/Additional Functions I/O port 1 I/O port 2 Input 8-bit AD converter analog input. The potential to DCREF can be inputted. I/O port 3 Output CMOS CMOS P4-0 I/O port 4 P4-1~3 P5-0 Serial interface 1/2 Schmitt trigger Buzzer output CMOS Serial interface 3/4 Schmitt trigger CMOS/ N-channel open drain CMOS CMOS I/O port 5 P5-1~3 I/O port 6 I/O port 7 Either pulled up/pulled down can be set. Note that pulled up or pulled down must be set for all the bits I/O port 8 I/O port 9 LCD driver segment output I/O port 10 1. I/O Port Control, I/O Port Data Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8 -0 -1 -2 -3 -0 -1 -2 -3 φL20 -0 φL21 -1 -2 -3 φL22 -1 -2 -3 φL23 -1 -2 -3 φL24 -1 -2 -3 I/O control data I/O control port 5 -0 φL25 -1 -2 -3 I/O control port 6 -0 φL26 -1 -2 φL27 -1 -2 -0 -1 -2 -1 -2 I/O control port 10 0: Input 1: Output -0 -1 -0 -1 -2 -3 -2 -3 I/O port data -1 -2 -3 I/O port 6 -1 -2 -3 I/O port 7 φL/K37 -1 -2 0: Input/output pin L level 1: Input/output pin H level -3 I/O port 8 -0 φL/K38 -1 -2 -3 I/O port 9 -0 87 -3 II/O port 5 -0 φL/K39 -2 I/O port 4 -0 -3 -3 I/O port 3 φL/K35 -3 -2 I/O port 2 -0 -3 I/O control port 9 -0 -1 φL/K36 I/O control port 8 φL28 -0 φL/K34 -3 I/O control port 7 -0 -1 φL/K33 I/O control port 4 -0 -0 φL/K32 I/O control port 3 -0 I/O port 1 φL/K31 I/O control port 2 -0 φL29 φL/K30 I/O control port 1 -1 -2 -3 I/O port 10 2002-05-14 TC9325F φL2A Y1 Y2 Y4 Y8 PD0 PD1 PD2 PD3 I/O port 8 pulled down I/O port 8 pull-down/pull-up control 0: Pull-up or pull-down off 1: Pull-up or pull-down on Note: PD0 to PD3 correspond to P8-0 to P8-3. Y1 φL3A Y2 Y4 Y8 Port 8 pulled up I/O port 8 pull-up/pull-down control bit 0: Pull-down 1: Pull-up The contents of the I/O control data port set the I/O ports to input/output. To set a port to input, set the I/O control data port bit corresponding to that I/O port to 0. To set to output, set the I/O control data port bit corresponding to the I/O port to 1. When an I/O port is set to output, the OUT3 instruction corresponding to the port controls the port’s output state. The IN3 instruction reads the data currently being output into data memory. Because the data read by the IN3 instruction are used to read the pin state, these do not always match the data output by the OUT3 instruction. When an I/O port is set to an input port, the IN3 instruction corresponding to that port is used to read the data being input to the port into data memory. At this time, the contents of the output latch do not affect the data. When the state of an I/O port set to input changes, I/O port 8 cancels the execution of the WAIT or CKSTP instruction and restarts the CPU operation. When the I/O bit of the MUTE port is set to 1, a change in the input state likewise forcibly sets the MUTE bit to 1. In addition, the I/O port 8 pull-down control port can set the port to pull-up or pull-down state. Each pin can be pulled up or pulled down. When the port is set to 1, it can be pulled up or pulled down. The I/O port 8 pull-up/pull-down control bit switches the pull-up and pull-down states. When the control bit is set to 0 the port is pulled down. When set to 1 the port is pulled up. 88 2002-05-14 TC9325F The pull-up/pull-down settings are useful for a key matrix structure where an I/O port output is set as the key matrix output and (pulled-up or pulled-down) I/O port 8 is set as the input. A low-noise key matrix can be formed by the following method. If I/O port 8 is pulled down, detect key input by setting the key matrix output side to high impedance (input state), outputting/scanning an H level signal to the key input line, and reading the input state of I/O port 8. If I/O port 8 is pulled up, detect key input by outputting an L level signal to the key input line in the same way. While the CKSTP or WAIT instruction is being executed, the key input can also be detected and the system can be restarted. If the restart is during execution of the CKSTP instruction, I/O port 1 is pulled up. Because all the I/O port outputs are set to L during Clock Stop mode, I/O port 8 waits in pulled-up state. Pressing a key changes the I/O port 8 input and restarts the system. Be sure to remember that a 100-ms standby period follows the release of Clock Stop mode at this time. Because the release of the WAIT instruction holds the output state, the system can be restarted either by a pull-up or pull-down, and because there is no standby after the release of the WAIT instruction, a key input can be immediately detected or implemented. Current dissipation can be minimized by using both these backup modes together. As the I/O port 8 input is the inverter input, I/O port 8 input cannot be used for methods involving intermediate potential. However, because other I/O ports input is on only when the input instruction is executed, inputting intermediate potential will not result in abnormal current dissipation. This allows such advantages as pull-ups with a lower potential than the VDD potential and the use of three-value output. I/O ports 2 and 3 are CMOS I/O ports, also used for 8-bit A/D converter input. I/O ports 4 and 5 are CMOS I/O ports. Pin P5-0 is also used for the buzzer output. Pins P4-1 to 3 and P5-1 to 3 are also used as serial interface pins. I/O ports 6 and 7 are CMOS I/O ports. I/O ports 9 and 10 are CMOS I/O ports and are also used as the LCD driver. A reset sets these pins as I/O port input pins. The diagram at left is an example of the structure of a key input matrix circuit. When no key is pressed, the ports are pulled up. Pressing a key inputs a source side (I/O port 9) L level signal. Be sure to keep in mind the time for the transition from L level to key input pull-up. Setting all the key source-side ports to L during WAIT instruction execution releases the WAIT instruction whenever a key is pressed. VDD P8-3 91 P8-2 90 P8-1 89 P8-3 P8-0 88 P7-3 87 P8-2 P7-2 86 P8-1 P7-1 85 P8-0 P7-0 84 Pulled up Pulled up P7-3 and P8-1 keys pressed Pulled up High impedance P7-3 P7-2 P7-1 Example of Key Input Matrix Circuit Structure P7-0 I/O port 8 data loading 89 2002-05-14 TC9325F ○ Register Ports The G-register, the data register, and the DAL address register mentioned in the CPU description are treated as an internal port. 1. G-Register (φ φKL1C, φKL1D) This register addresses the row address (DR = 04H to FFH) in data memory for the MVGD and MVGS instructions. This register is accessed by the OUT1/IN1 instruction with the operand [CN = CH to DH]. Using the STGI instruction, data can be set in the register with just one instruction. Note: The register value is only valid for the MVGD or MVGS instructions. The register is ignored for other instructions. The MVGD and MVGS instructions have no effect on this register. Note: Setting data 00H to FFH in the G-register allows all the data memory row addresses to be specified indirectly. (DR = 00H to FFH) Note: This register can be both read and written. If necessary, at an interrupt, save and restore the register contents using data memory. φL/K1D φL/K1C Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8 G0 G1 G2 G3 G4 G5 G6 G7 Data memory row address specification STGI instruction I0 I1 Transfer I2 I3 I4 I5 0 G7 G6 G5 G4 G3 G2 G1 G0 DR 0 0 0 0 0 1 0 0 04H 0 0 0 0 0 1 0 1 05H 0 0 0 0 0 1 1 0 06H 1 1 1 1 1 1 1 0 FEH 1 1 1 1 1 1 1 1 FFH 0 I* 90 2002-05-14 TC9325F 2. Data Register (φ φKL3C to φKL3F), DAL Address Register (φ φKL3B0 to φKL3B3), and Control Bits φL2D Y1 φL/K3A φL/K3B Y2 SEL1 SEL2 Y4 Y8 SEL4 SEL8 Y1 Y2 Y4 Y8 φL/K3B Y1 DALY2 Y41 address Y4 Y8 DAL (data) → DA/0 /0 /0 アドレス DA4Y1 DAL DA5Y2 DA6Y41DA7Y8 1 Data selection Y2 Y8 アドレス DA0Y1 DAL DA1Y2 DA2Y41DA3Y8 0 Y1 2 DA8 DAL DA9 アドレス DA10 1DA11 3 DA12 DA13 */0 0: Selects DAL ADDR3, (r) instruction. 1: Selects DAL DA instruction. */0 DAL address register DA0 DA1 DA2 DA3 DA4 LSB DA5 DA6 DA7 DA8 DA9 DA10 DA11 DA12 DA13 MSB DAL instruction indirect specification The data register contents are loaded to the DAL address register whenever 1 is set. φL/K3C φ L/K3D φ L/K3E φ L/K3F Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 LSB MSB 16-bit data register data Transfers 16 bits of program memory on execution of the DAL instruction. b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 16-bit program memory data The data register is a 16-bit register to load the program memory data when the DAL instruction is executed. The contents of the register are accessed in 4-bit unit by the OUT1/IN1 instruction with the operand [CN = CH to FH]. This register can be used for such purposes as LCD segment decoding, radio band edge data, and coefficient data for binary-to-BCD conversion. The DAL address register (DA) is a 14-bit register to indirectly specify program memory when the DAL instruction is executed. The DAL instruction has two operations, selected by the DAL bit. Setting DAL to 0 sets the program memory reference address to ADDR3 (6 bits) and the contents of the general register (r) in the operand. Setting DAL to 1 sets the reference address to the 14 bits of the DAL address register. Executing the DAL instruction with the DAL bit set to 0 sets the reference area to 0000H to 03FFH in program memory. However, executing the DAL instruction with the DAL bit set to 1 allows the whole program memory area (0000H to 3FFFH) to be referenced. Setting the (DATA) → DA bit to 1 transfers the data register contents to the 14-bit DAL address register with one instruction. The contents of the DAL address register can be accessed in 4-bit unit by the OUT3/IN3 instruction with the operand [CN = BH]. The DAL address register port can be divided/indirectly specified and set by the data selection port (øL2B). First set the data for the port you wish to set, then access the corresponding data port. The data selection port is incremented by 1 every time that port (φL3B, φK3B) is accessed. Accordingly, after setting the data selection port, the port can be repeatedly accessed. The DAL bit and (DATA) → DA bit can be accessed by the OUT3 instruction with the operand [CN = AH]. Note: The DAL address register is valid only at execution of the DAL instruction when the DAL bit is set to 1. The execution of other instructions has no effect on the register. The DAL instruction also does not affect the register. Note: The data register and DAL address register can be read and written. If necessary, at an interrupt, save and restore its contents using data memory. Note: Setting the (DATA) → DA bit to 0 performs no operation. When φK3A is accessed, only the DAL bit is read. (Other bits are 0.) 91 2002-05-14 TC9325F 3. Carry F/F (Ca Flag, φKL1B) This F/F is set when a carry or borrow occurs as the result of an arithmetic instruction. The F/F is reset if a carry or borrow does not occur. The carrier F/F can be accessed by the OUT1/IN1 instruction with the operand [CN = BH]. Accordingly, the carry F/F can be easily saved and restored when an interrupt occurs. When saving, use the IN1 instruction to write the carry F/F to data memory. When restoring, use the OUT1 instruction to transfer the saved data from data memory to the carry F/F. φL/K1C Y1 Y2 Y4 Y8 CA flag */0 */0 */0 Carry F/F ○ Timer Port The timer has a 500-Hz, 100-Hz, 10-Hz, and 2-Hz F/F bits. These are used for such purposes as clock operations or Tuning Scan mode counts. 1. Timer Port φL28P2 Y1 Y2 2 Hz F/F Timer Y4 Y8 Setting 1 resets the 500-Hz, 100-Hz, and 10-Hz bits and the counter for 1 kHz or below. Reset port Setting 1 resets the 2Hz-F/F. Y1 φK2F 2 Hz F/F Y2 Y4 Y8 10 Hz 100 Hz 500 Hz Timer The timer port is accessed by the OUT2 instruction with the operand [CN = 8H] and the IN2 instruction with the operand [CN = FH] on IO map page 2. 92 2002-05-14 TC9325F 2. Timer Port Timing The 2-Hz timer F/F is set by the 2-Hz (500 ms) signal, and reset by setting the RESET port 2-Hz F/F to 1. This bit can normally be used for the clock count. The 2-Hz timer F/F is only reset by the RESET port 2-Hz F/F. Therefore, if the F/F is not reset within 500 ms, the next count is missed and the correct time is not obtained. 2-Hz F/F output 2-Hz F/F reset execution t < 500 ms 2-Hz clock t 500 ms The 10-Hz, 100-Hz, and 500-Hz timers are output to the 10-Hz, 100-Hz, and 500-Hz bits with a cycle of 100 ms, 10ms, and 2 ms, respectively, and a pulse duty of 50%. Whenever the RESET port timer bit is set to 1, counters below 1 kHz are reset. 500 Hz 1 ms 2 ms 100 Hz 5 ms 10 ms 10 Hz 50 ms 100 ms 93 2002-05-14 TC9325F ○ Output Ports (Also Function as LCD Driver Pins) The output port includes 30 CMOS output ports, which also function as the LCD driver. The LCD OFF bit is used to switch the port to an output port. Setting the LCD OFF bit to 1 sets the port to an output port. The data output to the output port can be accessed by the OUT2 instruction with the operand [CN = CH]. These data can be divided/indirectly specified and set using the data selection port (φL2B). First set the data for the segment data port you wish to set, then access the corresponding data port. The data selection port is incremented by 1 every time a general-purpose output data port (φL2C) is accessed. Accordingly, after setting the data selection port, the data can be repeatedly set. In OT1 to OT20, output data can be incremented by 1 in one instruction by using the OT count UP bit. Therefore, OT1 to OT20 can be used for the address signal output when using external memory. Note: The data selection port is automatically incremented by 1 whenever φL2C, φL2D, φL2E, φL2F, φL3B, or φK3B on the I/O map are accessed. Note: Setting the OT count UP bit to 0 sets no count up. Note: See the LCD driver section. φL2B Y1 φL2C Y2 SEL1 SEL2 Y4 SEL4 Y8 Y1 SEL8 0 Data selection Y2 Y4 Y8 φL/K3B Y1 Output Y2 port data Y4 Setting the LCD OFF bit to 1 sets the segment output data to output port data. Y8 アドレス OT1Y1 DAL OT2Y2 OT3Y41OT4Y8 φL2C Y1 Y2 OT6 アドレス OT7Y41OT8Y8 1 OT5 DAL OT11Y41OT12Y8 DALY2 アドレス 2 OT9Y1 OT10 φL/K3B Y1出力ポートデータ OT14Y2 OT15Y4 OT16Y8 3 OT13 DALY2 アドレス OT19Y41OT20Y8 4 OT17Y1 OT18 5 OT27 1OT28 DAL アドレス 6 OT25 OT26 φL3A Y1 O21Y1 OT22 OT23Y41OT24Y8 DALY2 アドレス 7 OT29 OT30 Y2 Y4 OT count up * * Y8 OT1 to OT20 are counted up (incremented by 1) whenever this bit is set to 1. The OT1 bit is the lowest bit and OT20 the highest. The countup starts from OT1. 94 2002-05-14 TC9325F ○ MUTE Output This is a 1-bit CMOS output port for muting control. 1. MUTE Port φL/K19P1 Y1 Y2 Y4 Y8 MUTE I/O POL HOLD Control by change in HOLD input state 0: Even though HOLD input state changes, no change in MUTE output 1: MUTE bit set to 1 by change in HOLD input state MUTE output polarity setting 0: Positive logic: Directly outputs the MUTE bit. 1: Negative logic: Inverts the MUTE bit and outputs. Control by change in I/O port 8 input state 0: Even though I/O port 8 input state changes, no change in MUTE output 1: MUTE bit set to 1 by change in I/O port 8 input state MUTE output setting 0: MUTE output L level at positive logic and H level at negative logic 1: MUTE output H level at positive logic and L level at negative logic The MUTE port is accessed by the OUT1/IN2 instruction with the operand [CN = 9H]. The MUTE output is used for muting control. At such times as switching bands and turning the radio off using the I/O port 8 and HOLD input, the MUTE bit can be set to 1 to prevent linear circuit switching noise. The I/O bit and HOLD bit control the MUTE bit. The POL bit sets the MUTE output logic. Set depending on your specifications. 2. MUTE Output Circuit Structure MUTE bit 65 MUTE S POL bit HOLD bit I/O bit I/O port 8 input change signal HOLD input change signal Reset signal 95 2002-05-14 TC9325F ○ Test Ports These are internal ports for testing the device’s functions. The ports are accessed by the OUT1 instruction with the operand [CN = EH, FH]. The ports are normally set to 0. φL1F φL1E Y1 Y2 Y4 Y8 #0 #1 #2 #3 Y1 Y2 Y4 #4 Test port ○ Y8 Test port Test Page This port sets pages 1 to 3 of the I/O map. The port is accessed by the OUT1/IN1 instruction with the operand [CN = FH]. φL/K1F Y1 Y2 Page 2 Page 3 Y4 Y8 */0 I/O map page setting ○ Page 2 Page 3 Page 0 0 1 1 0 2 * 1 3 Using as Emulator Chip When an H level voltage is supplied to the TEST pin (Test mode), the device functions as an emulator chip. Three test modes are supported. A software development tool can be configured using two devices. Connecting this software development tool and a tuner IC enables you to check radio operations while developing software. For the development tool specifications, refer to the TC9325F software development tool specification sheet. 96 2002-05-14 TC9325F Maximum Ratings (Ta = 25°C) Characteristics Symbol Rating Unit Power supply voltage 1 VDD1 −0.3~4.0 V Power supply voltage 2 VDD2 −0.3~6.0 V VIN −0.3~VDD + 0.3 V Input voltage Power dissipation PD 400 mW Operating temperature Topr −40~85 °C Storage temperature Tstg −65~150 °C Electrical Characteristics (unless otherwise specified, Ta = −40~85°C, VDD = 3.0~3.6 V) Characteristics Symbol Test Circuit Operating power supply voltage range VDD Memory hold voltage range VHD Min Typ. Max Unit When CPU operating 3.0 3.3 3.6 V Crystal oscillation stopped (CKSTP instruction executed) 2.0 ~ 3.6 V IDD1 When PLL operating (VHF mode) and at FMin = 230 MHz input, Ta = 25°C 3.5 7.0 IDD2 When CPU only operating (4.5-MHz clock operating, 75-kHz oscillation stopped, PLL off, display lit), Ta = 25°C 1.0 2.0 IDD3 When CPU only operating (75-kHz clock operating, 4.5-MHz oscillation stopped, PLL off, display lit), Ta = 25°C 0.25 0.50 IDD4 In Hard Wait mode (4.5-MHz crystal only operating), Ta = 25°C 150 IDD5 In Hard Wait mode (75-kHz crystal only operating), Ta = 25°C 100 IDD6 When soft wait executed (PLL off, CPU operating intermittently on 4.5-MHz clock, display lit), Ta = 25°C 300 IDD7 When soft wait executed (PLL off, CPU operating intermittently on 75-kHz clock, display lit), Ta = 25°C 250 IHD Crystal oscillator stopped (CKSTP instruction executed) 0.1 10 µA fXT1 Crystal oscillator 1 (XIN1, XOUT1) 4.5 MHz fXT2 Crystal oscillator 2 (XIN2, XOUT2) 75 kHz Crystal oscillation startup time tst Crystal oscillator fXT2 = 75 kHz (XIN2, XOUT2) 1.0 s Low voltage detection voltage VSTOP (VCPU), STOP F/F bit detected 2.15 2.40 2.70 V Operating power supply current Memory hold current Crystal oscillator frequency Test Condition 97 mA µA 2002-05-14 TC9325F Programmable Counter and IF Counter Operating Frequency Ranges Characteristics Symbol Test Circuit fVHF fFM1 Min Typ. Max VIN = 0.2 Vp-p 50 ~ 230 VIN = 0.1 Vp-p 50 ~ 140 fFM2 VIN = 0.1 Vp-p 10 ~ 60 AMin (HF mode) fHF VIN = 0.1 Vp-p 1.0 ~ 30 AMin (LF mode) fLF VIN = 0.1 Vp-p 0.5 ~ 20 IFIN1, IFIN2 fIF VIN = 0.1 Vp-p 0.3 ~ 20 Min Typ. Max FMin (VHF mode) FMin (FM mode) Test Condition Unit MHz Programmable Counter and IF Counter Input Oscillation Ranges Symbol Test Circuit FMin (VHF mode) VVHF fVHF 0.2 ~ 1.0 FMin (FM mode) VFM fFM1/fFM2 0.1 ~ 1.0 AMin (HF mode) VHF fHF 0.1 ~ 1.0 AMin (LF mode) VLF fLF 0.1 ~ 1.0 IFIN1, IFIN2 VIF fIF 0.1 ~ 1.0 Min Typ. Max Characteristics Test Condition Unit Vp-p LCD Common Outputs/Segment Outputs (COM~COM4, S1~S22) Symbol Test Circuit GND level VBS1 VDD = 3.3 V, no load 0.00 0.15 1/3 VDD level VBS2 VDD = 3.3 V, no load 0.95 1.10 1.25 1/2 VDD level VBS3 VDD = 3.3 V, no load 1.50 1.65 1.80 2/3 VDD level VBS4 VDD = 3.3 V, no load 2.05 2.20 2.35 VDD level VBS5 VDD = 3.3 V, no load 3.15 3.30 Min Typ. Max Characteristics Bias output voltage Test Condition Unit V Output Ports and I/O Ports (OT1~OT30, P1-0~P10-3) Symbol Test Circuit IOH1 VDD = 3.3 V, VOH = VDD − 0.3 V −0.30 −0.80 IOL1 VDD = 3.3 V, VOL = 0.3 V, except for P5-1 to P5-3 0.30 0.80 IOL2 VDD2 = 3.3 V, VOL = 0.3 V, P5-1~P5-3 1.50 4.00 ILI VIH = VDD, VIL = 0 V (P1-0~P10-3) ±1.0 High level VIH (P1-0~P10-3) VDD × 0.8 ~ VDD Low level VIL (P1-0~P10-3) 0 ~ VDD × 0.2 RIN1 Ta = 25°C, When P8-0 to P8-3 pulled up/down 30 60 120 Characteristics High level Output current Low level Input leakage current Test Condition Input voltage Input pulled-up/down resistor 98 Unit mA µA V kΩ 2002-05-14 TC9325F MUTE, DO1, DO2 Output Symbol Test Circuit High level IOH1 Low level IOL1 ITL Characteristics Output current Output off leakage current Test Condition Min Typ. Max Unit VDD = 3.3 V, VOH = VDD − 0.3 V −0.30 −0.80 VDD = 3.3 V, VOL = 0.3 V 0.30 0.80 VDD = 3.3 V, VTLH = 3.3 V, VTLL = 0 V (DO1, DO2) ±100 nA Min Typ. Max Unit ±1.0 µA mA HOLD , INTR1/2, IN1/2 Input Ports, RESET Input Symbol Test Circuit ILI High level VIH VDD × 0.8 ~ VDD Low level VIL 0 ~ VDD × 0.2 Symbol Test Circuit Test Condition Min Typ. Max Unit VAD 0 ~ VDD V Resolution VRES 8 bit Linear error ±0.5 ±1.0 Conversion total error ±1.0 ±2.0 Analog input leakage ILI VIH = VDD, VIL = 0 V, (ADin1~ADin8) ±1.0 µA IREF Ta = 25°C, VDD = 3.3 V, DCREF = 3.3 V (DCREF) 0.35 0.70 mA Symbol Test Circuit Min Typ. Max Unit XIN1 amp feedback resistance RfXT1 VDD = 3.3 V, (XIN1−XOUT1) 1.0 XIN2 amp feedback resistance RfXT2 VDD = 3.3 V, (XIN2−XOUT2) 10 XOUT1 output resistance ROUT1 Ta = 25°C, (XOUT1) 2.0 4.0 8.0 XOUT2 output resistance ROUT2 Ta = 25°C, (XOUT2) 2.5 5.0 10.0 Symbol Test Circuit Min Typ. Max Input pulled-down resistance RIN2 Ta = 25°C, (TEST) 30 60 120 Input amp feedback resistance RfIN Ta = 25°C, VDD = 3.3 V (FMin, AMin, IFin1, IFin2) 0.5 1.0 2.0 Characteristics Input leakage current Output current Test Condition VIH = VDD, VIL = 0 V V AD Converter (ADIN1~ADIN8, DCREF) Characteristics Analog input voltage range Reference voltage input current ADin1~ADin8 LSB Crystal Oscillators Characteristics Test Condition MΩ kΩ Others Characteristics Test Condition 99 Unit kΩ 2002-05-14 TC9325F Package Dimensions Weight: 1.6 g (typ.) 100 2002-05-14 TC9325F RESTRICTIONS ON PRODUCT USE 000707EBA • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. • The products described in this document are subject to the foreign exchange and foreign trade laws. • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. • The information contained herein is subject to change without notice. 101 2002-05-14