100 MHz to 1000 MHz Integrated Broadband Receiver ADRF6850 FEATURES GENERAL DESCRIPTION IQ quadrature demodulator Integrated fractional-N PLL and VCO Gain control range: 60 dB Input frequency range: 100 MHz to 1000 MHz Input P1dB: +12 dBm at 0 dB gain Input IP3: +22.5 dBm at 0 dB gain Noise figure: 11 dB at >39 dB gain, 49 dB at 0 dB gain Baseband 1 dB bandwidth: 250 MHz in wideband mode, 50 MHz in narrow-band mode SPI/I2C serial interface Power supply: +3.3 V/350 mA The ADRF6850 is a highly integrated broadband quadrature demodulator, frequency synthesizer, and variable gain amplifier (VGA). The device covers an operating frequency range from 100 MHz to 1000 MHz for use in both narrow-band and wideband communications applications, performing quadrature demodulation from IF directly to baseband frequencies. The ADRF6850 demodulator includes a high modulus fractional-N frequency synthesizer with integrated VCO, providing better than 1 Hz frequency resolution, and a 60 dB gain control range provided by a front-end VGA. Control of all the on-chip registers is through a user-selected SPI interface or I2C interface. The device operates from a single power supply ranging from 3.15 V to 3.45 V. APPLICATIONS Broadband communications Cellular communications Satellite communications FUNCTIONAL BLOCK DIAGRAM VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 LOMON LOMON IBB IBB CCOMP1 CCOMP2 CCOMP3 60dB GAIN CONTROL RANGE RFI RFI 0°/90° DRIVER RFDIV VCO CORE VTUNE RFCM VGAIN VOCM SEQUENCED GAIN INTERFACE QBB QBB RSET REFERENCE REFIN ×2 DOUBLER 5-BIT DIVIDER ÷2 + PHASE FREQUENCY DETECTOR – CHARGE PUMP CURRENT SETTING N-COUNTER SDI/SDA CLK/SCL SDO CS SPI/ I2C INTERFACE THIRD-ORDER FRACTIONAL INTERPOLATOR FRACTIONAL REGISTER RFCP4 RFCP3 RFCP2 RFCP1 MODULUS 225 CP LF3 LF2 LDET TESTLO TESTLO INTEGER REGISTER GND MUXOUT 09316-001 ADRF6850 Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. www.analog.com Tel: 781.329.4700 Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved. ADRF6850 TABLE OF CONTENTS Features .............................................................................................. 1 I2C Interface ................................................................................ 20 Applications ....................................................................................... 1 SPI Interface ................................................................................ 22 General Description ......................................................................... 1 Program Modes .......................................................................... 24 Functional Block Diagram .............................................................. 1 Register Map ................................................................................... 26 Revision History ............................................................................... 2 Register Map Summary ............................................................. 26 Specifications..................................................................................... 3 Register Bit Descriptions ........................................................... 27 Timing Characteristics ................................................................ 5 Suggested Power-Up Sequence ..................................................... 30 Absolute Maximum Ratings ............................................................ 7 Initial Register Write Sequence ................................................ 30 ESD Caution .................................................................................. 7 Evaluation Board ............................................................................ 31 Pin Configuration and Function Descriptions ............................. 8 General Description ................................................................... 31 Typical Performance Characteristics ........................................... 10 Hardware Description ............................................................... 31 Theory of Operation ...................................................................... 18 PCB Schematic............................................................................ 33 Overview...................................................................................... 18 PCB Artwork............................................................................... 34 PLL Synthesizer and VCO......................................................... 18 Bill of Materials ........................................................................... 35 Quadrature Demodulator.......................................................... 20 Outline Dimensions ....................................................................... 36 Variable Gain Amplifier (VGA) ............................................... 20 Ordering Guide .......................................................................... 36 REVISION HISTORY 10/10—Revision 0: Initial Version Rev. 0 | Page 2 of 36 ADRF6850 SPECIFICATIONS VCC = 3.3 V; ambient temperature (TA) = 25°C; ZS = 50 Ω; ZL = 100 Ω differential; PLL loop bandwidth = 50 kHz; REFIN = 13.5 MHz; PFD = 27 MHz; baseband frequency = 20 MHz, narrow-band mode, unless otherwise noted. Table 1. Parameter RF INPUT Operating Frequency Range Input P1dB Input IP3 Input IP2 Noise Figure (NF) Maximum Gain Minimum Gain Gain Conformance Error 1 Gain Slope VGAIN Input Impedance Return Loss REFERENCE CHARACTERISTICS Input Frequency REFIN Input Sensitivity REFIN Input Capacitance REFIN Input Current CHARGE PUMP ICP Sink/Source High Value Low Value Absolute Accuracy VCO Gain SYNTHESIZER SPECIFICATIONS Frequency Increment Phase Frequency Detector Spurs Phase Noise Integrated Phase Noise Test Conditions/Comments RFI, RFI, VGAIN pins Min Typ Max Unit 1000 +12 −48 +22.5 −38 +40 −20 49 MHz dBm dBm dBm dBm dBm dBm dB 11 60 0 0.5 25 20 15 dB dB dB dB mV/dB kΩ dB 100 0 dB gain 60 dB gain 0 dB gain 60 dB gain 0 dB gain, single-ended input 60 dB gain, single-ended input 0 dB gain <39 dB gain NF rises 1:1 as gain in dB falls >39 dB gain ZS = 50 Ω single-ended, ZL = 100 Ω differential ZS = 50 Ω single-ended, ZL = 100 Ω differential VGAIN from 200 mV to 1.3 V Relative to ZS = 50 Ω, 100 MHz to 1 GHz REFIN pin With R divide-by-2 divider enabled With R divide-by-2 divider disabled 10 10 0.4 CP and RSET pins Programmable With RSET = 4.7 kΩ With RSET = 4.7 kΩ KVCO Loop bandwidth = 50 kHz 300 165 VCC 10 ±100 5 312.5 2.5 mA µA % 15 MHz/V 1 10 Integer boundary < loop bandwidth >10 MHz offset from carrier LO frequency = 1000 MHz @ 10 Hz offset @ 100 Hz offset @ 1 kHz offset @ 10 kHz offset @ 100 kHz offset @ 1 MHz offset >10 MHz offset 1 kHz to 8 MHz integration bandwidth Rev. 0 | Page 3 of 36 MHz MHz V p-p pF µA 30 Hz MHz −55 −70 dBc dBc −75 −80 −90 −98 −110 −136 −149 0.26 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz °rms ADRF6850 Parameter Frequency Settling Maximum Frequency Step for No Autocalibration BASEBAND OUTPUTS Maximum Swing Common-Mode Range Output Impedance Output DC Offset 1 dB Bandwidth Wideband Mode Narrow-Band Mode IQ Balance Amplitude Wideband Mode Narrow-Band Mode Phase Wideband Mode Narrow-Band Mode IQ Output Impedance Mismatch Group Delay Variation Wideband Mode Narrow-Band Mode LO to IQ Leakage RF to IQ Leakage MONITOR OUTPUT Nominal Output Power LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINH/IINL Input Capacitance, CIN LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL POWER SUPPLIES Test Conditions/Comments Any step size, maximum frequency error = 1 kHz Frequency step with no autocalibration routine; Register CR24, Bit 0 = 1 IBB, IBB, QBB, QBB, VOCM pins Driving ZL = 100 Ω differential Typ 260 Max 100 2.5 Unit μs kHz 28 ±20 V p-p V Ω mV 250 50 MHz MHz Baseband frequency ≤ 250 MHz Baseband frequency ≤ 33.2 MHz ±0.1 ±0.1 dB dB Baseband frequency ≤ 250 MHz Baseband frequency ≤ 33.2 MHz Baseband frequency = 10 MHz ±0.5 ±0.25 ±0.3 Degrees Degrees % Baseband frequency ≤ 210 MHz Baseband frequency ≤ 250 MHz Baseband frequency ≤ 33.2 MHz 1× LO 2× LO 4× LO Relative to IQ output level LOMON and LOMON pins 0.25 0.35 0.2 −40 −60 −60 −40 ns ns ns dBm dBm dBm dBc −24 dBm 1.2 Differential RFI terminated in ZS = 50 Ω SDI/SDA, CLK/SCL, CS pins CS CS SDI/SDA, CLK/SCL SDI/SDA, CLK/SCL CS, SDI/SDA, CLK/SCL CS, SDI/SDA, CLK/SCL SDO, LDET pins; IOH = 500 μA SDO, LDET pins; IOL = 500 μA SDA (SDI/SDA) pins; IOL = 3 mA VCC1, VCC2, VCC3, VCC4, VCC5, VCC6, VCC7, VCC8, and VCC9 pins Voltage Range Supply Current Operating Temperature 1 Min 1.4 0.4 0.4 V V V 3.45 440 +85 V mA °C 2.1 2.8 −40 Rev. 0 | Page 4 of 36 1.1 ±1 10 V V V V µA pF 0.6 3.15 Difference between channel gain and linear fit to channel gain. 1.6 3.3 350 ADRF6850 TIMING CHARACTERISTICS I2C Interface Timing Table 2. Parameter 1 SCL Clock Frequency SCL Pulse Width High SCL Pulse Width Low Start Condition Hold Time Start Condition Setup Time Data Setup Time Data Hold Time Stop Condition Setup Time Data Valid Time Data Valid Acknowledge Time Bus Free Time Limit 400 600 1300 600 600 100 300 600 900 900 1300 Unit kHz max ns min ns min ns min ns min ns min ns min ns min ns max ns max ns min See Figure 2. tVD;DAT AND tVD;ACK (ACK SIGNAL ONLY) tSU;DAT tBUF SDA tSU;STA tHD;STA tSU;STO tLOW SCL S START CONDITION 1/fSCL tHD;DAT S tHIGH P STOP CONDITION Figure 2. I2C Port Timing Diagram Rev. 0 | Page 5 of 36 S 09316-002 1 Symbol fSCL tHIGH tLOW tHD;STA tSU;STA tSU;DAT tHD;DAT tSU;STO tVD;DAT tVD;ACK tBUF ADRF6850 SPI Interface Timing Table 3. Parameter 1 CLK Frequency CLK Pulse Width High CLK Pulse Width Low Start Condition Hold Time Data Setup Time Data Hold Time Stop Condition Setup Time SDO Access Time CS to SDO High Impedance Limit 20 15 15 5 10 5 5 15 25 Unit MHz max ns min ns min ns min ns min ns min ns min ns min ns max See Figure 3. t3 CS t1 CLK t6 t2 SDI t4 t5 SDO t7 Figure 3. SPI Port Timing Diagram Rev. 0 | Page 6 of 36 t8 09316-003 1 Symbol fCLK t1 t2 t3 t4 t5 t6 t7 t8 ADRF6850 ABSOLUTE MAXIMUM RATINGS Table 4. Absolute Maximum Ratings Parameter Supply Voltage Pins (VCC1, VCC2, VCC3, VCC4, VCC5, VCC6, VCC7, VCC8, VCC9) Analog Input/Output Digital Input/Output RFI, RFI, RFCM θJA (Exposed Paddle Soldered Down) Maximum Junction Temperature Storage Temperature Range Rating −0.3 V to +4.0 V −0.3 V to +4.0 V −0.3 V to +4.0 V 0 V to 3.0 V 26°C/W 125°C −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. 0 | Page 7 of 36 ADRF6850 56 55 54 53 52 51 50 49 48 47 46 45 44 43 GND RFI GND RFCM GND RFI GND VCC9 GND GND GND GND GND VGAIN PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR ADRF6850 TOP VIEW (Not to Scale) 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VCC8 GND LDET MUXOUT VTUNE GND VCC7 CCOMP3 CCOMP2 CCOMP1 GND VCC6 CLK/SCL SDI/SDA NOTES 1. CONNECT EXPOSED PAD TO GROUND PLANE VIA A LOW IMPEDANCE PATH. 09316-004 VCC4 VCC5 REFIN REFIN GND GND GND TESTLO TESTLO GND LOMON LOMON CS SDO 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VCC1 1 IBB 2 IBB 3 QBB 4 QBB 5 GND 6 VOCM 7 GND 8 RSET 9 LF3 10 CP 11 LF2 12 VCC2 13 VCC3 14 Figure 4. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1, 13, 14, 15, 16, 31, 36, 42, 49 6, 8, 19, 20, 21, 24, 32, 37, 41, 44, 45, 46, 47, 48, 50, 52, 54, 56 2, 3, 4, 5 Mnemonic VCC1 to VCC9 GND 7 IBB, IBB, QBB, QBB VOCM 33 34 35 38 CCOMP1 CCOMP2 CCOMP3 VTUNE 9 RSET 11 CP 27 CS 29 SDI/SDA 30 CLK/SCL 28 SDO 17 18 REFIN REFIN Description Positive Power Supplies. Apply a 3.3 V power supply to all VCCx pins. Decouple each pin with a power supply decoupling capacitor. Analog Ground. Connect to a low impedance ground plane. Differential In-Phase and Quadrature Baseband Outputs. These low impedance outputs can drive 2.5 V p-p into 100 Ω differential loads. Baseband Common-Mode Voltage Input. When ac coupling the baseband output pins, ground VOCM. There is an option to apply an external voltage, which may be relevant when dc coupling the baseband output pins. Note that Register CR29, Bit 6 must be set accordingly. Internal Compensation Node. This pin must be decoupled to ground with a 100 nF capacitor. Internal Compensation Node. This pin must be decoupled to ground with a 100 nF capacitor. Internal Compensation Node. This pin must be decoupled to ground with a 100 nF capacitor. Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CP output voltage. Charge Pump Current Set. Connecting a resistor between this pin and ground sets the maximum charge pump output current. The relationship between ICP and RSET is 23.5 ICPmax = RSET where RSET = 4.7 kΩ and ICP max = 5 mA. Charge Pump Output. When enabled, this provides ±ICP to the external loop filter, which in turn, drives the internal VCO. Chip Select. CMOS input. When CS is high, the data stored in the shift registers is loaded into one of the 31 registers. In I2C mode, when CS is high, the slave address of the device is 0x78, and when CS is low, the slave address is 0x58. Serial Data Input for SPI Port, Serial Data Input/Output for I2C Port. In SPI mode. This input is a high impedance CMOS data input, and data is loaded in an 8-bit word. In I2C mode, this pin is a bidirectional port. Serial Clock Input for SPI/I2C Port. This serial clock is used to clock in the serial data to the registers. This input is a high impedance CMOS input. Serial Data Output for SPI Port. Register states can be read back on the SDO data output line in an 8-bit word. Reference Input. AC couple this high impedance CMOS input. Reference Input Bar. Ground this pin. Rev. 0 | Page 8 of 36 ADRF6850 Pin No. 51, 55 Mnemonic RFI, RFI 53 RFCM 25, 26 LOMON, LOMON 10, 12 40 LF3/LF2 LDET 39 22, 23 43 MUXOUT TESTLO, TESTLO VGAIN EP Description RF Inputs. 50 Ω internally biased RF inputs. For single-ended operation, RFI must be ac-coupled to the source, and RFI must be ac-coupled to the ground plane. RF Input Common Mode. Connect to RFI when driving the input in single-ended mode. When driving the input differentially using a balun, connect this pin to the common terminal of the output coil of the balun. Decouple RFCM to the ground plane. Differential Monitor Outputs. These pins provide a replica of the internal local oscillator frequency (1× LO) at four different power levels: −6 dBm, −12 dBm, −18 dBm, and −24 dBm, approximately. These open-collector outputs must be terminated with external resistors to VCCx. These outputs can be disabled through serial port programming and should be connected to VCCx if not used. Extra Loop Filter Pins for Fastlock. Use these pins to reduce lock time. Lock Detect. This pin provides an active high output when the PLL frequency is locked. The lock detect timing is controlled by Register CR14 (Bit 7) and Register CR23 (Bit 3). Muxout. This output is a test output for diagnostic use only. Allow this pin to remain open circuit. Differential Test Inputs. For internal use only. These pins should be grounded. VGA Gain Input. Drive this pin by a voltage in the range from 0 V to 1.5 V. This voltage controls the gain of the VGA. A 0 V input sets the VGA gain to 0 dB, whereas a 1.5 V input sets the VGA gain to +60 dB if the VGA Gain Mode Polarity Bit CR30, Bit 2, is set to 0. If the VGA gain mode polarity bit is set to 1, a 0 V input sets the VGA gain to +60 dB, whereas a 1.5 V input sets the VGA gain to 0 dB. Exposed Paddle. Connect the exposed pad to the ground plane via a low impedance path. Rev. 0 | Page 9 of 36 ADRF6850 TYPICAL PERFORMANCE CHARACTERISTICS A nominal condition is defined as 25°C, 3.30 V, and worst-case frequency. A worst-case condition is defined as having the worst-case temperature, supply voltage, and frequency. 20 RF RF RF RF RF 10 NOMINAL WORST-CASE 45 40 OCCURRENCE (%) IP1dB (dBm) 0 50 = 100MHz = 300MHz = 550MHz = 800MHz = 1000MHz –10 –20 –30 35 30 25 20 15 –40 09316-011 –60 0 10 20 30 40 50 09316-008 10 –50 5 0 60 8.6 9.0 CHANNE L GAIN (dB) Figure 8. Input 1dB Compression Point (IP1dB) Distribution with Channel Gain = 0 dB at Nominal and Worst-Case Conditions 20 NOMINAL WORST-CASE 55 50 45 OCCURRENCE (%) IP1dB (dBm) 60 3.30V, 25°C 3.15V, –40°C 3.45V, –40°C 3.15V, 85°C 3.45V, 85°C 0 9.8 10.2 10.6 11.0 11.4 11.8 12.2 12.6 13.0 13.4 INPUT P1dB AT CHANNEL GAIN OF 0dB (dBm) Figure 5. Input 1dB Compression Point (IP1dB) vs. Channel Gain, and RF Input Frequency, Nominal Conditions, Narrow-Band Mode 10 9.4 –10 –20 –30 –40 40 35 30 25 20 15 09316-012 –46.8 –47.2 CHANNE L GAIN (dB) –47.6 0 60 –48.0 50 –48.4 40 –48.8 30 –49.2 20 –49.6 10 –50.0 0 5 –50.4 –60 09316-009 10 –50 INPUT P1dB AT CHANNEL GAIN OF 60dB (dBm) 20 3.30V, 3.15V, 3.45V, 3.15V, 3.45V, 20 +25°C –40°C –40°C +85°C +85°C 0 0 –10 –10 –20 –30 –30 –40 –50 –50 10 20 30 40 CHANNEL GAIN (dB) 50 60 –60 –10 09316-034 0 Figure 7. Input 1dB Compression Point (IP1dB) vs. Channel Gain, Supply, and Temperature, RF Input Frequency = 1000 MHz, Narrow-Band Mode = 100MHz = 300MHz = 550MHz = 800MHz = 1000MHz –20 –40 –60 RF RF RF RF RF 10 IP1dB (dBm) IP1dB (dB) 10 Figure 9. Input 1dB Compression Point (IP1dB) Distribution with Channel Gain = 60 dB at Nominal and Worst-Case Conditions 0 10 20 30 40 CHANNEL GAIN (dB) 50 60 70 09316-033 Figure 6. Input 1dB Compression Point (IP1dB) vs. Channel Gain, Supply, and Temperature, RF Input Frequency = 100 MHz, Narrow-Band Mode Figure 10. Input 1dB Compression Point (IP1dB) vs. Channel Gain, and RF Input Frequency, VOCM = 1.2 V, Nominal Conditions, Narrow-Band Mode Rev. 0 | Page 10 of 36 ADRF6850 20 RF RF RF RF RF 10 30 = 100MHz = 300MHz = 550MHz = 800MHz = 1000MHz –10 –20 –30 0 –10 –20 –40 –30 –50 –40 –60 –10 0 10 20 30 40 50 60 70 CHANNEL GAIN (dB) = 100MHz = 300MHz = 550MHz = 800MHz = 1000MHz 09316-016 INPUT IP3 (dBm) 10 –50 09316-057 IP1dB (dBm) 0 0 10 20 30 40 50 60 70 CHANNE L GAIN (dB) Figure 11. Input 1dB Compression Point (IP1dB) vs. Channel Gain, and RF Input Frequency, VOCM = 1.6 V, Nominal Conditions, Narrow-Band Mode Figure 14. Input IP3 vs. Channel Gain, and RF Input Frequency, Worst-Case Conditions 70 IQ IQ IQ IQ IQ 10 0 = 20MHz = 50MHz = 100MHz = 200MHz = 250MHz NOMINAL WORST-CASE 60 50 OCCURRENCE (%) 20 IP1dB (dBm) RF RF RF RF RF 20 –10 –20 –30 40 30 20 –40 09316-010 –60 0 10 20 30 40 50 0 19.6 20.0 20.4 20.8 21.2 21.6 22.0 22.4 22.8 23.2 23.6 24.0 IIP3 AT CHANNEL GAIN = 0dB (dBm) 60 09316-035 10 –50 CHANNE L GAIN (dB) Figure 12. Input 1dB Compression Point (IP1dB) vs. Channel Gain, and IQ Output Frequency, LO = 1000 MHz, Nominal Conditions, Wideband Mode Figure 15. Input IP3 Distribution with Channel Gain = 0 dB at Nominal and Worst-Case Conditions 35 30 20 NOMINAL WORST-CASE 30 25 0 –10 –20 20 15 10 –30 –50 0 10 20 30 40 50 60 0 –40.4 –40.0 –39.6 –39.2 –38.8 –38.4 –38.0 –37.6 –37.2 –36.8 –36.4 –36.0 70 IIP3 AT CHANNEL GAIN = 60dB (dBm) CHANNE L GAIN (dB) Figure 13. Input IP3 vs. Channel Gain, and RF Input Frequency, Nominal Conditions 09316-036 5 –40 09316-015 INPUT IP3 (dBm) 10 = 100MHz = 300MHz = 550MHz = 800MHz = 1000MHz OCCURRENCE (%) RF RF RF RF RF Figure 16. Input IP3 Distribution with Channel Gain = 60 dB at Nominal and Worst-Case Conditions Rev. 0 | Page 11 of 36 ADRF6850 30 70 20 60 50 10 INPUT IP2 (dBm) INPUT IP3 (dBm) 40 0 –10 –20 30 20 10 0 –30 0 10 20 30 40 –10 DIRECT IIP2 DOWN-CONVERTED IIP2 –20 50 60 70 CHANNEL GAIN (dB) –30 –10 0 10 20 09316-014 –50 –10 FREQUENCIES = 16MHz AND 19MHz FREQUENCIES = 46MHz AND 49MHz FREQUENCIES = 96MHz AND 99MHz FREQUENCIES = 196MHz AND 199MHz FREQUENCIES = 246MHz AND 249MHz 09316-037 –40 IQ IQ IQ IQ IQ 30 40 50 30 60 RF RF RF RF RF 20 50 NOISE FIGURE (dB) 0 –10 –20 –50 –10 FREQUENCIES = 16MHz AND 19MHz FREQUENCIES = 46MHz AND 49MHz FREQUENCIES = 96MHz AND 99MHz FREQUENCIES = 196MHz AND 199MHz FREQUENCIES = 246MHz AND 249MHz 0 10 20 30 40 30 20 10 09316-023 IQ IQ IQ IQ IQ 0 50 60 70 CHANNEL GAIN (dB) 0 10 20 30 40 50 60 70 CHANNEL GAIN (dB) Figure 21. Noise Figure vs. Channel Gain, and RF Input Frequency, Narrow-Band Mode, Nominal Conditions Figure 18. Input IP3 vs. Channel Gain, and IQ Output Frequency, Wideband Mode, Worst-Case Conditions 60 70 RF RF RF RF RF 60 50 NOISE FIGURE (dB) 50 INPUT IP2 (dBm) = 100MHz = 300MHz = 550MHz = 800MHz = 1000MHz 40 09316-038 INPUT IP3 (dBm) 10 –40 70 Figure 20. Input IP2 vs. Channel Gain, Wideband Mode, Worst-Case Conditions Figure 17. Input IP3 vs. Channel Gain, and IQ Output Frequency, Wideband Mode, Nominal Conditions –30 60 CHANNE L GAIN (dB) 40 30 20 10 = 100MHz = 300MHz = 550MHz = 800MHz = 1000MHz 40 30 20 0 0 10 20 09316-013 –20 –10 DIRECT IIP2 DOWN-CONVERTED IIP2 30 40 50 60 09316-024 10 –10 0 0 70 10 20 30 40 50 60 70 CHANNEL GAIN (dB) CHANNE L GAIN (dB) Figure 19. Input IP2 vs. Channel Gain, Wideband Mode, Nominal Conditions Rev. 0 | Page 12 of 36 Figure 22. Noise Figure vs. Channel Gain, and RF Input Frequency, Narrow-Band Mode, Worst-Case Conditions ADRF6850 70 60 RF RF RF RF RF 60 50 CHANNEL GAIN (dB) NOISE FIGURE (dB) 50 40 30 20 = 100MHz = 300MHz = 550MHz = 800MHz = 1000MHz 40 30 20 10 10 0 10 20 30 40 50 60 –10 09316-045 0 70 CHANNEL GAIN (dB) 09316-007 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 VGAIN (V) Figure 23. Noise Figure Distribution vs. Channel Gain, Narrow-Band Mode, Nominal Conditions Figure 26. Channel Gain vs. VGAIN and RF Input Frequency, Nominal Conditions 60 60 NOMINAL WORST-CASE 50 40 OCCURRENCE (%) 30 20 10 40 30 20 62.2 62.0 61.8 61.6 61.4 0 61.2 70 61.0 60 60.8 50 60.6 40 60.4 30 CHANNEL GAIN (dB) 60.2 20 60.0 10 59.6 0 09316-046 0 09316-006 10 59.8 NOISE FIGURE (dB) 50 CHANNEL GAIN RANGE (dB) Figure 24. Noise Figure Distribution vs. Channel Gain, Narrow-Band Mode, Worst-Case Conditions RF RF RF RF RF 0.5 CHANNEL GAIN (dB) NOISE FIGURE (dB) 50 1.0 = 100MHz = 300MHz = 550MHz = 800MHz = 1000MHz 40 30 20 10 0 10 20 30 40 50 60 3.15V, 85°C 3.45V, 85°C 0 –0.5 –1.0 –1.5 09316-025 0 3.30V, 25°C 3.15V, –40°C 3.45V, –40°C –2.0 100 70 CHANNEL GAIN (dB) 09316-021 60 Figure 27. Channel Gain Range Distribution at Nominal and Worst-Case Conditions 200 300 400 500 600 700 800 900 RF INPUT FREQUENCY (MHz) Figure 25. Noise Figure vs. Channel Gain, and RF Input Frequency, Wideband Mode, Nominal Conditions Figure 28. Minimum Channel Gain vs. RF Input Frequency, Supply, and Temperature Rev. 0 | Page 13 of 36 1000 ADRF6850 3 20 15 10 09316-019 5 1 0 –1 –2 –3 1.2 1.0 0.8 0.6 0.4 0 0.2 –0.2 –0.4 –0.6 –0.8 –1.0 –1.2 –1.4 –1.6 –1.8 –2.0 –2.2 0 2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 VGAIN (V) MINIMUM CHANNEL GAIN (dB) Figure 29. Minimum Channel Gain Distribution at Nominal and Worst-Case Conditions Figure 32. Channel Gain Conformance Error vs. VGAIN and RF Input Frequency, Nominal Conditions 63.0 3.15V, 85°C 3.45V, 85°C –5 RETURN LOSS (dB) MAXIMUM CHANNEL GAIN (dB) 62.5 0 3.30V, 25°C 3.15V, –40°C 3.45V, –40°C 62.0 61.5 61.0 60.5 200 300 400 500 600 700 800 900 VGAIN = 0V VGAIN = 0.5V VGAIN = 1.0V VGAIN = 1.5V –10 –15 –20 –25 –30 09316-018 60.0 100 –35 100 1000 200 300 400 500 600 700 800 900 1000 RF INPUT FREQUENCY (MHz) RF INPUT FREQUENCY (MHz) Figure 30. Maximum Channel Gain vs. RF Input Frequency, Supply, and Temperature Figure 33. Input Return Loss vs. RF Input Frequency and Channel Gain, Nominal Conditions 0 25 NOMINAL WORST-CASE INTEGER BOUNDARY SPURS (dBc) –10 20 OCCURRENCE (%) = 100MHz = 300MHz = 550MHz = 800MHz = 1000MHz 15 10 09316-017 5 –20 –30 –40 –50 –60 –70 –80 –90 –100 100 62.2 62.0 61.8 61.6 61.4 61.2 61.0 60.8 60.6 60.4 60.2 60.0 59.8 59.6 0 INTEGER BOUNDARY SPUR AT 9.6kHz OFFSET INTEGER BOUNDARY SPUR AT 19.2kHz OFFSET INTEGER BOUNDARY SPUR AT 38.4kHz OFFSET 200 300 400 500 600 700 800 900 1000 LO FREQUENCY (MHz) MAXIMUM CHANNEL GAIN (dB) Figure 34. Integer Boundary Spurs vs. LO Frequency, Channel Gain, Supply, and Temperature Figure 31. Maximum Channel Gain Distribution at Nominal and Worst-Case Conditions Rev. 0 | Page 14 of 36 09316-044 OCCURRENCE (%) 25 RF RF RF RF RF 09316-005 CHANNEL GAIN CONFORMANCE ERROR (dB) NOMINAL WORST-CASE 09316-039 30 ADRF6850 TABLE OF DISTRIBUTION DATA: OFFSET FREQUENCY (Hz): 10 0 100 1k 10k 100k 1M 10M TYPICAL RANGE (dBc/Hz): –75/–85 –78/–89 –84/–95 –97/–100 –110/–113 –136/–138 –149/–153 WORST-CASE RANGE (dBc/Hz): –72/–82 –74/–89 –89/–96 –97/–100 –110/–112 –136/–138 –149/–152 –60 –70 –40 –80 –60 VGAIN = 1.5V –80 VGAIN ≤ 1.0V PHASE NOISE (dBc/Hz) –100 –100 –110 –120 –130 –140 200 300 400 500 600 700 800 900 1000 LO FREQUENCY (MHz) 09316-049 –120 100 –90 –150 –160 10 100 1k 10k 100k 1M 10M OFFSET FREQUENCY (Hz) Figure 35. Reference Spurs at 13.5 MHz from Carrier vs. LO Frequency, Channel Gain, Supply, and Temperature Figure 38. Phase Noise Performance Including Distribution Table at LO Frequency = 1000 MHz at Nominal and Worst-Case Conditions 0 0.4 3.30V; +25°C 3.15V; +85°C 3.45V; +85°C 3.15V; –40°C 3.45V; –40°C RMS JITTER (Degrees) –20 PFD SPUR (dBc) 09316-051 REFERENCE SPUR (dBc) –20 –40 –60 VGAIN = 1.5V –80 VGAIN ≤ 1.0V 0.3 0.2 0.1 200 300 400 500 600 700 800 900 1000 LO FREQUENCY (MHz) 0 100 09316-048 –120 100 200 300 400 500 600 700 800 900 09316-041 –100 1000 LO FREQUENCY (MHz) Figure 36. PFD Spurs at 27 MHz from Carrier vs. LO Frequency, Channel Gain, Supply, and Temperature Figure 39. Integrated Phase Noise vs. LO Frequency, Supply, and Temperature TABLE OF DISTRIBUTION DATA: OFFSET FREQUENCY (Hz): 10 100 1k 10k 100k 1M 10M TYPICAL RANGE (dBc/Hz): –91/–100 –99/–111 –107/–115 –118/–121 –129/–132 –150/–154 –151/–153 30 NOMINAL WORST-CASE WORST-CASE RANGE (dBc/Hz): –90/–105 –95/–108 –105/–116 –118/–121 –128/–131 –151/–154 –151/–153 25 –60 OCCURRENCE (%) –70 –90 –100 –110 20 15 10 –120 –130 5 –140 –150 0 0.19 –160 0.23 0.25 0.27 0.29 RMS JITTER (Degrees) 100 1k 10k 100k OFFSET FREQUENCY (Hz) 1M 10M 0.31 0.33 09316-052 –170 10 0.21 09316-040 PHASE NOISE (dBc/Hz) –80 Figure 37. Phase Noise Performance Including Distribution Table at LO Frequency = 100 MHz at Nominal and Worst-Case Conditions Rev. 0 | Page 15 of 36 Figure 40. Integrated Phase Noise Distribution with LO Frequency = 1000 MHz at Nominal and Worst-Case Conditions ADRF6850 1G 30 BEST CASE TYPICAL WORST CASE 100M 25 OCCURRENCE (%) ACQUISITION TO 1kHz 1M 100k 10k 1k 100 START OF ACQUISITION ON CR0 WRITE 10 CR23[3] = 1 LDET 0.1 10 5 0.090 0.095 0.100 0.080 0.085 0.070 0.075 0.065 0.055 0.060 0.050 0.045 0.040 0.030 0.035 0.020 0.025 TIME (µs) 0 0.010 0.015 100 150 200 250 300 350 400 450 500 550 0 50 0.005 0 15 CR23[3] = 0 LDET 0.01 –50 20 09316-031 1 09316-055 ERROR FREQUENCY (Hz) 10M ABSOLUTE IQ AMPLITUDE BALANCE (dB) Figure 44. Absolute IQ Amplitude Balance, Narrow-Band Mode, Nominal Conditions Figure 41. PLL Frequency Settling Time with Typical, Best-Case, and WorstCase Frequency Hop with Lock Detect Shown, Nominal Conditions 20 20 18 16 14 14 12 10 8 10 8 6 6 4 4 2 2 0 –18 –14 –10 –6 –2 2 6 10 14 18 22 26 30 OUTPUT DC OFFSET (mV) 0 –0.45 –0.35 –0.25 –0.15 –0.05 0.05 0.35 0.45 –10 –5 –10 –15 –20 WB MODE NB MODE= 50MHz NB MODE = 43MHz NB MODE = 37MHz NB MODE= 30MHz –30 VGAIN = 1.5V –40 –50 –60 –70 –80 VGAIN = 0V, 0.5V, 1V –90 10 100 1000 IQ OUTPUT FREQUENCY (MHz) 09316-047 1 –20 09316-026 1× LO FEEDTHROUGH (dBm) 0 –30 0.1 0.25 0 5 –25 0.15 IQ PHASE BALANCE (Degrees) Figure 45. IQ Phase Balance, Narrow-Band Mode, Nominal Conditions Figure 42. Output DC Offset Distribution for I and Q Outputs, Nominal Conditions OUTPUT POWER (dB) 12 09316-042 OCCURRENCE (%) 16 09316-050 OCCURRENCE (%) 18 I OUTPUT Q OUTPUT Figure 43. Normalized IQ Output Bandwidth, Narrow-Band, and Wideband Modes, Nominal Conditions –100 100 200 300 400 500 600 700 800 900 1000 LO FREQUENCY (MHz) Figure 46. 1× LO Feedthrough vs. LO Frequency, VGAIN, Supply, and Temperature (Narrow-Band Mode) Rev. 0 | Page 16 of 36 0 0 –20 –20 1× LO FEEDTHROUGH (dBm) –40 –60 –80 –100 VGAIN = 1.5V –40 VGAIN = 1.3V –60 –80 VGAIN = 0V, 0.5V, 1V 200 300 400 500 600 700 800 900 –120 330 1000 09316-022 –120 100 09316-029 –100 430 530 Figure 47. 2× LO Feedthrough vs. LO Frequency, VGAIN, Supply, and Temperature (Narrow-Band Mode) 730 830 930 Figure 50. 1× LO Feedthrough vs. LO Frequency, VGAIN, Supply, and Temperature, Fourth-Order Filter at 300 MHz Applied, Wideband Mode 0 0 –20 –20 1× RF TO IQ LEAKAGE (dBc) 4× LO FEEDTHROUGH (dBm) 630 LO FREQUENCY (MHz) LO FREQUENCY (MHz) –40 –60 –80 –40 VGAIN = 1.5V –60 –80 –100 –120 100 09316-030 –100 200 300 400 500 600 700 800 900 VGAIN = 0V, 0.5V, 1V –120 100 1000 200 300 LO FREQUENCY (MHz) 400 500 600 700 800 900 1000 RF FREQUENCY (MHz) Figure 48. 4× LO Feedthrough vs. LO Frequency, VGAIN, Supply, and Temperature (Narrow-Band Mode) 25 09316-028 2× LO FEEDTHROUGH (dBm) ADRF6850 Figure 51. 1× RF Feedthrough vs. RF Input Frequency, VGAIN, Supply, and Temperature, Narrow-Band Mode 0 NOMINAL WORST-CASE –20 15 10 09316-020 5 –46.5 –46.0 –45.5 –45.0 –44.5 –44.0 –43.5 –43.0 –42.5 –42.0 –41.5 –41.0 –40.5 –40.0 –39.5 –39.0 –38.5 –38.0 –37.5 –37.0 –36.5 –36.0 0 VGAIN = 1.0V –40 VGAIN = 1.5V VGAIN = 1.3V –60 –80 –100 –120 VGAIN = 0V, 0.5V, 1V –140 330 430 09316-027 1× RF TO IQ LEAKAGE (dBc) OCCURRENCE (%) 20 530 630 730 830 930 RF FREQUENCY (MHz) 1× LO FEEDTHOUGH (dBm) Figure 49. 1× LO Feedthrough Distribution at Nominal and Worst-Case Conditions with LO Frequency > 300 MHz, Narrow-Band Mode Figure 52. 1× RF Feedthrough vs. RF Input Frequency, VGAIN, Supply, and Temperature, Fourth-Order Filter at 300 MHz Applied, Wideband Mode Rev. 0 | Page 17 of 36 ADRF6850 OVERVIEW The ADRF6850 device can be separated into the following basic building blocks: • • • • FROM REFIN PIN ×2 DOUBLER 5-BIT R-DIVIDER 09316-061 THEORY OF OPERATION TO PFD ÷2 Figure 54. Reference Input Path The PFD frequency equation is PLL synthesizer and VCO Quadrature demodulator Variable gain amplifier (VGA) I2C/SPI interface fPFD = fREFIN × [(1 + D)/(R × (1 + T))] (1) PLL SYNTHESIZER AND VCO where: fREFIN is the reference input frequency. D is the doubler bit. R is the programmed divide ratio of the binary 5-bit programmable reference divider (1 to 32). T is the ÷2 bit (0 or 1). Overview RF Fractional-N Divider The phase-locked loop (PLL) consists of a fractional-N frequency synthesizer with a 25-bit fixed modulus, allowing a frequency resolution of less than 1 Hz over the entire frequency range. It also has an integrated voltage controlled oscillator (VCO) with a fundamental output frequency ranging from 2000 MHz to 4000 MHz. An RF divider, controlled by Register CR28, Bits[2:0], extends the lower limit of the frequency range to less than 400 MHz. This 400 MHz to 4000 MHz frequency output is then applied to a divide-by-4 quadrature circuit to provide a local oscillator (LO) ranging from 100 MHz to 1000 MHz to the quadrature demodulator. The RF fractional-N divider allows a division ratio in the PLL feedback path that can range from 23 to 4095. The relationship between the fractional-N divider and the LO frequency is described in the following section. Reference Input Section The LO frequency equation is The reference input stage is shown in Figure 53. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed, and SW1 and SW2 are open. This ensures that there is no loading of the REFIN pin at power-down. POWER-DOWN CONTROL 100kΩ NC TO R-DIVIDER SW2 REFIN NC BUFFER SW3 NC 09316-060 SW1 INT and FRAC Relationship The integer (INT) and fractional (FRAC) values make it possible to generate output frequencies that are spaced by fractions of the phase frequency detector (PFD) frequency. See the Programming the Correct LO Frequency section for more information. LO = fPFD × (INT + (FRAC/225))/2 × 2RFDIV where: LO is the local oscillator frequency. fPFD is the PFD frequency. INT is the integer component of the required division factor and is controlled by the CR6 and CR7 registers. FRAC is the fractional component of the required division factor and is controlled by the CR0 to CR3 registers. RFDIV is the setting in Register CR28, Bits[2:0], and controls the setting of a divider at the output of the PLL. RF N-DIVIDER FROM VCO OUTPUT DIVIDERS Figure 53. Reference Input Stage The 5-bit R-divider allows the input reference frequency (REFIN) to be divided down to produce the reference clock to the PFD. Division ratios from 1 to 32 are allowed. An additional divide-by-2 (÷2) function in the reference input path allows for a greater division range. N = INT + FRAC/225 TO PFD N-COUNTER THIRD-ORDER FRACTIONAL INTERPOLATOR Reference Input Path The on-chip reference frequency doubler allows the input frequency of the reference signal to be doubled. This is useful for increasing the PFD comparison frequency. Making the PFD frequency higher improves the noise performance of the system. Doubling the PFD frequency usually improves the in-band phase noise performance by 3 dBc/Hz. (2) INT REG FRAC VALUE 09316-062 Each of these building blocks is described in detail in the sections that follow. Figure 55. RF Fractional-N Divider Phase Frequency Detector (PFD) and Charge Pump The PFD takes inputs from the R-divider and the N-counter and produces an output proportional to the phase and frequency difference between them (see Figure 56 for a simplified schematic). The PFD includes a fixed delay element that sets the width of the antibacklash pulse, ensuring that there is no dead zone in the PFD transfer function. Rev. 0 | Page 18 of 36 ADRF6850 D1 Q1 The correct VCO and band are chosen automatically by the VCO and band select circuitry when Register CR0 is updated. This is referred to as autocalibration. The autocalibration time is set by Register CR25. UP U1 +IN CLR1 DELAY HI CHARGE PUMP U3 Autocalibration Time = (BSCDIV × 24)/PFD CP where: BSCDIV = Register CR25, Bits[7:0]. PFD = PFD frequency. CLR2 DOWN D2 Q2 For a PFD frequency of 27 MHz, BSCDIV = 112 to set an autocalibration time of 100 µs. 09316-063 U2 –IN Figure 56. PFD Simplified Schematic Lock Detect (LDET) LDET (Pin 40) signals when the PLL has achieved lock to an error frequency of less than 1 kHz. On a write to Register CR0, a new PLL acquisition cycle starts, and the LDET signal goes low. When lock has been achieved, this signal returns high. Note that BSCDIV must be recalculated if the PFD frequency is changed. The recommended autocalibration setting is 100 µs. During this time, the VCO VTUNE is disconnected from the output of the loop filter and is connected to an internal reference voltage. A typical frequency acquisition is shown in Figure 58. 1G 100M Voltage Controlled Oscillator (VCO) 10M FREQUENCY ERROR (Hz) The VCO core in the ADRF6850 consists of three separate VCOs, each with 16 overlapping bands. This configuration of 48 bands allows the VCO frequency range to extend from 2000 MHz to 4000 MHz. The three VCOs are divided externally by a programmable divider (RFDIV controlled by Register CR28, Bits[2:0]). This divider provides divisions of 1, 2, 4, and 8 to ensure that the frequency range is extended from 250 MHz (2000 MHz/8) to 4000 MHz (4000 MHz/1). A lower limit of only 400 MHz is required. A divide-by-4 quadrature circuit provides the full LO frequency range from 100 MHz to 1000 MHz. Figure 57 shows a sweep of VTUNE vs. LO frequency demonstrating the three VCOs overlapping and the multiple overlapping bands within each VCO at the LO frequency range of 100 MHz to 1000 MHz. Note that this plot includes the RFDIV divider being incorporated to provide further divisions of the fundamental VCO frequency; thus, each VCO is used on four different occasions throughout the full LO frequency range. The choice of three 16-band VCOs and an RFDIV divider allows the wide frequency range to be covered without large VCO sensitivity (KVCO) or resultant poor phase noise and spurious performance. AUTOCAL TIME (µs) 1M 100k ACQUISITION TO 1kHz 10k 1k 100 10 1 0 50 100 150 200 250 300 350 400 450 500 TIME (µs) Figure 58. PLL Acquisition After autocalibration, normal PLL action resumes, and the correct frequency is acquired to within a frequency error of 1 kHz in 260 μs typically. For a maximum cumulative step of 100 kHz, autocalibration can be turned off by Register CR24, Bit 0. This enables cumulative PLL acquisitions of 100 kHz or less to occur without the autocalibration procedure, which improves acquisition times significantly (see Figure 59). 1G 2.5 100M FREQUENCY ERROR (Hz) 2.3 2.1 1.9 1.7 1.5 10M 1M 100k ACQUISITION TO 1kHz 10k 1k 100 1.3 10 1 0 0.9 100 200 300 400 500 600 700 800 LO FREQUENCY (MHz) 900 1000 20 40 60 80 100 120 TIME (µs) 140 160 180 200 09316-053 1.1 09316-056 VTUNE (V) (3) 09316-054 HI Figure 59. PLL Acquisition Without Autocalibration for a 100 kHz Step Figure 57. VTUNE vs. LO Frequency Rev. 0 | Page 19 of 36 ADRF6850 The VCO displays a variation of KVCO as VTUNE varies within the band and from band to band. Figure 60 shows how the KVCO varies across the fundamental LO frequency range from 500 MHz to 1000 MHz. Note that KVCO is shown at the LO frequency rather than at the VCO frequency. Figure 60 is useful when calculating the loop filter bandwidth and individual loop filter components using ADISimPLL™. ADISimPLL is an Analog Devices, Inc., simulator that aids in PLL design, particularly with respect to the loop filter. It reports parameters such as phase noise, integrated phase noise, acquisition time, and so forth for a particular set of input conditions. ADISimPLL can be downloaded from www.analog.com. 20 VCO SENSITIVITY (MHz/V) Assume that the PFD frequency is 27 MHz and the required LO frequency is 330 MHz. Step 1. From Table 6, 2RFDIV = 2. Step 2. N = (2 × 2 × 330E+6)/(27E+6) = 48.88888889. The N-divider value is composed of integer (INT) and fractional (FRAC) components according to the following equation: N = INT + FRAC/225 (5) INT = 48 and FRAC = 29,826,162. The appropriate registers must then be programmed according to the register map, ensuring that Register CR0 is the last register to be programmed because this write starts a new PLL acquisition cycle. 25 QUADRATURE DEMODULATOR 15 The quadrature demodulator can be powered up by Register CR29, Bit 0. It has an output filter with narrow-band and wideband modes, which are selected by Register CR29, Bit 3. Wideband mode has a 1 dB filter cutoff of 250 MHz. Narrow-band mode has selectable cutoff filters of 30 MHz through 50 MHz by programming Register CR29, Bits[5:4]. A dc bias voltage of 1.4 V (VOCM) can be set internally by setting Register CR29, Bit 6 = 1. To select an external dc bias voltage, set Register CR29, Bit 6 = 0, and drive Pin 7, VOCM, with the requisite external bias voltage. 10 550 600 650 700 750 800 850 900 950 1000 LO FREQUENCY (MHz) 09316-059 5 0 500 Example to Program the Correct LO Frequency Figure 60. KVCO vs. LO Frequency Programming the Correct LO Frequency VARIABLE GAIN AMPLIFIER (VGA) There are two steps to programming the correct LO frequency. The user can calculate the N-divider ratio that is required in the PLL and the RFDIV value based on the required LO frequency and PFD frequency. The variable gain amplifier (VGA) at the input to the demodulator can be driven either single-ended or differentially. 1. Calculate the value of RFDIV, which is used to program Register CR28, Bits[2:0], from the following lookup table (Table 6). See also Table 24. Table 6. RFDIV Lookup Table LO Frequency (MHz) 500 to 1000 250 to 500 125 to 250 100 to 125 2. RFDIV = Register CR28[2:0] 000 = divide-by-1 001 = divide-by-2 010 = divide-by-4 011 = divide-by-8 Using the following equation, calculate the value of the N-divider: N = (2RFDIV × 2 × LO)/(fPFD) where: N is the N-divider value. RFDIV is the setting in Register CR28, Bits[2:0]. LO is the local oscillator frequency. fPFD is the PFD frequency. This equation is a different representation of Equation 2. (4) To drive single-ended, connect Pin 53, RFCM, to Pin 51, RFI, and decouple both pins to ground with a 10 nF capacitor. Drive the input signal through Pin 55, RFI. To drive differentially, use a balun with the RFI and RFI pins driven by the balanced outputs of the balun, and connect the RFCM pin to the common balun output terminal. Decouple RFCM to ground. The VGA gain range is approximately 60 dB and is achieved by varying the VGAIN voltage from 0 V to 1.5 V. The Typical Performance Characteristics section has more information on the VGA gain performance. A 0 V input on VGAIN sets the VGA gain to 0 dB, whereas a 1.5 V input sets the VGA gain to +60 dB if the VGA Gain Mode Polarity Bit CR30, Bit 2, is set to 0. If the VGA gain mode polarity bit is set to 1, a 0 V input voltage on VGAIN sets the VGA gain to +60 dB, whereas a 1.5 V input sets the VGA gain to 0 dB. The VGA can be powered down by setting Register CR30, Bit 0, to 0 and can be powered up by setting this same bit to 1. I2C INTERFACE The ADRF6850 supports a 2-wire, I2C-compatible serial bus that drives multiple peripherals. The part powers up in I2C mode but is not locked in this mode. To remain in I2C mode, it is Rev. 0 | Page 20 of 36 ADRF6850 recommended that the user tie the CS line to either 3.3 V or GND, thus disabling SPI mode. monitors the SDA and SCL lines waiting for the start condition and the correct transmitted address. The R/W bit determines the direction of the data. Logic 0 on the LSB of the first byte indicates that the master writes information to the peripheral. Logic 1 on the LSB of the first byte indicates that the master reads information from the peripheral. The serial data (SDA) and serial clock (SCL) inputs carry information between any devices that are connected to the bus. Each slave device is recognized by a unique address. The ADRF6850 has two possible 7-bit slave addresses for both read and write operations, 0x78 and 0x58. The MSB of the 7-bit slave address is set to 1. Bit 5 of the slave address is set by the CS pin (Pin 27). Bits[4:0] of the slave address are set to 11000. The slave address consists of the seven MSBs of an 8-bit word. The LSB of the word sets either a read or a write operation (see Figure 61). Logic 1 corresponds to a read operation, whereas Logic 0 corresponds to a write operation. 5. To control the device on the bus, the following protocol must be followed: Auto-increment mode is supported, which allows data to be read from or written to the starting subaddress, and each subsequent address, without manually addressing the subsequent subaddress. A data transfer is always terminated by a stop condition. The user can also access any unique subaddress register on a one-by-one basis without updating all registers. R/W CTRL SLAVE ADDRESS[6:0] 1 A5 MSB = 1 SET BY PIN 27 0 0 0 0 0 X 0 = WR 1 = RD Figure 61. Slave Address Configuration S SLAVE ADDR, LSB = 0 (WR) A(S) SUBADDR S = START BIT A(S) = ACKNOWLEDGE BY SLAVE A(S) DATA A(S) DATA A(S) P P = STOP BIT Figure 62. I2C Write Data Transfer S SLAVE ADDR, LSB = 0 (WR) A(S) SUBADDR S = START BIT A(S) = ACKNOWLEDGE BY SLAVE A(S) S SLAVE ADDR, LSB = 1 (RD) A(S) DATA A(M) DATA A(M) P P = STOP BIT A(M) = NO ACKNOWLEDGE BY MASTER A(M) = ACKNOWLEDGE BY MASTER Figure 63. I2C Read Data Transfer START BIT SDA SLAVE ADDRESS A6 SUBADDRESS A5 A7 STOP BIT DATA A0 D7 D0 SCL S WR SLAVE ADDR[4:0] ACK ACK SUBADDR[6:1] Figure 64. I2C Data Transfer Timing Rev. 0 | Page 21 of 36 ACK DATA[6:1] P 09316-066 4. 09316-065 3. Stop and start conditions can be detected at any stage of the data transfer. If these conditions are asserted out of sequence with normal read and write operations, they cause an immediate jump to the idle condition. If an invalid subaddress is issued by the user, the ADRF6850 does not issue an acknowledge and returns to the idle condition. In a no acknowledge condition, the SDA line is not pulled low on the ninth pulse. See Figure 62 and Figure 63 for sample write and read data transfers, Figure 64 for the timing protocol, and Figure 2 for a more detailed timing diagram. 09316-067 2. The master initiates a data transfer by establishing a start condition, defined by a high-to-low transition on SDA while SCL remains high. This indicates that an address/ data stream follows. All peripherals respond to the start condition and shift the next eight bits (the 7-bit address and the R/W bit). The bits are transferred from MSB to LSB. The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. This is known as an acknowledge bit. All other devices then withdraw from the bus and maintain an idle condition. During the idle condition, the device 09316-064 1. The ADRF6850 acts as a standard slave device on the bus. The data on the SDA pin is eight bits long, supporting the 7-bit addresses plus the R/W bit. The ADRF6850 has 34 subaddresses to enable the user-accessible internal registers; therefore, it interprets the first byte as the device address and the second byte as the starting subaddress. ADRF6850 of the part. The SDI line is used to write to the registers. The SDO pin is a dedicated output for the read mode. The part operates in slave mode and requires an externally applied serial clock to the CLK pin. The serial interface is designed to allow the part to be interfaced to systems that provide a serial clock that is synchronized to the serial data. SPI INTERFACE The ADRF6850 supports the SPI protocol; however, the part powers up in I2C mode. To select and lock the SPI mode, three pulses must be sent to the CS pin, as shown in Figure 65. When the SPI protocol is locked in, it cannot be unlocked while the device remains powered up. To reset the serial interface, the part must be powered down and powered up again. Figure 66 shows an example of a write operation to the ADRF6850. Data is clocked into the registers on the rising edge of CLK using a 24-bit write command. The first eight bits represent the write command (0xD4), the next eight bits are the register address, and the final eight bits are the data to be written to the specific register. Figure 67 shows an example of a read operation. In this example, a shortened 16-bit write command is first used to select the appropriate register for a read operation, the first eight bits representing the write command (0xD4) and the final eight bits representing the specific register. Then the CS line is pulsed low for a second time to retrieve data from the selected register using a 16-bit read command, the first eight bits representing the read command (0xD5) and the final eight bits representing the contents of the register being read. Figure 3 shows the timing for both SPI read and SPI write operations. Serial Interface Selection The CS pin controls selection of the I2C or SPI interface. Figure 65 shows the selection process that is required to lock in the SPI mode. To communicate with the part using the SPI protocol, three pulses must be sent to the CS pin. On the third rising edge, the part selects and locks the SPI protocol. Consistent with most SPI standards, the CS pin must be held low during all SPI communication to the part and held high at all other times. SPI Serial Interface Functionality The SPI serial interface of the ADRF6850 consists of the CS, SDI (SDI/SDA), CLK (CLK/SCL), and SDO pins. CS is used to select the device when more than one device is connected to the serial clock and data lines. CLK is used to clock data in and out A B C CS (STARTING HIGH) SPI LOCKED ON THIRD RISING EDGE A B C SPI LOCKED ON THIRD RISING EDGE Figure 65. Selecting the SPI Protocol Rev. 0 | Page 22 of 36 SPI FRAMING EDGE 09316-077 CS (STARTING LOW) SPI FRAMING EDGE ADRF6850 ••• CS ••• CLK D7 D6 D5 START D4 D3 D2 D1 D0 D7 D6 D5 D4 WRITE COMMAND [0xD4] D3 D2 D1 D0 D2 D1 D0 ••• REGISTER ADDRESS CS (CONTINUED) • • • CLK (CONTINUED) • • • SDI (CONTINUED) • • • D7 D6 D5 D4 D3 09316-068 SDI STOP DATA BYTE Figure 66. SPI Byte Write Example ••• CS ••• CLK SDI D7 D6 D5 START D4 D3 D2 D1 D0 D7 D6 D5 D4 WRITE COMMAND [0xD4] D3 D2 D1 D0 ••• REGISTER ADDRESS CS SDI D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X SDO X X X X X X X X D7 D6 D5 D4 D3 D2 D1 D0 START READ COMMAND [0xD5] DATA BYTE Figure 67. SPI Byte Read Example Rev. 0 | Page 23 of 36 STOP 09316-069 CLK ADRF6850 PROGRAM MODES The ADRF6850 has 34 8-bit registers to allow program control of a number of functions. Only 31 of these registers are writeable. Either an SPI or an I2C interface can be used to program the register set. For details about the interfaces and timing, see Figure 61 to Figure 67. The registers are documented in Table 8 to Table 27. Several settings in the ADRF6850 are double buffered. These settings include the FRAC value, the INT value, the RFDIV value, the 5-bit R-divider value, the reference doubler, the R ÷2 divider, and the charge pump current setting. This means that two events must occur before the part uses a new value for any of the double buffered settings. First, the new value is latched into the device by writing to the appropriate register. Next, a new write must be performed on Register CR0. When Register CR0 is written, a new PLL acquisition occurs. For example, updating the fractional value involves a write to Register CR3, Register CR2, Register CR1, and Register CR0. Register CR3 should be written to first, followed by Register CR2 and Register CR1 and, finally, Register CR0. The new acquisition begins after the write to Register CR0. Double buffering ensures that the bits written to do not take effect until after the write to Register CR0. 5-bit divider is enabled by programming Register CR5, Bit 4; and the division ratio is programmed through Register CR10, Bits[4:0]. The R ÷2 divider is programmed through Register CR10, Bit 6. Note that these registers are double buffered. Charge Pump Current Register CR9, Bits[7:4], set the charge pump current setting. With an RSET value of 4.7 kΩ, the maximum charge pump current is 5 mA. The following equation applies: ICP max = 23.5/RSET The charge pump current has 16 settings from 325 μA to 5 mA. Power-Down/Power-Up Control Bits The four programmable power-up and power-down control bits are as follows: 12-Bit Integer Value Register CR7 and Register CR6 program the integer value (INT) of the feedback division factor (N); see Equation 5 for details. The INT value is a 12-bit number whose MSBs are programmed through Register CR7, Bits[3:0]. The LSBs are programmed through Register CR6, Bits[7:0]. The LO frequency setting is described by Equation 2. An alternative to this equation is provided by Equation 4, which details how to set the N-divider value. Note that these registers are double buffered. 25-Bit Fractional Value Register CR3 to Register CR0 program the fractional value (FRAC) of the feedback division factor (N); see Equation 5 for details. The FRAC value is a 25-bit number whose MSB is programmed through Register CR3, Bit 0. The LSB is programmed through Register CR0, Bit 0. The LO frequency setting is described by Equation 2. Again, an alternative to this equation is described by Equation 4, which details how to set the N-divider value. Note that these registers are double buffered. RFDIV Value The RFDIV value is dependent on the value of the LO frequency. The RFDIV value can be selected from the list in Table 6. Apply the selected RFDIV value to Equation 4, together with the LO frequency and PFD frequency values, to calculate the correct Ndivider value. Reference Input Path The reference input path consists of a reference doubler, a 5-bit frequency divider, and a divide-by-2 function (see Figure 54). The doubler is programmed through Register CR10, Bit 5. The (6) Register CR12, Bit 2. Master power control bit for the PLL, including the VCO. This bit is normally set to a default value of 0 to power up the PLL. Register CR27, Bit 2. Controls the LO monitor outputs, LOMON and LOMON. The default is 0 when the monitor outputs are powered down. Setting this bit to 1 powers up the monitor outputs to one of −6 dBm, −12 dBm, −18 dBm, or −24 dBm, as controlled by Register CR27, Bits[1:0]. Register CR29, Bit 0. Controls the quadrature demodulator power. The default is 0, which powers down the demodulator. Write a 1 to this bit to power up the demodulator. Register CR30, Bit 0. This bit controls the VGA power and must be set to a 1 to power up the VGA. Lock Detect (LDET) Lock detect is enabled by setting Register CR23, Bit 4, to 1. Register CR23, Bit 3, in conjunction with Register CR14, Bit 7, sets the number of up/down pulses generated by the PFD before lock detect is declared by the LDET pin returning high. The options are 2048 pulses, 3072 pulses, and 4096 pulses. The default setting is 3072 pulses, which is selected by programming Register CR23, Bit 3, to 0, and Register CR14, Bit 7, to 0. A more aggressive setting of 2048 is selected when Register CR23, Bit 3, is set to 1 and Register CR14, Bit 7, is set to 0. This improves the lock detect time by 50 μs (for a PFD frequency of 27 MHz). Note, however, that it does not affect the acquisition time to an error frequency of 1 kHz. A setting of 4096 pulses is selected when Register CR14, Bit 7, is set to 1. For best operation, set Register CR23, Bit 2 to 0. This bit sets up the PFD up/down pulses to a coarse or low precision setting. Baseband VOCM Reference Register CR29, Bit 6, selects whether the common-mode reference for the baseband outputs is internal or external. When the baseband outputs are ac-coupled, then the internal reference must be selected by setting Register CR29, Bit 6, to 1, and by grounding Pin 7, VOCM. When the baseband outputs are dc-coupled, it is likely that an external bias is needed unless the internal dc bias provided is Rev. 0 | Page 24 of 36 ADRF6850 within a suitable range to match the specification of the followon device. This is accomplished by setting Register CR29, Bit 6, to 0, and driving Pin 7, VOCM, with the requisite external bias voltage. Narrow-Band and Wideband Filter Mode By default, the second-order low-pass filter in the output buffers of the baseband output signal paths is selected, and the baseband outputs are in narrow-band mode. By setting Register CR29, Bits[5:4], this filter can be set to a cutoff frequency of 50 MHz, 43 MHz, 37 MHz, or 30 MHz. By setting Register CR29, Bit 3, to 1, this filter is bypassed and wideband mode is selected. Table 7. Baseband Filter Settings CR29[5:4] 00 01 10 11 Filter Cutoff Frequency (MHz) 50 43 37 30 VGA Gain Mode Polarity The polarity of the VGA gain is set by programming Bit 2 of Register CR30. By setting Register CR30, Bit 2, to 0, a positive gain slope is selected where VGAIN = 0 V sets the VGA gain to be 0 dB, and VGAIN = 1.5 V sets the VGA gain to be 60 dB. By setting Register CR30, Bit 2, to 1, a negative gain slope is selected. Rev. 0 | Page 25 of 36 ADRF6850 REGISTER MAP REGISTER MAP SUMMARY Table 8. Register Map Summary Register Address (Hex) 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 Register Name CR0 CR1 CR2 CR3 CR4 CR5 CR6 CR7 CR8 CR9 CR10 CR11 CR12 CR13 CR14 CR15 CR16 CR17 CR18 CR19 CR20 CR21 CR22 CR23 CR24 CR25 CR26 CR27 CR28 CR29 CR30 CR31 CR32 CR33 Type Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read only Read only Read only Rev. 0 | Page 26 of 36 Description Fractional Word 4 Fractional Word 3 Fractional Word 2 Fractional Word 1 Reserved Reference 5-bit, R-divider enable Integer Word 2 Integer Word 1 Reserved Charge pump current setting Reference frequency control Reserved PLL power-up Reserved Lock Detector Control 2 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Lock Detector Control 1 Autocalibration Autocalibration timer Reserved LO monitor output LO selection Demodulator power and filter selection VGA Reserved Reserved Revision code ADRF6850 REGISTER BIT DESCRIPTIONS Table 13. Register CR5 (Address 0x05), Reference 5-Bit, R-Divider Enable Table 9. Register CR0 (Address 0x00), Fractional Word 4 Bit 7 6 5 4 3 2 1 0 1 Bit 7 6 5 4 Description Fractional Word F71 Fractional Word F61 Fractional Word F51 Fractional Word F41 Fractional Word F31 Fractional Word F21 Fractional Word F11 Fractional Word F0 (LSB)1 3 2 1 0 Double buffered. Load on the write to Register CR0. Table 10. Register CR1 (Address 0x01), Fractional Word 3 Bit 7 6 5 4 3 2 1 0 1 Description Fractional Word F151 Fractional Word F141 Fractional Word F131 Fractional Word F121 Fractional Word F111 Fractional Word F101 Fractional Word F91 Fractional Word F81 Bit 7 6 5 4 3 2 1 0 Table 11. Register CR2 (Address 0x02), Fractional Word 2 1 Description Fractional Word F231 Fractional Word F221 Fractional Word F211 Fractional Word F201 Fractional Word F191 Fractional Word F181 Fractional Word F171 Fractional Word F161 1 Double buffered. Load on the write to Register CR0. Bit [7:4] Table 12. Register CR3 (Address 0x03), Fractional Word 1 Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Fractional Word F24 (MSB)1 1 Description Integer Word N71 Integer Word N61 Integer Word N51 Integer Word N41 Integer Word N31 Integer Word N21 Integer Word N11 Integer Word N01 Table 15. Register CR7 (Address 0x07), Integer Word 1 Double buffered. Load on the write to Register CR0. Bit 7 6 5 4 3 2 1 0 Double buffered. Load on the write to Register CR0. Table 14. Register CR6 (Address 0x06), Integer Word 2 Double buffered. Load on the write to Register CR0. Bit 7 6 5 4 3 2 1 0 1 Description Reserved Reserved Reserved 5-bit R-divider enable1 0 = disable 5-bit R-divider (default) 1 = enable 5-bit R-divider Reserved Reserved Reserved Reserved 3 2 1 0 1 Description MUXOUT control 0000 = tristate 0001 = logic high 0010 = logic low 1101 = RCLK/2 1110 = NCLK/2 Integer Word N111 Integer Word N101 Integer Word N91 Integer Word N81 Double buffered. Load on the write to Register CR0. Double buffered. Load on the write to Register CR0. Rev. 0 | Page 27 of 36 ADRF6850 Table 16. Register CR9 (Address 0x09), Charge Pump Current Setting Bit [7:4] 3 2 1 0 1 Description Charge pump current1 0000 = 0.31 mA (default) 0001 = 0.63 mA 0010 = 0.94 mA 0011 = 1.25 mA 0100 = 1.57 mA 0101 = 1.88 mA 0110 = 2.19 mA 0111 = 2.50 mA 1000 = 2.81 mA 1001 = 3.13 mA 1010 = 3.44 mA 1011 = 3.75 mA 1100 = 4.06 mA 1101 = 4.38 mA 1110 = 4.69 mA 1111 = 5.00 mA Reserved Reserved Reserved Reserved Double buffered. Load on the write to Register CR0. Table 17. Register CR10 (Address 0x0A), Reference Frequency Control Bit 7 6 5 [4:0] 1 Description Reserved1 R divide-by-2 divider enable1 0 = bypass R divide-by-2 divider 1 = enable R divide-by-2 divider R-doubler enable1 0 = disable doubler (default) 1 = enable doubler 5-bit R-divider setting1 00000 = divide by 32 (default) 00001 = divide by 1 00010 = divide by 2 … 11110 = divide by 30 11111 = divide by 31 Double buffered. Load on the write to Register CR0. Table 18. Register CR12 (Address 0x0C), PLL Power-Up Bit 7 6 5 4 3 2 1 0 Description Reserved Reserved Reserved Reserved Reserved PLL power-down 0 = power up PLL (default) 1 = power down PLL Reserved Reserved Table 19. Register CR14 (Address 0x0E), Lock Detector Control 2 Bit 7 6 5 4 3 2 1 0 Description Lock Detector Up/Down Count 2 0 = 2048/3072 up/down pulses 1 = 4096 up/down pulses Reserved Reserved Reserved Reserved Reserved Reserved Reserved Table 20. Register CR23 (Address 0x17), Lock Detector Control 1 Bit 7 6 5 4 3 2 1 0 Rev. 0 | Page 28 of 36 Description Reserved Reserved Reserved Lock detector enable 0 = lock detector disabled (default) 1 = lock detector enabled Lock detector up/down count With Register CR14[7] = 0: 0 = 3072 up/down pulses 1 = 2048 up/down pulses Lock detector precision 0 = low, coarse (16 ns) 1 = high, fine (6 ns) Reserved Reserved ADRF6850 Table 21. Register CR24 (Address 0x18), Autocalibration Bit 7 6 5 4 3 2 1 0 Table 25. Register CR29 (Address 0x1D), Demodulator Power and Filter Selection Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Disable autocalibration 0 = enable autocalibration (default) 1 = disable autocalibration Bit 7 6 [5:4] 3 Table 22. Register CR25 (Address 0x19), Autocalibration Timer Bit [7:0] Description Autocalibration timer Table 23. Register CR27 (Address 0x1B), LO Monitor Output Bit 7 6 5 4 3 2 [1:0] Description Reserved Reserved Reserved Reserved Reserved Power-up monitor output 0 = power down (default) 1 = power up Monitor output power into 50 Ω 00 = −24 dBm (default) 01 = −18 dBm 10 = −12 dBm 11 = −6 dBm 2 1 0 Table 26. Register CR30 (Address 0x1E), VGA Bit 7 6 5 4 3 2 1 0 Table 24. Register CR28 (Address 0x1C), LO Selection Bit 7 6 5 4 3 [2:0] Description Reserved Reserved Reserved Reserved Reserved; set to 1 RFDIV 000 = divide by 1; LO = 500 MHz to 1000 MHz 001 = divide by 2; LO = 250 MHz to 500 MHz 010 = divide by 4; LO = 125 MHz to 250 MHz 011 = divide by 8; LO = 100 MHz to 125 MHz Description Reserved Internal baseband (VOCM) select 0 = select external baseband (VOCM) reference 1 = select internal baseband (VOCM) reference Narrow-band filter cut off 00 = 50 MHz 01 = 43 MHz 10 = 37 MHz 11 = 30 MHz Baseband wideband/narrow-band modes 0 = narrow-band mode 1 = wideband mode Reserved; set to 0 Reserved; set to 0 Power-up demodulator 0 = power down (default) 1 = power up Description Reserved Reserved Reserved Reserved Reserved VGA gain mode polarity 0 = positive gain slope 1 = negative gain slope Reserved Power-up VGA 0 = power down 1 = power up Table 27. Register CR33 (Address 0x21), Revision Code1 Bit 7 6 5 4 3 2 1 0 1 Description Revision code Revision code Revision code Revision code Revision code Revision code Revision code Revision code Read-only register. Rev. 0 | Page 29 of 36 ADRF6850 SUGGESTED POWER-UP SEQUENCE INITIAL REGISTER WRITE SEQUENCE After applying power to the device, adhere to the following write sequence, particularly with respect to the reserved register settings. Note that Register CR33, Register CR32, and Register CR31 are read-only registers. Also note that all writeable registers should be written to on power-up. Refer to the Register Map section for more details on all registers. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. Write the following to Register CR30 = 0x00. Set VGA power to off and the VGA gain slope to be positive. Write the following to Register CR29: 0x41. The demodulator is powered up. The baseband narrow-band mode is selected and set to a cutoff frequency of 50 MHz. The internal baseband VOCM reference is selected. Write the following to Register CR28: 0x0X RFDIV depends on the value of the LO frequency to be used and is set according to Table 6. Note that Register CR28, Bit 3, is set to 1. Write the following to Register CR27: 0x00. Power the LO monitor in a power-down state. Write the following to Register CR26: 0x00. Reserved register. Write the following to Register CR25: 0x70. Set the autocalibration time to 100 μs with a PFD frequency setting of 27 MHz. If the PFD frequency is different, set CR25 according to Equation 3. Write the following to Register CR24: 0x38. Enable autocalibration. Write the following to Register CR23: 0x70. Enable lock detector and set lock detector counter = 3072 up/down pulses. Write the following to Register CR22: 0x00. Reserved register. Write the following to Register CR21: 0x00. Reserved register. Write the following to Register CR20: 0x00. Reserved register. Write the following to Register CR19: 0x00. Reserved register. Write the following to Register CR18: 0x60. Reserved register. Write the following to Register CR17: 0x00. Reserved register. Write the following to Register CR16: 0x00. Reserved register. 16. Write the following to Register CR15: 0x00. Reserved register. 17. Write Register CR14: 0x00. Lock Detector Control 2. 18. Write Register CR13: 0x08. Reserved register. 19. Write the following to Register CR12: 0x18. PLL powered up. 20. Write the following to Register CR11: 0x00. Reserved register. 21. Write the following to Register CR10: 0x21. The reference path doubler is enabled and the 5-bit divider and R divideby-2 divider are bypassed. 22. Write the following to Register CR9: 0x70. With the recommended loop filter component values and RSET = 4.7 kΩ, the charge pump current is set to 2.5 mA for a loop bandwidth of 50 kHz. 23. Write the following to Register CR8: 0x00. Reserved register. 24. Write the following to Register CR7: 0x0X. Set according to Equation 4 and Equation 5 in the Theory of Operation section. 25. Write the following to Register CR6: 0xXX. Set according to Equation 4 and Equation 5 in the Theory of Operation section. 26. Write Register CR5: 0x00. Disable the 5-bit reference divider. 27. Write the following to Register CR4: 0x01. Reserved register. 28. Write the following to Register CR3: 0x0X. Set according to Equation 4 and Equation 5 in the Theory of Operation section. 29. Write the following to Register CR2: 0xXX. Set according to Equation 4 and Equation 5 in the Theory of Operation section. 30. Write the following to Register CR1: 0xXX. Set according to Equation 4 and Equation 5 in the Theory of Operation section. 31. Write the following to Register CR0: 0xXX. Set according to Equation 4 and Equation 5 in the Theory of Operation section. Register CR0 must be the last register written for all the double buffered bit writes to take effect. 32. Monitor the LDET output or wait 260 μs to ensure that the PLL is locked. 33. Write the following to Register CR30: 0x01. Set the VGA to power on. Rev. 0 | Page 30 of 36 ADRF6850 EVALUATION BOARD GENERAL DESCRIPTION and 56 pF capacitors that are placed as close to the DUT as possible for good local decoupling. The impedance of all these capacitors should be low and constant across a broad frequency range. Surface-mount multilayered ceramic chip (MLCC) Class II capacitors provide very low ESL and ESR, which assist in decoupling supply noise effectively. They also provide good temperature stability and good aging characteristics. Capacitance changes per the bias voltage that is applied. Larger case sizes have less capacitance change vs. applied bias voltage, and also lower ESR but higher ESL. A combination of 0402 size cases for the 56 pF capacitors and 0603 size cases for the 100 nF capacitors give a good compromise allowing the 56 pF capacitors to be placed as close as possible to the supply pins on the top side of the PCB with the 100 nF capacitors placed on the bottom side of the PCB quite close to the supply pins. X5R and X7R capacitors are examples of these types of capacitors and are recommended for decoupling. The evaluation board is designed to allow the user to evaluate the performance of the ADRF6850. It contains the following: • • • • • • • The ADRF6850 DUT. This is an I/Q demodulator with an integrated fractional-N PLL and VCO. SPI and I2C interface connectors. Baseband output connectors. Fourth-order low-pass loop filter circuitry. 13.5 MHz reference clock, and the ability to drive the reference input external to the board. Circuitry to support differential signaling to the TESTLO inputs, including dc biasing circuitry. Circuitry to monitor the LOMON outputs. SMA connectors for power supplies, the VGAIN input and a single-ended RF input. The evaluation board comes with associated software to allow easy programming of the ADRF6850. SPI and I2C Interface The SPI interface connector is a nine-way, D-type connector that can be connected to the printer port of a PC. Figure 68 shows the PC cable diagram that must be used with the provided software. HARDWARE DESCRIPTION For more information, refer to the circuit diagram in Figure 69. Power Supplies There is also an option to use the I2C interface by using the I2C receptacle connector. This is a standard I2C connector. A supply voltage of +3.3 V is provided by the I2C bus master. Pull-up resistors are required on the signal lines. The CS pin can be used to set the slave address of the ADRF6850. CS high sets the slave address to 0x78, and CS low sets the slave address to 0x58. An external +3.3 V supply (DUT + 3.3 V) powers each of the nine VCCx supplies on the ADRF6850 as well as the 13.5 MHz clock reference. Recommended Decoupling for Supplies Initially, the external +3.3 V supply is decoupled by a 10 µF capacitor and then further by a parallel combination of 100 nF 1 6 7 8 2 3 4 9 5 9-WAY FEMALE D-TYPE CLK 1 2 14 DATA 3 15 LE 4 16 5 17 18 6 GND 19 7 20 8 21 9 10 22 PC 23 11 24 12 13 25 25-WAY MALE D-TYPE TO PC PRINTER PORT Figure 68. SPI PC Cable Diagram Rev. 0 | Page 31 of 36 09316-070 • ADRF6850 Baseband Outputs and VOCM LOMON Outputs The pair of I and Q baseband outputs are connected to the board by SMA connectors. They are ac-coupled to the output connectors. VOCM, which sets the common-mode output voltage, is grounded and the internal baseband (VOCM) reference is selected by Register CR29, Bit 6. If the external baseband (VOCM) reference is selected by setting this bit to a 0, then a voltage needs to be applied through J6 and R20 needs to be removed. These pins are differential LO monitor outputs that provide a replica of the internal LO frequency at 1× LO. The single-ended power in a 50 Ω load can be programmed to −24 dBm, −18 dBm, −12 dBm, or −6 dBm. These open-collector outputs must be terminated to 3.3 V. Because both outputs must be terminated to 50 Ω, options are provided to terminate to 3.3 V using onboard 50 Ω resistors or by series inductors (or a ferrite bead), in which case the 50 Ω termination is provided by the measuring instrument. Loop Filter A fourth-order loop filter is provided at the output of the charge pump and is required to adequately filter noise from the Σ-Δ modulator used in the N-divider. With the charge pump current set to a midscale value of 2.5 mA and using the on-chip VCO, the loop bandwidth is approximately 50 kHz, and the phase margin is 55°. C0G capacitors are recommended for use in the loop filter because they have low dielectric absorption, which is required for fast and accurate settling time. The use of non C0G capacitors may result in a long tail being introduced into the PLL settling time transient. Reference Input The reference input can be supplied by a 13.5 MHz Jauch clock generator or by an external clock through the use of Connector J7. The frequency range of the reference input is from 10 MHz to 300 MHz with the PFD frequency limited to a maximum of 30 MHz. Double the 13.5 MHz clock to 27 MHz by using the onchip reference frequency doubler to optimize phase noise performance. TESTLO Inputs These pins are differential test inputs that allow a variety of debug options. On this board, the capability is provided to drive these pins with an external 4× LO signal that is then applied to an Anaren balun to provide a differential input signal. When driving the TESTLO pins, the PLL can be bypassed, and the demodulator can be driven directly by this external LO signal. The frequency of the LO signal needs to be 4 times the operating frequency. These inputs also require a dc bias. A dc bias of 3.3 V is the default option used on the board. CCOMPx Pins The CCOMPx pins are internal compensation nodes that must be decoupled to ground with a 100 nF capacitor. MUXOUT MUXOUT is a test output that allows different internal nodes to be monitored. It is a CMOS output stage that requires no termination. Lock Detect (LDET) Lock detect is a CMOS output that indicates the state of the PLL. A high level indicates a locked condition, and a low level indicates a loss of lock condition. RF Inputs (RFI, RFCM, and RFI) RFI and RFI are 50 Ω internally biased RF inputs. For singleended operation as demonstrated on the evaluation board, RFI must be ac-coupled to the source and RFI must be ac-coupled to the ground plane. RFCM is the RF input common-mode pin. It should be connected to RFI when driving the input in singleended mode. When driving the input differentially using a balun, connect this pin to the common terminal of the output coil of the balun. VGAIN The VGAIN pin sets the gain of the VGA. The VGAIN voltage range is from 0 V to 1.5 V. This allows the gain of the VGA to vary from 0 dB to +60 dB. Rev. 0 | Page 32 of 36 ADRF6850 PCB SCHEMATIC 09316-058 Figure 69. Applications Circuit Rev. 0 | Page 33 of 36 ADRF6850 PCB ARTWORK 09316-071 09316-072 Component Placement 09316-076 Figure 73. Evaluation Board, Bottom Side Component Placement 09316-073 Figure 70. Evaluation Board, Top Side Component 09316-075 09316-074 Figure 74. Evaluation Board Power—Layer 3 Figure 71. Evaluation Board, Top Side—Layer 1 Figure 75. Evaluation Board, Bottom Side—Layer 4 Figure 72. Evaluation Board, Ground—Layer 2 Rev. 0 | Page 34 of 36 ADRF6850 BILL OF MATERIALS Table 28. Bill of Materials Qty. 1 1 Reference Designator DUT Y2 Description ADRF6850 LFCSP, 56-lead 8 mm × 8 mm VCO, 13.5 MHz Manufacturer Analog Devices Jauch 1 1 2 10 Connector, 9-pin, D-sub plug, D-SUB9MR Connector, I2C, SEMCONN receptacle Capacitor, 10 µF, 25 V, tantalum, TAJ-C Capacitor, 56 pF, 50 V, ceramic, C0G, 0402 ITW McMurdo Digikey AVX AVX Capacitor, 100 nF, 25 V, X7R, ceramic, 0603 AVX FEC 317287 1 1 4 2 2 1 4 12 2 SPI I2 C C1, C34 C4, C6, C10, C12, C14, C16, C40, C48, C53, C55 C5, C7, C11, C13, C15, C17, C22, C27, C47, C49 to C52, C54 C3 C35 C2, C21, C38, C39 C44, C46 C43, C56 C18 C30 to C33 J2 to J12, J14 J20, J21 Part Number ADRF6850BCPZ 0 13.50-VX7-G-3.3-1T1-LF FEC 1071806 5-1761185-1-ND FEC 197518 FEC 1658861 Capacitor, 1.8 nF, 50 V, C0G, ceramic, 0603 Capacitor, 68 nF, 50 V, NPO, ceramic, 1206 Capacitor, 1 nF, 50 V, C0G, ceramic, 0603 Capacitor, 100 pF, 50 V, C0G, ceramic, 0402 Capacitor, 10 nF, 50 V, X7R, ceramic, 0402 Capacitor, 10 pF, 50 V, C0G, ceramic, 0402 Capacitor, 10 μF, 6.3 V, X5R, ceramic, 0603 SMA end launch connector Jumper, 3-pin plus shunt Murata Kemet Murata Murata Murata Murata Phycomp Johnson/Emerson Harwin 2 2 2 1 2 1 2 2 3 L1, L2 L3, L4 R20, R36 R13 R14, R39 R1 R3, R4 R17, R18 R35, R44, R45 Inductor, 20 nH, 0402, LQW series Inductor, 10 µH, 0805, LQM series Resistor, 0 Ω, 1/16 W, 1%, 0402 Resistor, 4.7 kΩ, 1/10 W, 1%, 0603 Resistor, 1.2 kΩ, 1/10 W, 5%, 0603 Resistor, 220 Ω, 1/16 W, 1%, 0603 Resistor, 200 Ω, 1/16 W, 5%, 0402 Resistor, 0603, spacing (do not install) Resistor, 51 Ω, 1/16 W, 1%, 0402 Murata Murata Vishay Draloric Multicomp Phycomp Multicomp Vishay Dale FEC 1402814 FEC 1535582 FEC 8819920 FEC 8819572 FEC 1414575 FEC 8819564 FEC 1458902 142-0701-851 FEC 148533 + FEC 150411 LQW15AN20N LQM21FN1N100M FEC 1158241 FEC 1576293 FEC 9233393 FEC 9330801 FEC 1514682 Multicomp FEC 1358008 4 2 R48 to R51 R60, R61 Resistor, 330 Ω, 1/10 W, 5%, 0805 Resistor, 100 Ω, 1/10 W, 5%, 0805 Vishay Draloric Bourns 2 7 R46, R47 CS, LDET, MUXOUT, VTUNE, SCLK, SDA, SDO BAL1 Resistor, 10 kΩ, 1/16 W, 1%, 0402 Test point, 1-pin, 0.035 inch diameter Phycomp Not inserted FEC 1739223 Digi Key RR12P100DTR-ND FEC 9239359 Balun, 0805, 50 Ω to 100 Ω balanced (1.3 GHz to 3.1 GHz) Anaren 14 1 Rev. 0 | Page 35 of 36 BD1631J50100A00 ADRF6850 OUTLINE DIMENSIONS 8.10 8.00 SQ 7.90 0.30 0.23 0.18 0.60 MAX 0.60 MAX 43 56 42 PIN 1 INDICATOR 7.85 7.75 SQ 7.65 PIN 1 INDICATOR 1 0.50 BSC EXPOSED PAD 5.25 5.10 SQ 4.95 14 29 1.00 0.85 0.80 0.80 MAX 0.65 TYP 12° MAX 28 15 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.20 REF 0.08 SEATING PLANE 0.25 MIN 6.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VLLD-2 081809-B TOP VIEW 0.50 0.40 0.30 Figure 76. 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 8 mm × 8 mm Body, Very Thin Quad (CP-56-5) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADRF6850BCPZ ADRF6850BCPZ-R7 EVAL-ADRF6850EB1Z 1 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ], Tray 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 7" Tape and Reel Evaluation Board Z = RoHS Compliant Part. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09316-0-10/10(0) Rev. 0 | Page 36 of 36 Package Option CP-56-5 CP-56-5