INTEGRATED CIRCUITS SA9024 900 MHz transmit modulator and 1.3 GHz fractional–N synthesizer Objective specification 1997 Aug 01 Philips Semiconductors Objective specification 900 MHz transmit modulator and 1.3 GHz fractional–N synthesizer SA9024 • Reference and clock buffers • Control logic for programming and power down modes DESCRIPTION This specification defines the requirements for a transmitter modulator and fractional–N synthesizer IC to be used in cellular telephones which employ the North American Dual Mode Cellular System (IS–136). 48 47 46 45 44 43 42 XTAL1 MCLK V CC RCLK XTAL2 35 TXEN RXLO1 3 34 DATA RXLO2 4 33 CLOCK 32 LOCK 31 STROBE V CC GND V CC • Cellular phones • Portable battery–powered radio equipment. 41 40 39 38 37 36 PHP APPLICATIONS PHA INA GND GND V CC RN PHI • Low current from 3.75V supply • Low phase noise • Main loop with internal charge pump and fractional compensation • 3–line serial interface bus • Power down for the synthesizers • Speedup mode for faster switching GND PIN CONFIGURATION FEATURES 1 2 5 SA9024 6 TXLO1 7 TXLO2 8 GND 9 PHS out 10 Ipeak 11 GENERAL DESCRIPTION TANK1 12 The SA9024 BICMOS device integrates: • Main channel synthesizer • Auxiliary synthesizer • Transmit offset synthesizer and oscillator • I/Q modulator • Power control 30 GND 29 V CC 28 I 27 I 26 Q 25 Q Figure 1. Vcc GND DUALTX2 GND DUALTX1 GND GND GND GND GND Vcc TANK2 13 14 15 16 17 18 19 20 21 22 23 24 SR01536 Pin Configuration QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS VCC MIN. TYP. MAX. UNIT VCC Supply voltage 3.6 3.75 3.9 V ICC Supply current – TBD – mA ICC_save Total supply current in power–down mode – TBD – mA fVCO Input frequency 800 – 1300 MHz fAUX Input frequency 10 – 500 MHz fXTAL Crystal reference input frequency 10 – 40 MHz fPC Maximum phase comparator frequency – – 5 MHz Tamb Operating ambient temperature –40 – +85 °C Main and Aux loops ORDERING INFORMATION TYPE NUMBER SA9024 1997 Aug 01 PACKAGE NAME DESCRIPTION VERSION LQFP48 Plastic low profile quad flat package; 48 leads; body 7x7x1.4 mm SOT313-2 2 Philips Semiconductors Objective specification 900 MHz transmit modulator and 1.3 GHz fractional–N synthesizer SA9024 XTAL1 MCLK RCLK V CC PHA GND INA CC V GND RN PHI GND CONNECTIONS XTAL 2 PHP MAIN PD and CP AUX PD and CP AUX. DIV. ÷A V CC TX EN DATA RXLO1 REF. DIV. MAIN DIV. ÷N RXLO2 CLOCK CONTROL LOGIC GND LOCK STROBE V CC GND TXLO1 V CC TXLO2 ∑ 0 0 90 90 I GND ∅ I PHS out ∑ 0 90 ÷M Q Ipeak TANK1 VCC GND DUALTX2 GND DUAL TX1 GND GND GND GND GND VCC TANK2 Q SR01455 Figure 2. 1997 Aug 01 SA9024 Block Diagram 3 Philips Semiconductors Objective specification 900 MHz transmit modulator and 1.3 GHz fractional–N synthesizer SA9024 PIN DESCRIPTIONS PIN NO. PIN 1 PHP Proportional charge pump output 2 VCC Digital supply voltage 3 RXLO1 Differential LO input 4 RXLO2 Differential LO input 5 GND Digital Ground 6 VCC Tank supply voltage 7 TXLO1 Differential Transmit LO Input 8 TXLO2 Differential Transmit LO Input 9 GND Tank Ground 10 PHS OUT 11 IPEAK 12 TANK1 VCO differential tank 13 TANK2 VCO differential tank 14 VCC Tx supply voltage 15 GND Tx Ground 16 GND Tx Ground 17 GND Tx Ground 18 GND Tx Ground 19 GND Tx Ground 20 DUALTX1 21 GND 22 DUALTX2 23 GND 1997 Aug 01 DESCRIPTION Charge pump output (transmit offset) PHS out current set resistor Dual mode RF output Tx Ground Dual mode RF output Tx Ground 4 24 VCC Tx supply voltage 25 Q Inverting quadrature input 26 Q Non–Inverting quadrature input 27 I Non–inverting in phase modulation input 28 I Inverting in phase modulation input 29 VCC Tx supply voltage 30 GND Tx Ground 31 STROBE Data input latch enable 32 LOCK 33 CLOCK Lock detect Serial clock input 34 DATA Serial data input 35 TXEN Transmit enable 36 XTAL2 Crystal Oscillator emitter input 37 XTAL1 Crystal Oscillator base Input 38 MCLK Buffered oscillator output 39 RCLK Buffered oscillator output 40 VCC REF supply voltage 41 PHA Auxiliary charge pump output 42 GND REF Ground 43 INA RXIF input 44 VCC CP supply voltage 45 GND CP Ground 46 RN 47 GND CP Ground 48 PHI Integral charge pump output CP current set resistor Philips Semiconductors Objective specification 900 MHz transmit modulator and 1.3 GHz fractional–N synthesizer SA9024 OPERATING MODES & POWER DOWN CONTROL the digital portion of the system is enabled. During receive mode, circuitry which is used to perform the receive function and provide a master clock is enabled. In transmit mode all the functions of the chip are enabled which are required to perform transmit, receive and provide master clock. There are two power saving modes of operation which the SA9024 can be put into, dependent on the status of the system. The intention of these different modes is to disable circuity that is not in use at the time in order to reduce power consumption. During sleep mode, only circuitry which is required to provide a master clock to SA9024 POWER MODE TRUTH TABLE Sleep Mode Enabled Crystal Oscillator yes no ✓ Receive Mode yes no ✓ Transmit Mode yes ✓ Phase detector and charge pump (transmit offset) ✓ ✓ ✓ VCO ✓ ✓ ✓ SSB Up-converter ✓ ✓ ✓ MCLK Buffer ✓ ✓ ✓ ✓ ✓ RCLK Buffer ✓ ÷M offset loop divider ✓ TXLO Buffer ✓ RXLO Buffer ✓ I/Q Modulator ✓ ✓ ✓ Variable Gain Amp. ✓ ✓ ✓ Control Logic ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ Main Divider ✓ ✓ ✓ Reference Divider ✓ ✓ ✓ Auxiliary Divider ✓ ✓ ✓ Main Phase Detector and charge pump ✓ ✓ ✓ Auxiliary Phase Detector and charge pump ✓ ✓ ✓ Lock Detect ✓ ✓ ✓ 1997 Aug 01 5 no Philips Semiconductors Objective specification 900 MHz transmit modulator and 1.3 GHz fractional–N synthesizer SA9024 ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER VALUE UNIT MIN. MAX. VCC Supply voltage -0.3 +4.5 V VIN Voltage applied to any other pin -0.3 VCC+0.3 V PN Power dissipation, TA = 25°C (still air) 980 mW TJMAX Operation junction temperature TBD °C PMAX Power input/output +10/+14 dBm IMAX DC current into any I/O pin -10 +10 mA TSTG Storage temperature –65 +150 °C Operating temperature -40 +85 °C To DC ELECTRICAL CHARACTERISTICS VCC = +3.75 V; TA = 25°C; unless otherwise stated. SYMBO L VCC ICC PARAMETER LIMITS TEST CONDITIONS Power supply range Supply y current MIN TYP MAX 3.6 3.75 3.9 Sleep mode 2 Standby mode 17 Operating: full power analog 95 UNITS V mA Operating: full power digital I/I Q/Q DUAL1 52 In-phase differential input quiescent VCC /2 V Quadrature phase differential input quiescent VCC /2 V VIL Clock, Data, Strobe, TXEN Input logic low –0.3 0.3 × VCC VIH Clock, data, strobe, TXEN Input logic high 0.7 × VCC VCC+0.3 V TA Ambient temperature range +85 °C 04 0.4 V -40 +25 V Digital Outputs Lock VOL O Output voltage LOW IO = 2mA VOH Output voltage HIGH IO = -2mA VCC – 0.4 V Charge Pump Current Setting Resistor Input; RN, RIpeak RN External resistor to ground RIpeak External resistor to ground 6 75 7.5 24 k 4.7 k V VRN Regulated voltage RN = 7.5 k 1.23 VIpeak Regulated voltage Ripeak = 4.7 k 1.3 V PHSOUT programming Ripeak = 4.7 k 0.26 mA PHSgain PHSOUT gain Ripeak = 4.7 k 24xIpeak mA K PD phase gain Transmit offset PLL in phase lock 4.33 mA/rad Ipeak Charge Pump Outputs (including fractional compensation pump, not PHS) RN = 7.5 k IOPH O IMATCH Charge g pump output current error versus expected current. Sink to source current matching Current output variation versus VPHX Charge pump off, leakage current VPH –15 15 15 % % VPHX = VCC/2 –5 5 VPHX in compliance range –10 10 % VPHX = VCC/2 –10 10 nA 0.7 VCC – 0.8 V –15 15 15 % –10 10 % Charge pump voltage compliance3 1 Charge Pump Outputs (only PHS) Ripeak = 4.7 k IOPH O IMATCH Charge g pump output current error versus expected current. Sink to source current matching 1997 Aug 01 VPHS = VCC/2 6 Philips Semiconductors Objective specification 900 MHz transmit modulator and 1.3 GHz fractional–N synthesizer Current output variation versus VPH VPH VPHS in compliance range Charge pump voltage compliance SA9024 –25 25 % 0.5 VCC–0.5 V AC ELECTRICAL CHARACTERISTICS VCC = +3.75 V; TA = 25°C; unless otherwise stated. SYMBOL PARAMETER TEST CONDITIONS LIMITS MIN TYP MAX UNITS Modulator TXLO O 1/2 / Transmit LO input ((AC-coupled; 50Ω single-ended, 100Ω differential) Input power Frequency range -13 900 VCO tank differential inputs Frequency range 90 Maximum input frequency 180 VSWR TANK1/2 ÷M -10 1100 dBm MHz 180 MHz 2:1 PLL offset divider MHz XTAL1 Osc. transistor base Osc. frequency 10 40 MHz XTAL2 Osc. transistor emitter Osc. frequency 10 40 MHz XO Negative resistance RCLK, MCLK Reference buffer output Frequency range Output levels Harmonic content TXEN Transmit enable Q/Q I/I Baseband in-phase differential inputs TXRF TXRF operating range ZLOAD = 5kΩ| | 7 pF 10 0.7 Transmit enable Transmit disable Maximum frequency Diff. mod. level Diff. input impedance DC bias point 1.8 0.8 10.0 1.8 40 1.4 –10 MHz VP–P dBc Logic 2.55 MHz VP-P kΩ V 820 920 MHz 853 MHz +13.5 dBm DUAL output SE=1, TXEN=1 (with external matching) (50Ω) AMPS/DAMPS 820 Differential output, (DUALTX) open-collector, matched to 200Ω differential impedance Output level (avg. min., I and Q quad., 0dB VGA) Gain flatness +6.0 DUALTX DUALTX Linearity worst case intermod. products (0dB VGA OR +6 dBm, whichever is less, I & Q in-phase) DUALTX Carrier suppression (I & Q in quadrature) DUALTX Sideband suppression (I & Q in quadrature) Spurious output 1.0 TXEN = 1 TXEN = 0 DUALTX DUALTX –100 0.9 1.0 VCC/2 +10 1 dB 3rd-order 5th-order 7th-order -42 -55 -65 -30 -45 -53 VGA = 0dB VGA = -38dB -45 -33 -30 -45 -32 2 to 284 MHz -45 824 to 849 MHz -47 849 to 869 MHz -45 dBc dBc dBc dBc 869 to 894 MHz -104 dBm 894 to 8490 MHz -45 dBc TXLO -21 Upper Side Band –21 TXLO ±3 × TXOFFSET -36 Harmonics ≤ 10th -21 869 to 894 MHz -123 dBm/Hz DUALTX TXLO u up-conversion -conversion products roducts DUALTX Broad-band noise (0dB VGA or +6 dBm, whichever is less) DUALTX Adjacent channel noise power @ 30 kHz 95 -95 dBc/Hz DUALTX Alternate channel noise power @ 60 kHz –101 dBc/Hz 1997 Aug 01 7 dBc Philips Semiconductors Objective specification 900 MHz transmit modulator and 1.3 GHz fractional–N synthesizer SA9024 Synthesizer Main Divider fMMAX Input frequency range Input harmonics RXLO 1/2 Synthesizer LO input (AC-coupled; external shunt 50Ω single-ended, 100Ω differential) 800 1300 MHz No multi–clocking –10 dBc Input power –20 0 dBm 10 40 MHz Reference Divider fRMAX Input frequency RANGE Input harmonics No multi–clocking –10 dBc Auxiliary Divider fAMAX Input frequency RANGE Input harmonics VINA 10 No multi–clocking Input signal amplitude 500 MHz –10 dBc 0.200 VP-P Serial Interface fCLOCK Clock frequency tSU Set-up time: DATA to CLOCK, CLOCK to STROBE tH Hold time: CLOCK to DATA tSW Pulse width 10 30 ns 30 ns CLOCK 30 STROBE (B - D words) 30 A word MHz ns 1 ) tW f REF @ NREF 1. Transmit mode @ 33% duty cycle. 2. The relative output current variation is defined thus: ąąDIout/Iout=2x(I2–I1)/|(I2+I1)|; with V1=0.7V, V2=VCC–0.8V (see figure 3) 3. Power supply current measured with ƒRX = 2100.54 MHZ, ƒREF = 19.44 MHz, ƒINA= 109.92 MHz, main phase detector bias resistor = 7.5 kW. Main phase detector reference frequency = 240 kHz, auxiliary phase detector frequency = 240 kHz. 4. Maximum and minimum levels guaranteed by design and random testing for temperature range of –40 to +85°C. 5. Power is rated at I/Q input level of 0.9VPP. 1997 Aug 01 8 Philips Semiconductors Objective specification 900 MHz transmit modulator and 1.3 GHz fractional–N synthesizer SA9024 CURRENT I2 I1 V1 V2 VOLTAGE I2 I1 SR00602 Figure 3. 1997 Aug 01 Output Current Definition 9 Philips Semiconductors Objective specification 900 MHz transmit modulator and 1.3 GHz fractional–N synthesizer SA9024 Functional Description Main Channel Synthesizer & Auxiliary Synthesizer CLOCK SERIAL INPUT + PROGRAM LATCHES DATA STROBE FMOD PD1 FB NF NMAIN FB 3 16 1 INM1 FRACTIONAL MAIN DIVIDERS ACCUMULATOR INM2 RN FDAC 8 PD1 MAIN PHASE DETECTOR NORMAL OUTPUT CHARGE PUMP 2 FDAC PHP SM 8 2 PD1 + PD2 12 FDAC ÷2 REFERENCE DIVIDER INR SPEED-UP OUTPUT CHARGE PUMP MAIN REFERENCE SELECT NR ÷2 8 ÷2 INTEGRAL OUTPUT CHARGE PUMP SA AUXILIARY REFERENCE SELECT 2 RN PD2 AUXILIARY PHASE DETECTOR NAUX PD2 PHI 2 AUXILIARY OUTPUT CHARGE PUMP PHA 14 LOCK INA AUXILIARY DIVIDER SR01112 Figure 4. Synthesizer Block Diagram clocked into a shift register. When STROBE = H, the clock is disabled and the data in the shift register remains stable. Serial Programming Input The serial input is a 3-wire input (CLOCK, DATA, STROBE) used to program all counter ratios, DACs, selection and enable bits. The programming data is structured into 24-bit words; each word includes 2 or 3 address bits. Figure [5] shows the timing diagram of the serial input. When STROBE = L, the clock driver is enabled and on positive edges of the CLOCK, the signal on DATA input is 1997 Aug 01 Depending on the 2 or 3 address bits, data is latched into different working or temporary registers. In order to fully program the synthesizer, 3 words must be sent: A, B and C. The D word programs all other functions within the SA9024. Those functions are 10 Philips Semiconductors Objective specification 900 MHz transmit modulator and 1.3 GHz fractional–N synthesizer power control, ÷M (offset loop), SE (Tx offset loop synthesizer enable), DUAL mode, Sleep Mode 1 and Sleep Mode 2. SA9024 reprogramming the main divider. The synchronization pulse is generated by the main divider when it has reached its terminal count, at which time a main divider output pulse is also sent to the main phase detector. This disables the loading of the A word each main divider cycle during maximum of (NREF / ƒREF) seconds. Therefore, to be sure that the A word will be correctly loaded, the STROBE signal must be high for at least (NREF / ƒREF) seconds. When programming the A word, the main charge pumps on output PHP and PHI are set into the speed–up mode as soon as the A word is latched into the working registers and remain so as long as STROBE is held high. The data for FDAC is stored by the B word into a temporary register. When the A word is loaded, the data in this temporary register is loaded together with the A word into the work registers to avoid false temporary main synthesizer output caused by changes in fractional compensation. The A word contains new data for the main divider. The A word is loaded into the working registers only when a main divider synchronization signal is active to avoid phase jumps when VALID DATA CHANGE DATA D0 tSU D21 D1 D23 D0 LAST CLOCK tH FIRST CLOCK CLOCK tSU tSU CLOCK DISABLED STORE DATA STROBE CLOCK ENABLED–SHIFT IN DATA SR01447 Figure 5. 1997 Aug 01 Serial Input Timing Sequence 11 Philips Semiconductors Objective specification 900 MHz transmit modulator and 1.3 GHz fractional–N synthesizer SA9024 Table 1. Function Table Symbol Bits FMOD 1 Fractional-N modulus selection flag: ‘0’ = modulo 8 ‘1’ = modulo 5 NF 3 Fractional-N increment NMAIN 16 Main divider ratio; 512 to 65,535 allowed NREF 10 Reference divider ratio; 4 to 1,023 allowed, RSM, RSA = “0 0” RSM 2 Reference select for main phase detector RSA 2 Reference select for auxiliary phase detector FDAC 8 Fractional compensation charge pump current DAC NAUX 14 Auxiliary divider ratio; 128 to 16,384 allowed CP 2 Charge pump current ratio select (see table 1) LD 2 Lock detect output select (see table 2) 1 PD1 = 0 for power down; shuts off power to main divider and main chargepumps, anded with PD2 to turn off ref. divider. PD1 2. On the rising edge of the strobe and with the address decoder output = 1, the contents of the input shift register are transferred to the working registers. The strobe rising edge comes one half clock period after the clock edge on which the MSB of a word is shifted in. Function 3. The PC bits are used for the power control function. Eight (8) bits of data allows for appropriate resolution of the power control. 00000000 = 0 dB: 11111111 = –45.9 dB (= 255 0.18). 4. The M bits are used to program the ÷M counter for integer values between 6 and 9. 00 = 6, 01 = 7, 10 = 8, 11 = 9. 5. The TM bit is used to put the SA9024 into DUAL mode operation. In DUAL mode (TM = 0). 6. The AD bit allows a reduction in the linearity of the DUAL output driver while in AMPS mode. 7. The SM1 bit is used to shut down the TXLO buffers. SM1 = 1, buffers on; SM1 = 0, buffers off. 8. The SM2 bit is used to shut down the RCLK buffer. SM2 = 1, buffer on; SM2 = 0, buffer off. 9. The SE bit turns on and off the offset loop synthesizer circuits. SE = 1, synthesizer on; SE = 0, synthesizer off. PD2 1 PD2 = 0 for power down; shuts off power to auxiliary divider, and auxiliary charge pumps; anded with PD1 to turn off ref. divider. PC 8 Power control (see note 3) M 2 ÷M, M = 6, 7, 8, 9 (see note 4) SE 1 Transmit offset synthesizer on/off TM 1 Transmit mode: ‘0’ = DUAL 00 Main, auxiliary and offset lock condition AD 1 Mode control, 1 = digital; 0 = analog 01 Main and auxiliary lock condition SM1 1 Sleep mode 1 10 Main lock detect condition SM2 1 Sleep mode 2 11 Auxiliary lock condition 10. The LOCK bits determine what signal is present on the LOCK pin as follows: Table 2. Lock Detect Output Select* LOCK 1. Data bits are shifted in on the the leading clock edge, with the least significant bit (LSB) first and the most significant bit (MSB) last. 1997 Aug 01 LOCK Pin Function *When a section is in power down mode, the lock indicator for that section is high. 12 Philips Semiconductors Objective specification 900 MHz transmit modulator and 1.3 GHz fractional–N synthesizer SA9024 TXEN CLOCK TEMPORARY REGISTER VCC DATA R Q WORKING REGISTER CLK D (2) Q SE R D R Q SYNEN CLK Q (1) (2) D STROBE Q CLK Q SR01449 Figure 6. Transmit Offset Synthesizer Reset Circuit The address decoder for program word ‘D’ ANDed together with the strobe is used to load the contents of the temporary register into the working registers. D flip-flop (3) is used to prevent multiple strobe and address pulses in the event the address decoder output toggles on garbage bits during the time the strobe remains in a ‘1’ state. In Figure 6, the falling edge of the strobe and address, inverted, toggles the Q output of flip-flop (1) to a ‘1’ state, enabling the phase detector, VCO, divide by M, TXIF buffer and SSB up-converter. Approximately 80µs after the synthesizer is locked, the TXEN signal (enabled = 1) turns on the modulator and variable gain amplifier. The rising edge of TXEN has no effect on SYNEN, however, the falling (rising inverted) edge toggles the Q output of D flip-flop (2) to a ‘0’ state. This disables the synthesizer, modulator and variable gain amplifier. To insure that slow edges on TXEN do not cause improper operation, the TXEN is a Schmitt trigger design. 1997 Aug 01 The temporary register is common to the transmit offset synthesizer, main channel synthesizer and auxiliary synthesizer. 13 Philips Semiconductors Objective specification 900 MHz transmit modulator and 1.3 GHz fractional–N synthesizer SA9024 TXen STROBE SYNen 80S 6.67mS SR01538 Figure 7. 1997 Aug 01 Transmit Offset Synthesizer Timing Diagram 14 Philips Semiconductors Objective specification 900 MHz transmit modulator and 1.3 GHz fractional–N synthesizer SA9024 Data format Format of programmed data LAST IN MSB p23 p22 SERIAL PROGRAMMING FORMAT p21 p20 ../.. FIRST IN LSB ../.. p1 p0 A word, length 24 bits Last in MSB Address 0 0 fmod Fractional–N Fmod NF2 NF1 0 0 1 Default: First IN LSB Main Divider ratio– Nmain Spare NF0 N15 N14 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0 sk1 sk2 0 0 0 1 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 A word select Fixed to 00. Fractional Modulus select FM 0=modulo 8, 1=modulo 5. Fractional–N Increment NF2..0 Fractional N Increment values 000 to 111. N–Divider N0..N15, Main divider values 512 to 65535 allowed for divider ratio. B word, length 24 bits ADDRESS 0 REFERENCE DIVIDER NREF 1 Default: RSM RSA FRACTIONAL COMPENSATION DAC R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 RSM 1 RSM 0 RSA 1 RSA 0 Fdac 7 Fdac 6 Fdac 5 Fdac 4 Fdac 3 Fdac 2 Fdac 1 Fdac 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 x x x x x x x x B word select Fixed to 01 R–Divider R0..R9, Reference divider values 4 to 1023 allowed for divider ration. Charge pump current Ratio Main comparison select Aux comparison select Fractional Compensation CP1, CP0: Charge pump current ratio, see table of charge pump currents. RSM Comparison divider select for main phase detector. RSA Comparison divider select for auxiliary phase detector. Fdac7..0, Fractional compensation charge pump current DAC, values 0 to 255. FDAC = 77 for best op MOD8. C word, length 24 bits ADDRESS 1 0 Default AUXILIARY DIVIDER NAUX LOCK PD SPARE A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 CP1 CP0 LD1 LD0 PD1 PD2 PD3 LOD 0 0 0 0 0 1 1 1 0 0 1 0 1 0 1 1 0 0 TXEN TXEN 0 0 C word select A–Divider Charge pump current Ratio Lock detect output Power down 1997 Aug 01 CP A13 Fixed to 10 A0..A13, Auxiliary divider values 128 to 16384 allowed for divider ratio. CP1, CP0: Charge pump current ratio, see table fo charge pump currents. LD1 LD0 0 0 Combined main, aux. & offset loop lock detect signal present at the LOCK pin. 0 1 Combined main and aux. lock detect signal present at the LOCK pin. 1 0 Main lock detect signal present at the LOCK pin. 1 1 Auxiliary loop lock detect signal present at the LOCK pin. When a section is in power down mode, the lock indicator for that section is high. PD1=1: power to N–divider, reference divider, main charge pumps, PD1=0 to power down. PD2=1: power to Aux divider, reference divider, Aux charge pump, PD2=0 to power down. 15 Philips Semiconductors Objective specification 900 MHz transmit modulator and 1.3 GHz fractional–N synthesizer SA9024 Table 3. Main and auxiliary chargepump currents CP1 CP0 IPHA IPHP IPHP–SU IPHI_SU 0 0 1.5xlset 3xIset 15xlset 36xlset 0 1 0.5xlset 1xlset 5xlset 12xlset 1 0 1.5xlset 3xlset 15xlset 0 1 1 0.5xlset 1xlset 5xlset 0 NOTES 1. ISET = Vset/RN; bias current for charge pumps. 2. CP1 is used to disable the PHI pump. 3. Iphp_su is the total current out of PHP in speedup mode. D word, length 24 bits Address 1 1 Power Control 0 Default: PC7 PC6 x x D0 word select Output Power Control M Divider Offset loop power down DUAL mode select AMPS/DAMPS mode select TX buffers power down Test: pa_current:pai 1997 Aug 01 PC5 PC4 PC3 PC2 PC1 PC0 x x x x x x M divider SE TM AD M1 M0 SE TM AD 0 0 0 0 0 Sleep Mode Test pa_current SM1 SM2 pai5 pai4 pai3 pai2 pai1 0 0 0 0 0 0 0 Fixed to 110. PC7(msb)...PC0(Isb) Provides output power attenuation for DUAL mode amplifier outputs in 0.18 dB steps, Fx = 45.9 dB. 00 = 6, 01 = 7, 10 = 8, 11 = 9 SE Offset loop synthesizer power down, SE = 1 power on, SE = 0 power down (sleep mode). TM = 0 DUALmode AD = 1 DAMPS mode. AD = 0 AMPs mode SM1 TX Local oscillator buffers power down. SM1 = 1 power on, SM1 = 0 to power down. SM2 RCLK buffer power down. SM2 = 1 power on, SM2 = 0 to power down. TX test bits for controlling the current in the power amp. Should be 0 during normal operation. 16 pai0 0 Philips Semiconductors Objective specification 900 MHz transmit modulator and 1.3 GHz fractional–N synthesizer SA9024 the digital portion of the system is enabled. During receive mode, circuitry which is used to perform the receive function and provide a master clock is enabled. In transmit mode all the functions of the circuit are enabled which are required to perform transmit, receive and provide master clock. When the circuit is powered for the first time, it is in DUAL MODE SLEEP. MODES OF OPERATION There are two power saving modes of operation which the circuit can be put into, dependent on the status of the system. The intention of these different modes is to disable circuitry that is not in use at the time in order to reduce power consumption. During sleep mode, only circuitry which is required to provide a master clock to Mode Programming Mode Dual Mode AMPS Mode Setting and BlockStatus (X = ON) Sleep RX TX TXEN 0 0 1 PD1 0 1 1 Logic PD2 0 1 1 SE–>SYNen 0 0 1 TM 0 0 0 SM1 0 0 1 SM2 0 1 1 Main loop, Ndivider, RXLO buffer X X PD1 Aux loop, Adivider X X PD2 Rdivider X X PD1 .OR. PD2 X SE (+delay) See SE–>SYNEN diagram X X SM2 X Offset VCO, Mdivider RCL buffer MCL buffer, reference input X 1 (always ON) DUALTX PA X X (.not. TM) .and. TXEN .and. SM1 TXLO buffer, SSB up–converter X SM1 X TXEN .AND. SM1 X 1 (always ON) I/Q MODULATOR, VGA Control Logic X X Main Divider Auxiliary Divider The input signal on RXLO is amplified to a logic level by a balanced input comparator giving a common mode rejection. This input stage is enabled by serial control bit PD1 = 1. Disabling means that all currents in the comparator are switched off. The main divider is built up to be a 16-bit counter. The input signal on INA is amplified to logic level by a single-ended input buffer, which accepts low level AC-coupled input signals. This input stage is enabled if the serial control bit PD2 = ‘1’. Disabling means that all currents in the buffer and prescaler are switched off. The auxiliary divider is programmed with 14 bits and has continuous integer division ratios over the range of 128 to 16,384. The loading of the work registers FMOD, NF and NMAIN is synchronized with the state of the main counter to avoid extra phase disturbance when switching over to another main divider ratio as is explained in the Serial Programming Input chapter. Reference Divider (Figure 8) The input can be driven by a differential crystal input or an external TCXO. This input stage is enabled by the OR function of the serial input bits PD1 and PD2. Disabling means that all currents are switched off. The reference divider consists of a programmable divide by NREF (NREF = 4 to 1,023) followed by a 3-bit binary counter. The 2 bit SM determines which of the four output pulses is selected as the main phase detector signal. To obtain the best time spacing for the main and auxiliary reference signals, a different output will be used for the auxiliary phase detector, reducing the possibility of unwanted interactions. At the completion of a main divider cycle, a main divider output pulse is generated which will drive the main phase comparator. Also, the fractional accumulator is incremented with NF. The accumulator works modulo Q. Q is preset by the serial control bit FMOD to 8 when FMOD = ‘0’. Each time the accumulator overflows, the total divide ratio will be NMAIN + 1 for the next cycle. The mean division ratio over Q main divider cycles will then be: NQ + NMAIN ) NF Q Synchronization is provided to avoid a random phase on the phase detector upon the loading of a new ratio and when powering up the loop. 1997 Aug 01 17 Philips Semiconductors Objective specification 900 MHz transmit modulator and 1.3 GHz fractional–N synthesizer SA9024 MAIN SELECT RSM = “00” RSM = “01” RSM = “10” RSM = “11” REFERENCE INPUT DIVIDE BY NREF /2 /2 /2 RSA = “11” RSA = “10” RSA = “01” RSA = “00” AUXILIARY SELECT Figure 8. SR01440 Reference Variable Divider Phase Detectors (Figure 9) Current Settings The auxiliary and main phase detectors each consist of a 2 D-type flip-flop phase and frequency detector. Each flip-flop is set by the negative edge of the divider terminal count output pulse. The reset inputs are activated after a delay when both flip-flops have been set. This avoids non-linearity or dead-band around zero phase error. The flip-flops drive on-chip charge pumps. A pull-up current from the charge pump indicates the VCO frequency shall be increased while a pull-down pulse indicates the VCO frequency shall be decreased. The IC has two current setting pins, RN and IPEAK. The active charge pump currents and the fractional compensation currents are linearly dependent on the current in the current setting pins. This current, ISET, is set by an external resistor connected between the current setting pin and VSS. 1997 Aug 01 Auxiliary Output Charge Pumps The auxiliary charge pumps on pin PHA are driven by the auxiliary phase detector and the current value is determined by the external resistor attached to pin RN. 18 Philips Semiconductors Objective specification 900 MHz transmit modulator and 1.3 GHz fractional–N synthesizer SA9024 VDDA “1” INR REF DIVIDER P–TYPE CHARGE PUMP P D Q CLK R R τ “1” R D AUX/MAIN DIVIDER PH N–TYPE CHARGE PUMP CLK Q X N GND VSSA INR R X P N IPH SR01451 Figure 9. Phase Detector Structure With Timing on the main charge pump current and its level relative to the main charge pumps is set by an 8-bit programmable DAC. The timing for the fractional compensation is derived from the main divider. The current level based on the value of FRD, FDAC and ISET. Figure 10 shows the waveforms (not to scale) for a typical base. Main Output Charge Pumps and Fractional Compensation Currents The main charge pumps on pin PHP and PHI are driven by the main phase detector. The current value is determined by the current at pin RN. The fractional compensation current is linearly dependent 1997 Aug 01 19 Philips Semiconductors Objective specification 900 MHz transmit modulator and 1.3 GHz fractional–N synthesizer SA9024 REFERENCE R MAIN M VCO CYCLES N N N+1 N 2 4 1 N+1 DETECTOR OUTPUT 3 0 ACCUMULATOR CONTENTS FRACTIONAL COMPENSATION CURRENT PULSE WIDTH MODULATION mA OUTPUT ON PHP, PHI µA PULSE LEVEL MODULATION SR01454 Figure 10. Waveforms for NF = 2; Fraction = 0.4 when the relative counter is disabled (PD1 = ‘0’ or PD2 = ‘0’) for the main or auxiliary counter, respectively. Figure 10 shows that for a proper fractional compensation, the area of the fractional compensation current pulse must be equal to the area of the charge pump ripple output. Functional Description of Offset Loop, Modulator and Power Control The fractional compensation current is derived from the main charge pump in that it will follow all the current scaling through external resistor setting, programming or speedup operation. Transmit Offset Synthesizer The transmit offset phase locked loop portion of the SA9024 design consists of the following functional blocks: reference oscillator, limiters, phase detector, ÷M, IF VCO and passive loop filter. Harmonic contents of this signal are attenuated by an LP filter. The output of the IF VCO is also divided by N and compared with the reference oscillator in the phase detector. For a given pump, |comp + |pump x Fdac x FRD 128 5 x 128 Where: Icomp is the compensation current, Ipump is the pump current, Fdac is the fractional DAC value and FRD is the fractional accumulator value. Reference Oscillator This Oscillator is used to generate the reference frequency together with an external crystal and varicap. The output is internally routed to three buffers and a phase comparator. It is possible to run the oscillator as an amplifier from an external reference signal (TCXO). The theoretical value for Fdac would then be: 128 for Fmod = 1 (modulo 5) and 80 for Fmod = 0 (modulo 8). When the serial input A word is loaded, the output circuits are in the “speedup mode” as long as the STROBE is H, otherwise the “normal mode” is active. Phase Detector and Charge Pump The phase comparator is used to compare the output of the divider with the reference. It provides an output proportional to the phase difference between the divided down VCO and the reference. This output is then filtered and used as the control voltage input to the VCO. The phase detector is a Gilbert multiplier cell type, having a linear output from 0 to π (π/2 ±π/2), followed by a charge pump. The charge pump peak output current is programmable to 6.4mA via the use of an external resistor. Lock Detect The output LOCK maintains a logic ‘1’ when the auxiliary phase detector ANDed with the main phase detector ANDed with Offset Phase Detector indicates a lock condition. During the Standby mode of operation when the offset loop is unlocked, (SYNEN = low – see figure 6), the offset phase detector lock output is forced to an on (locked) state so that the lock detect will give an indication of receiver lock. The lock condition for the main and auxiliary synthesizers is defined as a phase difference of less than "1 cycle on the reference input INR. The LOCK condition is also fulfilled 1997 Aug 01 A preliminary design analysis has been performed with the following loop parameters: 20 Philips Semiconductors Objective specification 900 MHz transmit modulator and 1.3 GHz fractional–N synthesizer SA9024 quadrature phase shift networks and a low pass filter. The SSB up-converter is used to reject the unwanted upper sideband that would normally occur during the up-conversion process. A lock detect signal is provided and ANDed together with lock detect signals from both the main channel synthesizer and auxiliary synthesizer. While in standby mode, the lock detect signal will be forced to a valid lock state so that the lock detect signal will indicate when the main and auxiliary phase detectors have achieved phase lock. I/Q Modulator The quadrature modulator is an active Gilbert cell multiplier (matched pair) with cross coupled outputs. These outputs are then provided to the variable gain amplifier. When the in-phase input I = cos (ωt) and the quadrature-phase input Q = sin (ωt) (i.e., Q lags I by 90°), the resulting output should be upper single sideband. Divide by M The ÷M is a 2-bit programmable divider which can be configured for ney integer divide from 6 to 9. The divider is used to convert the VCO output down to the reference frequency before feeding it into the phase comparator. Variable Gain Amplifiers The variable gain amplifiers are used to control the output level of the device, with a power control range of 45.9dB. The output stages are differential, matched from 200Ω to 50Ω. VCO This oscillator is used to generate the transmit IF frequency between 90MHz and 180MHz. The VCO tank is configured using a parallel inductor tuning varactor diode. DC blocking capacitors are used to isolate the varactor control voltage from the VCO tank DC bias voltages. Power Control The power control range should be greater than or equal to 45.9dB, having a monotonically decreasing slope, with 0dB = +11.5 dBm nominal. Eight bits are available for power control programming. The top 6 bits (PC7 to PC2) provide coarse attenuation with .6dB step size accuracy. The bottom 2 bits provide fine attenuation with .18 dB step size accuracy. SSB Up-converter and TXIF Buffer The TXIF buffer provides isolation between the SSB Up-converter and the VCO output. The Single Sideband Up-converter (SSB) is an active Gilbert cell multiplier (matched pair), combined with two +11.5 TOP 12 dB FINE STEP ACURACY POWER OUT (dBm nom) –3 MAXIMUM ACCUMULATED ERROR (NOT TO SCALE) –15 –26 BOTTOM 25 dB COARSE STEP ACCURACY –28 0 12 24 38 45.9 VGA SETTING (dB) SR01453 Figure 11. Power Control circuitry which is always on, while the third buffer (RCLK) is used as a clock for external digital circuitry which is not used in sleep mode. Oscillator Buffers There are three buffers for the reference signal, two of which are used to provide external reference signals. The internal reference signal is used for the main and auxiliary synthesizer reference. The second buffer (MCLK) is used as a master clock for external digital 1997 Aug 01 LO Buffers The LO buffers are used to provide isolation for the VCO and between the transmitter up-converter and channel synthesizer. 21 Philips Semiconductors Objective specification 900 MHz transmit modulator and 1.3 GHz fractional–N synthesizer LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm 1997 Aug 01 22 SA9024 SOT313-2 Philips Semiconductors Objective specification 900 MHz transmit modulator and 1.3 GHz fractional–N synthesizer SA9024 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Philips Semiconductors and Philips Electronics North America Corporation register eligible circuits under the Semiconductor Chip Protection Act. Copyright Philips Electronics North America Corporation 1997 All rights reserved. Printed in U.S.A. print code Document order number: 1997 Aug 01 23 Date of release: 05-96