19-3889; Rev 1; 1/06 Stand-Alone, 4.5-/3.5-Digit Panel Meters with 4–20mA Output Features The MAX1365/MAX1367 low-power, 4.5- and 3.5-digit, panel meters feature an integrated sigma-delta analogto-digital converter (ADC), LED display drivers, voltage digital-to-analog converter (DAC), and a 4–20mA (or 0 to 16mA) current driver. The MAX1365/MAX1367’s analog input voltage range is programmable to either ±2V or ±200mV. The MAX1367 drives a 3.5-digit (±1999 count) display and the MAX1365 drives a 4.5-digit (±19,999 count) display. The ADC output directly drives the LED display as well as the voltage DAC, which in turn drives the 4–20mA (or 0 to 16mA) current-loop output. In normal operation, the 0 to 16mA/4–20mA currentloop output follows the ±2V or ±200mV analog input to drive remote panel-meter displays, data loggers, and other industrial controllers. For added flexibility, the MAX1365/MAX1367 allow direct access to the DAC output and the V/I converter input. ♦ Stand-Alone, Digital Panel Meter 20-Bit Sigma-Delta ADC 4.5-Digit Resolution (±19,999 Count, MAX1365) 3.5-Digit Resolution (±1999 Count, MAX1367) No Integrating/Autozeroing Capacitors 100MΩ Input Impedance ±200mV or ±2.000V Input Range The sigma-delta ADC does not require external precision integrating capacitors, autozero capacitors, crystal oscillators, charge pumps, or other circuitry commonly required in dual-slope ADC panel-meter circuits. Onchip analog input and reference buffers allow direct interface with high-impedance signal sources. Excellent common-mode rejection and digital filtering provide greater than 100dB rejection of simultaneous 50Hz and 60Hz line noise. Other features include data hold, peak detection, and overrange/underrange detection. ♦ LED Display Common-Cathode 7-Segment LED Driver Programmable LED Current (0 to 20mA) 2.5Hz Update Rate ♦ Output DAC and Current Driver ±15-Bit DAC with 14-Bit Linear V/I Converter Selectable 0 to 16mA or 4–20mA Current Output Unipolar/Bipolar Modes ±50µA Zero Scale, ±40ppmFS/°C (typ) ±0.5% Gain Error, ±25ppmFS/°C (typ) Separate 7V to 30V Supply for Current-Loop Output ♦ 2.7V to 5.25V ADC/DAC Supply ♦ 4.75V to 5.25V V/I Converter Supply ♦ Internal 2.048V Reference or External Reference ♦ 48-Pin, 7mm x 7mm TQFP Package The MAX1365/MAX1367 require a 2.7V to 5.25V supply, a 4.75V to 5.25V V/I supply, and a 7V to 30V loop supply. They are available in a space-saving (7mm x 7mm), 48-pin TQFP package and operate over the extended (-40°C to +85°C) temperature range. Applications Automated Test Equipment Data-Acquisition Systems Ordering Information TEMP RANGE PIN-PACKAGE MAX1365ECM PART -40°C to +85°C 48 TQFP MAX1367ECM -40°C to +85°C 48 TQFP Digital Multimeters Digital Panel Meters Selector Guide Digital Voltmeters Industrial Process Control PART RESOLUTION (DIGITS) PKG CODE MAX1365ECM 4.5 C48-6 MAX1367ECM 3.5 C48-6 Pin Configuration appears at end of datasheet. Typical Operating Circuits appear at end of datasheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX1365/MAX1367 General Description MAX1365/MAX1367 Stand-Alone, 4.5-/3.5-Digit Panel Meters with 4–20mA Output ABSOLUTE MAXIMUM RATINGS AVDD, DVDD ....................................................................-0.3V to +6.0V AIN+, AIN-, REF+, REF-.........................VNEGV to (AVDD + 0.3V) REG_FORCE, CMP, DAC_VDD, DACVOUT, CONV_IN, 4-20OUT .............................-0.3V to (AVDD + 0.3V) EN_BPM, EN_I, REFSELE, DACDATA_SEL, INTREF, RANGE, DPSET1, DPSET2, HOLD, PEAK, DPON, CS_DAC...............................................-0.3V to (DVDD + 0.3V) NEGV .......................................................-2.6V to (AVDD + 0.3V) LED_EN....................................................-0.3V to (DVDD + 0.3V) SET...........................................................-0.3V to (AVDD + 0.3V) REG_AMP, REG_VDD ...........................................-0.3V to +6.0V LEDV......................................................................-0.3V to +6.0V LEDG .....................................................................-0.3V to +0.3V GND_DAC .............................................................-0.3V to +0.3V GND_V/I.................................................................-0.3V to +0.3V SEG_ to LEDG.........................................-0.3V to (VLEDV + 0.3V) DIG_ to LEDG..........................................-0.3V to (VLEDV + 0.3V) REF_DAC .................................................-0.3V to (AVDD + 0.3V) DIG_ Sink Current .............................................................300mA DIG_ Source Current...........................................................50mA SEG_ Sink Current . ............................................................50mA SEG_ Source Current..........................................................50mA Maximum Current Input into Any Other Pin . ......................50mA Continuous Power Dissipation (TA = +70°C) 48-Pin TQFP (derate 22.7mW/°C above +70°C).....1818.2mW Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-60°C to +150°C Junction Temperature ......................................................+150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (AVDD = DVDD = DAC_VDD = +2.7V to +5.25V, GND = 0, VLEDV = +2.7V to +5.25V, LEDG = 0, VREF+ - VREF- = 2.048V (external reference), 4-20OUT = 7V, VREG_AMP = +5.0V, CREF+ = 0.1µF, REF- = GND, CNEGV = 0.1µF. Internal clock mode, unless otherwise noted. All specifications are at TA = TMIN to TMAX. Typical values are at TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ADC ACCURACY Noise-Free Resolution Integral Nonlinearity (Note 1) INL MAX1365 -19,999 +19,999 MAX1367 -1999 +1999 2.000V range ±1 200mV range ±1 Range Change Ratio (VAIN+ - VAIN- = 0.100V) on 200mV range; (VAIN+ - VAIN- = 0.100V) on 2.0V range Rollover Error VAIN+ - VAIN- = full scale Output Noise Offset Error (Zero Input Reading) Counts 10:1 Ratio ±1 Counts 10 VAIN+ - VAIN- = 0 (Note 2) Gain Error (Note 3) Offset Drift (Zero Reading Drift) VAIN+ - VAIN- = 0 (Note 4) -0 -0.5 Gain Drift Counts µVP-P +0 Counts +0.5 %FSR 0.1 µV/°C ±1 ppm/°C 5 Hz INPUT CONVERSION RATE Update Rate ANALOG INPUTS (AIN+, AIN-) (bypass to GND with 0.1µF or greater capacitors) AIN Input Voltage Range (Note 5) RANGE = GND -2.0 +2.0 RANGE = DVDD -0.2 +0.2 -2.2 +2.2 AIN Absolute Input Voltage Range to GND Normal-Mode 50Hz and 60Hz Rejection (Simultaneously) 2 50Hz and 60Hz ±2% 100 _______________________________________________________________________________________ V V dB Stand-Alone, 4.5-/3.5-Digit Panel Meters with 4–20mA Output (AVDD = DVDD = DAC_VDD = +2.7V to +5.25V, GND = 0, VLEDV = +2.7V to +5.25V, LEDG = 0, VREF+ - VREF- = 2.048V (external reference), 4-20OUT = 7V, VREG_AMP = +5.0V, CREF+ = 0.1µF, REF- = GND, CNEGV = 0.1µF. Internal clock mode, unless otherwise noted. All specifications are at TA = TMIN to TMAX. Typical values are at TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Common-Mode 50Hz and 60Hz Rejection (Simultaneously) CMR For 50Hz and 60Hz ±2%, RSOURCE < 10kΩ 150 dB Common-Mode Rejection CMR At DC 100 dB Input Leakage Current 10 nA Input Capacitance 10 pF Average Dynamic Input Current -20 +20 nA 2.089 V INTERNAL REFERENCE (REF- = GND, INTREF = DVDD) REF Input Voltage VREF 2.007 REF Output Short-Circuit Current REF Output Temperature Coefficient TCVREF Load Regulation ISOURCE = 0 to 300µA, ISINK = 0 to 30µA Line Regulation Noise Voltage 2.048 1 mA 40 ppm/°C 6 µV/µA 50 µV/V 0.1Hz to 10Hz 25 10Hz to 10kHz 400 µVP-P EXTERNAL REFERENCE (INTREF = GND) REF Input Voltage Differential (VREF+ - VREF-) Absolute REF+, REF- Input Voltage to GND (VREF+ Must Be Greater Than VREF-) 2.048 -2.2 Normal-Mode 50Hz and 60Hz Rejection (Simultaneously) V +2.2 V 50Hz and 60Hz ±2% 100 dB Common-Mode 50Hz and 60Hz Rejection (Simultaneously) CMR For 50Hz and 60Hz ±2%, RSOURCE < 10kΩ 150 dB Common-Mode Rejection CMR At DC 100 dB Input Leakage Current 10 nA Input Capacitance 10 Average Dynamic Input Current (Note 6) -20 pF +20 nA -2.30 V +10 µA 0.3 x DVDD V CHARGE PUMP Output Voltage NEGV CNEGV = 0.1µF to GND -2.60 -2.42 DIGITAL INPUTS (INTREF, RANGE, PEAK, HOLD, DPSET1, DPSET2) Input Current IIN Input Low Voltage VINL Input High Voltage VINH Input Hysteresis VHYS VIN = 0 or DVDD -10 0.7 x DVDD DVDD = 3V V 200 mV _______________________________________________________________________________________ 3 MAX1365/MAX1367 ELECTRICAL CHARACTERISTICS (continued) MAX1365/MAX1367 Stand-Alone, 4.5-/3.5-Digit Panel Meters with 4–20mA Output ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = DAC_VDD = +2.7V to +5.25V, GND = 0, VLEDV = +2.7V to +5.25V, LEDG = 0, VREF+ - VREF- = 2.048V (external reference), 4-20OUT = 7V, VREG_AMP = +5.0V, CREF+ = 0.1µF, REF- = GND, CNEGV = 0.1µF. Internal clock mode, unless otherwise noted. All specifications are at TA = TMIN to TMAX. Typical values are at TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 5.25 V ADC POWER SUPPLY (Note 7) AVDD Voltage AVDD DVDD Voltage DVDD Power-Supply Rejection AVDD PSRA (Note 8) 80 dB Power-Supply Rejection DVDD PSRD (Note 8) 100 dB AVDD Current (Note 9) IAVDD DVDD Current (Note 9) IDVDD 2.70 2.70 5.25 640 Standby mode 305 DVDD = +5.25V 320 DVDD = +3.3V 180 Standby mode 20 V µA µA DAC POWER SUPPLY DAC Supply Voltage VDAC_VDD 2.70 DAC Supply Current 5.25 V 0.10 0.21 mA 5.25 V 0.19 0.30 mA 27.4 mA LINEAR REGULATOR AND V/I CONVERTER POWER REQUIREMENTS REG_AMP Supply Voltage VREG_AMP 4.75 REG_AMP Supply Current REG_VDD Supply Voltage VREG_VDD REG_VDD Supply Current 5.20 Includes 20mA programmed current 25.2 V LED DRIVERS LED Supply Voltage VLEDV LED Shutdown Supply Current ISHDN LED Supply Current ILEDV Display Scan Rate fOSC Segment Current Slew Rate 2.70 176 MAX1365 512 MAX1367 640 5.25 V 10 µA 180 mA Hz ISEG/∆t 25 DIG_ Voltage Low VDIG 0.178 0.300 V Segment-Drive Source-Current Matching ∆ISEG 3 ±12 % Segment-Drive Source Current ISEG 21.5 25.5 mA LED Drivers Bias Current Interdigit Blanking Time 4 VLEDV - VSEG = 0.6V, RSET = 25kΩ From AVDD 15.0 mA/µs 120 µA 4 µs _______________________________________________________________________________________ Stand-Alone, 4.5-/3.5-Digit Panel Meters with 4–20mA Output (AVDD = DVDD = DAC_VDD = +2.7V to +5.25V, GND = 0, VLEDV = +2.7V to +5.25V, LEDG = 0, VREF+ - VREF- = 2.048V (external reference), 4-20OUT = 7V, VREG_AMP = +5.0V, CREF+ = 0.1µF, REF- = GND, CNEGV = 0.1µF. Internal clock mode, unless otherwise noted. All specifications are at TA = TMIN to TMAX. Typical values are at TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DAC OUTPUT ACCURACY Zero-Scale Error 4–20mA or 0 to 16mA mode, TA = +25°C ±50 ±40 Zero-Scale Error Tempco Gain Error 4–20mA or 0 to 16mA mode, TA = +25°C ±0.5 Gain-Error Tempco ±25 Span Linearity ±2 Power-Supply Rejection PSR VEXT = 7V to 30V µA ppmFS/°C %FS ppmFS/°C ±4 µA 4 µA/V Signal Path Noise 10pF to GND on 4-20OUT 2.0 µARMS 4–20mA Current Limit Limited to 12.5 x VREF / 1.28kΩ 20 mA Note 1: Integral nonlinearity is the deviation of the analog value at any code from its theoretical value after nulling the gain error and offset error. Note 2: Offset calibrated. Note 3: Offset nulled. Note 4: Drift error is eliminated by recalibration at the new temperature. Note 5: The input voltage range for the analog inputs is given with respect to the voltage on the negative input of the differential pair. Note 6: VAIN+ or VAIN- = -2.2V to +2.2V. VREF+ or VREF- = -2.2V to +2.2V. All input structures are identical. Production tested on AIN+ and REF+ only. VREF+ must always be greater than VREF-. Note 7: Power-supply currents are measured with all digital inputs at either GND or DVDD. Note 8: Measured at DC by changing the power-supply voltage from 2.7V to 5.25V and measuring the effect on the conversion error with external reference. PSRR at 50Hz and 60Hz exceeds 120dB with filter notches at 50Hz and 60Hz (Figure 1). Note 9: LED drivers are disabled. _______________________________________________________________________________________ 5 MAX1365/MAX1367 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (AVDD = DVDD = +5V, VDAC_VDD = +5.0V, GND = 0, LEDG = 0, VLEDV = +2.7V to +5.25V, VREF+ - VREF- = 2.048V (external reference), VEXT = 7V, CREF+ = CREF- = 0.1µF, CNEGV = 0.1µF. Internal clock mode, unless otherwise noted. TA = +25°C, unless otherwise noted.) SUPPLY CURRENT vs. SUPPLY VOLTAGE 500 400 DVDD 500 AVDD 400 DVDD 300 200 MAX1365/67 toc03 MAX1365/67 toc02 0.19 0.14 OFFSET ERROR (LSB) AVDD 600 300 600 SUPPLY CURRENT (µA) 800 SUPPLY CURRENT (µA) 700 MAX1365/67 toc01 900 700 MAX1365 OFFSET ERROR vs. SUPPLY VOLTAGE SUPPLY CURRENT vs. TEMPERATURE 1000 0.09 0.04 -0.01 -0.06 200 100 100 2.7 3.2 3.7 0 4.2 4.7 -0.16 5.2 -40 10 35 60 85 2.75 3.25 3.75 4.25 4.75 TEMPERATURE (°C) SUPPLY VOLTAGE (V) MAX1365 OFFSET ERROR vs. TEMPERATURE MAX1365 GAIN ERROR vs. SUPPLY VOLTAGE MAX1365 GAIN ERROR vs. TEMPERATURE 0.1 0 0 -0.02 -0.04 -0.06 -0.1 -0.08 -0.2 -0.10 10 20 30 40 50 60 70 2.75 3.25 3.75 4.25 4.75 1.0 0.5 INL (COUNTS) -0.5 0 OUTPUT CODE 10,000 20,000 MAX1365/67 toc06 -0.06 -0.07 -0.08 5.25 0 0 -1.0 -20,000 10 20 30 40 50 60 NOISE DISTRIBUTION 25 20 15 10 5 0 -10,000 0 OUTPUT CODE 10,000 70 TEMPERATURE (°C) -0.5 -10,000 -0.05 MAX1365 INL (±2V INPUT RANGE) vs. OUTPUT CODE MAX1365/67 toc07 0 -1.0 -20,000 -0.04 SUPPLY VOLTAGE (V) MAX1365 INL (±200mV INPUT RANGE) vs. OUTPUT CODE 0.5 -0.03 -0.09 TEMPERATURE (°C) 1.0 -0.02 -0.10 PERCENTAGE OF UNITS (%) 0 MAX1365/67 toc05 0.02 5.25 MAX1365/67 toc09 0.2 0.04 0 -0.01 GAIN ERROR (% FULL SCALE) 0.3 0.06 MAX1365/67 toc08 0.4 0.08 GAIN ERROR (% FULL SCALE) MAX1365/67 toc04 0.5 6 -15 SUPPLY VOLTAGE (V) 0.6 OFFSET ERROR (LSB) -0.11 DAC_VDD DAC_VDD 0 INL (COUNTS) MAX1365/MAX1367 Stand-Alone, 4.5-/3.5-Digit Panel Meters with 4–20mA Output 20,000 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 NOISE (LSB) _______________________________________________________________________________________ Stand-Alone, 4.5-/3.5-Digit Panel Meters with 4–20mA Output 2.051 2.050 2.049 2.048 2.047 2.046 2.048 2.047 2.046 5.08 5.06 5.04 5.02 5.00 4.98 4.96 4.94 2.045 4.92 2.045 4.90 2.044 2.044 10 20 30 40 50 60 2.75 70 3.25 3.75 4.25 4.75 -15 -40 5.25 OFFSET ERROR vs. COMMON-MODE VOLTAGE DATA OUTPUT RATE vs. SUPPLY VOLTAGE 5.015 0.15 OFFSET ERROR (LSB) 5.010 5.005 5.000 4.995 35 60 85 VNEG STARTUP SCOPE SHOT MAX1365/67 toc14 0.20 MAX1365/67 toc13 5.020 10 TEMPERATURE (°C) SUPPLY VOLTAGE (V) TEMPERATURE (°C) 0.10 MAX1365/67 toc15 0 VDD 2V/div 0.05 1V/div 0 VNEG -0.05 4.990 -0.10 4.985 -0.15 -0.20 3.21 3.72 4.23 4.74 -2.0 -1.5 -1.0 -0.5 5.25 0 0.5 1.0 SUPPLY VOLTAGE (V) COMMON-MODE VOLTAGE (V) CHARGE-PUMP OUTPUT VOLTAGE vs. ANALOG SUPPLY VOLTAGE SEGMENT CURRENT vs. SUPPLY VOLTAGE VNEG VOLTAGE (V) -2.42 -2.44 -2.46 -2.48 30 2.0 DAC ZERO-CODE OFFSET ERROR vs. TEMPERATURE RISET = 25kΩ 25 20 15 10 3.25 3.75 4.25 SUPPLY VOLTAGE (V) 4.75 5.25 0.3 0.2 0.1 0 -0.2 0 2.75 0.4 -0.1 5 -2.50 20ms/div OFFSET ERROR (LSB) MAX1365/67 toc16 -2.40 1.5 MAX1365/67 toc17 2.70 MAX1365/67 toc18 4.980 SEGMENT CURRENT (µA) DATA OUTPUT RATE (Hz) MAX1365/67 toc12 2.049 5.10 DATA OUTPUT RATE (Hz) 2.052 2.050 MAX1365/67 toc11 REFERENCE VOLTAGE (V) 2.053 REFERENCE VOLTAGE (V) MAX1365/67 toc10 2.054 DATA OUTPUT RATE vs. TEMPERATURE INTERNAL REFERENCE VOLTAGE vs. ANALOG SUPPLY VOLTAGE INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE 2.70 3.21 3.72 4.23 SUPPLY VOLTAGE (V) 4.74 5.25 -40 -15 10 35 60 85 TEMPERATURE (°C) _______________________________________________________________________________________ 7 MAX1365/MAX1367 Typical Operating Characteristics (continued) (AVDD = DVDD = +5V, VDAC_VDD = +5.0V, GND = 0, LEDG = 0, VLEDV = +2.7V to +5.25V, VREF+ - VREF- = 2.048V (external reference), VEXT = 7V, CREF+ = CREF- = 0.1µF, CNEGV = 0.1µF. Internal clock mode, unless otherwise noted. TA = +25°C, unless otherwise noted.) Stand-Alone, 4.5-/3.5-Digit Panel Meters with 4–20mA Output Typical Operating Characteristics (continued) 50 30 -0.15 4–20OUT = 21.7mA 10mA/div -0.20 EXTERNAL REFERENCE = 2.048V 40 CONV_IN = 1V 500mV/div -0.10 20 10 0 -10 -20 -30 -0.25 -40 -50 -0.30 -40 -15 10 35 60 -40 85 POWER-SUPPLY REJECTION vs. CURRENT OUTPUT (4-20OUT) 4–20mA MODE 20 10 0 0 TO 16mA MODE -10 -20 -30 MAX1365/67 toc23 30 150 POWER-SUPPLY REJECTION (nA/V) EXTERNAL REFERENCE = 2.048V MAX1365/67 toc22 40 0 100 50 0 -50 -100 -40 -50 -150 -40 -20 0 20 40 60 4 80 6 TEMPERATURE (°C) 8 10 12 14 16 18 20 4-20OUT OUTPUT CURRENT (mA) 4–20OUT vs. DAC CODE (4–20OUT SPAN LINEARITY) MAX1365/67 toc24 2.5 SPAN LINEARITY (µA) 2.0 1.5 1.0 0.5 OFFSET ENABLED (EN_I = HIGH) 0 -0.5 -20,000 -10,000 0 10,000 20,000 DAC CODE (COUNTS) 8 20 40 TEMPERATURE (°C) 4–20OUT GAIN ERROR vs. TEMPERATURE 50 -20 100µs/div TEMPERATURE (°C) GAIN ERROR (%) GAIN ERROR (LSB) -0.05 MAX1365/67 toc20 CURRENT OUTPUT (µA) MAX1365/67 toc19 0 MAX1365/67 toc21 (AVDD = DVDD = +5V, VDAC_VDD = +5.0V, GND = 0, LEDG = 0, VLEDV = +2.7V to +5.25V, VREF+ - VREF- = 2.048V (external reference), VEXT = 7V, CREF+ = CREF- = 0.1µF, CNEGV = 0.1µF. Internal clock mode, unless otherwise noted. TA = +25°C, unless otherwise noted.) DAC GAIN ERROR 4–20OUT ZERO-SCALE ERROR vs. TEMPERATURE vs. TEMPERATURE STEP RESPONSE _______________________________________________________________________________________ 60 80 Stand-Alone, 4.5-/3.5-Digit Panel Meters with 4–20mA Output PIN NAME FUNCTION 1 AIN+ Positive Analog Input. Positive side of fully differential analog input. Bypass AIN+ to GND with a 0.1µF or greater capacitor. 2 AIN- Negative Analog Input. Negative side of fully differential analog input. Bypass AIN- to GND with a 0.1µF or greater capacitor. 3 GND Ground. Connect to star ground. 4 AVDD Analog Positive Supply Voltage. Connect AVDD to a +2.7V to +5.25V power supply. Bypass AVDD to GND with a 0.1µF capacitor. 5 DVDD Digital Positive Supply Voltage. Connect DVDD to a +2.7V to +5.25V power supply. Bypass DVDD to GND with a 0.1µF capacitor. 6 SET Segment Current Set. Connect to ground through a resistor to set the segment current. See Table 7 for segment-current selection. 7 REG_VDD 8 REG_FORCE 9 REG_AMP 10 CMP V/I Converter Regulated Supply Output (5.2V typ) REG_VDD Control. Drives the gate of external depletion-mode FET. Regulator/Reference Buffer Supply. Connect to a 4.75V to 5.25V power supply. Regulator Compensation Node. Connect a 0.1µF capacitor from CMP to REG_FORCE. 11 DAC_VDD 12 DACVOUT DAC Voltage Output. DAC output impedance is typically 6.2kΩ. 13 CONV_IN V/I Converter Input 14 4-20OUT 4–20mA (0 to 16mA) Current-Loop Output. Referenced to GND. 15 GND_DAC 16 GND_V/I V/I Converter Analog Ground. Connect to star ground. 17 REF_DAC V-to-I Converter/DAC Reference Input. Connect a voltage source for external reference operation or leave floating for internal reference. Bypass REF_DAC with a 0.1µF capacitor to GND for either internal or external reference operation. 18 EN_BPM 19 EN_I 20 REFSELE 21 DAC Analog Supply. Connect DAC_VDD to a +2.7V to +5.25V power supply. DAC Analog Ground. Connect to star ground. Active-High V/I-Converter Bipolar-Mode Enable. Set high for bipolar mode. Set low for unipolar mode. Active-High V/I-Converter 4mA Offset Enable. Set low for 0 to 16mA output. Set high for 4–20mA. DAC External Reference Selection. Set low for internal reference. Set high for external reference. Leave REF_DAC unconnected when REFSELE is low. DACDATA_SEL DAC Data-Source Select. Connect to logic high for the MAX1365/MAX1367. 22 CS_DAC DAC Chip Select. Connect to logic high for the MAX1365/MAX1367. 23 INTREF ADC Reference Selection. Set INTREF high to select the internal ADC reference. Set INTREF low to select external ADC reference. 24 RANGE ADC Range Select. Set RANGE low for ±2V analog input voltage range. Set RANGE high for ±200mV analog input voltage range. 25 PEAK Peak Logic Input. Connect PEAK to DVDD to display the highest ADC value on the LED. Connect PEAK to GND to disable the PEAK function (see Table 1). _______________________________________________________________________________________ 9 MAX1365/MAX1367 Pin Description Stand-Alone, 4.5-/3.5-Digit Panel Meters with 4–20mA Output MAX1365/MAX1367 Pin Description (continued) PIN 10 NAME FUNCTION 26 HOLD Hold Logic Input. Connect HOLD to DVDD to hold the current ADC value on the LED. Connect HOLD to GND to update the LED at a rate of 2.5Hz and disable the hold function. Placing the device into hold mode initiates an offset mismatch calibration. Assert HOLD high for a minimum of 2s to ensure the completion of offset mismatch calibration (see Table 1). 27 DPSET2 Display Decimal-Point Logic-Input 2. Controls the decimal point of the LED. See the Decimal-Point Control section. 28 DPSET1 Display Decimal-Point Logic-Input 1. Controls the decimal point of the LED. See the Decimal-Point Control section. 29 LEDG LED Segment-Drivers Ground 30 DIG0 Digit 0 Driver Out (Connected to GLED for the MAX1367) 31 DIG1 Digit 1 Driver Out 32 DIG2 Digit 2 Driver Out 33 DIG3 Digit 3 Driver Out 34 DIG4 Digit 4 Driver Out 35 SEGA Segment A Driver 36 SEGB Segment B Driver 37 LEDV LED-Display Segment-Driver Supply. Connect to a +2.7V to +5.25V supply. Bypass with a 0.1µF capacitor to LEDG. 38 SEGC Segment C Driver 39 SEGD Segment D Driver 40 SEGE Segment E Driver 41 SEGF Segment F Driver 42 SEGG Segment G Driver 43 SEGDP Segment DP Driver 44 LED_EN Active-High LED Enable. The MAX1365/MAX1367 display driver turns off when LED_EN is low. The MAX1365/MAX1367 LED-display driver turns on when LED_EN is high. 45 NEGV -2.5V Charge-Pump Voltage Output. Connect a 0.1µF capacitor to GND. 46 DPON Decimal-Point Enable Input. Controls the decimal point of the LED. See the Decimal-Point Control section. Connect DPON to DVDD to enable the decimal point. 47 REF- ADC Negative Reference Voltage Input. For internal reference operation, connect REF- to GND. For external reference operation, bypass REF- to GND with a 0.1µF capacitor and set VREF- from -2.2V to +2.2V (VREF+ > VREF-). 48 REF+ ADC Positive Reference Voltage Input. For internal reference operation, connect a 4.7µF capacitor from REF+ to GND. For external reference operation, bypass REF+ to GND with a 0.1µF capacitor and set VREF+ from -2.2V to +2.2V (VREF+ > VREF-). ______________________________________________________________________________________ Stand-Alone, 4.5-/3.5-Digit Panel Meters with 4–20mA Output AVDD DVDD INTREF PEAK RANGE DPON DPSET1 DPSET 2 HOLD CS_DAC DACDATA_SEL SET LEDV LOGIC +2.5V SEGA AIN+ SEGG LED DRIVER ADC DIG0(1) AIN- DIG4(4) INPUT BUFFER LED_EN LEDG DAC_VDD DACVOUT CONV_IN REF+ REF- OUTPUT DAC -2.5V 2.048V BANDGAP REFERENCE NEGV CHARGE PUMP -2.5V CURRENT SUMMER AND AMPLIFIER V/I CONVERTER DAC REF BUFFER OFFSET GENERATOR 4-20OUT EN_I EN_BPM 5V REGULATOR MAX1365 MAX1367 GND REFSELE REF_DAC REG_AMP CMP REG_FORCE REG_VDD Detailed Description The MAX1365/MAX1367 low-power, highly integrated ADCs with LED drivers convert a ±2V differential input voltage (one count is equal to 100µV for the MAX1365 and 1mV for the MAX1367) with a sigma-delta ADC and output the result to an LED display. An additional ±200mV input range (one count is equal to 10µV for the MAX1365 and 100µV for the MAX1367) is available to measure small signals with finer resolution. In addition to displaying the results on an LED display, these devices feature a DAC and V-to-I converter for 4–20mA (or 0 to 16mA) current output that proportionally follows the ADC input. The MAX1365/MAX1367 use an external depletion-mode NMOS transistor to regulate 7V to 30V for the V/I converter. Use the 4–20mA (or 0 to 16mA) output to drive a remote display, data logger, PLC input, or other 4–20mA devices in a current loop. The MAX1365/MAX1367 include a 2.048V reference, internal charge pump, and a high-accuracy on-chip oscillator. The devices feature on-chip buffers for the differential input signal and external-reference inputs, allowing direct interface with high-impedance signal sources. In addition, they use continuous internal offsetcalibration and offer > 100dB of 50Hz and 60Hz linenoise rejection. Other features include data hold and peak detection and overrange/underrange detection. Analog Input Protection The MAX1365/MAX1367 provide internal protection diodes that limit the analog input range on AIN+, AIN-, REF+, and REF- from NEGV to (AVDD + 0.3V). If the analog input exceeds this range, limit the input current to 10mA. Internal Analog Input/Reference Buffers The MAX1365/MAX1367 analog input/reference buffers allow the use of high-impedance signal sources. The input buffers’ common-mode input range allows the analog inputs and the reference to range from -2.2V to +2.2V. Modulator The MAX1365/MAX1367 perform analog-to-digital conversions using a single-bit, 3rd-order, sigma-delta modulator. The sigma-delta modulator converts the input ______________________________________________________________________________________ 11 MAX1365/MAX1367 Functional Diagram signal into a digital pulse train whose average duty cycle represents the digitized signal information. The modulator quantizes the input signal at a much higher sample rate than the bandwidth of the input. The MAX1365/MAX1367 modulator provides 3rd-order frequency shaping of the quantization noise resulting from the single-bit quantizer. The modulator is fully differential for maximum signal-to-noise ratio and minimum susceptibility to power-supply noise. A single-bit data stream is then presented to the digital filter to remove the frequency-shaped quantization noise. 0 -40 GAIN (dB) MAX1365/MAX1367 Stand-Alone, 4.5-/3.5-Digit Panel Meters with 4–20mA Output -80 -120 -160 Digital Filtering The MAX1365/MAX1367 contain an on-chip digital lowpass filter that processes the data stream from the modulator using a SINC4 response: sin(x) x 4 4 f sin Nπ f 1 m H(f ) = N sin πf f m 10 20 30 40 50 60 FREQUENCY (Hz) step changes at the input, allow a settling time of 800ms before valid data is read. Internal Clock The MAX1365/MAX1367 contain an internal oscillator. Using the internal oscillator saves board space by removing the need for an external clock source. The oscillator is optimized to give 50Hz and 60Hz powersupply and common-mode rejection. Charge Pump 4 where N is the oversampling ratio, and fm = N x output data rate = 5Hz. Filter Characteristics Figure 1 shows the filter frequency response. The SINC4 characteristic -3dB cutoff frequency is 0.228 times the first notch frequency (5Hz). The oversampling ratio (OSR) for the MAX1367 is 128 and the OSR for the MAX1365 is 1024. The output data rate for the digital filter corresponds to the positioning of the first notch of the filter’s frequency response. The notches of the SINC4 filter are repeated at multiples of the first notch frequency. The SINC4 filter provides an attenuation of better than 100dB at these notches. For example, 50Hz is equal to 10 times the first notch frequency and 60Hz is equal to 12 times the first notch frequency. For large 12 0 Figure 1. Frequency Response of the SINC4 Filter (Notch at 60Hz) The SINC4 filter has a settling time of four output data periods (4 x 200ms). The MAX1365/MAX1367 have 25% overrange capability built into the modulator and digital filter. The digital filter is optimized for the fCLK equal to 4.9152MHz. The frequency response of the SINC4 filter is calculated as follows: 1(1− Z −N ) H(z) = N (1− Z −1 ) -200 The MAX1365/MAX1367 contain an internal charge pump to provide the negative supply voltage for the internal analog input/reference buffers. The bipolar input range of the analog input/reference buffers allows this device to accept negative inputs with high source impedances. Connect a 0.1µF capacitor from NEGV to GND. LED Driver (Table 1) The MAX1365 has a 4.5-digit common-cathode display driver, and the MAX1367 has a 3.5-digit common-cathode display driver. In addition, the LED drivers of the MAX1365/MAX1367 feature peak-detection and datahold circuitry. Figures 2 and 3 show the connection schemes for a standard seven-segment LED display. The LED update rate is 2.5Hz. Figure 4 shows a typical common-cathode configuration for two digits. In common-cathode configuration, the cathodes of all LEDs in a digit are connected together. Each segment driver of the MAX1365/MAX1367 connects to its corresponding LED’s anodes. For example, segment driver SEGA connects to all LED segments designated as A. Similar configurations are used for other segment drivers. ______________________________________________________________________________________ Stand-Alone, 4.5-/3.5-Digit Panel Meters with 4–20mA Output A A B F C E DP G F D A B F C E DP A G B F C E DP A G B F C E DP G HOLD PEAK 1 X Hold value 0 1 Peak value 0 0 Latest ADC result B C DP G D D D D DIGIT 4 DIGIT 3 DIGIT 2 DIGIT 1 DIGIT 0 DISPLAY VALUES FORM X = Don’t care. Figure 2. Segment Connection for the MAX1365 (4.5 Digits) A A B F C E DP F D G DIGIT 4 G A B F C E DP G Table 2. Decimal-Point Control Table— MAX1365 A B F C E DP G B DPSET1 DPSET2 DISPLAY OUTPUT ZERO INPUT READING 0 0 0 18888 0 0 0 1 18888 0 0 1 0 18888 0 0 1 1 18888 0 1 0 0 1888.8 0.0 1 0 1 188.88 0.00 1 1 0 18.888 0.000 1 1 1 1.8888 0.0000 C DP D D D DIGIT 3 DIGIT 2 DIGIT 1 Figure 3. Segment Connection for the MAX1367 (3.5 Digits) The MAX1365/MAX1367 use a multiplexing scheme to drive one digit at a time. The scan rate is fast enough to make the digits appear to be lit. Figure 5 shows the data-timing diagram for the MAX1365/MAX1367 where T is the display scan period (typically around 1/512Hz or 1.9531ms). TON in Figure 5 denotes the amount of time each digit is on and is calculated as follows: TON = DPON T 1.95312ms = = 390.60µs 5 5 Table 3. Decimal-Point Control Table— MAX1367 DPON DPSET1 DPSET2 DISPLAY OUTPUT ZERO INPUT READING 1 0 0 1888. 0. Decimal-Point Control 1 0 1 188.8 0.0 The MAX1365/MAX1367 allow for full decimal-point control and feature leading-zero suppression. 1 1 0 18.88 0.00 1 1 1 1.888 0.000 Use the DPON, DPSET1, and DPSET2 bits in the control register to set the value of the decimal point (Tables 2 and 3). The MAX1365/MAX1367 overrange and underrange display is shown in Table 4. Table 4. LED During Overrange and Underrange Conditions Leading-Zero Suppression The MAX1365/MAX1367 include a leading-zero suppression circuitry to turn off unnecessary zeros. For example, when DPSET1 and DPSET2 = [0,0], 0.0 is displayed instead of 000.0 (MAX1365). This feature saves a substantial amount of power by not lighting unnecessary LEDs. Interdigit Blanking The MAX1365/MAX1367 also include an interdigitblanking circuitry. Without this feature, it is possible to CONDITION MAX1367 MAX1365 Overrange 1--- 1---- Underrange -1--- -1---- see a faint digit next to a digit that is completely on. The interdigit-blanking circuitry prevents ghosting over into the next digit for a short period of time. The typical interdigit blanking time is 4µs. ______________________________________________________________________________________ 13 MAX1365/MAX1367 Table 1. LED Priority Table MAX1365/MAX1367 Stand-Alone, 4.5-/3.5-Digit Panel Meters with 4–20mA Output SEGDP SEGG SEGF SEGE SEGD SEGC SEGB SEGA A B C F D E F G DP A B C D E DIGIT 1 DIGIT 2 A A G F B C E F G DP B G C E DP DP D D Figure 4. 2-Digit Common-Cathode Configuration TON DIGIT 4 (MSD) INTERDIGIT BLANKING TIME DIGIT 3 DIGIT 2 DIGIT 1 DIGIT 0 (LSD) T DATA 4 MSD 3 2 1 0 LSD 4 3 2 1 0 4 Figure 5. LED Voltage Waveform Current Output The MAX1365/MAX1367 feature a 4–20mA (0 to 16mA) current output for driving remote panel meters, data loggers, and process controllers in industrial applications. The DAC output is proportional to the input of the ADC and LED display. In the simplest configuration, connect DAC_VOUT directly to CONV_IN to have the current output (4–20mA or 0 to 16mA) follow the analog inputs. Custom signal conditioning can be inserted between DAC_VOUT and CONV_IN, or CONV_IN can be driven independently by a voltage source if desired. See Figures 11–14 for the transfer functions of the DAC and V/I converter. Note: The MAX1365/MAX1367 expect a 6kΩ (typ) source impedance from the external voltage source driving CONV_IN. 14 Current Offset Set EN_I high for a current span of 4–20mA. Set EN_I low for a current span of 0 to 16mA. See Table 5 for current output. Unipolar Mode Set EN_BPM low to engage unipolar operation. In unipolar mode, the current output at 4-20OUT (4–20mA or 0 to 16mA) maps the analog input voltage (0 to 2V or 0 to 200mV). Negative voltages at the analog input result in a 4mA or 0mA output, depending on the EN_I setting. See Table 5 for current output. See Figures 12 and 13. ______________________________________________________________________________________ Stand-Alone, 4.5-/3.5-Digit Panel Meters with 4–20mA Output MAX1365/MAX1367 Table 5. Current Output Table CURRENT OUTPUT (mA) ANALOG INPUT UNIPOLAR MODE (EN_I = LOW) UNIPOLAR MODE (EN_I = HIGH) BIPOLAR MODE (EN_I = LOW) BIPOLAR MODE (EN_I = HIGH) Negative Full Scale 0 4 0 4 0V 0 4 8 12 Positive Full Scale 16 20 16 20 ANALOG SUPPLY FERRITE BEAD 10µF 0.1µF 10µF 0.1µF AVDD DVDD REF+ NEGV 0.1µF RREF REF0.1µF ACTIVE GAUGE MAX1365 MAX1367 R 4-20OUT AIN+ 0.1µF AIN- DUMMY GAUGE 4–20mA/0 TO 16mA CURRENT-LOOP OUTPUT 0.1µF R GND Figure 6. Strain-Gauge Application with the MAX1365/MAX1367 Bipolar Mode Set EN_BPM high to engage bipolar operation. In bipolar mode, the current output at 4–20OUT (4–20mA or 0 to 16mA) maps the analog input voltage (±2V or ±200mV). In bipolar mode, a 0V analog input maps to midscale (12mA). See Table 5 for current output (see Figures 12 and 13). 5.2V Linear Regulator with Compensation The MAX1365/MAX1367 feature a 5.2V linear regulator. The 5.2V regulator consists of an op amp and connections to an external depletion-mode FET. The 5.2V regulator regulates the loop voltage that powers the voltage-to-current converter and the rest of the transmitter circuitry. The regulator output voltage is available at REG_VDD and is given by the equation: VREG_VDD = 2.54 x VREF+ The FET breakdown and saturation voltages determine the usable range of loop voltages (VEXT). The external FET parameters such as VGS (off), IDSS, and transconductance must be chosen so that the op amp output on the REG_FORCE pin can control the FET operating point while swinging in the range from VREG_AMP to REG_VDD. See the Selecting Depletion-Mode FET section in the Applications Information section. Connect a 0.1µF capacitor between CMP and REG_FORCE to ensure stable operation of the regulator. Applications Information Power-On Reset At power-on, the digital filter and modulator circuits reset. The MAX1365 allows 6s for the reference to stabilize before performing enhanced offset calibration. ______________________________________________________________________________________ 15 MAX1365/MAX1367 Stand-Alone, 4.5-/3.5-Digit Panel Meters with 4–20mA Output During these 6s, the MAX1365 displays 1.2V to 1.5V when a stable reference is detected. If a valid reference is not found, the MAX1365 times out after 6s and begins enhanced offset calibration. Enhanced offset calibration typically lasts 2s. The MAX1365 begins converting after enhanced offset calibration. Reference ADC Reference The MAX1365/MAX1367 reference sets the full-scale range of the ADC transfer function. With a nominal 2.048V reference, the ADC full-scale range is ±2V with RANGE = GND. With RANGE = DVDD, the full-scale range is ±200mV. A decreased reference voltage decreases full-scale range (see the Transfer Functions section). The ADC of the MAX1365/MAX1367 can accept either an external reference or an internal reference (INTREF). The INTREF logic selects the reference mode. For internal-reference operation, set INTREF to DVDD, connect REF- to GND, and bypass REF+ to GND with a 4.7µF capacitor. The internal reference provides a nominal 2.048V source between REF+ and GND. The internalreference temperature coefficient is typically 40ppm/°C. For external-reference operation, set INTREF to GND. REF+ and REF- are fully differential. For a valid external-reference input, VREF+ must be greater than VREF-. Bypass REF+ and REF- with a 0.1µF or greater capacitor to GND in external-reference mode. Figure 6 shows the MAX1365/MAX1367 operating with an external differential reference. In this figure, REF- is connected to the top of the strain gauge and REF+ is connected to the midpoint of the resistor-divider of the supply. DAC Reference The DAC of the MAX1365/MAX1367 accept either an external reference or an internal reference. The REFSELE enables or disables the internal reference. For externalreference operation, disable the DAC reference buffer by setting REFSELE to DVDD and connect a voltage source to REF_DAC. DAC Operation For the MAX1365/MAX1367, a voltage proportional to the ADC input is available at DACVOUT. Connect DACVOUT to CONV_IN for normal operation. See Figure 11 for the DAC transfer function. Offset Calibration The MAX1365/MAX1367 offer on-chip offset calibration. The device offset calibrates during every conversion cycle. Enhanced Offset Calibration Enhanced offset calibration is a more accurate calibration method that is needed in the case of the ±200mV range and 4.5-digit resolution. In addition to enhanced offset calibration at power-up, the MAX1365/MAX1367 perform enhanced calibration on demand by connecting HOLD to AVDD for > 2s. Peak The MAX1365/MAX1367 feature peak-detection circuitry. When activated, the devices display only the highest voltage measured to the LED. First, the current ADC result is displayed. The new ADC conversion result is compared to the current result. If the new value is larger than the previous peak value, the new value is displayed. If the new value is less than the previous peak value, the display remains unchanged. Connect PEAK to GND to clear the peak value and disable the peak function. See Table 1 for LED Display priority. Hold The MAX1365/MAX1367 feature data-hold circuitry. When activated, the device holds the current reading on the LED. Strain-Gauge Measurement Connect the differential inputs of the MAX1365/ MAX1367 to the bridge network of the strain gauge. In Figure 6, the analog supply voltage powers the bridge network and the MAX1365/MAX1367, along with the reference voltage. The MAX1365/MAX1367 handle an analog input voltage range of ±200mV and ±2V full scale. The analog/reference inputs of the parts allow the analog input range to have an absolute value of anywhere between -2.2V and +2.2V. For internal-reference operation, enable the DAC reference buffer by setting REFSELE to GND. In this mode, leave REFDAC floating. In either internal or external reference operation, bypass REF_DAC with a 0.1µF capacitor to GND. Choose a reference with output impedance (load regulation equivalent) of 100mΩ or less, such as the MAX6126. For best performance, use an external reference source for the ADC and DAC. 16 ______________________________________________________________________________________ Stand-Alone, 4.5-/3.5-Digit Panel Meters with 4–20mA Output MAX1365/MAX1367 LED LED 1---- 1--- 19,999 1999 2 1 2 1 0 0 -0 -0 -1 -1 -2 -2 -19,999 -1999 -1---- -1---100µV 0 100µV -2V -200mV +2V -100µV 0 100µV +200mV ANALOG INPUT VOLTAGE ANALOG INPUT VOLTAGE Figure 7. MAX1365 Transfer Function—±2V Range LED Figure 9. MAX1367 Transfer Function—±200mV Range LED 1---- 1--- 19,999 1999 2 1 2 1 0 0 -0 -0 -1 -1 -2 -2 -19,999 -1999 -1---- -1---200mV -10µV 0 10µV +200mV ANALOG INPUT VOLTAGE Figure 8. MAX1365 Transfer Function—±200mV Range Transfer Functions ADC Transfer Functions Figures 7–10 show the transfer functions of the MAX1365/MAX1367. The output data is stored in the ADC data register in two’s complement. The transfer function for the MAX1365 with AIN+ - AIN≥ 0 and RANGE = GND is: V − VAIN− (1) COUNT = 1.024 AIN+ x 20, 000 V V − REF+ REF− -2V -1mV 0 1mV +2V ANALOG INPUT VOLTAGE Figure 10. MAX1367 Transfer Function—±2V Range The transfer function for the MAX1365 with AIN+ - AIN< 0 and RANGE = GND is: V − VAIN− (2) COUNT = 1.024 AIN+ x 20, 000 + 1 V V − REF+ REF− The transfer function for the MAX1367 with AIN+ - AIN≥ 0 and RANGE = GND is: V − VAIN− (3) COUNT = 1.024 AIN+ x 2000 VREF+ − VREF− ______________________________________________________________________________________ 17 UNIPOLAR : BIPLOLAR : UNIPOLAR : BIPLOLAR : CURRENT OFFSET DISABLED (EN_I = 0) 1. 25 4-20OUT (mA) DAC OUTPUT VOLTAGE (V) 16 8 0 0 - FS FS = FULL SCALE 0 ADC OUTPUT CODE - FS + FS Figure 13. Output Current (4-20OUT) vs. ADC Output Code (Current Offset Disabled) UNIPOLAR : BIPLOLAR : CURRENT OFFSET ENABLED (EN_I = 1) + FS 0 ADC OUTPUT CODE FS = FULL SCALE Figure 11. DAC Output Voltage vs. ADC Output Code OFFSET ENABLED : OFFSET DISABLED : 20 20 16 16 4-20OUT (mA) 4-20OUT (mA) MAX1365/MAX1367 Stand-Alone, 4.5-/3.5-Digit Panel Meters with 4–20mA Output 12 4 4 0 - FS 0 ADC OUTPUT CODE + FS 0 1. 25 0 V/I CONVERTER INPUT ( V ) FS = FULL SCALE Figure 12. Output Current (4-20OUT) vs. ADC Output Code (Current Offset Enabled) The transfer function for the MAX1367 with AIN+ - AIN< 0 and RANGE = GND is: V − VAIN− (4) COUNT = 1.024 AIN+ x 2000 + 1 VREF+ − VREF− The transfer function for the MAX1365 with AIN+ - AIN≥ 0 and RANGE = DVDD is: 18 Figure 14. 4-20OUT Output Current vs. V/I Converter Input Voltage V − VAIN− (5) COUNT = 1.024 AIN+ x 20, 000 x10 VREF+ − VREF− The transfer function for the MAX1365 with AIN+ - AIN< 0 and RANGE = DVDD is: V − VAIN− (6) COUNT = 1.024 AIN+ x 20, 000 x 10 + 1 VREF+ − VREF− ______________________________________________________________________________________ Stand-Alone, 4.5-/3.5-Digit Panel Meters with 4–20mA Output V − VAIN− (7) COUNT = 1.024 AIN+ x 2000 x 10 VREF+ − VREF− The transfer function for the MAX1367 with AIN+ - AIN< 0 and RANGE = DVDD is: V − VAIN− (8) COUNT = 1.024 AIN+ x 2000 x 10 + 1 V V − REF+ REF− DAC Transfer Functions Figure 11 shows the DAC transfer function for the MAX1365/MAX1367 in unipolar and bipolar modes. The transfer function for the DAC in the MAX1365/ MAX1367 unipolar mode is: VDACVOUT = N x VREF 32, 768 − 1 where N = two’s complement ADC output code. In unipolar mode, VDACVOUT is equal to 0V for all two’s complement ADC codes less than zero (see Figure 12). The transfer function for the DAC in the MAX1365/ MAX1367 in bipolar mode is: VDACVOUT = N +19, 999 x VREF 65, 536 where N = two’s complement ADC output. Voltage-to-Current Transfer Function Figures 12 and 13 show the MAX1365/MAX1367 transfer function of the output current (4-20OUT) versus the ADC input code. The transfer function for the MAX1365/MAX1367 with the current offset enabled (EN_I is high) is: IOUT ≅ 16mA x VCONV _IN + 4mA 1.25 The transfer function for the MAX1365/MAX1367 with the current offset disabled (EN_I is low) is: IOUT ≅ 16mA x VCONV _IN 1.25 Note: The input at VCONV_IN expects a source impedance of typically 6kΩ when driving VCONV_IN externally. Supplies, Layout, and Bypassing Power up AVDD and DVDD before applying an analog input and external-reference voltage to the device. If this is not possible, limit the current into these inputs to 50mA. When the analog and digital supplies come from the same source, isolate the digital supply from the analog supply with a low-value resistor (10Ω) or ferrite bead. For best performance, ground the MAX1365/ MAX1367 to the analog ground plane of the circuit board. Avoid running digital lines under the device as this can couple noise onto the IC. Run the analog ground plane under the MAX1365/MAX1367 to minimize coupling of digital noise. Make the power-supply lines to the MAX1365/MAX1367 as wide as possible to provide low-impedance paths and reduce the effects of glitches on the power-supply line. Shield fast-switching signals, such as clocks, with digital ground to avoid radiating noise to other sections of the board. Avoid running clock signals near the analog inputs. Avoid crossover of digital and analog signals. Running traces that are on opposite sides of the board at right angles to each other reduces feedthrough effects. Good decoupling is important when using high-resolution ADCs. Decouple the supplies with 0.1µF ceramic capacitors to GND. Place these components as close to the device as possible to achieve the best decoupling. Selecting Segment Current A resistor from ISET to ground sets the current for each LED segment. See Table 6 for more detail. Use the following formula to set the segment current: 1.20V ISEG = x 450 RISET RISET values below 25kΩ increase the ISEG. However, the internal current-limit circuit limits the ISEG to less than 30mA. At higher ISEG values, proper operation of the device is not guaranteed. In addition, the power dissipated may exceed the package power-dissipation limit. Choosing Supply Voltage to Minimize Power Dissipation The MAX1365/MAX1367 drive a peak current of 25.5mA into LEDs with a 2.2V forward voltage drop when operated from a supply voltage of at least 3.0V. Therefore, the minimum voltage drop across the internal LED drivers is 0.8V (3.0V - 2.2V = 0.8V). The MAX1365/MAX1367 sink when the outputs are operating and the LED segment drivers are at full current (8 x 25.5mA = 204mA). For a 3.3V supply, the MAX1365/MAX1367 dissipate 224.4mW ((3.3V - 2.2V) x 204 = 224.4mW). If a higher supply voltage is used, the driver absorbs a higher voltage, and the driver’s power dissipation increases accordingly. ______________________________________________________________________________________ 19 MAX1365/MAX1367 The transfer function for the MAX1367 with AIN+ - AIN≥ 0 and RANGE = DVDD is: MAX1365/MAX1367 Stand-Alone, 4.5-/3.5-Digit Panel Meters with 4–20mA Output However, if the LEDs used have a higher forward voltage drop than 2.2V, the supply voltage must be raised accordingly to ensure that the driver always has at least 0.8V headroom. For a LEDV supply voltage of 2.7V, the maximum LED forward voltage is 1.9V to ensure 0.8V driver headroom. The voltage drop across the drivers with a nominal +5V supply (5.0V - 2.2V = 2.8V) is almost three times the drop across the drivers with a nominal 3.3V supply (3.3V - 2.2V = 1.1V). Therefore, the driver’s power dissipation increases three times. The power dissipation in the part causes the junction temperature to rise accordingly. In the high ambient temperature case, the total junction temperature may be very high (> +125°C). At higher junction temperatures, the ADC performance degrades. To ensure the dissipation limit for the MAX1365/MAX1367 is not exceeded and the ADC performance is not degraded; a diode can be inserted between the power supply and LEDV. Selecting Depletion-Mode FET An external depletion-mode FET (DMOS) works in conjunction with the regulator circuit to supply the V/I converter with loop power. REG_FORCE regulates the gate of the DMOS so that the drain voltage is 5.2V (typ) and allows the 4–20mA (0 to 16mA) loop to be directly powered from a 7V to 30V supply. DMOS IDS consists of the current output at 4-20OUT, a 4mA offset current, and 1mA (typ) consumed by the V/I converter. For offset-enabled mode (EN_I = 1): IDS = I4-20OUT + 4mA + 1mA where IDS is the current in the DMOS. For offset-disabled mode (EN_I = 0): IDS = I4-20OUT + 1mA where IDS is the current in the DMOS. Table 7 provides the FET characteristics for selecting an external DMOS transistor. The DN25D FET transistor from Supertex meets all the requirements of Table 7. Other suitable transistors include ND2020L and ND2410L from Siliconix. Connect a 0.1µF capacitor between CMP and REG_FORCE to ensure stable regulator compensation. 20 Definitions Integral Nonlinearity (INL) INL is the deviation of the values on an actual transfer function from a straight line. This straight line is either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. INL for the MAX1365/ MAX1367 is measured using the end-point method. Differential Nonlinearity (DNL) DNL is the difference between an actual step width and the ideal value of ±1 LSB. A DNL error specification of less than ±1 LSB guarantees no missing codes and a monotonic transfer function. Rollover Error Rollover error is defined as the absolute-value difference between a near positive full-scale reading and near negative full-scale reading. Rollover error is tested by applying a full-scale positive voltage, swapping AIN+ and AIN-, and adding the results. Zero-Input Reading Ideally, with AIN+ connected to AIN-, the MAX1365/ MAX1367 LED displays zero. Zero-input reading is the measured deviation from the ideal zero and the actual measured point. Gain Error Gain error is the amount of deviation between the measured full-scale transition point and the ideal full-scale transition point. Common-Mode Rejection (CMR) CMR is the ability of a device to reject a signal that is common to both input terminals. The common-mode signal can be either an AC or a DC signal or a combination of the two. CMR is often expressed in decibels. Normal-Mode 50Hz and 60Hz Rejection (Simultaneously) Normal-mode rejection is a measure of how much output changes when 50Hz and 60Hz signals are injected into only one of the differential inputs. The MAX1365/ MAX1367 sigma-delta converter uses its internal digital filter to provide normal-mode rejection to both 50Hz and 60Hz power-line frequencies simultaneously. ______________________________________________________________________________________ Stand-Alone, 4.5-/3.5-Digit Panel Meters with 4–20mA Output MAX1365/MAX1367 Power-Supply Rejection (PSR)—ADC PSR is a measure of the data converter’s level of immunity to power-supply fluctuations. PSR assumes that the converter’s linearity is unaffected by changes in the power-supply voltage. Power-supply rejection ratio (PSRR) is the ratio of the input signal change to the change in the converter output. PSRR is typically measured in dB. Power-Supply Rejection—V/I Converter PSR is a measure of the data converter’s level of immunity to power-supply fluctuations. PSR assumes that the converter’s linearity is unaffected by changes in the power-supply voltage. Note: The V/I converter current output (4–20mA) power-supply rejection is with respect to the 7V to 30V loop supply. Table 6. Segment-Current Selection RSET (kΩ) ISEG (mA) 25 21.6 50 10.8 100 5.4 500 1.1 > 2500 LED driver disabled Table 7. FET Characteristics FET TYPE N-CHANNEL DEPLETION MODE IDS 30mA BVDS (VEXT* - REG_VDD) min VPINCHOFF REG_VDD max Power dissipation 30mA x (VEXT - REG_VDD) min *VEXT is the 7V to 30V loop voltage. ______________________________________________________________________________________ 21 Stand-Alone, 4.5-/3.5-Digit Panel Meters with 4–20mA Output MAX1365/MAX1367 MAX1365 Typical Operating Circuit DAC_VDD SUPPLY VOLTAGE IN MAX6126 OUTF 0.1µF OUTS GNDS VEXT 7V TO 30V VIN AIN+ AIN- GND 0.1µF DIG0–DIG4 DIGIT CONNECTIONS SEGA–SEGDP SEGMENT CONNECTIONS GND_DAC DACVOUT 0.1µF DEPLETIONMODE FET REF_DAC CMP CONV_IN REG_FORCE EN_BPM EN_I REG_VDD REG_AMP 4.75V TO 5.25V DACDATA_SEL TO DVDD CS_DAC 4-20mA/0 TO 16mA CURRENT-LOOP OUTPUT 4-20OUT REFSELE MAX1365 4-20mA PLC INPUT INTREF RANGE RL ADC PEAK LEDV 0.1µF HOLD LED_EN DVDD DPON 10µF 10µF DPSET2 DAC_VDD LISO 2.7V TO 5.25V DPSET1 AVDD 0.1µF SET 10µF NEGV GND REF0.1µF REF+ LEDG GND_V/I 10µF 25kΩ 22 ______________________________________________________________________________________ Stand-Alone, 4.5-/3.5-Digit Panel Meters with 4–20mA Output DAC_VDD SUPPLY VOLTAGE IN MAX6126 OUTF 0.1µF OUTS GNDS VEXT 7V TO 30V VIN SEGA–SEGDP SEGMENT CONNECTIONS AIN+ AIN- DIGO GND 0.1µF DIG1–DIG4 DIGIT CONNECTIONS GND_DAC DACVOUT 0.1µF DEPLETIONMODE FET REF_DAC CMP CONV_IN REG_FORCE EN_BPM EN_I REG_VDD REG_AMP 4.75V TO 5.25V DACDATA_SEL TO DVDD CS_DAC 4-20mA/0 TO 16mA CURRENT-LOOP OUTPUT 4-20OUT REFSELE MAX1367 4-20mA PLC INPUT INTREF RANGE ADC RL PEAK LEDV 0.1µF HOLD LED_EN DVDD DPON 10µF 10µF DPSET2 DAC_VDD LISO 2.7V TO 5.25V DPSET1 AVDD 0.1µF SET 10µF NEGV GND REF0.1µF REF+ LEDG GND_V/I 10µF 25kΩ ______________________________________________________________________________________ 23 MAX1365/MAX1367 MAX1367 Typical Operating Circuit Stand-Alone, 4.5-/3.5-Digit Panel Meters with 4–20mA Output PEAK HOLD DPSET2 DPSET1 LEDG DIG0 DIG1 DIG2 DIG3 SEGA DIG4 TOP VIEW SEGB MAX1365/MAX1367 Pin Configuration 36 35 34 33 32 31 30 29 28 27 26 25 LEDV 37 24 RANGE SEGC 38 23 INTREF SEGD 39 22 CS_DAC SEGE 40 21 DACDATA_SEL SEGF 41 20 REFSELE 19 EN_I SEGG 42 MAX1365 MAX1367 SEGDP 43 18 EN_BPM 17 REF_DAC LED_EN 44 NEGV 45 16 GND_V/I DPON 46 15 GDN_DAC DVDD 8 9 10 11 12 DACVOUT AVDD 7 DAC_VDD AIN- 6 CMP 5 REG_AMP 4 REG_VDD 3 REG_FORCE 2 SET 1 GND 14 4-200UT 13 CONV_IN AIN+ REF- 47 REF+ 48 TQFP Chip Information TRANSISTOR COUNT: 83,463 PROCESS: CMOS 24 ______________________________________________________________________________________ Stand-Alone, 4.5-/3.5-Digit Panel Meters with 4–20mA Output 32L/48L,TQFP.EPS PACKAGE OUTLINE, 32/48L TQFP, 7x7x1.4mm 21-0054 E 1 2 PACKAGE OUTLINE, 32/48L TQFP, 7x7x1.4mm 21-0054 E 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 25 © 2006 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc. MAX1365/MAX1367 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)