230 19-2316; Rev 0; 1/02 Dual, 10-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC Features ♦ Ultra-Low Supply Current 115µA at VDD = 3.6V 135µA at VDD = 5.5V The MAX5821 features a double-buffered I2C-compatible serial interface that allows multiple devices to share a single bus. All logic inputs are CMOS-logic compatible and buffered with Schmitt triggers, allowing direct interfacing to optocoupled and transformer-isolated interfaces. The MAX5821 minimizes digital noise feedthrough by disconnecting the clock (SCL) signal from the rest of the device when an address mismatch is detected. The MAX5821 is specified over the extended temperature range of -40°C to +85°C and is available in a miniature 8-pin µMAX package. Refer to the MAX5822 data sheet for the 12-bit version. ♦ Rail-to-Rail Output Buffer Amplifiers Applications Digital Gain and Offset Adjustments ♦ 300nA Low-Power Power-Down Mode ♦ Single 2.7V to 5.5V Supply Voltage ♦ Fast 400kHz I2C-Compatible 2-Wire Serial Interface ♦ Schmitt-Trigger Inputs for Direct Interfacing to Optocouplers ♦ Three Software-Selectable Power-Down Output Impedances 100kΩ, 1kΩ, and High Impedance ♦ Read-Back Mode for Bus and Data Checking ♦ Power-On Reset to Zero ♦ 8-Pin µMAX Package Ordering Information PART TEMP RANGE MAX5821LEUA -40oC to +85oC 8 µMAX 0111 00X MAX5821MEUA -40oC to +85oC 8 µMAX 1011 00X Programmable Voltage and Current Sources PINPACKAGE ADDRESS Typical Operating Circuit Programmable Attenuation VDD VCO/Varactor Diode Control Low-Cost Instrumentation Battery-Operated Instrumentation µC SDA VDD SCL RP RP Pin Configuration RS TOP VIEW SCL VDD 1 GND 8 2 OUTB 7 OUTA 3 6 REF SCL 4 5 SDA RS SDA VDD MAX5821 REF OUTA OUTB MAX5821 ADD RS SDA µMAX Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd. I2C is a trademark of Philips Corp. VDD SCL RS REF MAX5821 OUTA OUTB REF ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX5821 General Description The MAX5821 is a dual, 10-bit voltage-output, digital-toanalog converter (DAC) with an I 2 C ™ -compatible, 2-wire interface that operates at clock rates up to 400kHz. The device operates from a single 2.7V to 5.5V supply 115µA at V DD = 3.6V. A power-down mode decreases current consumption to less than 1µA. The MAX5821 features three software-selectable powerdown output impedances: 100kΩ, 1kΩ, and high impedance. Other features include internal precision Rail-to-Rail® output buffers and a power-on reset (POR) circuit that powers up the DAC in the 100kΩ powerdown mode. MAX5821 Dual, 10-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC ABSOLUTE MAXIMUM RATINGS VDD, SCL, SDA to GND ............................................-0.3V to +6V OUT_, REF, ADD to GND..............................-0.3V to VDD + 0.3V Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +70°C) 8-Pin µMAX (derate 4.5mW above +70°C) ...................362mW Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Maximum Junction Temperature .....................................+150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +2.7V to +5.5V, GND = 0, VREF = VDD, RL = 5kΩ, CL = 200pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +5V, TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ±0.5 ±4 LSB ±0.5 LSB STATIC ACCURACY (NOTE 2) Resolution N 10 Integral Nonlinearity INL (Note 3) Differential Nonlinearity DNL Guaranteed monotonic (Note 2) Zero-Code Error ZCE Code = 000 hex, VDD = 2.7V 6 Zero-Code Error Tempco Gain Error 40 GE Code = 3FF hex -0.8 PSRR Code = 3FF hex, VDD = 4.5V to 5.5V DC Crosstalk mV ppm/oC 2.3 Gain-Error Tempco Power-Supply Rejection Ratio Bits -3 %FSR 0.26 ppm/oC 58.8 dB 30 µV REFERENCE INPUT Reference Input Voltage Range VREF 0 Reference Input Impedance 65 Reference Current Power-down mode VDD 90 0.3 V kΩ 1 µA VDD V DAC OUTPUT Output-Voltage Range No load (Note 4) DC Output Impedance Code = 200 hex 1.2 VDD = 5V, VOUT = full scale (short to GND) 42.2 VDD = 3V, VOUT = full scale (short to GND) 15.1 Short-Circuit Current Wake-Up Time 0 VDD = 5V 8 VDD = 3V 8 Power-down mode = high impedance, VDD = 5.5V, VOUT_ = VDD to GND DAC Output Leakage Current ±0.1 Ω mA µs ±1 µA DIGITAL INPUTS (SCL, SDA) Input High Voltage VIH Input Low Voltage VIL 2 0.7 ✕ VDD _______________________________________________________________________________________ V 0.3 ✕ VDD V Dual, 10-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC (VDD = +2.7V to +5.5V, GND = 0, VREF = VDD, RL = 5kΩ, CL = 200pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +5V, TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX 0.05 ✕ VDD Input Hysteresis Input Leakage Current V ±0.1 Digital inputs = 0 or VDD Input Capacitance UNITS ±1 6 µA pF DIGITAL OUTPUT (SDA) Output Logic Low Voltage Three-State Leakage Current VOL IL ISINK = 3mA ±0.1 Digital inputs = 0 or VDD Three-State Output Capacitance 0.4 V ±1 µA 6 pF 0.5 V/µs DYNAMIC PERFORMANCE Voltage-Output Slew Rate SR Voltage-Output Settling Time To 1/2LSB code 100 hex to 300 hex or 300 hex to 100 hex (Note 5) Digital Feedthrough Code = 000 hex, digital inputs from 0 to VDD 0.2 nV-s Digital-to-Analog Glitch Impulse Major carry transition (code = 1FF hex to 200 hex and 200 hex to 1FF hex) 12 nV-s 2.4 nV-s 4 DAC-to-DAC Crosstalk 12 µs POWER SUPPLIES Supply Voltage Range VDD Supply Current with No Load IDD Power-Down Supply Current IDDPD 2.7 5.5 V All digital inputs at 0 or VDD = 3.6V 115 205 All digital inputs at 0 or VDD = 5.5V 135 215 All digital inputs at 0 or VDD = 5.5V 0.3 1 µA 400 kHz µA TIMING CHARACTERISTICS (FIGURE 1) Serial Clock Frequency fSCL 0 Bus Free Time Between STOP and START Conditions tBUF 1.3 µs START Condition Hold Time tHD,STA 0.6 µs SCL Pulse Width Low tLOW 1.3 µs SCL Pulse Width High tHIGH 0.6 µs Repeated START Setup Time tSU,STA 0.6 Data Hold Time tHD,DAT 0 Data Setup Time tSU,DAT 100 µs 0.9 µs ns SDA and SCL Receiving Rise Time tr (Note 5) 0 300 ns SDA and SCL Receiving Fall Time tf (Note 5) 0 300 ns SDA Transmitting Fall Time tf (Note 5) 20 + 0.1Cb 250 ns _______________________________________________________________________________________ 3 MAX5821 ELECTRICAL CHARACTERISTICS (continued) ELECTRICAL CHARACTERISTICS (continued) (VDD = +2.7V to +5.5V, GND = 0, VREF = VDD, RL = 5kΩ, CL = 200pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +5V, TA = +25°C.) (Note 1) PARAMETER SYMBOL STOP Condition Setup Time Cb Maximum Duration of Suppressed Pulse Widths tSP Note 1: Note 2: Note 3: Note 4: Note 5: CONDITIONS MIN tSU,STO Bus Capacitance TYP MAX UNITS 0.6 µs (Note 5) 400 pF 50 ns 0 All devices are 100% production tested at TA = +25°C and are guaranteed by design for TA = TMIN to TMAX. Static specifications are tested with the output unloaded. Linearity is guaranteed from codes 115 to 3981. Offset and gain error limit the FSR. Guaranteed by design. Not production tested. Typical Operating Characteristics (VDD = +5V, RL = 5kΩ, TA = +25°C.) 1.00 MAX5821 toc03 0.75 1.25 MAX5821 toc02 1.25 MAX5821 toc01 1.00 INTEGRAL NONLINEARITY vs. TEMPERATURE INTEGRAL NONLINEARITY vs. SUPPLY VOLTAGE INTEGRAL NONLINEARITY vs. INPUT CODE 1.00 0 -0.25 -0.50 0.75 INL (LSB) 0.25 INL (LSB) INL (LSB) 0.50 0.50 0.75 0.50 0.25 0.25 -0.75 0 0 -1.00 256 512 768 2.7 1024 3.4 4.1 4.8 -40 5.5 -15 10 35 60 INPUT CODE SUPPLY VOLTAGE (V) TEMPERATURE (°C) DIFFERENTIAL NONLINEARITY vs. INPUT CODE DIFFERENTIAL NONLINEARITY vs. SUPPLY VOLTAGE DIFFERENTIAL NONLINEARITY vs. TEMPERATURE 0.75 0 -0.1 85 MAX5821 toc06 0 MAX5821 toc04 1.00 MAX5821 toc05 0 -0.1 0.50 0 -0.25 -0.50 -0.2 DNL (LSB) 0.25 DNL (LSB) DNL (LSB) MAX5821 Dual, 10-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC -0.3 -0.4 -0.2 -0.3 -0.4 -0.75 -0.5 -1.00 0 256 512 INPUT CODE 4 768 1024 -0.5 2.7 3.4 4.1 SUPPLY VOLTAGE (V) 4.8 5.5 -40 -15 10 35 TEMPERATURE (°C) _______________________________________________________________________________________ 60 85 Dual, 10-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC ZERO-CODE ERROR vs. TEMPERATURE 4 2 6 4 2 3.4 4.1 4.8 5.5 10 35 60 85 2.7 3.4 4.1 5.5 4.8 SUPPLY VOLTAGE (V) GAIN ERROR vs. TEMPERATURE DAC OUTPUT VOLTAGE vs. OUTPUT SOURCE CURRENT (NOTE 6) DAC OUTPUT VOLTAGE vs. OUTPUT SINK CURRENT (NOTE 6) -0.8 -0.4 4 3 2 2.0 1 -15 10 35 60 1.5 CODE = 100 hex 1.0 0.5 CODE = 3FF hex NO LOAD 0 MAX5821 toc12 5 DAC OUTPUT VOLTAGE (V) -1.2 2.5 MAX5821 toc11 MAX5821 toc10 6 DAC OUTPUT VOLTAGE (V) 0 0 0 85 2 4 6 10 8 0 2 4 6 OUTPUT SOURCE CURRENT (mA) OUTPUT SINK CURRENT (mA) SUPPLY CURRENT vs. INPUT CODE SUPPLY CURRENT vs. TEMPERATURE SUPPLY CURRENT vs. SUPPLY VOLTAGE 140 120 100 160 SUPPLY CURRENT (µA) SUPPLY CURRENT (µA) 160 140 120 410 615 INPUT CODE 820 1024 160 140 120 CODE = 3FF hex NO LOAD NO LOAD CODE = 3FF hex 100 205 180 MAX5821 toc15 180 MAX5821 toc13 180 10 8 TEMPERATURE (°C) MAX5821 toc14 GAIN ERROR (%FSR) -15 TEMPERATURE (°C) -1.6 0 NO LOAD 0 -40 SUPPLY VOLTAGE (V) -2.0 -40 -0.8 NO LOAD 0 2.7 -1.2 -0.4 NO LOAD 0 SUPPLY CURRENT (µA) -1.6 GAIN ERROR (%FSR) 6 -2.0 MAX5821 toc08 8 ZERO-CODE ERROR (mV) ZERO-CODE ERROR (mV) 8 GAIN ERROR vs. SUPPLY VOLTAGE 10 MAX5821 toc07 10 MAX5821 toc09 ZERO-CODE ERROR vs. SUPPLY VOLTAGE 100 -40 -15 10 35 TEMPERATURE (°C) 60 85 2.7 3.4 4.1 4.8 5.5 SUPPLY VOLTAGE (V) _______________________________________________________________________________________ 5 MAX5821 Typical Operating Characteristics (continued) (VDD = +5V, RL = 5kΩ, TA = +25°C.) Typical Operating Characteristics (continued) (VDD = +5V, RL = 5kΩ, TA = +25°C.) POWER-DOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE POWER-UP GLITCH EXITING SHUTDOWN MAX5821 toc17 MAX5821 toc16 500 ZOUT = HIGH IMPEDANCE NO LOAD POWER-DOWN SUPPLY CURRENT (nA) MAX5821 Dual, 10-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC 400 300 MAX5821 toc18 5V VDD TA = -40°C TA = +25°C 0 500mV/div OUT_ 200 10mV/div OUT_ 100 TA = +85°C CLOAD = 200pF CODE = 200 hex 0 2.7 3.4 4.1 5.5 4.8 100µs/div 2µs/div MAJOR CARRY TRANSITION (NEGATIVE) SETTLING TIME (POSITIVE) SUPPLY VOLTAGE (V) MAJOR CARRY TRANSITION (POSITIVE) MAX5821 toc19 MAX5821 toc20 5mV/div OUT_ OUT_ MAX5821 toc21 5mV/div OUT_ CLOAD = 200pF RL = 5kΩ CODE = 1FF hex TO 200 hex CLOAD = 200pF RL = 5kΩ CODE = 200 hex TO 1FF hex 2µs/div CLOAD = 200pF CODE = 100 hex TO 300 hex 2µs/div SETTLING TIME (NEGATIVE) 2µs/div DIGITAL FEEDTHROUGH MAX5821 toc22 500mV/div CROSSTALK MAX5821 toc23 MAX5821 toc24 SCL 2V/div VOUTA 2V/div OUT_ V 2mV/div OUTB 1mV/div 500mV/div OUT_ CLOAD = 200pF fSCL = 12kHz CODE = 000 hex CLOAD = 200pF CODE = 300 hex TO 100 hex 2µs/div 40µs/div 4µs/div Note 6: The ability to drive loads greater than 5kΩ is not implied. 6 _______________________________________________________________________________________ Dual, 10-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC PIN NAME FUNCTION 1 VDD Power Supply 2 GND Ground 3 ADD Address Select. A logic high sets the address LSB to 1; a logic low sets the address LSB to zero. 4 SCL Serial Clock Input 5 SDA Bidirectional Serial Data Interface 6 REF Reference Input 7 OUTA DAC A Output 8 OUTB DAC B Output Detailed Description The MAX5821 is a dual, 10-bit, voltage-output DAC with an I2C/SMBus-compatible 2-wire interface. The device consists of a serial interface, power-down circuitry, dual input and DAC registers, two 10-bit resistor string DACs, two unity-gain output buffers, and output resistor networks. The serial interface decodes the address and control bits, routing the data to the proper input or DAC register. Data can be directly written to the DAC register, immediately updating the device output, or can be written to the input register without changing the DAC output. Both registers retain data as long as the device is powered. DAC Operation The MAX5821 uses a segmented resistor string DAC architecture, which saves power in the overall system and guarantees output monotonicity. The MAX5821’s input coding is straight binary, with the output voltage given by the following equation: with the output buffers disabled and the outputs pulled to GND through the 100kΩ termination resistor. Following power-up, a wake-up command must be initiated before any conversions are performed. Power-Down Modes The MAX5821 has three software-controlled low-power power-down modes. All three modes disable the output buffers and disconnect the DAC resistor strings from REF, reducing supply current draw to 1µA and the reference current draw to less than 1µA. In power-down mode 0, the device output is high impedance. In power-down mode 1, the device output is internally pulled to GND by a 1kΩ termination resistor. In powerdown mode 2, the device output is internally pulled to GND by a 100kΩ termination resistor. Table 1 shows the power-down mode command words. Upon wake-up, the DAC output is restored to its previous value. Data is retained in the input and DAC registers during power-down mode. Digital Interface V × (D) VOUT _ = REF N 2 where N = 10 (bits), and D = the decimal value of the input code (0 to 1023). Output Buffer The MAX5821 analog outputs are buffered by precision, unity-gain followers that slew 0.5V/µs. Each buffer output swings rail-to-rail, and is capable of driving 5kΩ in parallel with 200pF. The output settles to ±0.5LSB within 4µs. Power-On Reset The MAX5821 features an internal POR circuit that initializes the device upon power-up. The DAC registers are set to zero scale and the device is powered down, The MAX5821 features an I2C/SMBus-compatible 2wire interface consisting of a serial data line (SDA) and a serial clock line (SCL). The MAX5821 is SMBus compatible within the range of VDD = 2.7V to 3.6V. SDA and SCL facilitate bidirectional communication between the MAX5821 and the master at rates up to 400kHz. Figure 1 shows the 2-wire interface timing diagram. The MAX5821 is a transmit/receive slave-only device, relying upon a master to generate a clock signal. The master (typically a microcontroller) initiates data transfer on the bus and generates SCL to permit that transfer. A master device communicates to the MAX5821 by transmitting the proper address followed by command and/or data words. Each transmit sequence is framed by a START (S) or REPEATED START (Sr) condition and a STOP (P) condition. Each word transmitted over the _______________________________________________________________________________________ 7 MAX5821 Pin Description MAX5821 Dual, 10-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC START and STOP Conditions When the serial interface is inactive, SDA and SCL idle high. A master device initiates communication by issuing a START condition. A START condition is a high-tolow transition on SDA with SCL high. A STOP condition is a low-to-high transition on SDA, while SCL is high (Figure 2). A START condition from the master signals the beginning of a transmission to the MAX5821. The master terminates transmission by issuing a not acknowledge followed by a STOP condition (see Acknowledge Bit (ACK)). The STOP condition frees the bus. If a repeated START condition (Sr) is generated instead of a STOP condition, the bus remains active. When a STOP condition or incorrect address is detected, the MAX5821 internally disconnects SCL from the serial interface until the next START condition, minimizing digital noise and feedthrough. Table 1. Power-Down Command Bits POWER-DOWN COMMAND BITS MODE/FUNCTION PD1 PD0 0 0 Power-up device. DAC output restored to previous value. 0 1 Power-down mode 0. Power down device with output floating. 1 0 Power-down mode 1. Power down device with output terminated with 1kΩ to GND. 1 1 Power-down mode 2. Power down device with output terminated with 100kΩ to GND. bus is 8 bits long and is always followed by an acknowledge clock pulse. The MAX5821 SDA and SCL drivers are open-drain outputs, requiring a pullup resistor to generate a logic high voltage (see the Typical Operating Circuit). Series resistors RS are optional. These series resistors protect the input stages of the MAX5821 from high-voltage spikes on the bus lines, and minimize crosstalk and undershoot of the bus signals. Bit Transfer One data bit is transferred during each SCL clock cycle. The data on SDA must remain stable during the high period of the SCL clock pulse. Changes in SDA while SCL is high are control signals (see the START and STOP Conditions section). Both SDA and SCL idle high when the I2C bus is not busy. Early STOP Conditions The MAX5821 recognizes a STOP condition at any point during transmission except if a STOP condition occurs in the same high pulse as a START condition (Figure 3). This condition is not a legal I2C format; at least one clock pulse must separate any START and STOP conditions. Repeated START Conditions A repeated START (S r ) condition may indicate a change of data direction on the bus. Such a change occurs when a command word is required to initiate a read operation. S r may also be used when the bus master is writing to several I2C devices and does not want to relinquish control of the bus. The MAX5821 serial interface supports continuous write operations with or without an Sr condition separating them. Continuous read operations require Sr conditions because of the change in direction of data flow. SDA tSU, DAT tBUF tSU, STA tHD, STA tLOW tHD, DAT tSP tSU, STO SCL tHIGH tHD, STA tR tF START CONDITION REPEATED START CONDITION STOP CONDITION Figure 1. 2-Wire Serial Interface Timing Diagram 8 _______________________________________________________________________________________ START CONDITION Dual, 10-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC Sr P SCL SDA Figure 2. START and STOP Conditions SCL waits for a START condition followed by its slave address. The serial interface compares each address value bit-by-bit, allowing the interface to power down immediately if an incorrect address is detected. The LSB of the address word is the Read/Write (R/W) bit. R/W indicates whether the master is writing to or reading from the MAX5821 (R/W = 0 selects the write condition, R/W = 1 selects the read condition). After receiving the proper address, the MAX5821 issues an ACK by pulling SDA low for one clock cycle. The MAX5821 has four different factory/user-programmed addresses (Table 2). Address bits A6 through A1 are preset, while A0 is controlled by ADD. Connecting ADD to GND sets A0 = 0. Connecting ADD to V DD sets A0 = 1. This feature allows up to four MAX5821s to share the same bus. Table 2. MAX5821 I2C Slave Addresses SDA STOP PART VADD DEVICE ADDRESS (A6...A0) MAX5821L GND 0111 000 0111 001 START LEGAL STOP CONDITION SCL MAX5821L VDD MAX5821M GND 1011 000 MAX5821M VDD 1011 001 SDA START ILLEGAL STOP ILLEGAL EARLY STOP CONDITION Figure 3. Early STOP conditions Acknowledge Bit (ACK) The acknowledge bit (ACK) is the ninth bit attached to any 8-bit data word. ACK is always generated by the receiving device. The MAX5821 generates an ACK when receiving an address or data by pulling SDA low during the ninth clock period. When transmitting data, the MAX5821 waits for the receiving device to generate an ACK. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master should reattempt communication at a later time. Slave Address A bus master initiates communication with a slave device by issuing a START condition followed by the 7bit slave address (Figure 4). When idle, the MAX5821 Write Data Format In write mode (R/W = 0), data that follows the address byte controls the MAX5821 (Figure 5). Bits C3–C0 configure the MAX5821 (Table 3). Bits D9–D0 are DAC data. Bits S0 and S1 are sub-bits and are always 0. Input and DAC registers update on the falling edge of SCL during the acknowledge bit. Should the write cycle be prematurely aborted, data is not updated and the write cycle must be repeated. Figure 6 shows two example-write data sequences. Extended Command Mode The MAX5821 features an extended command mode that is accessed by setting C3–C0 = 1 and D9–D6 = 0. S A6 A5 A4 A3 A2 A1 R/W A0 Figure 4. Slave Address Byte Definition C3 C2 C1 C0 D9 D8 D7 D6 Figure 5. Command Byte Definition _______________________________________________________________________________________ 9 MAX5821 S MAX5821 Dual, 10-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC MSB S LSB A6 A5 A4 A3 A2 A1 A0 R/W MSB D5 MSB ACK C3 LSB C2 C1 C0 D9 D8 D7 D6 ACK LSB D4 D3 D2 D1 D0 S1 S0 ACK P EXAMPLE-WRITE DATA SEQUENCE MSB S LSB A6 A5 A4 A3 A2 A1 A0 R/W MSB X MSB ACK C3 LSB C2 C1 C0 D9 D8 D7 D6 ACK LSB X X X B A PD1 PD0 ACK P EXAMPLE-WRITE TO POWER-DOWN REGISTER SEQUENCE Figure 6. Example-Write Command Sequences The next command word writes to the power-down registers (Figure 7). Setting bits A or B to 1 sets that DAC to the selected power-down mode based on the states of PD0 and PD1 (Table 1). Any combination of the DACs can be controlled with a single write sequence. Read Data Format In read mode (R/W = 1), the MAX5821 writes the contents of the DAC register to the bus. The direction of data flow reverses following the address acknowledge by the MAX5821. The device transmits the first byte of data, waits for the master to acknowledge, then transmits the second byte. Figure 8 shows an example-read data sequence. I2C Compatibility The MAX5821 is compatible with existing I2C systems. SCL and SDA are high-impedance inputs; SDA has an open drain that pulls the data line low during the ninth clock pulse. The Typical Operating Circuit shows a typical I2C application. The communication protocol supports the standard I 2 C 8-bit communications. The general call address is ignored. The MAX5821 address is compatible with the 7-bit I2C addressing protocol only. No 10-bit address formats are supported. Digital Feedthrough Suppression When the MAX5821 detects an address mismatch, the serial interface disconnects the SCL signal from the 10 X X X X B A PD1 PD0 Figure 7. Extended Command Byte Format core circuitry. This minimizes digital feedthrough caused by the SCL signal on a static output. The serial interface reconnects the SCL signal once a valid START condition is detected. Applications Information Digital Inputs and Interface Logic The MAX5821 2-wire digital interface is I 2C/SMBus compatible. The two digital inputs (SCL and SDA) load the digital input serially into the DAC. Schmitt-trigger buffered inputs allow slow-transition interfaces, such as optocouplers to interface directly to the device. The digital inputs are compatible with CMOS logic levels. Power-Supply Bypassing and Ground Management Careful PC board layout is important for optimal system performance. Keep analog and digital signals separate to reduce noise injection and digital feedthrough. Use a ground plane to ensure that the ground return from GND to the power-supply ground is short and low ______________________________________________________________________________________ Dual, 10-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC MAX5821 impedance. Bypass V DD with a 0.1µF capacitor to ground as close to the device as possible. Chip Information TRANSISTOR COUNT: 11,186 PROCESS: BiCMOS Table 3. Command Byte Definitions SERIAL DATA INPUT FUNCTION C3 C2 C1 C0 D9 D8 D7 D6 0 0 0 0 DAC DATA DAC DATA DAC DATA DAC DATA Load DAC A input and DAC registers with new data. Contents of DAC B input registers are transferred to the DAC register. All outputs are updated. 0 0 0 1 DAC DATA DAC DATA DAC DATA DAC DATA Load DAC B input and DAC registers with new data. Contents of DAC A input registers are transferred to the DAC register. All outputs are updated. 0 1 0 0 DAC DATA DAC DATA DAC DATA DAC DATA Load DAC A input register with new data. DAC outputs remain unchanged. 0 1 0 1 DAC DATA DAC DATA DAC DATA DAC DATA Load DAC B input register with new data. DAC outputs remain unchanged. 1 0 0 0 DAC DATA DAC DATA DAC DATA DAC DATA Data in all input registers is transferred to respective DAC registers. All DAC outputs are updated simultaneously. New data is loaded into DAC A input register. 1 0 0 1 DAC DATA DAC DATA DAC DATA DAC DATA Data in all input registers is transferred to respective DAC registers. All DAC outputs are updated simultaneously. New data is loaded into DAC B input register. 1 1 0 0 DAC DATA DAC DATA DAC DATA DAC DATA Load all DACs with new data and update all DAC outputs simultaneously. Both input and DAC registers are updated with new data. 1 1 0 1 DAC DATA DAC DATA DAC DATA DAC DATA Load all input registers with new data. DAC outputs remain unchanged. 1 1 1 0 X X X X Update all DAC outputs simultaneously. Device ignores D9–D6. Do not send the data byte. 1 1 1 1 0 0 0 0 Extended command mode. The next word writes to the power-down registers (Extended Command Mode). 1 1 1 1 0 0 0 1 Read DAC A data. The device expects an Sr condition followed by an address word with R/W = 1. 1 1 1 1 0 0 1 0 Read DAC B data. The device expects an Sr condition followed by an address word with R/W = 1. ______________________________________________________________________________________ 11 MAX5821 Dual, 10-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC MSB S A6 LSB A4 A5 A3 A2 A1 MSB R/W =0 A0 LSB C3 ACK C2 C1 C0 D9 D8 D7 D6 ACK DATA BYTES GENERATED BY MASTER DEVICE Sr MSB LSB A6 R/W =1 A4 A5 A3 A2 A1 A0 MSB ACK X DATA BYTES GENERATED BY MAX5821 MSB D5 LSB X PD1 PD0 D9 D8 D7 D6 ACK ACK GENERATED BY MASTER DEVICE LSB D4 D3 D2 D1 D0 S1 S0 ACK P Figure 8. Example-Read Word Data Sequence Functional Diagram REF INPUT REGISTER A 10-BIT DAC A MUX AND DAC REGISTER MAX5821 OUTA RESISTOR NETWORK INPUT REGISTER B 10-BIT DAC B MUX AND DAC REGISTER OUTB RESISTOR NETWORK SERIAL INTERFACE SDA 12 ADD SCL POWER-DOWN CIRCUITRY VDD GND ______________________________________________________________________________________ Dual, 10-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC 8LUMAXD.EPS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13 © 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX5821 Package Information