19-3502; Rev 5; 5/07 125V/2A, High-Speed, Half-Bridge MOSFET Drivers Features The MAX5062/MAX5063/MAX5064 high-frequency, 125V half-bridge, n-channel MOSFET drivers drive highand low-side MOSFETs in high-voltage applications. These drivers are independently controlled and their 35ns typical propagation delay, from input to output, are matched to within 3ns (typ). The high-voltage operation with very low and matched propagation delay between drivers, and high source/sink current capabilities in a thermally enhanced package make these devices suitable for the high-power, high-frequency telecom power converters. The 125V maximum input voltage range provides plenty of margin over the 100V input transient requirement of telecom standards. A reliable on-chip bootstrap diode connected between VDD and BST eliminates the need for an external discrete diode. The MAX5062A/C and the MAX5063A/C offer both noninverting drivers (see the Selector Guide). The MAX5062B/D and the MAX5063B/D offer a noninverting high-side driver and an inverting low-side driver. The MAX5064A/B offer two inputs per driver that can be either inverting or noninverting. The MAX5062A/B/C/D and the MAX5064A feature CMOS (VDD / 2) logic inputs. The MAX5063A/B/C/D and the MAX5064B feature TTL logic inputs. The MAX5064A/B include a break-beforemake adjustment input that sets the dead time between drivers from 16ns to 95ns. The drivers are available in the industry-standard 8-pin SO footprint and pin configuration, and a thermally enhanced 8-pin SO and 12-pin (4mm x 4mm) thin QFN packages. All devices operate over the -40°C to +125°C automotive temperature range. ♦ HIP2100/HIP2101 Pin Compatible (MAX5062A/ MAX5063A) ♦ Up to 125V Input Operation ♦ 8V to 12.6V VDD Input Voltage Range ♦ 2A Peak Source and Sink Current Drive Capability ♦ 35ns Typical Propagation Delay ♦ Guaranteed 8ns Propagation Delay Matching Between Drivers ♦ Programmable Break-Before-Make Timing (MAX5064) ♦ Up to 1MHz Combined Switching Frequency while Driving 100nC Gate Charge (MAX5064) ♦ Available in CMOS (VDD / 2) or TTL Logic-Level Inputs with Hysteresis ♦ Up to 15V Logic Inputs Independent of Input Voltage ♦ Low 2.5pF Input Capacitance ♦ Instant Turn-Off of Drivers During Fault or PWM Start-Stop Synchronization (MAX5064) ♦ Low 200µA Supply Current ♦ Versions Available With Combination of Noninverting and Inverting Drivers (MAX5062B/D and MAX5063B/D) ♦ Available in 8-Pin SO, Thermally Enhanced SO, and 12-Pin Thin QFN Packages Ordering Information Applications Telecom Half-Bridge Power Supplies Two-Switch Forward Converters PART TEMP RANGE PINTOP PKG PACKAGE MARK CODE MAX5062AASA -40°C to +125°C 8 SO — S8-5 MAX5062BASA -40°C to +125°C 8 SO — S8-5 MAX5062CASA -40°C to +125°C 8 SO-EP* — S8E-14 Active-Clamp Forward Converters MAX5062DASA -40°C to +125°C 8 SO-EP* — S8E-14 Power-Supply Modules *EP = Exposed paddle. Devices are available in both leaded and lead-free packaging. Specify lead-free by replacing “-T” with “+T” when ordering. Ordering Information continued at end of data sheet. Full-Bridge Converters Motor Control Selector Guide PART HIGH-SIDE DRIVER LOW-SIDE DRIVER LOGIC LEVELS PIN COMPATIBLE MAX5062AASA MAX5062BASA Noninverting Noninverting Noninverting Inverting CMOS (VDD / 2) CMOS (VDD / 2) HIP 2100IB — MAX5062CASA Noninverting Noninverting CMOS (VDD / 2) — MAX5062DASA Noninverting Inverting CMOS (VDD / 2) — Selector Guide continued at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX5062/MAX5063/MAX5064 General Description MAX5062/MAX5063/MAX5064 125V/2A, High-Speed, Half-Bridge MOSFET Drivers ABSOLUTE MAXIMUM RATINGS (All voltages referenced to GND, unless otherwise noted.) VDD, IN_H, IN_L, IN_L+, IN_L-, IN_H+, IN_H-........-0.3V to +15V DL, BBM .....................................................-0.3V to (VDD + 0.3V) HS............................................................................-5V to +130V DH to HS.....................................................-0.3V to (VDD + 0.3V) BST to HS ...............................................................-0.3V to +15V AGND to PGND (MAX5064) ..................................-0.3V to +0.3V dV/dt at HS ........................................................................50V/ns Continuous Power Dissipation (TA = +70°C) 8-Pin SO (derate 5.9mW/°C above +70°C)...............470.6mW 8-Pin SO with Exposed Pad (derate 19.2mW/°C above +70°C)* ....................................................1538.5mW 12-Pin Thin QFN (derate 24.4mW/°C above +70°C)* ....................................................1951.2mW Maximum Junction Temperature .....................................+150°C Operating Temperature Range .........................-40°C to +125°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C *Per JEDEC 51 standard multilayer board. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = VBST = +8V to +12.6V, VHS = GND = 0V, BBM = open, TA = -40°C to +125°C, unless otherwise noted. Typical values are at VDD = VBST = +12V and TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 12.6 V POWER SUPPLIES Operating Supply Voltage VDD Quiescent Supply Current VDD (Note 2) IDD IN_H = IN_L = GND (no switching) 8.0 MAX5062_/ MAX5063_ 70 140 MAX5064_ 120 260 3 mA 15 40 µA VDD Operating Supply Current IDDO fSW = 500kHz, VDD = +12V BST Quiescent Supply Current IBST IN_H = IN_L = GND (no switching) IBSTO fSW = 500kHz, VDD = VBST = +12V BST Operating Supply Current µA 3 mA UVLO (VDD to GND) UVLOVDD VDD rising 6.5 7.3 8.0 V UVLO (BST to HS) UVLOBST BST rising 6.0 6.9 7.8 V UVLO Hysteresis 0.5 V 0.67 x VDD 0.55 x VDD V 2 1.65 LOGIC INPUT Input-Logic High VIH_ MAX5062_/MAX5064A, CMOS (VDD / 2) version MAX5063_/MAX5064B, TTL version Input-Logic Low Logic-Input Hysteresis 2 VIL_ VHYS 0.4 x VDD 0.33 x VDD MAX5063_/MAX5064B, TTL version 1.4 0.8 MAX5062_/MAX5064A, CMOS (VDD / 2) version 1.6 MAX5063_/MAX5064B, TTL version 0.25 MAX5062_/MAX5064A, CMOS (VDD / 2) version _______________________________________________________________________________________ V V 125V/2A, High-Speed, Half-Bridge MOSFET Drivers (VDD = VBST = +8V to +12.6V, VHS = GND = 0V, BBM = open, TA = -40°C to +125°C, unless otherwise noted. Typical values are at VDD = VBST = +12V and TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS -1 0.001 +1 µA VIN_H+, VIN_L+ = 0V Logic-Input Current I_IN VIN_L = VDD for MAX5062B/D, MAX5063B/D VIN_H-, VIN_L-, VIN_H = VDD VIN_L = 0V for MAX5062A/C, MAX5063A/C IN_H+, IN_L+ IN_H, to GND Input Resistance RIN IN_L to VDD for MAX5062B/D, MAX5063B/D 1 MΩ 2.5 pF IN_H-, IN_L-, IN_H, to VDD IN_L for MAX5062A/C, MAX5063A/C to GND Input Capacitance CIN HIGH-SIDE GATE DRIVER HS Maximum Voltage VHS_MAX 125 V BST Maximum Voltage VBST_MAX 140 V Driver Output Resistance (Sourcing) RON_HP VDD = 12V, IDH = 100mA (sourcing) Driver Output Resistance (Sinking) RON_HN VDD = 12V, IDH = 100mA (sinking) TA = +25°C 2.5 3.3 TA = +125°C 3.5 4.6 TA = +25°C 2.1 2.8 TA = +125°C 3.2 4.2 DH Reverse Current (Latchup Protection) (Note 3) Power-Off Pulldown Clamp Voltage VBST = 0V or floating, IDH = 1mA (sinking) Peak Output Current (Sourcing) Peak Output Current (Sinking) IDH_PEAK 400 Ω Ω mA 0.94 1.16 V CL = 10nF, VDH = 0V 2 A CL = 10nF, VDH = 12V 2 A LOW-SIDE GATE DRIVER Driver Output Resistance (Sourcing) RON_LP VDD = 12V, IDL = 100mA (sourcing) TA = +25°C 2.5 3.3 TA = +125°C 3.5 4.6 Driver Output Resistance (Sinking) RON_LN VDD = 12V, IDL = 100mA (sinking) TA = +25°C 2.1 2.8 TA = +125°C 3.2 4.2 Reverse Current at DL (Latchup Protection) (Note 3) Power-Off Pulldown Clamp Voltage VDD = 0V or floating, IDL = 1mA (sinking) 400 Ω Ω mA 0.95 1.16 V Peak Output Current (Sourcing) IPK_LP CL = 10nF, VDL = 0V 2 A Peak Output Current (Sinking) IPK_LN CL = 10nF, VDL = 12V 2 A INTERNAL BOOTSTRAP DIODE Forward Voltage Drop Vf IBST = 100mA 0.91 Turn-On and Turn-Off Time tR IBST = 100mA 40 1.11 V ns _______________________________________________________________________________________ 3 MAX5062/MAX5063/MAX5064 ELECTRICAL CHARACTERISTICS (continued) MAX5062/MAX5063/MAX5064 125V/2A, High-Speed, Half-Bridge MOSFET Drivers ELECTRICAL CHARACTERISTICS (continued) (VDD = VBST = +8V to +12.6V, VHS = GND = 0V, BBM = open, TA = -40°C to +125°C, unless otherwise noted. Typical values are at VDD = VBST = +12V and TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SWITCHING CHARACTERISTICS FOR HIGH- AND LOW-SIDE DRIVERS (VDD = VBST = +12V) Rise Time Fall Time tR tF CL = 1000pF 7 CL = 5000pF 33 CL = 10,000pF 65 CL = 1000pF 7 CL = 5000pF 33 CL = 10,000pF 65 ns ns Turn-On Propagation Delay Time tD_ON Figure 1, CL = 1000pF (Note 3) CMOS 30 55 TTL 35 63 Turn-Off Propagation Delay Time tD_OFF Figure 1, CL = 1000pF (Note 3) CMOS 30 55 TTL 35 63 ns ns Delay Matching Between Inverting Input to Output and Noninverting Input to Output tMATCH1 CL = 1000pF, BBM open for MAX5064, Figure 1 (Note 3) 2 8 ns Delay Matching Between DriverLow and Driver-High tMATCH2 CL = 1000pF, BBM open for MAX5064, Figure 1 (Note 3) 2 8 ns 72 ns RBBM = 10kΩ Break-Before-Make Accuracy (MAX5064 Only) RBBM = 47kΩ (Notes 3, 4) 16 40 RBBM = 100kΩ 95 VDD = VBST = 12V 135 VDD = VBST = 8V 170 Internal Nonoverlap Minimum Pulse-Width Input Logic (High or Low) (Note 5) Note 1: Note 2: Note 3: Note 4: Note 5: 4 56 1 tPW-MIN All devices are 100% tested at TA = +125°C. Limits over temperature are guaranteed by design. Ensure that the VDD-to-GND or BST-to-HS voltage does not exceed 13.2V. Guaranteed by design, not production tested. Break-before-make time is calculated by tBBM = 8ns x (1 + RBBM / 10kΩ). See the Minimum Pulse Width section. _______________________________________________________________________________________ ns ns 125V/2A, High-Speed, Half-Bridge MOSFET Drivers UNDERVOLTAGE LOCKOUT (VDD AND VBST RISING) vs. TEMPERATURE 7.3 7.0 UVLOBST 6.8 0.8 0.7 MAX5064 IN_L-, IN_H- = VDD IN_L+, IN_H+ = GND 2V/div VDD UVLOVDD HYSTERESIS 0.6 0.5 UVLOBST HYSTERESIS 0.4 0V 0.3 6.7 0.2 500μA/div 6.6 0.1 0A IDD 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) INTERNAL BST DIODE (I-V) CHARACTERISTICS 200 MAX5062/3/4 toc04 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 180 TA = +25°C 140 TA = 0°C 120 TA = -40°C 100 80 60 40 20 0 0.5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 VDD (V) 140 TA = +125°C 120 0.8 0.9 1.0 1.1 21 18 VBST = VDD + 1V, NO SWITCHING 15 IBST (μA) TA = +25°C, TA = 0°C 80 MAX5062/3/4 toc07 MAX5064 0.7 BST QUIESCENT CURRENT vs. BST VOLTAGE MAX5062/3/4 toc06 160 0.6 VDD - VBST (V) VDD QUIESCENT CURRENT vs. VDD (NO SWITCHING) 100 TA = +125°C 160 IDIODE (mA) IDDO + IBSTO (mA) IDDO + IBSTO vs. VDD (fSW = 250kHz) 40μs/div MAX5062/3/4 toc05 6.5 IDD (μA) UVLO (V) 7.1 6.9 0.9 UVLO HYSTERESIS (V) UVLOVDD 7.2 MAX5062/3/4 toc02 7.4 IDD vs. VDD MAX5062/3/4 toc03 1.0 MAX5062/3/4 toc01 7.5 VDD AND BST UNDERVOLTAGE LOCKOUT HYSTERESIS vs. TEMPERATURE 12 TA = +125°C 9 60 TA = -40°C 40 6 20 3 0 0 TA = -40°C, TA = 0°C, TA = +25°C 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VDD (V) VBST (V) _______________________________________________________________________________________ 5 MAX5062/MAX5063/MAX5064 Typical Operating Characteristics (Typical values are at VDD = VBST = +12V and TA = +25°C, unless otherwise specified.) Typical Operating Characteristics (continued) (Typical values are at VDD = VBST = +12V and TA = +25°C, unless otherwise specified.) IDDO + IBSTO (mA) 8 7 6 5 4 3 2 1 0 0.34 0.32 0.30 0.28 0.26 0.24 0.22 0.20 0.18 0.16 0.14 0.12 0.10 MAX5062/3/4 toc09 CL = 0 SINKING 100mA -40 -25 -10 5 20 35 50 65 80 95 110 125 0 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (kHz) TEMPERATURE (°C) PEAK DH AND DL SOURCE/SINK CURRENT DH OR DL RISE TIME vs. TEMPERATURE (CL = 10nF) MAX5062/3/4 toc10 120 CL = 100nF 108 96 DH OR DL 84 tR (ns) 5V/div 72 60 VDD = VBST = 12V 48 SINK AND SOURCE CURRENT 2A/div VDD = VBST = 8V MAX5062/3/4 toc11 9 MAX5062/3/4 toc08 10 DH OR DL OUTPUT LOW VOLTAGE vs. TEMPERATURE OUTPUT LOW VOLTAGE (V) VDD AND BST OPERATING SUPPLY CURRENT vs. FREQUENCY 36 24 12 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 1μs/div TEMPERATURE (°C) 100 90 VDD = VBST = 8V 80 70 60 50 VDD = VBST = 12V 40 30 55 50 45 DH 40 35 30 25 DL 20 15 20 10 10 5 0 6 60 MAX5062/3/4 toc13 110 PROPAGATION DELAY (ns) 120 DH OR DL RISE PROPAGATION DELAY vs. TEMPERATURE MAX5062/3/4 toc12 DH OR DL FALL TIME vs. TEMPERATURE (CLOAD = 10nF) tF (ns) MAX5062/MAX5063/MAX5064 125V/2A, High-Speed, Half-Bridge MOSFET Drivers 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) _______________________________________________________________________________________ 125V/2A, High-Speed, Half-Bridge MOSFET Drivers DH OR DL FALL PROPAGATION DELAY vs. TEMPERATURE PROPAGATION DELAY (ns) DH 45 MAX5064 225 200 175 tBBM (ns) 40 35 30 DL 25 150 125 100 20 75 15 50 10 25 5 0 0 10 -40 -25 -10 5 20 35 50 65 80 95 110 125 90 130 170 210 250 290 RBBM (kΩ) BREAK-BEFORE-MAKE DEAD TIME vs. TEMPERATURE DELAY MATCHING (DH/DL RISING) RBBM = 100kΩ 100 MAX5062/3/4 toc17 MAX5062/3/4 toc16 MAX5064 110 50 TEMPERATURE (°C) 120 90 80 tBBM (ns) MAX5062/3/4 toc15 55 50 250 MAX5062/3/4 toc14 60 BREAK-BEFORE-MAKE DEAD TIME vs. RBBM CL = 0 5V/div INPUT 5V/div DH/DL 70 60 50 40 30 RBBM = 10kΩ 20 10 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 10ns/div TEMPERATURE (°C) DH/DL RESPONSE TO VDD GLITCH DELAY MATCHING (DH/DL FALLING) MAX5062/3/4 toc19 MAX5062/3/4 toc18 CL = 0 5V/div INPUT 5V/div DH/DL 10V/div DH 10V/div DL 10V/div VDD INPUT 5V/div 10ns/div 40μs/div _______________________________________________________________________________________ 7 MAX5062/MAX5063/MAX5064 Typical Operating Characteristics (continued) (Typical values are at VDD = VBST = +12V and TA = +25°C, unless otherwise specified.) 125V/2A, High-Speed, Half-Bridge MOSFET Drivers MAX5062/MAX5063/MAX5064 MAX5062/MAX5063 Pin Description PIN NAME FUNCTION 1 VDD Power Input. Bypass to GND with a parallel combination of 0.1µF and 1µF ceramic capacitor. 2 BST Boost Flying Capacitor Connection. Connect a 0.1µF ceramic capacitor between BST and HS for the high-side MOSFET driver supply. 3 DH High-Side-Gate Driver Output. Driver output for the high-side MOSFET gate. 4 HS Source Connection for High-Side MOSFET. Also serves as a return terminal for the high-side driver. 5 IN_H High-Side Noninverting Logic Input 6 IN_L Low-Side Noninverting Logic Input (MAX5062A/C, MAX5063A/C). Low-side inverting logic input (MAX5062B/D, MAX5063B/D). 7 GND 8 DL Low-Side-Gate Driver Output. Drives low-side MOSFET gate. — EP Exposed Pad. Internally connected to GND. Externally connect the exposed pad to a large ground plane to aid in heat dissipation (MAX5062C/D, MAX5063C/D only). Ground. Use GND as a return path to the DL driver output and IN_H/IN_L inputs. MAX5064 Pin Description 8 PIN NAME FUNCTION 1 BST Boost Flying Capacitor Connection. Connect a 0.1µF ceramic capacitor between BST and HS for the high-side MOSFET driver supply. 2 DH High-Side-Gate Driver Output. Drives high-side MOSFET gate. 3 HS 4 AGND Source Connection for High-Side MOSFET. Also serves as a return terminal for the high-side driver. Analog Ground. Return path for low-switching current signals. IN_H/IN_L inputs referenced to 5 BBM Break-Before-Make Programming Resistor Connection. Connect a 10kΩ to 100kΩ resistor from BBM to AGND to program the break-before-make time (tBBM) from 16ns to 95ns. Resistance values greater than 200kΩ disables the BBM function and makes tBBM = 1ns. Bypass this pin with at least a 1nF capacitor to AGND. 6 IN_H- High-Side Inverting CMOS (VDD / 2) (MAX5064A), or TTL (MAX5064B) Logic Input. Connect to AGND when not used. 7 IN_H+ High-Side Noninverting CMOS (VDD / 2) (MAX5064A), or TTL (MAX5064B) Logic Input. Connect to VDD when not used. 8 IN_L- Low-Side Inverting CMOS (VDD / 2) (MAX5064A), or TTL (MAX5064B) Logic Input. Connect to AGND when not used. 9 IN_L+ Low-Side Noninverting CMOS (VDD / 2) (MAX5064A), or TTL (MAX5064B) Logic Input. Connect to VDD when not used. 10 PGND Power Ground. Return path for high-switching current signals. Use PGND as a return path for the low-side driver. 11 DL Low-Side-Gate Driver Output. Drives the low-side MOSFET gate. 12 VDD Power Input. Bypass to PGND with a 0.1µF ceramic in parallel with a 1µF ceramic capacitor. — EP Exposed Pad. Internally connected to AGND. Externally connect to a large ground plane to aid in heat dissipation. _______________________________________________________________________________________ 125V/2A, High-Speed, Half-Bridge MOSFET Drivers MAX5062/MAX5063/MAX5064 IN_L+ VIH VIL 90% DL 10% tD_OFF1 tD_ON1 tF IN_L- tR VIH VIL tD_OFF2 tD_ON2 VIH IN_H+ VIL 90% DH 10% tD_OFF3 tD_ON3 tF IN_H- tR VIH VIL tD_OFF4 tD_ON4 tMATCH1 = (tD_ON2 - tD_ON1) or (tD_OFF2 - tD_OFF1) tMATCH2 = (tD_ON3 - tD_ON1) or (tD_ON4 - tD_ON2) or (tD_OFF3 - tD_OFF1) or (tD_OFF4 - tD_OFF2) Figure 1. Timing Characteristics for Noninverting and Inverting Logic Inputs Detailed Description The MAX5062/MAX5063/MAX5064 are 125V/2A highspeed, half-bridge MOSFET drivers that operate from a supply voltage of +8V to +12.6V. The drivers are intended to drive a high-side switch without any isolation device like an optocoupler or drive transformer. The high-side driver is controlled by a TTL/CMOS logic signal referenced to ground. The 2A source and sink drive capability is achieved by using low RDS_ON pand n-channel driver output stages. The BiCMOS process allows extremely fast rise/fall times and low propagation delays. The typical propagation delay from the logic-input signal to the drive output is 35ns with a matched propagation delay of 3ns typical. Matching these propagation delays is as important as the absolute value of the delay itself. The high 125V input voltage range allows plenty of margin above the 100V transient specification per telecom standards. The MAX5064 is available in a thermally enhanced TQFN package, which can dissipate up to 1.95W (at +70°C) and allow up to 1MHz switching frequency while driving 100nC combined gate-charge MOSFETs. _______________________________________________________________________________________ 9 MAX5062/MAX5063/MAX5064 125V/2A, High-Speed, Half-Bridge MOSFET Drivers Undervoltage Lockout Internal Bootstrap Diode Both the high- and low-side drivers feature undervoltage lockout (UVLO). The low-side driver’s UVLOLOW threshold is referenced to GND and pulls both driver outputs low when VDD falls below 6.8V. The high-side driver has its own undervoltage lockout threshold (UVLOHIGH), referenced to HS, and pulls DH low when BST falls below 6.4V with respect to HS. During turn-on, once VDD rises above its UVLO threshold, DL starts switching and follows the IN_L logic input. At this time, the bootstrap capacitor is not charged and the BST-to-HS voltage is below UVLOBST. For synchronous buck and half-bridge converter topologies, the bootstrap capacitor can charge up in one cycle and normal operation begins in a few microseconds after the BST-to-HS voltage exceeds UVLOBST. In the two-switch forward topology, the BST capacitor takes some time (a few hundred microseconds) to charge and increase its voltage above UVLOBST. The typical hysteresis for both UVLO thresholds is 0.5V. The bootstrap capacitor value should be selected carefully to avoid unintentional oscillations during turn-on and turn-off at the DH output. Choose the capacitor value about 20 times higher than the total gate capacitance of the MOSFET. Use a low-ESR-type X7R dielectric ceramic capacitor at BST (typically a 0.1µF ceramic is adequate) and a parallel combination of 1µF and 0.1µF ceramic capacitors from V DD to GND (MAX5062_, MAX5063_) or to PGND (MAX5064_). The high-side MOSFET’s continuous on-time is limited due to the charge loss from the high-side driver’s quiescent current. The maximum on-time is dependent on the size of CBST, IBST (50µA max), and UVLOBST. An internal diode connects from VDD to BST and is used in conjunction with a bootstrap capacitor externally connected between BST and HS. The diode charges the capacitor from VDD when the DL low-side switch is on and isolates VDD when HS is pulled high as the highside driver turns on (see the Typical Operating Circuit). Output Driver The MAX5062/MAX5063/MAX5064 have low 2.5Ω RDS_ON p-channel and n-channel devices (totem pole) in the output stage. This allows for a fast turn-on and turn-off of the high gate-charge switching MOSFETs. The peak source and sink current is typically 2A. Propagation delays from the logic inputs to the driver outputs are matched to within 8ns. The internal p- and n-channel MOSFETs have a 1ns break-before-make logic to avoid any cross conduction between them. This internal break-before-make logic eliminates shootthrough currents reducing the operating supply current as well as the spikes at VDD. The DL voltage is approximately equal to VDD and the DH-to-HS voltage, a diode drop below VDD, when they are in a high state and to zero when in a low state. The driver RDS_ON is lower at higher VDD. Lower RDS_ON means higher source and sink currents and faster switching speeds. 10 The internal bootstrap diode has a typical forward voltage drop of 0.9V and has a 10ns typical turn-off/turn-on time. For lower voltage drops from VDD to BST, connect an external Schottky diode between VDD and BST. Programmable Break-Before-Make (MAX5064) Half-bridge and synchronous buck topologies require that the high- or low-side switch be turned off before the other switch is turned on to avoid shoot-through currents. Shoot-through occurs when both high- and low-side switches are on at the same time. This condition is caused by the mismatch in the propagation delay from IN_H/IN_L to DH/DL, driver output impedance, and the MOSFET gate capacitance. Shootthrough currents increase power dissipation, radiate EMI, and can be catastrophic, especially with high input voltages. The MAX5064 offers a break-before-make (BBM) feature that allows the adjustment of the delay from the input to the output of each driver. The propagation delay from the rising edges of IN_H and IN_L to the rising edges of DH and DL, respectively, can be programmed from 16ns to 95ns. Note that the BBM time (tBBM) has a higher percentage error at lower value because of the fixed comparator delay in the BBM block. The propagation delay mismatch (t MATCH_ ) needs to be included when calculating the total tBBM error. The low 8ns (maximum) delay mismatch reduces the total tBBM variation. Use the following equations to calculate R BBM for the required BBM time and tBBM_ERROR: ⎛t ⎞ RBBM = 10kΩ × ⎜ BBM − 1⎟ for RBBM < 200kΩ ⎝ 8ns ⎠ tBBM _ ERROR = 0.15 × tBBM + tMATCH _ where tBBM is in nanoseconds. The voltage at BBM is regulated to 1.3V. The BBM circuit adjusts tBBM depending on the current drawn by RBBM. Bypass BBM to AGND with a 1nF or smaller ceramic capacitor (CBBM) to avoid any effect of ground bounce caused during switching. The charging time of CBBM does not affect tBBM at turn-on because the BBM voltage is stabilized before the UVLO clears the device turn-on. ______________________________________________________________________________________ 125V/2A, High-Speed, Half-Bridge MOSFET Drivers Driver Logic Inputs (IN_H, IN_L, IN_H+, IN_H-, IN_L+, IN_L-) The MAX5062_/MAX5064A are CMOS (VDD / 2) logicinput drivers while the MAX5063_/MAX5064B have TTLcompatible logic inputs. The logic-input signals are independent of VDD. For example, the IC can be powered by a 10V supply while the logic inputs are provided from a 12V CMOS logic. Also, the logic inputs are protected against voltage spikes up to 15V, regardless of the VDD voltage. The TTL and CMOS logic inputs have 400mV and 1.6V hysteresis, respectively, to avoid double pulsing during transition. The logic inputs are high-impedance pins and should not be left floating. The low 2.5pF input capacitance reduces loading and increases switching speed. The noninverting inputs are pulled down to GND and the inverting inputs are pulled up to VDD internally using a 1MΩ resistor. The PWM output from the controller must assume a proper state while powering up the device. With the logic inputs floating, the DH and DL outputs pull low as VDD rises up above the UVLO threshold. The MAX5064_ has two logic inputs per driver, which provide greater flexibility in controlling the MOSFET. Use IN_H+/IN_L+ for noninverting logic and IN_H-/ IN_L- for inverting logic operation. Connect IN_H+/IN_L+ to VDD and IN_H-/IN_L- to GND if not used. Alternatively, the unused input can be used as an ON/OFF function. Use IN_+ for active-low and IN_- for active-high shutdown logic. shoot-through in the absence of external BBM delay during the narrow pulse at low duty cycle (see Figure 2). At high duty cycle (close to 100%) the DH minimum low pulse width (tDmin-DH-L) must be higher than the DL minimum low pulse width (tDmin-DL-L) to avoid overlap and shoot-through (see Figure 3). In the case of MAX5062/MAX5063/MAX5064, there is a possibility of about 40ns overlap if an external BBM delay is not provided. We recommend adding external delay in the INH path so that the minimum low pulse width seen at INH is always longer than t PW-min . See the Electrical Characteristics table for the typical values of tPW-MIN. VDD VIN A) PWMIN IN_H-/IN_L- DH N VOUT HS INL DL N MAX5062B/MAX5062D/MAX5063B/MAX5063D/MAX5064 B) PWMIN Table 1. MAX5064_ Truth Table IN_H+/IN_L+ INH tDMIN-DH-H DH/DL Low Low Low Low High Low High Low High High High Low DH Minimum Pulse Width The MAX5062/MAX5063/MAX5064 uses a single-shot level shifter architecture to achieve low propagation delay. Typical level shifter architecture causes a minimum (high or low) pulse width (tDmin) at the output that may be higher than the logic-input pulse width. For MAX5062/MAX5063/MAX5064 devices, the DH minimum high pulse width (tDmin-DH-H) is lower than the DL minimum low pulse width (t Dmin-DL-L ) to avoid any BUILT-IN DEAD TIME DL tDMIN-DL-L Figure 2. Minimum Pulse-Width Behavior for Narrow DutyCycle Input (On-Time < tPW_MIN) ______________________________________________________________________________________ 11 MAX5062/MAX5063/MAX5064 Topologies like the two-switch forward converter, where both high- and low-side switches are turned on and off simultaneously, can have the BBM function disabled by leaving BBM unconnected. When disabled, tBBM is typically 1ns. MAX5062/MAX5063/MAX5064 125V/2A, High-Speed, Half-Bridge MOSFET Drivers VDD VIN A) C) PWMIN EXTERNAL BBM DELAY PWMIN INH DH N VOUT HS INL DL EXTERNAL BBM DELAY N tDMIN-DH-L DH MAX5062B/MAX5062D/MAX5063B/MAX5063D/MAX5064 VDD VIN B) PWMIN EXTERNAL BBM DELAY POTENTIAL OVERLAP TIME INH DH N HS INL DL VOUT DL N tDMIN-DL-H MAX5062A/MAX5062C/MAX5063A/MAX5063C/MAX5064 Figure 3. Minimum Pulse-Width Behavior for High Duty-Cycle Input (Off-Time < tPW_MIN) Applications Information Supply Bypassing and Grounding Pay extra attention to bypassing and grounding the MAX5062/MAX5063/MAX5064. Peak supply and output currents may exceed 4A when both drivers are driving large external capacitive loads in-phase. Supply drops and ground shifts create forms of negative feedback for inverters and may degrade the delay and transition times. Ground shifts due to insufficient device grounding may also disturb other circuits sharing the same AC ground return path. Any series inductance in the VDD, DH, DL, and/or GND paths can cause oscillations due to the very high di/dt when switching the MAX5062/ MAX5063/MAX5064 with any capacitive load. Place one or more 0.1µF ceramic capacitors in parallel as close to the device as possible to bypass VDD to GND (MAX5062/MAX5063) or PGND (MAX5064). Use a ground plane to minimize ground return resistance and 12 series inductance. Place the external MOSFET as close as possible to the MAX5062/MAX5063/MAX5064 to further minimize board inductance and AC path resistance. For the MAX5064_ the low-power logic ground (AGND) is separated from the high-power driver return (PGND). Apply the logic-input signal between IN_ to AGND and connect the load (MOSFET gate) between DL and PGND. Power Dissipation Power dissipation in the MAX5062/MAX5063/MAX5064 is primarily due to power loss in the internal boost diode and the nMOS and pMOS FETS. For capacitive loads, the total power dissipation for the device is: PD = ⎛⎝ CL × VDD2 × fSW ⎞⎠ + (IDDO + IBSTO ) × VDD ______________________________________________________________________________________ 125V/2A, High-Speed, Half-Bridge MOSFET Drivers PDIODE = CDH × (VDD − 1) × fSW × Vf The total power dissipation when using the internal boost diode will be PD and, when using an external Schottky diode, will be PD - PDIODE. The total power dissipated in the device must be kept below the maximum of 1.951W for the 12-pin TQFN package, 1.5W for the 8-pin SO with exposed pad, and 0.471W for the regular 8-pin SO package at TA = +70°C ambient. Layout Information The MAX5062/MAX5063/MAX5064 drivers source and sink large currents to create very fast rise and fall edges at the gates of the switching MOSFETs. The high di/dt can cause unacceptable ringing if the trace lengths and impedances are not well controlled. Use the following PC board layout guidelines when designing with the MAX5062/MAX5063/MAX5064: • It is important that the VDD voltage (with respect to ground) or BST voltage (with respect to HS) does not exceed 13.2V. Voltage spikes higher than 13.2V from VDD to GND or BST to HS can damage the device. Place one or more low ESL 0.1µF decoupling ceramic capacitors from V DD to GND (MAX5062/MAX5063) or to PGND (MAX5064), and from BST to HS as close as possible to the part. The ceramic decoupling capacitors should be at least 20 times the gate capacitance being driven. • There are two AC current loops formed between the device and the gate of the MOSFET being driven. The MOSFET looks like a large capacitance from gate to source when the gate is being pulled low. The active current loop is from the MOSFET driver output (DL or DH) to the MOSFET gate, to the MOSFET source, and to the return terminal of the MOSFET driver (either GND or HS). When the gate of the MOSFET is being pulled high, the active current loop is from the MOSFET driver output, (DL or DH), to the MOSFET gate, to the MOSFET source, to the return terminal of the drivers decoupling capacitor, to the positive terminal of the decoupling capacitor, and to the supply connection of the MOSFET driver. The decoupling capacitor will be either the flying capacitor connected between BST and HS or the decoupling capacitor for V DD . Care must be taken to minimize the physical distance and the impedance of these AC current paths. • Solder the exposed pad of the TQFN (MAX5064) or SO (MAX5062C/D and MAX5063C/D) package to a large copper plane to achieve the rated power dissipation. Connect AGND and PGND at one point near VDD’s decoupling capacitor return. ______________________________________________________________________________________ 13 MAX5062/MAX5063/MAX5064 where CL is the combined capacitive load at DH and DL. VDD is the supply voltage and fSW is the switching frequency of the converter. PD includes the power dissipated in the internal bootstrap diode. The internal power dissipation reduces by PDIODE, if an external bootstrap Schottky diode is used. The power dissipation in the internal boost diode (when driving a capacitive load) will be the charge through the diode per switching period multiplied by the maximum diode forward voltage drop (Vf = 1V). MAX5062/MAX5063/MAX5064 125V/2A, High-Speed, Half-Bridge MOSFET Drivers Typical Application Circuits VIN = 0 TO 125V VDD = 8V TO 12.6V VDD BST N DH IN_H MAX5062A/ MAX5063A PWM CONTROLLER HS IN_L N DL VOUT GND PIN FOR PIN REPLACEMENT FOR THE HIP2100/HIP2101 Figure 4. MAX5062 Half-Bridge Conversion VDD = 8V TO 12.6V VIN = 0 TO 125V VDD CBST BST DH N MAX5064 IN_H+ PWM VOUT HS IN_LBBM CBBM RBBM DL AGND N PGND Figure 5. Synchronous Buck Converter 14 ______________________________________________________________________________________ 125V/2A, High-Speed, Half-Bridge MOSFET Drivers VDD = 8V TO 12.6V VIN = 0 TO 125V CBST VDD BST N DH MAX5064 HS IN_H+ PWM VOUT IN_L+ BBM N DL AGND PGND Figure 6. Two-Switch Forward Conversion VIN = 0 TO 125V VDD = 8V TO 12.6V VDD CBST BST DH PWM N MAX5064_ IN_H+ HS IN_LBBM CBBM RBBM AGND DL N VOUT PGND Figure 7. MAX5064 Half-Bridge Converter ______________________________________________________________________________________ 15 MAX5062/MAX5063/MAX5064 Typical Application Circuits (continued) 125V/2A, High-Speed, Half-Bridge MOSFET Drivers MAX5062/MAX5063/MAX5064 Functional Diagrams MAX5062A MAX5062C MAX5062B/ MAX5062D VDD/2 CMOS VDD/2 CMOS BST 2 5 IN_H DH IN_L 3 5 IN_H DH DL 8 6 IN_L 3 5 IN_H DH 6 IN_L DL 8 GND 7 GND 7 SO/SO-EP SO/SO-EP SO/SO-EP MAX5063B/ MAX5063D MAX5064A MAX5064B VDD/2 CMOS IN_H DH 7 3 6 HS 4 VDD 1 IN_L TTL BST 1 BST 2 5 9 DL 8 8 GND 7 4 BST 1 IN_H+ DH IN_H- 7 2 6 HS 3 VDD 12 BBM IN_L+ 5 9 DL 11 IN_L- 8 AGND SO/SO-EP 3 HS 4 VDD 1 DL 8 TTL 6 BST 2 HS 4 VDD 1 GND 7 5 TTL BST 2 HS 4 VDD 1 6 MAX5063A/ MAX5063C PGND 10 4 THIN QFN IN_H+ DH IN_H- 2 HS 3 VDD 12 BBM IN_L+ DL 11 IN_LAGND PGND 10 THIN QFN Pin Configurations TOP VIEW IN_L+ 9 VDD 1 8 DL VDD 1 8 DL BST 2 7 GND BST 2 7 GND DH 3 6 IN_L DH 3 6 IN_L 5 IN_H HS 4 5 IN_H MAX5062A/B MAX5063A/B HS 4 SO MAX5062C/D MAX5063C/D SO-EP IN_L- IN_H+ 8 7 PGND 10 DL 11 MAX5064A/ MAX5064B VDD 12 1 2 3 BST DH HS THIN QFN 16 ______________________________________________________________________________________ 6 IN_H- 5 BBM 4 AGND 125V/2A, High-Speed, Half-Bridge MOSFET Drivers VIN = 125V VDD 8V TO 12.6V MAX5064A/ MAX5064B BST PWM IN IN_H+ DH CBST IN_H- VOUT HS VDD IN_L+ DL VDD CDD IN_LBBM PGND AGND RBBM CBBM Selector Guide (continued) PART HIGH-SIDE DRIVER LOW-SIDE DRIVER LOGIC LEVELS PIN COMPATIBLE MAX5063AASA Noninverting Noninverting TTL HIP2101IB MAX5063BASA Noninverting Inverting TTL — MAX5063CASA MAX5063DASA Noninverting Noninverting Noninverting Inverting TTL TTL — — MAX5064AATC Both Inverting and Noninverting Both Inverting and Noninverting CMOS (VDD / 2) — MAX5064BATC Both Inverting and Noninverting Both Inverting and Noninverting TTL — Ordering Information (continued) PART TEMP RANGE PINPACKAGE MAX5063AASA -40°C to +125°C MAX5063BASA TOP MARK PKG CODE 8 SO — S8-5 -40°C to +125°C 8 SO — S8-5 MAX5063CASA -40°C to +125°C 8 SO-EP* — S8E-14 MAX5063DASA -40°C to +125°C 8 SO-EP* — S8E-14 MAX5064AATC -40°C to +125°C 12 TQFN AAEF T1244-4 MAX5064BATC -40°C to +125°C 12 TQFN AAEG T1244-4 Chip Information TRANSISTOR COUNT: 790 PROCESS: HV BiCMOS *EP = Exposed paddle. Devices are available in both leaded and lead-free packaging. Specify lead-free by replacing “-T” with “+T” when ordering. ______________________________________________________________________________________ 17 MAX5062/MAX5063/MAX5064 Typical Operating Circuit Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) 8L, SOIC EXP. PAD.EPS MAX5062/MAX5063/MAX5064 125V/2A, High-Speed, Half-Bridge MOSFET Drivers PACKAGE OUTLINE 8L SOIC, .150" EXPOSED PAD 21-0111 18 ______________________________________________________________________________________ C 1 1 125V/2A, High-Speed, Half-Bridge MOSFET Drivers 24L QFN THIN.EPS PACKAGE OUTLINE, 12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm 21-0139 E 1 2 ______________________________________________________________________________________ 19 MAX5062/MAX5063/MAX5064 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) MAX5062/MAX5063/MAX5064 125V/2A, High-Speed, Half-Bridge MOSFET Drivers Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) PACKAGE OUTLINE, 12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm 21-0139 E 2 2 Revision History Pages changed at Rev 5: 1, 2, 4, 5, 11–15, 19, 20 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.