MOTOROLA 2N7002LT1

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by 2N7002LT1/D
SEMICONDUCTOR TECHNICAL DATA
N–Channel Enhancement
3 DRAIN
Motorola Preferred Device
1
GATE
3
2 SOURCE
1
MAXIMUM RATINGS
2
Rating
Symbol
Value
Unit
Drain–Source Voltage
VDSS
60
Vdc
Drain–Gate Voltage (RGS = 1.0 MΩ)
VDGR
60
Vdc
ID
ID
IDM
± 115
± 75
± 800
mAdc
VGS
VGSM
± 20
± 40
Vdc
Vpk
Drain Current — Continuous TC = 25°C(1)
Drain Current — Continuous TC = 100°C(1)
Drain Current — Pulsed(2)
Gate–Source Voltage
— Continuous
— Non–repetitive (tp ≤ 50 µs)
CASE 318 – 08, STYLE 21
SOT– 23 (TO – 236AB)
THERMAL CHARACTERISTICS
Characteristic
Total Device Dissipation FR–5 Board,(3) TA = 25°C
Derate above 25°C
Thermal Resistance, Junction to Ambient
Total Device Dissipation
Alumina Substrate,(4) TA = 25°C
Derate above 25°C
Thermal Resistance, Junction to Ambient
Junction and Storage Temperature
Symbol
Max
Unit
PD
225
1.8
mW
mW/°C
RθJA
556
°C/W
PD
300
mW
2.4
mW/°C
RθJA
417
°C/W
TJ, Tstg
– 55 to +150
°C
DEVICE MARKING
2N7002LT1 = 702
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
V(BR)DSS
60
—
—
Vdc
IDSS
—
—
—
—
1.0
500
µAdc
Gate–Body Leakage Current, Forward
(VGS = 20 Vdc)
IGSSF
—
—
100
nAdc
Gate–Body Leakage Current, Reverse
(VGS = – 20 Vdc)
IGSSR
—
—
–100
nAdc
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage
(VGS = 0, ID = 10 µAdc)
Zero Gate Voltage Drain Current
(VGS = 0, VDS = 60 Vdc)
1.
2.
3.
4.
TJ = 25°C
TJ = 125°C
The Power Dissipation of the package may result in a lower continuous drain current.
Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%.
FR–5 = 1.0 x 0.75 x 0.062 in.
Alumina = 0.4 x 0.3 x 0.025 in 99.5% alumina.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 2
Motorola Small–Signal Transistors, FETs and Diodes Device Data
 Motorola, Inc. 1997
1
2N7002LT1
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) (Continued)
Characteristic
Symbol
Min
Typ
Max
Unit
VGS(th)
1.0
—
2.5
Vdc
On–State Drain Current
(VDS ≥ 2.0 VDS(on), VGS = 10 Vdc)
ID(on)
500
—
—
mA
Static Drain–Source On–State Voltage
(VGS = 10 Vdc, ID = 500 mAdc)
(VGS = 5.0 Vdc, ID = 50 mAdc)
VDS(on)
—
—
—
—
3.75
0.375
Static Drain–Source On–State Resistance
(VGS = 10 V, ID = 500 mAdc)
TC = 25°C
TC = 125°C
(VGS = 5.0 Vdc, ID = 50 mAdc) TC = 25°C
TC = 125°C
rDS(on)
—
—
—
—
—
—
—
—
7.5
13.5
7.5
13.5
gFS
80
—
—
mmhos
Input Capacitance
(VDS = 25 Vdc, VGS = 0, f = 1.0 MHz)
Ciss
—
—
50
pF
Output Capacitance
(VDS = 25 Vdc, VGS = 0, f = 1.0 MHz)
Coss
—
—
25
pF
Reverse Transfer Capacitance
(VDS = 25 Vdc, VGS = 0, f = 1.0 MHz)
Crss
—
—
5.0
pF
td(on)
—
—
30
ns
td(off)
—
—
40
ns
VSD
—
—
–1.5
Vdc
IS
—
—
–115
mAdc
ISM
—
—
– 800
mAdc
ON CHARACTERISTICS(2)
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
Forward Transconductance
(VDS ≥ 2.0 VDS(on), ID = 200 mAdc)
Vdc
Ohms
DYNAMIC CHARACTERISTICS
SWITCHING CHARACTERISTICS(2)
Turn–On Delay Time
Turn–Off Delay Time
^
( DD = 25 Vdc,, ID
(V
500 mAdc,,
RG = 25 Ω, RL = 50 Ω)
BODY–DRAIN DIODE RATINGS
Diode Forward On–Voltage
(IS = 11.5 mAdc, VGS = 0 V)
Source Current Continuous
(Body Diode)
Source Current Pulsed
2. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%.
2
Motorola Small–Signal Transistors, FETs and Diodes Device Data
2N7002LT1
2.0
1.0
VDS = 10 V
TA = 25°C
1.6
VGS = 10 V
1.4
9V
1.2
I D, DRAIN CURRENT (AMPS)
I D, DRAIN CURRENT (AMPS)
1.8
8V
1.0
7V
0.8
6V
0.6
0.4
5V
0.2
4V
3V
0
0
1.0
2.0 3.0 4.0 5.0
6.0
7.0 8.0
VDS, DRAN SOURCE VOLTAGE (VOLTS)
9.0
0.8
125°C
0.6
0.4
0.2
10
0
2.4
2.2
1.8
VGS = 10 V
ID = 200 mA
1.6
1.4
1.2
1.0
0.8
0.6
0.4
– 60
– 20
+ 20
+ 60
T, TEMPERATURE (°C)
1.0
2.0 3.0 4.0
5.0
6.0
7.0 8.0
VGS, GATE SOURCE VOLTAGE (VOLTS)
9.0
10
Figure 2. Transfer Characteristics
VGS(th) , THRESHOLD VOLTAGE (NORMALIZED)
r DS(on) , STATIC DRAIN–SOURCE ON–RESISTANCE
(NORMALIZED)
Figure 1. Ohmic Region
2.0
25°C
– 55°C
+ 100
+ 140
Figure 3. Temperature versus Static
Drain–Source On–Resistance
Motorola Small–Signal Transistors, FETs and Diodes Device Data
1.2
1.05
VDS = VGS
ID = 1.0 mA
1.1
1.10
1.0
0.95
0.9
0.85
0.8
0.75
0.7
– 60
– 20
+ 20
+ 60
T, TEMPERATURE (°C)
+ 100
+ 140
Figure 4. Temperature versus Gate
Threshold Voltage
3
2N7002LT1
INFORMATION FOR USING THE SOT–23 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must
be the correct size to insure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
0.037
0.95
0.037
0.95
0.079
2.0
0.035
0.9
0.031
0.8
inches
mm
SOT–23
SOT–23 POWER DISSIPATION
The power dissipation of the SOT–23 is a function of the
pad size. This can vary from the minimum pad size for
soldering to a pad size given for maximum power dissipation.
Power dissipation for a surface mount device is determined
by TJ(max), the maximum rated junction temperature of the
die, RθJA, the thermal resistance from the device junction to
ambient, and the operating temperature, TA . Using the
values provided on the data sheet for the SOT–23 package,
PD can be calculated as follows:
PD =
TJ(max) – TA
RθJA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature TA of 25°C, one can
calculate the power dissipation of the device which in this
case is 225 milliwatts.
PD =
150°C – 25°C
556°C/W
= 225 milliwatts
The 556°C/W for the SOT–23 package assumes the use
of the recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 225 milliwatts. There
are other alternatives to achieving higher power dissipation
from the SOT–23 package. Another alternative would be to
use a ceramic substrate or an aluminum core board such as
Thermal Clad. Using a board material such as Thermal
Clad, an aluminum core board, the power dissipation can be
doubled using the same footprint.
4
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within a
short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
• Always preheat the device.
• The delta temperature between the preheat and
soldering should be 100°C or less.*
• When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering method,
the difference shall be a maximum of 10°C.
• The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
• When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
• After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and result
in latent failure due to mechanical stress.
• Mechanical stress or shock should not be applied during
cooling.
* Soldering a device without preheating can cause excessive
thermal shock and stress which can result in damage to the
device.
Motorola Small–Signal Transistors, FETs and Diodes Device Data
2N7002LT1
PACKAGE DIMENSIONS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. MAXIUMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD THICKNESS
IS THE MINIMUM THICKNESS OF BASE
MATERIAL.
A
L
3
B S
1
V
2
G
C
D
H
K
J
CASE 318–08
ISSUE AF
SOT–23 (TO–236AB)
Motorola Small–Signal Transistors, FETs and Diodes Device Data
DIM
A
B
C
D
G
H
J
K
L
S
V
INCHES
MIN
MAX
0.1102 0.1197
0.0472 0.0551
0.0350 0.0440
0.0150 0.0200
0.0701 0.0807
0.0005 0.0040
0.0034 0.0070
0.0140 0.0285
0.0350 0.0401
0.0830 0.1039
0.0177 0.0236
MILLIMETERS
MIN
MAX
2.80
3.04
1.20
1.40
0.89
1.11
0.37
0.50
1.78
2.04
0.013
0.100
0.085
0.177
0.35
0.69
0.89
1.02
2.10
2.64
0.45
0.60
STYLE 21:
PIN 1. GATE
2. SOURCE
3. DRAIN
5
2N7002LT1
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
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6
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2N7002LT1/D
Motorola Small–Signal Transistors, FETs and Diodes Device
Data