MAXIM MAX8566ETJ

19-3690; Rev 3; 3/11
KIT
ATION
EVALU
E
L
B
AVAILA
High-Efficiency, 10A, PWM
Internal-Switch Step-Down Regulator
Features
The MAX8566 high-efficiency switching regulator delivers up to 10A load current at output voltages from 0.6V
to (0.87 x VIN). The IC operates from 2.3V to 3.6V input
supplies, making it ideal for point-of-load applications.
The total output-voltage set error is less than ±1% over
load, line, and temperature.
The MAX8566 operates in pulse-width-modulation
(PWM) mode with a 250kHz to 2.4MHz switching frequency range that is programmable by an external
resistor. The IC can be synchronized to an external
clock in the same frequency range using the SYNC
input. The high operating frequency minimizes the size
of external components. Using low-RDS(ON) n-channel
MOSFETs for both high- and low-side switches maintains high efficiency at both heavy-load and highswitching frequencies.
o Internal 8mΩ On-Resistance MOSFETs
o 10A Output PWM Step-Down Regulator
o ±1% Output Accuracy over Load, Line, and
Temperature
o Operates from 2.3V to 3.6V Input Supply
o Adjustable Output from 0.6V to (0.87 x VIN)
o 250kHz to 2.4MHz Adjustable Frequency or SYNC
Input
o Allows All-Ceramic-Capacitor Design
o SYNCOUT Drives 2nd Regulator 180° Out-of-Phase
o Prebiased or Monotonic Soft-Start
o Programmable Soft-Start Time
o Output Tracking or Sequencing
o Sourcing and Sinking Output Current
o Power-Good Output
o 32-Lead TQFN Package
o REFIN for DDR-Termination Application
PART
MAX8566ETJ+
PIN-PACKAGE
32 TQFN-EP*
+Denotes lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Typical Operating Circuit
IN
IN
IN
IN
REFIN
PGND
REFIN FOR
TRACKING
LSS
IN
VDD
INPUT
2.25V TO 3.6V
PGND
SS
PGND
EN
PGND
SYNC INPUT
SYNC
MAX8566ETJ+
PROGRAMMABLE
FREQUENCY
FREQ
STEP-DOWN REGULATOR
TQFN 5mm x 5mm
LX
GND
LX
L1
330nH/10A
LX
LX
BST
LX
LX
FB
ASIC/CPU/DSP Core Voltages
LX
SYNCOUT
COMP
SYNC OUTPUT 180°
PGND
LX
SYSTEM
ENABLE
Applications
POL Power Supplies
DDR Power Supplies
Base-Station Power Supplies
Fiber Power Supplies
Telecom Power Supplies
TEMP RANGE
-40°C to +85°C
PWRGD
The MAX8566 is available in a 32-pin, 5mm x 5mm TQFN
package. The MAX8566 and all the required external
components fit into a footprint of less than 0.80in2.
Ordering Information
MODE
The MAX8566 employs a voltage-mode control architecture with a high-bandwidth (> 10MHz) error amplifier. The voltage-mode control architecture makes
switching frequencies greater than 1MHz possible,
achieving all-ceramic-capacitor designs to minimize PC
board space. The error amplifier works with Type 3
compensation to fully utilize the bandwidth of the highfrequency switching to obtain fast transient response.
Adjustable soft-start time provides flexibility to minimize
input startup inrush current. An open-drain, powergood (PWRGD) signal goes high when the output
reaches 90% of its regulation point.
The MAX8566 provides a SYNCOUT output to synchronize a second MAX8566 or a second regulator switching 180° out-of-phase with the first to reduce the input
ripple current, which consequently reduces the inputcapacitance requirements. The MAX8566 also provides an external reference input (REFIN) for
output-tracking applications.
OUTPUT
UP TO 10A
C5
2 x 22µF
6.3V
MONOTONIC SS
SELECTION
POWER-GOOD
OUTPUT
COMPENSATION
Network Power Supplies
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
MAX8566
General Description
MAX8566
High-Efficiency, 10A, PWM
Internal-Switch Step-Down Regulator
ABSOLUTE MAXIMUM RATINGS
EN/SS, EN, IN, SYNC, VDD,
LSS, PWRGD to GND ..........-0.3V to +4V (4.5V nonswitching)
SYNCOUT, SS, COMP, FB, REFIN,
FREQ to GND .........................................-0.3V to (VDD + 0.3V)
LX Current (Note 1) .................................................-12A to +12A
BST to LX .................................-0.3V to +4V (4.5V nonswitching)
PGND to GND .......................................................-0.3V to +0.3V
Continuous Power Dissipation (TA = +85°C)
TQFN (derate 33.3mW/°C above +70°C) ..................2666.7W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Note 1: LX has internal clamp diodes to PGND and IN. Applications that forward bias these diodes should take care not to exceed
the IC’s package power-dissipation limits.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = VDD = VEN = 3.3V, VFB = 0.5V, VSYNC = 0V, TA = 0°C to +85°C, typical values are at TA = +25°C, unless otherwise noted.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
IN/VDD
IN and VDD Voltage Range
2.3
3.6
V
LSS Voltage Range
2.3
3.6
V
IN Supply Current
Quiescent current, VFB = 0.7V
0.7
fS = 1MHz, no load
14
Quiescent current, VFB = 0.7V
1.8
fS = 1MHz, VLSS = VDD
16
Total Shutdown Current into IN
and VDD
VIN = VDD = VLSS = (VBST - VLX) = TA = +25°C
3.6V, VEN = 0V
TA = 0°C to +85°C
3
VDD Undervoltage-Lockout
Threshold
LX starts/stops switching, 2µs
deglitch
VDD falling
VIN = VDD = VBST = 3.6V, VLX =
3.6V or 0V, VEN = 0V
TA = 0°C to +85°C
VDD Supply Current
2.2
4
50
VDD rising
2.0
1.72
2.2
1.90
mA
mA
µA
V
BST
Shutdown Supply Current
TA = +25°C
10
0.05
µA
PWM COMPARATOR
Comparator Propagation Delay
10mV overdrive
20
ns
COMP
Clamp Voltage, High
VIN = 2.3V to 3.6V, VFB = 0.7V
Slew Rate
Shutdown Resistance
1.80
2.0
0.75
1.4
From COMP to GND, VEN = 0V
2.15
V
V/µs
30
100
Ω
0.6
0.606
V
ERROR AMPLIFIER
FB Regulation Voltage
Error-Amplifier Common-Mode
Input Range
Error-Amplifier Maximum Output
Current
2
VCOMP = 1V to 2V, VDD = 2.5V and 3.3V
0.594
VDD = 2.3V to 2.6V
0
VDD 1.65
VDD = 2.6V to 3.6V
0
VDD 1.7
V
0.8
_______________________________________________________________________________________
mA
High-Efficiency, 10A, PWM
Internal-Switch Step-Down Regulator
(VIN = VDD = VEN = 3.3V, VFB = 0.5V, VSYNC = 0V, TA = 0°C to +85°C, typical values are at TA = +25°C, unless otherwise noted.)
TYP
MAX
FB Input Bias Current
PARAMETER
VFB = 0.7V, TA = +25°C
CONDITIONS
MIN
40
200
nA
REFIN Input Bias Current
VREFIN = 0.6V, TA = +25°C
70
250
nA
VDD = 2.3V to 2.6V
0
VDD 1.65
VDD = 2.6V to 3.6V
0
VDD 1.7
REFIN Common-Mode Range
UNITS
V
LX (ALL PINS COMBINED)
VIN = VBST - VLX = 3.3V
8
16
VIN = VBST - VLX = 2.5V
12
20
VIN = VLSS = 3.3V
8
16
VIN = VLSS = 2.5V
12
20
15
20
5
200
On-Resistance, High Side
ILX = -2A
On-Resistance, Low Side
ILX = 2A
Current-Limit Threshold
VIN = 2.5V or 3.3V, high side
Leakage Current
VIN = 3.6V, VEN = 0V,
TA = +25°C
Switching Frequency
VIN = 2.5V or 3.3V
12
VLX = 3.6V
VLX = 0V
+5
RFREQ = 50kΩ
0.8
1
1.2
RFREQ = 23.3kΩ
1.7
2
2.3
50
75
87
95
VIN = 2.5V or 3.3V
Maximum Duty Cycle
RFREQ = 50kΩ, VIN = 2.5V or 3.3V
Minimum Duty Cycle
RFREQ = 50kΩ, VIN = 2.5V or 3.3V
A
MHz
ns
%
10
RMS LX Output Current
mΩ
µA
-200
Minimum Off-Time
mΩ
%
10
A
0.7
V
ENABLE/SOFT-START
EN Input Logic-Low Threshold
0.4
EN Input Logic-High Threshold
MODE Input Threshold
1.65
VDD = 2.3V to 3.6V
Monotonic start
30
VEN = VMODE = 0V or 3.6V, VDD = 3.6V, TA = +25°C
Soft-Start Charging Current
VSS = 0.3V
5
V
45
20
% of
VDD
0.01
1
µA
8
11
No monotonic start
EN, MODE Input Current
SS Discharge Resistance
1.90
8
µA
kΩ
_______________________________________________________________________________________
3
MAX8566
ELECTRICAL CHARACTERISTICS (continued)
MAX8566
High-Efficiency, 10A, PWM
Internal-Switch Step-Down Regulator
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VDD = VEN = 3.3V, VFB = 0.5V, VSYNC = 0V, TA = 0°C to +85°C, typical values are at TA = +25°C, unless otherwise noted.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
2.40
MHz
SYNC
Capture Range
VDD = 2.3V to 3.6V
Pulse Width
VDD = 2.3V to 3.6V
Input Threshold
VDD = 2.3V to 3.6V
Input Current
VSYNC = 0V or 3.6V, VDD = 3.6V
0.25
tLO
100
tHI
100
VIH
0.4
VIL
IIH
IIL, TA = +25°C
ns
0.95
1
-1
-1
1.6
+10
+0.01
+1
V
µA
SYNCOUT
Frequency Range
VDD = 2.3V to 3.6V
0.25
Phase Shift from SYNC or
Internal Oscillator
Frequency = 1MHz
160
180
Output Voltage
ISYNCOUT = ±1mA,
VDD = 2.3V to 3.6V
VDD 0.4
VDD 0.05
VOH
VOL
0.05
2.40
MHz
230
Degrees
V
0.4
THERMAL SHUTDOWN
Thermal-Shutdown Threshold
When LX stops switching
Thermal-Shutdown Hysteresis
+165
°C
20
°C
POWER GOOD
Threshold Voltage
VFB falling, 3mV hysteresis
Falling-Edge Deglitch
86
93
% of
VREFIN
or 0.6V
µs
50
80
Output Low Voltage
IPWRGD = 4mA
0.15
0.3
V
Leakage Current
VPWRGD = 3.6V, VFB = 0.9V, TA = +25°C
0.01
1
µA
4
30
90
_______________________________________________________________________________________
High-Efficiency, 10A, PWM
Internal-Switch Step-Down Regulator
(VIN = VDD = VEN = 3.3V, VFB = 0.5V, VSYNC = 0V, TA = -40°C to +85°C, unless otherwise noted. Note 2)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
IN/VDD
IN and VDD Voltage Range
2.325
3.600
V
LSS Voltage Range
2.325
3.600
V
IN Supply Current
Quiescent current, VFB = 0.7V
2.2
mA
VDD Supply Current
Quiescent current, VFB = 0.7V
4
mA
VDD Undervoltage-Lockout
Threshold
LX starts/stops switching,
2µs rising/falling-edge delay
VDD rising
VDD falling
2.2
1.72
V
COMP
Clamp Voltage, High
VIN = 2.3V to 3.6V, VFB = 0.7V
1.80
Slew Rate
2.18
0.75
Shutdown Resistance
V
V/µs
100
Ω
0.591
0.609
V
VDD = 2.325V to 2.6V
0
VDD 1.65
VDD = 2.6V to 3.6V
0
VDD 1.7
From COMP to GND, VEN = 0V
ERROR AMPLIFIER
FB Regulation Voltage
Error-Amplifier Common-Mode
Input Range
VCOMP = 1V to 2V, VIN = 2.3V or 3.6V
Error-Amplifier Maximum Output
Current
0.8
mA
VDD = 2.325V to 2.5V
0
VDD 1.65
VDD = 2.6V to 3.6V
0
VDD 1.7
REFIN Common-Mode Range
V
V
LX (ALL PINS COMBINED)
On-Resistance, High Side
ILX = -2A
On-Resistance, Low Side
ILX = 2A
Current-Limit Threshold
VIN = 2.5V or 3.3V
VIN = VBST - VLX = 3.3V
16
VIN = VBST - VLX = 2.5V
20
VIN = VLSS = 3.3V
15
VIN = VLSS = 2.5V
20
12
20
mΩ
mΩ
A
_______________________________________________________________________________________
5
MAX8566
ELECTRICAL CHARACTERISTICS
MAX8566
High-Efficiency, 10A, PWM
Internal-Switch Step-Down Regulator
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VDD = VEN = 3.3V, VFB = 0.5V, VSYNC = 0V, TA = -40°C to +85°C, unless otherwise noted. Note 2)
PARAMETER
CONDITIONS
MIN
TYP
MAX
RFREQ = 50kΩ
0.8
1.2
RFREQ = 23.3kΩ
1.7
2.3
Switching Frequency
VIN = 2.5V or 3.3V
Minimum Off-Time
VIN = 2.5V or 3.3V
Maximum Duty Cycle
RFREQ = 50kΩ, VIN = 2.5V or 3.3V
90
87
RMS Output Current
UNITS
MHz
ns
%
10
A
ENABLE/SOFT-START
EN Input Logic-Low Threshold
0.7
EN Input Logic-High Threshold
MODE Input Threshold
1.65
VIN = 2.3V to 3.6V
Monotonic start
30
No monotonic start
EN, MODE Input Current
VEN or VMODE = 0V or 3.6V, VDD = 3.6V
Soft-Start Charging Current
VSS = 0.3V
V
V
45
20
% of
VDD
1
µA
5
12
µA
0.25
2.40
MHz
SYNC
Capture Range
VIN = 2.3V to 3.6V
Pulse Width
VIN = 2.3V to 3.6V
Input Threshold
VIN = 2.3V to 3.6V
6
tLO
100
tHI
100
VIH
0.4
VIL
_______________________________________________________________________________________
ns
1.6
V
High-Efficiency, 10A, PWM
Internal-Switch Step-Down Regulator
(VIN = VDD = VEN = 3.3V, VFB = 0.5V, VSYNC = 0V, TA = -40°C to +85°C, unless otherwise noted. Note 2)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SYNCOUT
Frequency Range
VDD = 2.3V to 3.6V
0.25
2.40
MHz
Phase Shift from SYNC or
Internal Oscillator
Frequency = 1MHz
160
230
Degrees
Output Voltage
ISYNCOUT = ±1mA,
VDD = 2.3V to 3.6V
VDD 0.4
VOH
V
VOL
0.4
POWER-GOOD
Threshold Voltage
VFB falling, 3mV hysteresis
Falling-Edge Deglitch
PWRGD Output Voltage
85
93
% of
VREF
30
80
µs
0.3
V
IPWRGD = 4mA
Note 2: Specifications to -40°C are guaranteed by design and not production tested.
Typical Operating Characteristics
(Typical values are at VIN = VDD = 3.3V, VOUT = 1.8V, RFREQ = 50kΩ, IOUT = 10A, and TA = +25°C.)
90
85
EFFICIENCY (%)
EFFICIENCY (%)
90
VOUT = 1.8V
80
75
95
90
VOUT = 1.8V
85
VOUT = 1.5V
80
75
75
70
65
65
65
10
LOAD CURRENT (A)
100
VOUT = 0.8V
60
60
1
VOUT = 1.5V
80
70
0.1
VOUT = 1.8V
85
70
60
MAX8566 toc03
95
EFFICIENCY (%)
VOUT = 2.5V
100
MAX8566 toc02
95
100
MAX8566 toc01
100
EFFICIENCY vs. LOAD CURRENT
VIN = 2.5V, VLSS = 3.3V
EFFICIENCY vs. LOAD CURRENT
VIN = VLSS = 2.5V
EFFICIENCY vs. LOAD CURRENT
VIN = VLSS = 3.3V
0.1
1
10
LOAD CURRENT (A)
100
0.1
1
10
100
LOAD CURRENT (A)
_______________________________________________________________________________________
7
MAX8566
ELECTRICAL CHARACTERISTICS (continued)
Typical Operating Characteristics (continued)
(Typical values are at VIN = VDD = 3.3V, VOUT = 1.8V, RFREQ = 50kΩ, IOUT = 10A, and TA = +25°C.)
2.0
0.62
0.61
0.60
0.59
0.58
1.5
RFREQ = 50kΩ
1.0
RFREQ = 100kΩ
0.57
0.5
0.05
0
VOUT = 2.5V
VOUT = 1.8V
-0.05
-0.10
-0.15
-0.20
VOUT = 0.8V
-0.25
-0.30
-0.35
0.56
-0.40
0
-40
0
40
120
80
10
35
60
0
85
1
2
3
4
5
6
7
8
9
LOAD CURRENT (A)
SHUTDOWN SUPPLY CURRENT
vs. INPUT VOLTAGE
MAXIMUM OUTPUT CURRENT
vs. OUTPUT VOLTAGE
EXPOSED PADDLE TEMPERATURE
vs. LOAD CURRENT
14.5
14.0
OUTPUT CURRENT (A)
8
7
6
5
4
3
13.5
13.0
12.5
12.0
11.5
2
11.0
1
10.5
0
10.0
1.0
1.5
2.0
2.5
3.0
3.5
4.0
70
TA = +25°C
20
TA = -40°C
-30
MAX8566 EV KIT PCB
200LFM
0
OUTPUT VOLTAGE (V)
0.4
0.3
0.2
ILOAD = 0A
0
-0.1
-0.2
ILOAD = 4.5A
ILOAD = 10A
-0.3
-0.4
2.50
2.75
3.00
3.25
3.50
INPUT VOLTAGE (V)
4
6
LOAD CURRENT (A)
3.75
4.00
10.0
OUTPUT SHORT-CIRCUIT CURRENT (A)
MAX8566 toc10
0.5
0.1
2
OUTPUT SHORT-CIRCUIT CURRENT
vs. INPUT VOLTAGE
LINE REGULATION
OUTPUT VOLTAGE CHANGE (%)
TA = +85°C
10
-80
0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5
INPUT VOLTAGE (V)
-0.5
2.25
120
MAX8566 toc11
0.5
MAX8566 toc08
MAX8566 toc07
15.0
EXPOSED PADDLE TEMPERATURE (°C)
TEMPERATURE (°C)
VEN = 0V
0
-15
TEMPERATURE (°C)
10
9
-40
MAX8566 toc09
0.55
8
MAX8566 toc06
RFREQ = 23.3kΩ
0.10
OUTPUT VOLTAGE CHANGE (%)
0.63
MAX8566 toc05
MAX8566 toc04
2.5
FREQUENCY (MHz)
REFERENCE VOLTAGE (V)
0.64
LOAD REGULATION
FREQUENCY vs. TEMPERATURE
REFERENCE VOLTAGE vs. TEMPERATURE
0.65
SHUTDOWN SUPPLY CURRENT (µA)
MAX8566
High-Efficiency, 10A, PWM
Internal-Switch Step-Down Regulator
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
2.25 2.45 2.65 2.85 3.05 3.25 3.45 3.65 3.85
INPUT VOLTAGE (V)
_______________________________________________________________________________________
8
10
High-Efficiency, 10A, PWM
Internal-Switch Step-Down Regulator
GAIN/PHASE OF THE VOLTAGE LOOP
LOAD TRANSIENT (0 TO 5A)
MAX8566 toc13
MAX8566 toc12
147 kHz
VOUT
AC-COUPLED
(50mV/div)
0dB
GAIN
(10dB/div)
5A
56°
0°
IOUT
(2A/div)
PHASE
(45°/div)
1
10
100
1000
0
t = 10µs/div
FREQUENCY (kHz)
STARTUP INTO 0.18Ω LOAD
(RLOAD = 0.18Ω)
FULL-LOAD SWITCHING WAVEFORMS
MAX8566 toc14
MAX8566 toc15
7A
(PEAK)
IIN
(5A/div) 0A
IL 12A
(2A/div)
10A
3.3V
VOUT
(10mV/div)
3V
VLX
(2V/div)
0V
0A
t = 400ns/div
VEN
(2V/div) 0V
1.8V
VOUT
(1V/div)
3V
0V
VPWRGD
0V (2V/div)
t = 400µs/div
_______________________________________________________________________________________
9
MAX8566
Typical Operating Characteristics (continued)
(Typical values are at VIN = VDD = 3.3V, VOUT = 1.8V, RFREQ = 50kΩ, IOUT = 10A, and TA = +25°C.)
Typical Operating Characteristics (continued)
(Typical values are at VIN = VDD = 3.3V, VOUT = 1.8V, RFREQ = 50kΩ, IOUT = 10A, and TA = +25°C.)
SOFT-START WITH REFIN
SYNCHRONIZED OPERATION (NO LOAD)
MAX8566 toc16
MAX8566 toc17
6.5A
IIN
(5A/div)
IIN
(AC-COUPLED)
(20mA/div)
0A
IL1
(2A/div)
0A
VREFIN 0.6V
(500mV/div)
0V
1.8V
VOUT
(1V/div)
0V
IL2
(2A/div) 0A
3V
VPWRGD
(2V/div)
0V
VLX1
(5V/div)
VLX2
(5V/div)
3.3V
0V
3.3V
0V
t = 400µs/div
t = 400ns/div
SOFT-START TIME
vs. SOFT-START CAPACITANCE
STARTUP INTO PREBIASED OUTPUT
(RLOAD = 0.18Ω)
MAX8566 toc19
MAX8566 toc18
800
700
SOFT-START TIME (ms)
MAX8566
High-Efficiency, 10A, PWM
Internal-Switch Step-Down Regulator
600
500
400
300
200
7.5A
IIN (PEAK)
(5A/div)
0A
3.3V
VEN
(12V/div)
0V
1.8V
VOUT 0.9V
(1V/div)
0V
3V
VPWRGD
(2V/div)
0V
100
0
0
1
2
3
4
5
6
7
8
9
10
t = 400µs/div
CSS (µF)
10
______________________________________________________________________________________
High-Efficiency, 10A, PWM
Internal-Switch Step-Down Regulator
PIN
NAME
FUNCTION
1
MODE
Monotonic Startup Enable/Disable. Connect MODE to GND or to the center tap of an external
resistor-divider to enable/disable monotonic startup mode.
2
COMP
Error-Amplifier Output. Connect the necessary compensation network from COMP to FB. COMP is
internally pulled to GND when the IC is in shutdown mode.
3
PWRGD
4
BST
5–12
LX
13–17
PGND
18–22
IN
23
LSS
Low-Side MOSFET-Driver Supply Voltage. Connect LSS to a 2.3V to 3.6V supply voltage.
24
VDD
IC Supply Voltage Input. Connect VDD to IN through an external 2 resistor. Bypass VDD to GND
with a 4.7µF capacitor.
25
REFIN
26
SS
Soft-Start Input. Connect a capacitor from SS to GND to set the soft-start time. See the Soft-Start and
REFIN section.
27
EN
Enable Input. Active-high logic input to enable/disable the MAX8566. Connect EN to IN to enable
the IC. Connect EN to GND to disable the IC.
28
SYNC
Synchronization Input. Synchronize to an external clock with a frequency of 250kHz to 2.4MHz.
Leave SYNC unconnected to disable the synchronization function.
29
FREQ
Oscillator Frequency Selection. Connect a resistor from FREQ to GND to select the switching
frequency. See the Frequency Select (FREQ) section.
30
SYNCOUT
31
GND
Power-Good Output. Open-drain output that is high impedance when VFB 90% of 0.6V. Otherwise,
PWRGD is internally pulled low. PWRGD is internally pulled low when the IC is in shutdown mode,
VDD is below the UVLO threshold, or the IC is in thermal shutdown.
High-Side MOSFET Driver Supply. Bypass BST to LX with a 0.1µF capacitor. BST is connected to
LSS through an internal pMOS switch.
Inductor Connection. All LX pins are internally connected together. Connect all LX pins to the
switched side of the inductor. LX is high impedance when the IC is in shutdown mode.
Power Ground. All PGND pins are internally connected. Connect all PGND pins externally to the
power ground plane.
Input Power Supply. All IN pins are internally connected. Connect all IN pins externally to an input
supply from 2.3V to 3.6V. Bypass IN to PGND with 20µF of ceramic capacitance.
External Reference Input. Connect to an external reference. FB regulates to the voltage at REFIN.
Connect REFIN to SS to use the internal reference.
Oscillator Output. The SYNCOUT output is 180° out-of-phase from the internal oscillator or the
SYNC signal to facilitate running a second regulator 180° out-of-phase with the first to reduce input
ripple current.
Analog Circuit Ground
32
FB
Feedback Input. Connect FB to the center tap of an external resistor-divider from the output to GND
to set the output voltage.
—
EP
Exposed Pad. Internally connected to GND. Connect to a large ground plane to maximize thermal
performance. Not indented as an electrical connection point.
______________________________________________________________________________________
11
MAX8566
Pin Description
MAX8566
High-Efficiency, 10A, PWM
Internal-Switch Step-Down Regulator
VDD
SHUTDOWN
CONTROL
EN
UVLO
CIRCUITRY
CURRENT-LIMIT
COMPARATOR
BST
ILIM THRESHOLD
LX
BIAS
GENERATOR
IN
P
VOLTAGE
REFERENCE
LSS
N
LX
CONTROL
LOGIC
SS
SOFT-START
REFIN
THERMAL
SHUTDOWN
+
ERROR
AMPLIFIER
-
FB
N
PWM
COMPARATOR
-
PGND
LSS
MODE
+
COMP
FREQ
SYNC
SYNCOUT
OSCILLATOR
COMP LOW
DETECTOR
SHDN
PWRGD
FB
MAX8566
N
0.54V
GND
Figure 1. Functional Diagram
12
______________________________________________________________________________________
High-Efficiency, 10A, PWM
Internal-Switch Step-Down Regulator
The MAX8566 high-efficiency, voltage-mode switching
regulator is capable of delivering up to 10A of output
current. The MAX8566 provides output voltages from
0.6V to (0.87 x VIN) from 2.3V to 3.6V input supplies,
making it ideal for on-board point-of-load applications.
The output voltage accuracy is better than ±1% over
load, line, and temperature.
The MAX8566 features a wide switching frequency
range, allowing the user to achieve all-ceramic-capacitor designs and faster transient responses. The high
operating frequency minimizes the size of external
components. The MAX8566 also features a wide 2.3V
to 3.6V input voltage range, making it ideal for point-ofload applications with both 3.3V and 2.5V input voltages. The MAX8566 is available in a small (5mm x
5mm), 32-pin TQFN package. The SYNCOUT function
allows end users to operate two MAX8566s at the same
switching frequency with 180° out-of-phase operation
to minimize the input ripple current, consequently
reducing the input capacitance requirements. The
REFIN function makes the MAX8566 an ideal candidate
for DDR and tracking power supplies. Using internal
low-RDS(ON) (8mΩ) n-channel MOSFETs for both highand low-side switches maintains high efficiency at both
heavy-load and high-switching frequencies. In addition,
the MAX8566 features a low-side-driver supply input
(LSS) to boost the efficiency with a higher driver voltage (3.3V) for 2.5V input applications.
The MAX8566 employs the voltage-mode control architecture with a high bandwith (> 10MHz) error amplifier.
The voltage-mode control architecture allows above
2MHz switching, reducing board area. The op-amp
voltage error amplifier works with Type 3 compensation
to fully utilize the bandwidth of the high-frequency
switching to obtain fast transient response. Adjustable
soft-start time provides flexibilities to minimize input
startup inrush current. An open-drain power-good
(PWRGD) output goes high when VFB reaches 0.54V.
Principle of Operation
The controller logic block is the central processor that
determines the duty cycle of the high-side MOSFET
under different line, load, and temperature conditions.
Under normal operation, where the current limit and
temperature protection are not triggered, the controller
logic block takes the output from the PWM comparator
and generates the driver signals for both high-side and
low-side MOSFETs. The break-before-make logic and
the timing for charging the bootstrap capacitors are
calculated by the controller logic block. The error signal
from the voltage error amplifier is compared with the
ramp signal generated by the oscillator at the PWM
comparator and thus the required PWM signal is produced. The high-side switch is turned on at the beginning of the oscillator cycle and turns off when the ramp
voltage exceeds the VCOMP signal or the current-limit
threshold is exceeded. The low-side switch is then
turned on for the remainder of the oscillator cycle.
Current Limit
The internal, high-side MOSFET has a typical 15A peak
current-limit threshold. When current flowing out of LX
exceeds this limit, the high-side MOSFET turns off and
the synchronous rectifier turns on. The synchronous
rectifier remains on until the inductor current falls below
the low-side current limit. This lowers the duty cycle
and causes the output voltage to droop until the current
limit is no longer exceeded.
The MAX8566 uses a hiccup mode to prevent overheating during short-circuit output conditions. The
device enters hiccup mode when V FB drops below
420mV and the current limit is reached. The IC turns off
for 3.4ms and then enters soft-start. If the short-circuit
condition remains after the soft-start time, the IC shuts
down for another 3.4ms. The IC repeats this behavior
until the short-circuit condition is removed.
Soft-Start and REFIN
The MAX8566 utilizes an adjustable soft-start function
to limit inrush current during startup. An 8µA (typ) current source charges an external capacitor connected to
SS to increase the capacitor voltage in a controlled
manner. The soft-start time is adjusted by the value of
the external capacitor from SS to GND. The required
capacitance value is determined as:
C=
8µ A × t SS
0 . 6V
where tSS is the required soft-start time in seconds.
The MAX8566 also features an external reference input
(REFIN). The IC regulates FB to the voltage applied to
REFIN. The internal soft-start is not available when
using an external reference. A method of soft-start
when using an external reference is shown in Figure 2.
Connect REFIN to SS to use the internal 0.6V reference.
______________________________________________________________________________________
13
MAX8566
Detailed Description
High-Efficiency, 10A, PWM
Internal-Switch Step-Down Regulator
MAX8566
High-Side MOSFET Driver Supply (BST)
The gate-drive voltage for the high-side, n-channel
switch is generated by a flying-capacitor boost circuit.
The capacitor between BST and LX is charged from the
VLSS supply while the low-side MOSFET is on. When
the low-side MOSFET is switched off, the stored voltage
of the capacitor is stacked above LX to provide the
necessary turn-on voltage for the high-side internal
MOSFET.
R1
REFIN
C
R2
MAX8566
Frequency Select (FREQ)
Figure 2. Soft-Start Implementation with External Reference
Undervoltage Lockout (UVLO)
The UVLO circuitry inhibits switching when V DD is
below 2V. Once VDD rises above 2V, UVLO clears and
the soft-start function activates. A 100mV hysteresis is
built in for glitch immunity.
Monotonic Startup Modes (MODE)
When starting up into a precharged output, the MAX8566
does not discharge the output prior to entering soft-start
(known as monotonic startup). Drive MODE to 1/3 of VDD
to enable monotonic startup mode. Connect MODE to
GND to disable monotonic startup mode.
23
18
VIN
2.3V TO 3.6V
19
20
21
C3
0.22µF
C2
10µF
22
24
R2
20kΩ
LX
LX
IN
IN
IN
LX
LX
LX
C4
1µF
3
27
LX
LX
LX
PGND
PGND
PGND
PWRGD
PGND
PGND
EN
R17
20kΩ
FB
1
25
R18
10kΩ
28
29
R3
50kΩ
MODE
COMP
REFIN
SYNC
SYNCOUT
SS
FREQ
GND
31
⎞
0 . 05µ s ⎟
⎠
SYNC Function (SYNC, SYNCOUT)
IN
MAX8566
−
The MAX8566 features a SYNC function that allows the
switching frequency to be synchronized to any frequency between 250kHz to 2.4MHz. Drive SYNC with a
IN
VDD
50k Ω ⎛ 1
×
0 . 95µ s ⎜⎝ fs
where fS is the desired switching frequency in Hz.
BST
LSS
R1
10Ω
POWER-GOOD
OUTPUT
R FREQ =
C5
0.047µF
C24
OPEN
C1
10µF
The switching frequency is resistor programmable from
250kHz to 2.4MHz. Set the switching frequency of the
IC with a resistor from FREQ to GND (RFREQ). RFREQ is
calculated as:
L1
0.47µH
4
5
6
7
8
C6
22µF
2kΩ
VOUT
1.8V AT 10A
C7
22µF
R4
100Ω
9
10
11
12
17
16
3300pF
R5
24.9kΩ
15
14
13
R6
12.4kΩ
32
2
R7
16.9kΩ
C9
330pF
30
26
C11
0.022µF
C10
22pF
Figure 3. Typical Application Circuit
14
______________________________________________________________________________________
C8
120pF
High-Efficiency, 10A, PWM
Internal-Switch Step-Down Regulator
The MAX8566 has a SYNCOUT output that generates a
clock signal that is 180° out-of-phase with its internal
oscillator, or the signal applied to SYNC. This allows for
another regulator to be synchronized 180° out-of-phase
to reduce the input ripple current.
Power-Good Output (PWRGD)
PWRGD is an open-drain output that goes high impedance once the soft-start ramp has concluded, provided
V FB is above 0.54V. PWRGD pulls low when V FB is
below 0.54V for at least 50µs. PWRGD is low during
shutdown.
Low-Side MOSFET Driver Supply (LSS)
The MAX8566 provides an external input for the lowside MOSFET driver supply (LSS). This allows for higher gate-drive voltages to maximize converter efficiency
at low input voltages.
Shutdown Mode
Drive EN to GND to shut down the IC and reduce quiescent current to 4µA. During shutdown, the output is
high impedance. Drive EN high to enable the
MAX8566.
Thermal Protection
Thermal-overload protection limits total power dissipation in the device. When the junction temperature
exceeds T J = +165°C a thermal sensor forces the
device into shutdown, allowing the die to cool. The thermal sensor turns the device on again after the junction
temperature cools by 20°C, causing a pulsed output
during continuous overload conditions. The soft-start
sequence begins after a thermal-shutdown condition.
Applications Information
VDD Decoupling
To decrease the noise effects due to the high switching
frequency and maximize the output accuracy of the
MAX8566, decouple VDD with a 4.7µF capacitor from
VDD to GND and a 2Ω resistor from VDD to VIN. Place
the capacitor as close to VDD as possible.
Inductor Design
Choose an inductor with the following equation:
L=
VOUT × ( VIN − VOUT )
fs × VIN × LIR × IOUT(MA X)
where LIR is the ratio of the inductor ripple current to
average continuous current at the minimum duty cycle.
Choose the LIR between 20% to 40% for best performance and stability.
Use a low-loss inductor with the lowest possible DC
resistance that fits in the allotted dimensions. Powered
iron ferrite core types are often the best choice for performance. With any core material the core must be
large enough not to saturate at the peak inductor current (IPEAK). Calculate IPEAK as follows:
LIR ⎞
⎛
× IOUT(MAX)
IPEAK = ⎜ 1 +
⎝
2 ⎟⎠
Output Capacitor Selection
The key selection parameters for the output capacitor
are capacitance, ESR, ESL, and voltage rating requirements. These affect the overall stability, output ripple
voltage, and transient response of the DC-DC converter. The output ripple occurs due to variations in the
charge stored in the output capacitor, the voltage drop
due to the capacitor’s ESR, and the voltage drop due to
the capacitor’s ESL. Calculate the output voltage ripple
due to the output capacitance, ESR, and ESL as:
VRIPPLE = VRIPPLE(C) + VRIPPLE(ESR) + VRIPPLE(ESL)
where the output ripple due to output capacitance,
ESR, and ESL are:
IP −P
8 × C OUT × fs
VRIPPLE(ESR) = IP −P × ESR
VRIPPLE(C) =
I
VRIPPLE(ESL) = P −P × ESL
t ON
I
or VRIPPLE(ESL) = P −P × ESL, whichever is greater.
t OFF
______________________________________________________________________________________
15
MAX8566
square wave at the desired synchronization frequency.
A rising edge on SYNC triggers the internal SYNC circuitry. The frequency of the input into SYNC must be
higher than the internal oscillator frequency set by
RFREQ. Leave SYNC disconnected to disable the function and operate on the internal oscillator.
MAX8566
High-Efficiency, 10A, PWM
Internal-Switch Step-Down Regulator
determines the zero. The double pole and zero frequencies are given as follows:
The peak inductor current (IP-P) is:
IP −P =
VIN − VOUT VOUT
×
fs × L
VIN
Use these equations for initial capacitor selection.
Determine final values by testing a prototype or an
evaluation circuit. A smaller ripple current results in less
output voltage ripple. Since the inductor ripple current
is a factor of the inductor value, the output voltage ripple decreases with larger inductance. Use ceramic
capacitors for low ESR and low ESL at the switching
frequency of the converter. The low ESL of ceramic
capacitors makes ripple voltages negligible.
Load-transient response depends on the selected output capacitance. During a load transient, the output
instantly changes by ESR x ILOAD. Before the controller
can respond, the output deviates further, depending on
the inductor and output capacitor values. After a short
time (see the Typical Operating Characteristics), the
controller responds by regulating the output voltage
back to its predetermined value. The controller
response time depends on the closed-loop bandwidth.
A higher bandwidth yields a faster response time, preventing the output from deviating further from its regulating value. See the Compensation Design section for
more details.
Input Capacitor Selection
The input capacitor reduces the current peaks drawn
from the input power supply and reduces switching
noise in the IC. The impedance of the input capacitor at
the switching frequency should be less than that of the
input source so high-frequency switching currents do
not pass through the input source but are instead
shunted through the input capacitor. High source
impedance requires high input capacitance. The input
capacitor must meet the ripple-current requirement
imposed by the switching currents. The RMS input ripple current is given by:
IRIPPLE = ILOAD ×
VOUT × ( VIN − VOUT )
VIN
where IRIPPLE is the input RMS ripple current.
Compensation Design
The power transfer function consists of one double pole
and one zero. The double pole is introduced by the output filtering inductor, L, and the output filtering capacitor, C O . The ESR of the output filtering capacitor
16
fP1_ LC = fP2 _ LC =
f Z _ ESR =
1
⎛ R + ESR ⎞
2π × L × C O × ⎜ O
⎟
⎝ R O + RL ⎠
1
2π × ESR × C O
where RL is equal to the sum of the output inductor’s
DCR and the internal switch resistance, RDS(ON). A
typical value for RDS(ON) is 8mΩ. RO is the output load
resistance, which is equal to the rated output voltage
divided by the rated output current. ESR is the total
equivalent series resistance of the output filtering
capacitor. If there is more than one output capacitor of
the same type in parallel, the value of the ESR in the
above equation is equal to that of the ESR of a single
output capacitor divided by the total number of output
capacitors.
The high switching frequency range of the MAX8566
allows the use of ceramic output capacitors. Since the
ESR of ceramic capacitors is typically very low, the frequency of the associated transfer-function zero is higher than the unity-gain crossover frequency, fC, and the
zero cannot be used to compensate for the double pole
created by the output filtering inductor and capacitor.
The double pole produces a gain drop of 40dB and a
phase shift of 90 degrees per decade. The error amplifier must compensate for this gain drop and phase shift
to achieve a stable high-bandwidth closed-loop system. Therefore, use Type 3 compensation as shown in
Figure 4. Type 3 compensation possesses three poles
and two zeros with the first pole, fP1_EA, located at zero
frequency (DC). Locations of other poles and zeros of
the Type 3 compensation are given by:
1
f Z1_ EA =
2π × R1 × C1
1
f Z2 _ EA =
2π × R3 × C3
1
2π × R1 × C2
1
fP3 _ EA =
2π × R2 × C3
fP2 _ EA =
The above equations are based on the assumptions
that C1>>C2, and R3>>R2, which are true in most
applications. Placement of these poles and zeros is
______________________________________________________________________________________
High-Efficiency, 10A, PWM
Internal-Switch Step-Down Regulator
L
LX
R2
MAX8566
R3
C3
R1 =
1
×
0. 8 × C1
C3 =
1
×
0. 8 × R3
FB
R1
C1
COMP
R4
L × C O × ( R O + ESR )
RL + R O
Set the second compensation pole, fP2_EA, at fZ_ESR
yields:
C2
C2 =
Figure 4. Type 3 Compensation Network
determined by the frequencies of the double pole and
ESR zero of the power transfer function. It is also a function of the desired closed-loop bandwidth. The following
section outlines the step-by-step design procedure to
calculate the required compensation components.
Begin by setting the desired output voltage. The output
voltage is set using a resistor-divider from the output to
GND with FB at the center tap (R3 and R4 in Figure 4).
Use 20kΩ for R4 and calculate R3 as:
⎛V
R3 = R4 × ⎜ OUT
⎝ 0 . 6V
L × C O × ( R O + ESR )
RL + R O
⎞
⎠
− 1⎟
The zero-cross frequency of the closed-loop, fC, should
be less than 20% of the switching frequency, fS.
Higher zero-cross frequency results in faster transient
response. It is recommended that the zero-cross frequency of the closed loop should be chosen between
10% and 20% of the switching frequency. Once fC is
chosen, C1 is calculated from the following equation:
V
1. 5625 × IN
VP -P
C1 =
⎛
R ⎞
fC × 2 × π × R3 × ⎜ 1 + L ⎟
RO ⎠
⎝
where VP-P is the ramp peak-to-peak voltage (1V typ).
C O × C1 × ESR
R1 × C1 − C O × ESR
Set the third compensation pole at 1/2 of the switching
frequency to gain some phase margin. Calculate R2 as
follows:
R2 =
1
π × C3 × fS
The above equations provide accurate compensation
when the zero-cross frequency is significantly higher
than the double-pole frequency. When the zero-cross
frequency is near the double-pole frequency, the actual
zero-cross frequency is higher than the calculated frequency. In this case, lowering the value of R1 reduces
the zero-cross frequency. Also, set the third pole of the
Type 3 compensation close to the switching frequency
if the zero-cross frequency is above 200kHz to boost
the phase margin. Note that the value of R4 can be
altered to make the values of the compensation components practical. The recommended range for R4 is
10kΩ to 50kΩ.
PCB Layout Considerations
and Thermal Performance
The MAX8566EVKIT provides an optimal layout and
should be followed closely. For custom design, follow
these guidelines:
1) Place decoupling capacitors (VDD and SS) as close
to the IC as possible. Keep the power ground plane
(connected to PGND) and signal ground plane (connected to GND) separate.
______________________________________________________________________________________
17
MAX8566
Due to the underdamped nature of the output LC double pole, set the two zero frequencies of the Type 3
compensation less than the LC double-pole frequency
to provide adequate phase boost. Set the two zero frequencies to 80% of the LC double-pole frequency.
Hence:
MAX8566
High-Efficiency, 10A, PWM
Internal-Switch Step-Down Regulator
OPEN-LOOP
GAIN
COMPENSATION
TRANSFER
FUNCTION
THE THIRD
POLE
DOUBLE POLE
GAIN
(dB)
THE SECOND
POLE
POWER-STAGE
TRANSFER FUNCTION
THE FIRST AND
SECOND ZEROS
FREQUENCY
Figure 5. Transfer Function for Type 3 Compensation
2) Connect input and output capacitors to the power
ground plane; connect all other capacitors to the signal ground plane.
3) Keep the high-current paths as short and wide as
possible. Keep the path of switching current short
and minimize the loop area formed by LX, the output
capacitors, and the input capacitors.
18
4) Connect IN, LX, and PGND separately to a large
copper area to help cool the IC to further improve
efficiency and long-term reliability.
5) Ensure all feedback connections are short and
direct. Place the feedback resistors and compensation components as close to the IC as possible.
6) Route high-speed switching nodes away from sensitive analog areas (FB, COMP).
______________________________________________________________________________________
High-Efficiency, 10A, PWM
Internal-Switch Step-Down Regulator
LSS
IN
IN
IN
IN
IN
PGND
TOP VIEW
VDD
PROCESS: BiCMOS
24
23
22
21
20
19
18
17
Package Information
REFIN
25
16
PGND
SS
26
15
PGND
EN
27
14
PGND
SYNC
28
13
PGND
FREQ
29
12
LX
SYNCOUT
30
11
LX
GND
31
10
LX
FB
32
9
LX
5
6
7
8
LX
LX
PWRGD
4
LX
3
LX
2
BST
1
COMP
*EP
MODE
+
MAX8566
For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
32 TQFN-EP
T3255+4
21-0140
90-0012
THIN QFN
*CONNECT EP TO GND.
______________________________________________________________________________________
19
MAX8566
Chip Information
Pin Configuration
MAX8566
High-Efficiency, 10A, PWM
Internal-Switch Step-Down Regulator
Revision History
REVISION
NUMBER
REVISION
DATE
0
6/05
Initial release
1
2/09
Made corrections to Ordering Information, Pin Description, Compensation Design section,
Pin Configuration, and Package Information
2
12/10
Modified the Typical Application Circuit (Figure 3) to change the 2.4kΩ resistor to 2kΩ
14
3
3/11
Corrected error in C1 equation and added descriptive verbiage
17
DESCRIPTION
PAGES
CHANGED
—
1, 11, 17,
19, 20, 21
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2011 Maxim Integrated Products
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