Revised November 1999 74ABT240 Octal Buffer/Line Driver with 3-STATE Outputs General Description Features The ABT240 is an inverting octal buffer and line driver designed to be employed as a memory address driver, clock driver and bus oriented transmitter or receiver which provides improved PC board density. ■ Output sink capability of 64 mA, source capability of 32 mA ■ Guaranteed latchup protection ■ High impedance glitch free bus loading during entire power up and power down cycle ■ Nondestructive hot insertion capability Ordering Code: Order Number 74ABT240CSC 74ABT240CSJ Package Number M20B M20D Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ABT240CMSA MSA20 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 74ABT240CMTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names Description OE1, OE2 3-STATE Output Enable Inputs I0–I7 Inputs O0–O7 Outputs Truth Tables Inputs OE1 In Outputs (Pins 12, 14, 16, 18) L L L H L H X Z Inputs H Outputs (Pins 3, 5, 7, 9) OE2 In L L L H L H X Z H H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance © 1999 Fairchild Semiconductor Corporation DS011664 www.fairchildsemi.com 74ABT240 Octal Buffer/Line Driver with 3-STATE Outputs March 1994 74ABT240 Absolute Maximum Ratings(Note 1) Storage Temperature −65°C to +150°C Junction Temperature under Bias −55°C to +150°C Recommended Operating Conditions −40°C to +85°C Free Air Ambient Temperature VCC Pin Potential to Ground Pin −0.5V to +7.0V Supply Voltage Input Voltage (Note 2) −0.5V to +7.0V Minimum Input Edge Rate (∆V/∆t) Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Any Output +4.5V to +5.5V Data Input 50 mV/ns Enable Input 20 mV/ns in the Disabled or Power-Off State −0.5V to 5.5V in the HIGH State −0.5V to VCC Current Applied to Output in LOW State (Max) twice the rated IOL (mA) DC Latchup Source Current (Across Comm Operating Range) −150 mA Over Voltage Latchup (I/O) Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. 10V Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol Parameter Min Typ Max 2.0 Units VCC V Conditions VIH Input HIGH Voltage VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V Min VOH Output HIGH Voltage 2.5 V Min IOH = −3 mA 2.0 V Min IOH = −32 mA V Min VOL Output LOW Voltage 0.55 IIH Input HIGH Current 1 IBVI Input HIGH Current Breakdown Test 7 IIL Input LOW Current −1 1 −1 VID Input Leakage Test 4.75 IOZH Output Leakage Current IOZL Output Leakage Current IOS Output Short-Circuit Current ICEX Recognized HIGH Signal Recognized LOW Signal µA Max µA Max µA Max V 0.0 IIN = −18 mA IOL = 64 mA VIN = 2.7V (Note 3) VIN = VCC VIN = 7.0V VIN = 0.5V (Note 3) VIN = 0.0V IID = 1.9 µA All Other Pins Grounded 10 µA 0 − 5.5V VOUT = 2.7V; OEn = 2.0V 0 − 5.5V VOUT = 0.5V; OEn = 2.0V −10 µA −275 mA Max VOUT = 0.0V Output HIGH Leakage Current 50 µA Max VOUT = VCC IZZ Bus Drainage Test 100 µA 0.0 VOUT = 5.5V; All Others GND ICCH Power Supply Current 50 µA Max All Outputs HIGH ICCL Power Supply Current 30 mA Max All Outputs LOW ICCZ Power Supply Current 50 µA Max −100 OEn = VCC; All Others at VCC or Ground ICCT Additional ICC/Input Outputs Enabled 1.5 mA VI = VCC − 2.1V Outputs 3-STATE 1.5 mA Enable Input VI = VCC − 2.1V Outputs 3-STATE 50 µA Max Data Input VI = VCC − 2.1V All Others at VCC or Ground ICCD Dynamic ICC No Load mA/ (Note 3) 0.1 MHz Outputs Open Max OEn = GND, (Note 4) One Bit Toggling, 50% Duty Cycle Note 3: Guaranteed, but not tested. Note 4: For 8 bits toggling, ICCD < 0.8 mA/MHz. www.fairchildsemi.com 2 Symbol Parameter Min TA = +25°C TA = −55°C to +125°C TA = −40°C to +85°C VCC = +5V VCC = 4.5V–5.5V VCC = 4.5V–5.5V CL = 50 pF CL = 50 pF Typ CL = 50 pF Max Min Max Min Max tPLH Propagation Delay 1.0 4.8 0.8 5.5 1.0 4.8 tPHL Data to Outputs 1.6 4.8 1.0 5.5 1.6 4.8 tPZH Output Enable 1.1 6.2 0.8 7.5 1.1 6.2 tPZL Time 1.1 6.2 0.8 7.7 1.1 6.2 tPHZ Output Disable 1.8 6.4 1.0 7.5 1.8 6.4 tPLZ Time 1.6 5.8 1.0 7.2 1.6 5.8 Units ns ns ns Capacitance Symbol Parameter Typ Units Conditions TA = 25°C CIN Input Capacitance 5.0 pF VCC = 0V COUT (Note 5) Output Capacitance 9.0 pF VCC = 5.0V Note 5: COUT is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012. 3 www.fairchildsemi.com 74ABT240 AC Electrical Characteristics 74ABT240 AC Loading *Includes jig and probe capacitance Standard AC Test Load Test Input Signal Levels Amplitude Rep. Rate tW tr tf 3.0V 1 MHz 500 ns 2.5 ns 2.5 ns Test Input Signal Requirements AC Waveforms Propagation Delay, Pulse Width Waveforms Propagation Delay Waveforms for Inverting and Non-Inverting Functions 3-STATE Output HIGH and LOW Enable and Disable Times Setup Time, Hold Time and Recovery Time Waveforms www.fairchildsemi.com 4 74ABT240 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body Package Number M20B 5 www.fairchildsemi.com 74ABT240 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.com 6 74ABT240 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide Package Number MSA20 7 www.fairchildsemi.com 74ABT240 Octal Buffer/Line Driver with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 8