Revised January 1999 74ABT16952 16-Bit Registered Transceiver with 3-STATE Outputs General Description Features The ABT16952 is a 16-bit registered transceiver. Two 8-bit back to back registers store data flowing in both directions between two bidirectional buses. Separate clock, clock enable and 3-STATE output enable signals are provided for each register. The output pins are guaranteed to source 32 mA and to sink 64 mA. ■ Separate clock, clock enable and 3-STATE output enable provided for each register ■ A and B output sink capability of 64 mA source capability of 32 mA ■ Guaranteed latchup protection ■ High impedance glitch free bus loading during entire power up and power down cycle ■ Nondestructive hot insertion capability Ordering Code: Order Number Package Number 74ABT16952CSSC MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide Package Description 74ABT16952CMTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the letter suffix “X” to the ordering code. Pin Descriptions Connection Diagram Pin Names A0–A15 Description Pin Assignment for SSOP Data Register A Inputs/ B-Register 3-STATE Outputs B0–B15 Data Register B Inputs/ A-Register 3-STATE Outputs CPABn, CPBAn Clock Pulse Inputs CEAn, CEBn Clock Enable OEABn, OEBAn Output Enable Inputs Output Control OE Internal Q Output Function H X Z Disable Outputs L L L Enable Outputs L H H Register Function Table (Applies to A or B Register) Inputs Internal D CP CE Q X H NC Hold Data L L Load Data L H L H X H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Function Z = HIGH Impedance = LOW-to-HIGH Transition NC = No Change © 1999 Fairchild Semiconductor Corporation DS011647.prf www.fairchildsemi.com 74ABT16952 16-Bit Registered Transceiver with 3-STATE Outputs November 1993 74ABT16952 Block Diagram n for either byte 1 or byte 2 www.fairchildsemi.com 2 −500 mA DC Latchup Source Current Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C Over Voltage Latchup (I/O) 10V Recommended Operating Conditions VCC Pin Potential to −0.5V to +7.0V Free Air Ambient Temperature Input Voltage (Note 2) −0.5V to +7.0V Supply Voltage Input Current (Note 2) −30 mA to +5.0 mA Ground Pin −0.5V to +5.5V −0.5V to VCC in the HIGH State Data Input 50 mV/ns Enable Input 20 mV/ns Clock Input 100 mV/ns Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Current Applied to Output twice the rated IOL (mA) in LOW State (Max) +4.5V to +5.5V Minimum Input Edge Rate (∆V/∆t) Voltage Applied to Any Output in the Disable or Power-Off State −40°C to +85°C Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol Parameter VIH Input HIGH Voltage Min Typ Max 2.0 Units VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V VOH Output HIGH Voltage VOL Output LOW Voltage VID Input Leakage Test IIH Input HIGH Current VCC V Conditions Recognized HIGH Signal Recognized LOW Signal Min IIN = −18 mA (Non I/O Pins) 2.5 IOH = −3 mA (An, Bn) 2.0 IOH = −32 mA (An, Bn) IOL = 64 mA (An, Bn) 0.55 4.75 V 0.0 µA Max IID = 1.9 µA (Non-I/O Pins) All Other Pins Grounded 1 IBVI Input HIGH Current VIN = 2.7V (Non-I/O Pins) (Note 4) VIN = VCC (Non-I/O Pins) 1 7 µA Max VIN = 7.0V (Non-I/O Pins) 100 µA Max VIN = 5.5V (An, B n) −1 µA Max Breakdown Test IBVIT Input HIGH Current Breakdown Test (I/O) IIL Input LOW Current −1 VIN = 0.5V (Non-I/O Pins) (Note 4) VIN = 0.0V (Non-I/O Pins) IIH + IOZH Output Leakage Current 10 µA 0V–5.5V VOUT = 2.7V (An, Bn); IIL + IOZL Output Leakage Current −10 µA 0V–5.5V VOUT = 0.5V (An, Bn); IOS Output Short-Circuit Current −275 mA ICEX Output HIGH Leakage Current 50 IZZ Bus Drainage Test 100 OEA or OEB = 2.0V OEA or OEB = 2.0V −100 Max VOUT = 0V (An, Bn) µA Max VOUT = VCC (An, Bn) µA 0.0V VOUT = 5.5V (An, Bn); All Others GND ICCH Power Supply Current 1.0 mA Max All Outputs HIGH ICCL Power Supply Current 60 mA Max All Outputs LOW ICCZ Power Supply Current 1.0 mA Max Outputs 3-STATE; ICCT Additional ICC/Input 2.5 mA Max VI = VCC − 2.1V; All Others ICCD Dynamic ICC All Others GND at VCC or GND No Load Outputs Open (Note 4) 0.18 mA/MHz Max OEA or OEB = GND, Non-I/O = GND or VCC One Bit toggling, 50% duty cycle (Note 3) Note 3: For 8-bit toggling, ICCD <1.4 mA/MHz. Note 4: Guaranteed, but not tested. 3 www.fairchildsemi.com 74ABT16952 Absolute Maximum Ratings(Note 1) 74ABT16952 AC Electrical Characteristics (SSOP Package) Symbol Parameter TA = +25°C TA = −40°C to +85°C VCC = +5.0V VCC = 4.5V to 5.5V CL = 50 pF CL = 50 pF Min Max Clock fmax Max Min 200 Units Max 200 MHz Frequency tPLH Propagation Delay 1.5 5.3 1.5 5.3 tPHL CPABn or CPBAn to 1.5 5.3 1.5 5.3 ns An or Bn tPZH Output Enable Time 1.5 5.5 1.5 5.5 tPZL OEABn or OEBAn to 1.5 5.5 1.5 5.5 ns An or Bn tPHZ Output Disable Time 1.5 6.0 1.5 6.0 tPLZ OEABn or OEBAn to 1.5 6.0 1.5 6.0 ns An or Bn AC Operating Requirements Symbol Parameter TA = +25°C TA = −40°C to +85°C VCC = +5.0V VCC = 4.5V to 5.5V CL = 50 pF CL = 50 pF Min Max Min tS(H) Setup Time, HIGH 2.5 2.5 tS(L) or LOW An or Bn 2.5 2.5 tH(H) Hold Time, HIGH 1.5 1.5 tH(L) or LOW An or Bn 1.5 1.5 tS(H) Setup Time, HIGH 2.5 2.5 tS(L) or LOW CEAn or CEBn 2.5 2.5 tH(H) Hold Time, HIGH 1.5 1.5 tH(L) or LOW CEAn or CEBn 1.5 1.5 tW(H) Pulse Width, 3.0 3.0 tW(L) HIGH or LOW 3.0 3.0 Units Max ns to CPABn or CPBAn ns to CPABn or CPBAn ns to CPABn or CPBAn ns to CPABn or CPBAn ns to CPABn or CPBAn Capacitance Symbol Parameter Typ Units Conditions TA = 25°C CIN Input Capacitance 5 pF VCC = 0V (Non I/O Pins) CI/O (Note 5) Output Capacitance 11 pF VCC = 5.0V (An, Bn) Note 5: CI/O is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012. www.fairchildsemi.com 4 74ABT16952 AC Loading *Includes jig and probe capacitance FIGURE 2. Test Input Signal Levels FIGURE 1. Standard AC Test Load Amplitude Rep. Rate tW tr tf 3.0V 1 MHz 500 ns 2.5 ns 2.5 ns FIGURE 3. Input Signal Requirements AC Waveforms FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions FIGURE 6. 3-STATE Output HIGH and LOW Enable and Disable Times FIGURE 5. Propagation Delay, Pulse Width Waveforms FIGURE 7. Setup Time, Hold Time and Recovery Time Waveforms 5 www.fairchildsemi.com 74ABT16952 Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide Package Number MS56A www.fairchildsemi.com 6 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56 LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 74ABT16952 16-Bit Registered Transceiver with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued)