Order this document by MTP3N120E/D SEMICONDUCTOR TECHNICAL DATA Motorola Preferred Device N–Channel Enhancement–Mode Silicon Gate TMOS POWER FET 3.0 AMPERES 1200 VOLTS RDS(on) = 5.0 OHM This advanced high–voltage TMOS E–FET is designed to withstand high energy in the avalanche mode and switch efficiently. This new high energy device also offers a drain–to–source diode with fast recovery time. Designed for high voltage, high speed switching applications such as power supplies, PWM motor controls, and other inductive loads, the avalanche energy capability is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. • Avalanche Energy Capability Specified at Elevated Temperature • Low Stored Gate Charge for Efficient Switching • Internal Source–to–Drain Diode Designed to Replace External Zener Transient Suppressor Absorbs High Energy in the Avalanche Mode • Source–to–Drain Diode Recovery Time Comparable to Discrete Fast Recovery Diode * See App. Note AN1327 — Very Wide Input Voltage Range; Off–line Flyback Switching Power Supply D G S CASE 221A–06, Style 5 TO–220AB MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Symbol Value Unit Drain–Source Voltage VDSS 1200 Vdc Drain–Gate Voltage (RGS = 1.0 MΩ) VDGR 1200 Vdc Gate–Source Voltage — Continuous Gate–Source Voltage — Non–Repetitive (tp ≤ 50 ms) VGS VGSM ± 20 ± 40 Vdc Vpk Drain Current — Continuous @ 25°C Drain Current — Continuous @ 100°C Drain Current — Single Pulse (tp ≤ 10 µs) ID ID IDM 3.0 2.2 11 Adc Total Power Dissipation Derate above 25°C PD 125 1.0 Watts W/°C TJ, Tstg – 55 to 150 °C Rating Operating and Storage Temperature Range UNCLAMPED DRAIN–TO–SOURCE AVALANCHE CHARACTERISTICS (TJ Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C (VDD = 100 Vdc, VGS = 10 Vdc, PEAK IL = 4.5 Apk, L = 10 mH, RG = 25 Ω) t150°C) EAS Apk mJ 101 THERMAL CHARACTERISTICS Thermal Resistance — Junction to Case Thermal Resistance — Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds RθJC RθJA 1.0 62.5 °C/W TL 260 °C E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc. Preferred devices are Motorola recommended choices for future use and best overall value. REV 1 TMOS Motorola Motorola, Inc. 1995 Power MOSFET Transistor Device Data 1 MTP3N120E ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Symbol Characteristic Min Typ Max Unit 1200 — — 1.28 — — Vdc mV/°C — — — — 10 100 — — 100 nAdc 2.0 — 3.0 7.1 4.0 — Vdc mV/°C — 4.0 5.0 Ohm — — — — 18.0 15.8 gFS 2.5 3.1 — mhos Ciss — 2130 2980 pF Coss — 1710 2390 Crss — 932 1860 td(on) — 13.6 30 tr — 12.6 30 td(off) — 35.8 70 tf — 20.7 40 QT — 31 40 Q1 — 8.0 — Q2 — 11 — Q3 — 14 — — — 0.80 0.65 1.0 — trr — 394 — ta — 118 — tb — 276 — QRR — 2.11 — — — 3.5 4.5 — — — 7.5 — OFF CHARACTERISTICS Drain–Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 µAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 1200 Vdc, VGS = 0 Vdc) (VDS = 1200 Vdc, VGS = 0 Vdc, TJ = 125°C) IDSS Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 Vdc) IGSS µAdc ON CHARACTERISTICS (1) Gate Threshold Voltage (VDS = VGS, ID = 250 µAdc) Temperature Coefficient (Negative) VGS(th) Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 1.5 Adc) RDS(on) Drain–Source On–Voltage (VGS = 10 Vdc) (ID = 3.0 Adc) (ID = 1.5 Adc, TJ = 125°C) VDS(on) Forward Transconductance (VDS = 15 Vdc, ID = 1.5 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (2) Turn–On Delay Time (VDD = 600 Vdc, ID = 3.0 Adc, VGS = 10 Vdc, RG = 9.1 Ω) Rise Time Turn–Off Delay Time Fall Time Gate Charge (VDS = 600 Vdc, ID = 3.0 Adc, VGS = 10 Vdc) ns nC SOURCE–DRAIN DIODE CHARACTERISTICS Forward On–Voltage (IS = 3.0 Adc, VGS = 0 Vdc) (IS = 3.0 Adc, VGS = 0 Vdc, TJ = 125°C) Reverse Recovery Time (IS = 3.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A/µs) Reverse Recovery Stored Charge VSD Vdc ns µC INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25″ from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25″ from package to source bond pad) LS nH (1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%. (2) Switching characteristics are independent of operating junction temperature. 2 Motorola TMOS Power MOSFET Transistor Device Data MTP3N120E TYPICAL ELECTRICAL CHARACTERISTICS 6 6 5 I D , DRAIN CURRENT (AMPS) I D , DRAIN CURRENT (AMPS) VDS ≥ 10 V VGS = 10 V TJ = 25°C 6V 4 3 2 5V 1 5 4 100°C 3 2 25°C 1 TJ = – 55°C 4V 0 6 12 18 24 30 3.0 3.4 3.8 4.2 4.6 5.0 5.4 5.8 VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) Figure 1. On–Region Characteristics Figure 2. Transfer Characteristics TJ = 100°C VGS = 10 V 6 4 25°C 2 – 55°C 0 1 2 3 4 5 6 RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS) VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) 8 0 0 6.2 5.4 TJ = 25°C 5.0 VGS = 10 V 4.6 15 V 4.2 3.8 0 1 2 3 4 5 6 ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) Figure 3. On–Resistance versus Drain Current and Temperature Figure 4. On–Resistance versus Drain Current and Gate Voltage 2.5 2.0 10,000 VGS = 0 V VGS = 10 V ID = 1.5 A TJ = 125°C 1,000 I DSS , LEAKAGE (nA) RDS(on) , DRAIN–TO–SOURCE RESISTANCE (NORMALIZED) RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS) 0 1.5 1.0 0.5 0 – 50 – 25 0 25 50 75 100 125 150 100°C 100 25°C 10 1 0 200 400 600 800 1000 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) Figure 5. On–Resistance Variation with Temperature Figure 6. Drain–To–Source Leakage Current versus Voltage Motorola TMOS Power MOSFET Transistor Device Data 1200 3 MTP3N120E POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (∆t) are determined by how fast the FET input capacitance can be charged by current from the generator. The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off–state condition when calculating td(on) and is read at a voltage corresponding to the on–state when calculating td(off). The published capacitance data is difficult to use for calculating rise and fall because drain–gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG – VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn–on and turn–off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG – VGSP)] td(off) = RG Ciss In (VGG/VGSP) 10,000 2800 VDS = 0 V VGS = 0 V TJ = 25°C Ciss Ciss 2000 Crss 1600 C, CAPACITANCE (pF) C, CAPACITANCE (pF) 2400 TJ = 25°C VGS = 0 V Ciss 1200 800 Coss 1,000 Coss 100 Crss 400 Crss 0 10 5 0 VGS 5 10 15 20 VDS 25 10 10 100 1000 DRAIN–TO–SOURCE VOLTAGE (VOLTS) GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS) Figure 7a. Capacitance Variation 4 Figure 7b. High Voltage Capacitance Variation Motorola TMOS Power MOSFET Transistor Device Data MTP3N120E 350 12 300 QT 10 250 200 8 Q2 Q1 6 VGS 150 ID = 3 A TJ = 25°C 4 2 0 0 4 50 VDS Q3 8 12 16 100 20 24 28 0 32 1000 t, TIME (ns) 14 VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) 400 VDS , DRAIN–TO–SOURCE VOLTAGE (VOLTS) 16 VDD = 600 V ID = 3 A VGS = 10 V TJ = 25°C 100 td(off) tf td(on) tr 10 1 Qg, TOTAL GATE CHARGE (nC) 1 10 RG, GATE RESISTANCE (OHMS) Figure 8. Gate–To–Source and Drain–To–Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance 100 DRAIN–TO–SOURCE DIODE CHARACTERISTICS I S , SOURCE CURRENT (AMPS) 3.0 VGS = 0 V TJ = 25°C 2.4 1.8 1.2 0.6 0 0.55 0.59 0.63 0.67 0.71 0.75 0.79 VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS) Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain–to–source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance–General Data and Its Use.” Switching between the off–state and the on–state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 µs. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) – TC)/(RθJC). A Power MOSFET designated E–FET can be safely used in switching circuits with unclamped inductive loads. For reli- Motorola TMOS Power MOSFET Transistor Device Data able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non–linearly with an increase of peak current in avalanche and peak junction temperature. Although many E–FETs can withstand the stress of drain– to–source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. 5 MTP3N120E SAFE OPERATING AREA 120 VGS = 20 V SINGLE PULSE TC = 25°C 10 EAS, SINGLE PULSE DRAIN–TO–SOURCE AVALANCHE ENERGY (mJ) I D , DRAIN CURRENT (AMPS) 100 10 µs 100 µs 1.0 1 ms 0.1 10 ms dc RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.01 0.1 1.0 10 100 1,000 ID = 3 A 100 80 60 40 20 0 10,000 25 50 75 100 125 150 VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 1.0 D = 0.5 0.2 0.1 0.1 P(pk) 0.05 0.02 t1 0.01 SINGLE PULSE 0.01 1.0E–05 1.0E–04 t2 DUTY CYCLE, D = t1/t2 1.0E–03 1.0E–01 1.0E–02 t, TIME (s) RθJC(t) = r(t) RθJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) – TC = P(pk) RθJC(t) 1.0E+00 1.0E+01 Figure 13. Thermal Response di/dt IS trr ta tb TIME 0.25 IS tp IS Figure 14. Diode Reverse Recovery Waveform 6 Motorola TMOS Power MOSFET Transistor Device Data MTP3N120E D1 – D4 1N4007s L1 H1 90VAC– 600VAC C1 0.1 1 kV C4 0.1 1 kV L1 +Vin H2 C3 0.0047 3 kV C2 0.0047 3 kV EARTH GND C6 100 mF 450 V + C5 100 mF 450 V + R4 470 k 1/2 W R3 470 k 1/2 W R2 470 k 1/2 W R1 470 k 1/2 W INPUT GND Figure 15. The AC Input/Filter Circuit Section T1 C11 D8 100 mF MBR370 10 V +Vin R9 R8 100 mF 20 V D9 MUR430 Vaux 82 k, 1/2 W R7 R6 R5 R16 100 k 1/2 W 10 mF 25 V + D10 + C13 C9 LL MUR1100 6 4 C7 220 pF 1 U2 1/2 MOC8102 2 5 3 R12 10 W R15 680 W U2 MOC8102 D6 D7 R13 1k R20 120 W C15 1.5 nF R19 32.4 k 1.3 mF 7.5 k C17 2.2 nF Q1 C8 1000 pF +5 V C14 MTP3N120E UC3845BN D5 3.3 V C12 Vaux 7 R10 27 k + + MUR130 C10 R11 1.8 k 1 nF 3 kV + +12 V U3 TL431 C16 R17 R21 2.49 k GND R14 1.2 W 1/2 W INPUT GND Figure 16. The DC/DC Converter Circuit Section Motorola TMOS Power MOSFET Transistor Device Data 7 MTP3N120E PACKAGE DIMENSIONS –T– B NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. SEATING PLANE C F T S 4 A Q 1 2 3 U STYLE 5: PIN 1. 2. 3. 4. H K Z L GATE DRAIN SOURCE DRAIN R V J G D N CASE 221A–06 ISSUE Y DIM A B C D F G H J K L N Q R S T U V Z INCHES MIN MAX 0.570 0.620 0.380 0.405 0.160 0.190 0.025 0.035 0.142 0.147 0.095 0.105 0.110 0.155 0.018 0.025 0.500 0.562 0.045 0.060 0.190 0.210 0.100 0.120 0.080 0.110 0.045 0.055 0.235 0.255 0.000 0.050 0.045 ––– ––– 0.080 MILLIMETERS MIN MAX 14.48 15.75 9.66 10.28 4.07 4.82 0.64 0.88 3.61 3.73 2.42 2.66 2.80 3.93 0.46 0.64 12.70 14.27 1.15 1.52 4.83 5.33 2.54 3.04 2.04 2.79 1.15 1.39 5.97 6.47 0.00 1.27 1.15 ––– ––– 2.04 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA / EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315 MFAX: [email protected] – TOUCHTONE (602) 244–6609 INTERNET: http://Design–NET.com HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 8 ◊ *MTP3N120E/D* Motorola TMOS Power MOSFET Transistor Device Data MTP3N120E/D