FAIRCHILD 74LCX14SJ

Revised February 2005
74LCX14
Low Voltage Hex Inverter
with 5V Tolerant Schmitt Trigger Inputs
General Description
Features
The LCX14 contains six inverter gates each with a Schmitt
trigger input. They are capable of transforming slowly
changing input signals into sharply defined, jitter-free output signals. In addition, they have a greater noise margin
than conventional inverters.
■ 5V tolerant inputs
The LCX14 has hysteresis between the positive-going and
negative-going input thresholds (typically 1.0V) which is
determined internally by transistor ratios and is essentially
insensitive to temperature and supply voltage variations.
■ r24 mA output drive (VCC
The inputs tolerate voltages up to 7V allowing the interface
of 5V, 3V and 2.5V systems.
The 74LCX14 is fabricated with advanced CMOS technology to achieve high speed operation while maintaining
CMOS low power dissipation.
■ 2.3V–3.6V VCC specifications provided
■ 6.5 ns tPD max (VCC
3.3V), 10 PA ICC max
■ Power down high impedance inputs and outputs
3.0V)
■ Implements patented noise/EMI reduction circuitry
■ Latch-up performance exceeds JEDEC 78 conditions
■ ESD performance:
Machine model ! 200V
Human model ! 2000V
■ Leadless Pb-Free DQFN package
Ordering Code:
Order Number
Package
Package Description
Number
74LCX14M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74LCX14MX_NL
(Note 2)
M14A
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74LCX14SJ
M14D
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LCX14BQX
(Note 1)
MLP014A
Pb-Free 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC
MO-241, 2.5 x 3.0mm
74LCX14MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74LCX14MTCX_NL
(Note 2)
MTC14
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: DQFN package available in Tape and Reel only.
Note 2: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
© 2005 Fairchild Semiconductor Corporation
DS012412
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74LCX14 Low Voltage Hex Inverter with 5V Tolerant Schmitt Trigger Inputs
March 1995
74LCX14
Connection Diagrams
Logic Symbol
IEEE/IEC
Pin Assignments for SOIC, SOP, and TSSOP
Pin Descriptions
Pad Assignments for DQFN
Pin Names
Description
In
Inputs
On
Outputs
Truth Table
Input
Output
A
O
L
H
H
L
(Top View)
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2
Symbol
Parameter
VCC
Supply Voltage
VI
DC Input Voltage
VO
DC Output Voltage
IIK
DC Input Diode Current
IOK
DC Output Diode Current
Value
IO
DC Output Source/Sink Current
ICC
DC Supply Current per Supply Pin
IGND
DC Ground Current per Ground Pin
TSTG
Storage Temperature
Conditions
0.5 to 7.0
0.5 to 7.0
0.5 to VCC 0.5
50
50
50
r50
r100
r100
65 to 150
Units
V
V
Output in HIGH or LOW State (Note 4)
VI GND
V
mA
VO GND
mA
VO ! VCC
mA
mA
mA
qC
Recommended Operating Conditions (Note 5)
Symbol
VCC
Parameter
Min
Max
Operating
2.0
3.6
Data Retention
1.5
3.6
Supply Voltage
VI
Input Voltage
VO
Output Voltage
IOH/IOL
Output Current
HIGH or LOW State
VCC
3.0V 3.6V
VCC
2.7V 3.0V
VCC
2.3V 2.7V
Units
V
0
5.5
V
0
VCC
V
r24
r12
r8
mA
Note 3: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.
Note 4: IO Absolute Maximum Rating must be observed.
Note 5: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
Vt
Vt
VH
VOH
Parameter
Conditions
Positive Input Threshold
Negative Input Threshold
Hysteresis
HIGH Level Output Voltage
IOH
100PA
IOH = -8 mA
VOL
LOW Level Output Voltage
40qC to 85qC
Min
Max
2.5
0.9
1.7
3.0
1.2
2.2
2.5
0.4
1.1
3.0
0.6
1.5
2.5
0.3
1.0
3.0
0.4
1.2
2.3 3.6
VCC - 0.2
2.3
1.8
12 mA
2.7
2.2
IOH
18 mA
3.0
2.4
3.0
2.2
IOH
24 mA
IOL
100PA
Units
V
V
V
V
2.3 3.6
0.2
IOL = 8mA
2.3
0.6
IOL
12 mA
2.7
0.4
IOL
16 mA
3.0
0.4
IOL
24 mA
V
3.0
0.55
2.3 3.6
r5.0
PA
0
10
PA
VCC or GND
2.3 3.6
10
3.6V d VI d 5.5V
2.3 3.6
r10
VCC 0.6V
2.3 3.6
500
Input Leakage Current
0 d VI d 5.5V
IOFF
Power-Off Leakage Current
VI or VO
ICC
Quiescent Supply Current
VI
Increase in ICC per Input
TA
(V)
IOH
II
'ICC
VCC
VIH
5.5V
3
PA
PA
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74LCX14
Absolute Maximum Ratings(Note 3)
74LCX14
AC Electrical Characteristics
TA
Symbol
Parameter
VCC
40qC to 85qC, RL
3.3V r 0.3V
CL 50 pF
tPHL
Propagation Delay Time
tPLH
VCC
2.7V
CL
50 pF
500 :
VCC
CL
2.5V r 0.2V
Min
Max
Min
Max
Min
Max
1.5
6.5
1.5
7.5
1.5
7.8
1.5
6.5
1.5
7.5
1.5
7.8
tOSHL
Output to Output Skew
1.0
tOSLH
(Note 6)
1.0
Units
30 pF
ns
ns
Note 6: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Dynamic Switching Characteristics
Symbol
VOLP
VOLV
Parameter
Quiet Output Dynamic Peak VOL
Quiet Output Dynamic Valley VOL
VCC
Conditions
TA
25qC
(V)
Typical
CL
50 pF, VIH 3.3V, VIL
0V
3.3
0.8
CL
30 pF, VIH
2.5V, VIL
0V
2.5
0.6
CL
50 pF, VIH
3.3V, VIL
0V
3.3
0.8
CL
30 pF, VIH 2.5V, VIL
0V
2.5
0.6
Units
V
V
Capacitance
Symbol
Parameter
Conditions
CIN
Input Capacitance
VCC
Open, VI
COUT
Output Capacitance
VCC
3.3V, VI
0V or VCC
CPD
Power Dissipation Capacitance
VCC
3.3V, VI
0V or VCC, f
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4
0V or VCC
10 MHz
Typical
Units
7
pF
8
pF
25
pF
74LCX14
AC Loading and Waveforms Generic for LCX Family
FIGURE 1. AC Test Circuit
(CL includes probe and jig capacitance)
Test
Switch
tPLH, tPHL
Open
tPZL, tPLZ
6V at VCC 3.3 r 0.3V
VCC x 2 at VCC 2.5 r 0.2V
tPZH,tPHZ
GND
Waveform for Inverting and Non-Inverting Functions
3-STATE Output Low Enable and
Disable Times for Logic
Propagation Delay, Pulse Width and trec Waveforms
Setup Time, Hold TIme and Recovery TIme for Logic
3-STATE Output High Enable and
Disable TImes for Logic
trise and tfall
FIGURE 2. Waveforms
(Input Pulse Characteristics; f = 1MHz, tr = tf = 3ns)
VCC
3.3V r 0.3V
2.7V
2.5V r 0.2V
Vmi
1.5V
1.5V
VCC/2
Vmo
1.5V
1.5V
VCC/2
Vx
VOL 0.3V
VOL 0.3V
VOL 0.15V
Vy
VOH 0.3V
VOH 0.3V
VOH 0.15V
Symbol
5
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74LCX14
Schematic Diagram Generic for LCX Family
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6
Tape Format for DQFN
Package
Designator
BQX
Tape
Number
Cavity
Section
Cavities
Status
Cover Tape
Status
Leader (Start End)
125 (typ)
Empty
Sealed
Carrier
2500/3000
Filled
Sealed
Trailer (Hub End)
75 (typ)
Empty
Sealed
TAPE DIMENSIONS inches (millimeters)
REEL DIMENSIONS inches (millimeters)
Tape Size
12 mm
A
B
C
D
N
W1
W2
13.0
0.059
0.512
0.795
7.008
0.488
0.724
(330)
(1.50)
(13.00)
(20.20)
(178)
(12.4)
(18.4)
7
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74LCX14
Tape and Reel Specification
74LCX14
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M14A
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8
74LCX14
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
9
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74LCX14
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 3.0mm
Package Number MLP014A
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10
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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74LCX14 Low Voltage Hex Inverter with 5V Tolerant Schmitt Trigger Inputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)