19-3641; Rev 1; 10/07 Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers The MAX9234/MAX9236/MAX9238 deserialize three LVDS serial-data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel-rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a separate supply, allowing 1.8V to 5V output logic levels. All these devices are hot-swappable and allow “on-the-fly” frequency programming. The MAX9234/MAX9236/MAX9238 feature DC balance, which allows isolation between a serializer and deserializer using AC-coupling. Each deserializer decodes data transmitted by one of the MAX9209/MAX9211/ MAX9213/MAX9215 serializers. The MAX9234 has a rising-edge output strobe. The MAX9236/MAX9238 have a falling-edge output strobe. The MAX9234/MAX9236/MAX9238 operate in DCbalanced mode only. The MAX9234/MAX9236 operate with a parallel input clock of 8MHz to 34MHz, while the MAX9238 operates from 16MHz to 66MHz. The transition time of the singleended outputs is increased on the low-frequency version parts (MAX9234/MAX9236) for reduced EMI. The LVDS inputs meet ISO 10605 ESD specification, ±25kV for AirGap Discharge and ±8kV Contact Discharge. The MAX9234/MAX9236/MAX9238 are available in 48-pin TSSOP packages and operate over the -40°C to +85°C temperature range. Applications Features ♦ DC Balance Allows AC-Coupling for Wider Input Common-Mode Voltage Range ♦ On-the-Fly Frequency Programming ♦ Operating Frequency Range 8MHz to 34MHz (MAX9234/MAX9236) 16MHz to 66MHz (MAX9238) ♦ Falling-Edge Output Strobe (MAX9236/MAX9238) ♦ Slower Output Transitions for Reduced EMI (MAX9234/MAX9236) ♦ High-Impedance Outputs when PWRDWN Is Low Allow Output Busing ♦ 5V-Tolerant PWRDWN Input ♦ PLL Requires No External Components ♦ Up to 1.386Gbps Throughput ♦ Separate Output Supply Pins Allow Interface to 1.8V, 2.5V, 3.3V, and 5V Logic ♦ LVDS Inputs Meet ISO 10605 ESD Requirements ♦ LVDS Inputs Conform to ANSI TIA/EIA-644 LVDS Standard ♦ Low-Profile, 48-Lead TSSOP Package ♦ +3.3V Main Power Supply ♦ -40°C to +85°C Operating Temperature Range Automotive Navigation Systems Ordering Information Automotive DVD Entertainment Systems Digital Copiers PART TEMP RANGE PINPACKAGE PKG CODE MAX9234EUM -40°C to +85°C 48 TSSOP U48-1 MAX9236EUM -40°C to +85°C 48 TSSOP U48-1 MAX9238EUM -40°C to +85°C 48 TSSOP U48-1 Laser Printers Functional Diagram and Pin Configuration appear at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX9234/MAX9236/MAX9238 General Description MAX9234/MAX9236/MAX9238 Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers ABSOLUTE MAXIMUM RATINGS VCC to GND ...........................................................-0.5V to +4.0V VCCO to GND.........................................................-0.5V to +6.0V RxIN_, RxCLK IN_ to GND ....................................-0.5V to +4.0V PWRDWN to GND....................................................-0.5V to 6.0V RxOUT_, RxCLK OUT to GND ................-0.5V to (VCCO + 0.5V) Continuous Power Dissipation (TA = +70°C) 48-Pin TSSOP (derate 16mW/°C above +70°C) ....... 1282mW Storage Temperature Range .............................-65°C to +150°C Junction Temperature ......................................................+150°C ESD Protection Human Body Model (RD = 1.5kΩ, CS = 100pF) All Pins to GND ..................................………………….±5kV IEC 61000-4-2 (RD = 330Ω, CS = 150pF) Contact Discharge (RxIN_, RxCLK IN_) to GND .........±8kV Air-Gap Discharge (RxIN_, RxCLK IN_) to GND .......±15kV ISO 10605 (RD = 2kΩ, CS = 330pF) Contact Discharge (RxIN_, RxCLK IN_) to GND ........±8kV Air Discharge (RxIN_, RxCLK IN_) to GND ...............±25kV Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, VCCO = +3.0V to +5.5V, PWRDWN = high, differential input voltage ⏐VID⏐ = 0.05V to 1.2V, input commonmode voltage VCM = ⏐VID/2⏐ to 2.4V - ⏐VID/2⏐, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = VCCO = +3.3V, ⏐VID⏐ = 0.2V, VCM = 1.25V, TA = +25°C.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SINGLE-ENDED INPUT (PWRDWN) High-Level Input Voltage VIH 2.0 5.5 V Low-Level Input Voltage VIL -0.3 +0.8 V Input Current IIN -70 +70 µA -1.5 V Input Clamp Voltage VCL VIN = high or low ICL = -18mA SINGLE-ENDED OUTPUTS (RxOUT_, RxCLK OUT) VCCO 0.1 IOH = -100µA High-Level Output Voltage RxCLK OUT VCCO 0.25 RxOUT_ VCCO 0.40 MAX9234/ MAX9236 VOH IOH = -2mA V VCCO 0.25 MAX9238 IOL = 100µA Low-Level Output Voltage VOL IOL = 2mA 0.1 MAX9234/ MAX9236 RxCLK OUT 0.2 RxOUT_ 0.26 MAX9238 High-Impedance Output Current Output Short-Circuit Current (Note: Short one output at a time.) 2 IOZ 0.2 PWRDWN = low, VOUT_ = -0.3V to VCCO + 0.3V VCCO = 3.0V to 3.6V, VOUT = 0 IOS VCCO = 4.5V to 5.5V, VOUT = 0 MAX9234/ MAX9236 -20 +20 RxCLK OUT -10 -40 RxOUT_ -5 -20 -10 -40 RxCLK OUT -28 -75 RxOUT_ -14 -37 -28 -75 MAX9238 MAX9234/ MAX9236 MAX9238 V _______________________________________________________________________________________ µA mA Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers (VCC = +3.0V to +3.6V, VCCO = +3.0V to +5.5V, PWRDWN = high, differential input voltage ⏐VID⏐ = 0.05V to 1.2V, input commonmode voltage VCM = ⏐VID/2⏐ to 2.4V - ⏐VID/2⏐, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = VCCO = +3.3V, ⏐VID⏐ = 0.2V, VCM = 1.25V, TA = +25°C.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 50 mV LVDS INPUTS Differential Input-High Threshold Differential Input-Low Threshold Input Current VTH VTL IIN+, IIN- Power-Off Input Current Input Resistor 1 IINO+, IINORIN1 -50 mV PWRDWN = high or low -25 +25 µA VCC = VCCO = 0 or open, PWRDWN = 0 or open -40 +40 µA 42 78 kΩ PWRDWN = high or low (Figure 1) VCC = VCCO = 0 or open (Figure 1) POWER SUPPLY Worst-Case Supply Current Power-Down Supply Current ICCW ICCZ CL = 8pF, worst-case pattern; VCC = VCCO = 3.0V to 3.6V, Figure 2 PWRDWN = low MAX9234/ MAX9236 MAX9238 8MHz 42 16MHz 57 34MHz 98 16MHz 63 34MHz 106 66MHz 177 50 mA µA _______________________________________________________________________________________ 3 MAX9234/MAX9236/MAX9238 DC ELECTRICAL CHARACTERISTICS (continued) MAX9234/MAX9236/MAX9238 Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers AC ELECTRICAL CHARACTERISTICS (VCC = VCCO = +3.0V to +3.6V, 100mVP-P at 200kHz supply noise, CL = 8pF, PWRDWN = high, differential input voltage ⏐VID⏐ = 0.1V to 1.2V, input common mode voltage VCM = ⏐VID/2⏐ to 2.4V - ⏐VID/2⏐, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = VCCO = +3.3V, ⏐VID⏐ = 0.2V, VCM = 1.25V, TA = +25°C.) (Notes 3, 4, 5) PARAMETER Output Rise Time Output Fall Time RxIN Skew Margin SYMBOL CLHT CHLT RSKM CONDITIONS 0.1VCCO to 0.9VCCO, Figure 3 MAX9234/ MAX9236 0.9VCCO to 0.1VCCO, Figure 3 MAX9234/ MAX9236 MIN 3.52 5.04 6.24 RxCLK OUT 2.2 3.15 3.9 2.2 3.15 3.9 RxOUT 1.95 3.18 4.35 RxCLK OUT 1.3 2.12 2.9 2.9 MAX9238 MAX9238 MAX RxOUT MAX9238 Figure 4 (Note 6) TYP 1.3 2.12 8MHz 6600 7044 16MHz 2560 3137 34MHz 900 1327 66MHz 330 685 UNITS ns ns ps RxCLK OUT High Time RCOH Figures 5a, 5b 0.35 x RCOP ns RxCLK OUT Low Time RCOL Figures 5a, 5b 0.35 x RCOP ns RxOUT Setup to RxCLK OUT RSRC Figures 5a, 5b 0.30 x RCOP ns RxOUT Hold from RxCLK OUT RHRC Figures 5a, 5b 0.45 x RCOP ns RxCLK IN to RxCLK OUT Delay RCCD Figures 6a, 6b 4.9 Deserializer Phase-Locked Loop Set RPLLS Deserializer Power-Down Delay RPDD 6.17 8.1 ns Figure 7 32800 x RCIP ns Figure 8 100 ns Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground except VTH and VTL. Note 2: Maximum and minimum limits overtemperature are guaranteed by design and characterization. Devices are production tested at TA = +25°C. Note 3: AC parameters are guaranteed by design and characterization, and are not production tested. Limits are set at ±6 sigma. Note 4: CL includes probe and test jig capacitance. Note 5: RCIP is the period of RxCLK IN. RCOP is the period of RxCLK OUT. RCIP = RCOP. Note 6: RSKM measured with ≤ 150ps cycle-to-cycle jitter on RxCLK IN. 4 _______________________________________________________________________________________ Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers (VCC = VCCO = +3.3V, CL = 8pF, PWRDWN = high, differential input voltage ⏐VID⏐ = 0.2V, input common-mode voltage VCM = 1.2V, TA = +25°C, unless otherwise noted.) MAX9234/MAX9236 WORST-CASE PATTERN AND PRBS SUPPLY CURRENT vs. FREQUENCY MAX9238 WORST-CASE PATTERN AND PRBS SUPPLY CURRENT vs. FREQUENCY 80 WORST CASE 70 60 27 - 1 PRBS 50 140 WORST CASE 120 100 40 27 - 1 PRBS 80 60 30 40 5 10 15 20 25 35 30 40 10 20 30 40 50 60 70 FREQUENCY (MHz) FREQUENCY (MHz) MAX9234/MAX9236 RxOUT TRANSITION TIME vs. OUTPUT SUPPLY VOLTAGE (VCCO) MAX9238 RxOUT TRANSITION TIME vs. OUTPUT SUPPLY VOLTAGE (VCCO) 6 CLHT 5 4 CHLT 3 2 5 OUTPUT TRANSITION TIME (ns) MAX9234/6/8 toc03 7 OUTPUT TRANSITION TIME (ns) MAX9234/6/8 toc02 160 MAX9234/6/8 toc04 SUPPLY CURRENT (mA) 90 180 SUPPLY CURRENT (mA) MAX9234/6/8 toc01 100 4 CLHT 3 2 CHLT 1 0 1 2.5 3.0 3.5 4.0 4.5 OUTPUT SUPPLY VOLTAGE (V) 5.0 2.5 3.0 3.5 4.0 4.5 5.0 OUTPUT SUPPLY VOLTAGE (V) _______________________________________________________________________________________ 5 MAX9234/MAX9236/MAX9238 Typical Operating Characteristics Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers MAX9234/MAX9236/MAX9238 Pin Description PIN 1, 2, 4, 5, 45, 46, 47 3, 25, 32, 38, 44 NAME FUNCTION RxOUT14–RxOUT20 Channel 2 Single-Ended Outputs GND Ground 6 N.C. No Connection 7, 13, 18 LVDS GND LVDS Ground 8 RxIN0- 9 RxIN0+ Noninverting Channel 0 LVDS Serial-Data Input 10 RxIN1- Inverting Channel 1 LVDS Serial-Data Input 11 RxIN1+ 12 LVDS VCC Inverting Channel 0 LVDS Serial-Data Input Noninverting Channel 1 LVDS Serial-Data Input LVDS Supply Voltage. Bypass to LVDS GND with 0.1µF and 0.001µF capacitors in parallel as close to LVDS VCC as possible, with the smallest value capacitor closest to the supply pin. 14 RxIN2- Inverting Channel 2 LVDS Serial-Data Input 15 RxIN2+ Noninverting Channel 2 LVDS Serial-Data Input 16 RxCLK IN- Inverting LVDS Parallel Rate Clock Input Noninverting LVDS Parallel Rate Clock Input 17 RxCLK IN+ 19, 21 PLL GND PLL Ground 20 PLL VCC PLL Supply Voltage. Bypass to PLL GND with 0.1µF and 0.001µF capacitors in parallel as close to PLL VCC as possible, with the smallest value capacitor closest to the supply pin. 22 PWRDWN 23 RxCLK OUT 24, 26, 27, 29, 30, 31, 33 RxOUT0–RxOUT6 28, 36, 48 VCCO 34, 35, 37, 39, 40, 41, 43 42 6 5V Tolerant LVTTL/LVCMOS Power-Down Input. Internally pulled down to GND. Outputs are high impedance when PWRDWN = low or open. Parallel Rate Clock Single-Ended Output. The MAX9234 has a rising-edge strobe. The MAX9236/MAX9238 have a falling-edge strobe. Channel 0 Single-Ended Outputs Output Supply Voltage. Bypass to GND with 0.1µF and 0.001µF capacitors in parallel as close to VCCO as possible, with the smallest value capacitor closest to the supply pin. RxOUT7–RxOUT13 Channel 1 Single-Ended Outputs VCC Digital Supply Voltage. Bypass to GND with 0.1µF and 0.001µF capacitors in parallel as close to VCC as possible, with the smallest value capacitor closest to the supply pin. _______________________________________________________________________________________ Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers PART EQUIVALENT WITH DCB/NC = HIGH OR OPEN OPERATING FREQUENCY (MHz) MAX9234 MAX9210 8 to 34 Rising edge MAX9236 MAX9220 8 to 34 Falling edge MAX9238 MAX9222 16 to 66 Falling edge Detailed Description The MAX9234/MAX9236 operate at a parallel clock frequency of 8MHz to 34MHz. The MAX9238 operates at a parallel clock frequency of 16MHz to 66MHz. The transition times of the single-ended outputs are increased on the MAX9234/MAX9236 for reduced EMI. DC Balance Data coding by the MAX9209/MAX9211/MAX9213/ MAX9215 serializers (which are companion devices to the MAX9234/MAX9236/MAX9238 deserializers) limits the imbalance of ones and zeros transmitted on each channel. If +1 is assigned to each binary 1 transmitted and -1 is assigned to each binary 0 transmitted, the variation in the running sum of assigned values is called the digital sum variation (DSV). The maximum DSV for the data channels is 10. At most, 10 more zeros than ones, or 10 more ones than zeros, are transmitted. The maximum DSV for the clock channel is five. Limiting the DSV and choosing the correct coupling capacitors maintains differential signal amplitude and reduces jitter due to droop on AC-coupled links. To obtain DC balance on the data channels, the serializer parallel data is inverted or not inverted, depending on the sign of the digital sum at the word boundary. Two complementary bits are appended to each group of 7 parallel input data bits to indicate to the MAX9234/ MAX9236/MAX9238 deserializers whether the data bits are inverted (see Figure 9). The deserializer restores the original state of the parallel data. The LVDS clock signal alternates duty cycles of 4/9 and 5/9, which maintain DC balance. AC-Coupling Benefits Bit errors experienced with DC-coupling can be eliminated by increasing the receiver common-mode voltage range by AC-coupling. AC-coupling increases the common-mode voltage range of an LVDS receiver to nearly the voltage rating of the capacitor. The typical LVDS driver output is 350mV centered on an offset voltage of 1.25V, making single-ended output voltages of 1.425V and 1.075V. An LVDS receiver accepts signals from 0 to 2.4V, allowing approximately ±1V common-mode difference between the driver and receiver on a DC-coupled OUTPUT STROBE link (2.4V - 1.425V = 0.975V and 1.075V - 0V = 1.075V). Common-mode voltage differences may be due to ground potential variation or common-mode noise. If there is more than ±1V of difference, the receiver is not guaranteed to read the input signal correctly and may cause bit errors. AC-coupling filters low-frequency ground shifts and common-mode noise and passes high-frequency data. A common-mode voltage difference up to the voltage rating of the coupling capacitor (minus half the differential swing) is tolerated. DC-balanced coding of the data is required to maintain the differential signal amplitude and limit jitter on an AC-coupled link. A capacitor in series with each output of the LVDS driver is sufficient for AC-coupling. However, two capacitors—one at the serializer output and one at the deserializer input—provide protection in case either end of the cable is shorted to a high voltage. RxIN_ + OR RxCLK IN+ RIN1 1.2V RIN1 RxIN_ - OR RxCLK IN- Figure 1. LVDS Input Circuit RCIP RxCLK OUT ODD RxOUT EVEN RxOUT RISING-EDGE STROBE SHOWN. Figure 2. Worst-Case Test Pattern _______________________________________________________________________________________ 7 MAX9234/MAX9236/MAX9238 Table 1. Part Equivalent Table MAX9234/MAX9236/MAX9238 Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers 90% RxOUT_ OR RxCLK OUT 90% 10% RxOUT_ OR RxCLK OUT 10% 8pF CLHT CHLT Figure 3. Output Load and Transition Times IDEAL SERIAL BIT TIME 1.3V RxCLK IN VID = 0 RCCD 1.5V 1.1V RSKM RxCLK OUT RSKM IDEAL MIN IDEAL Figure 6a. MAX9234 Clock-IN to Clock-OUT Delay MAX INTERNAL STROBE + RxCLK IN Figure 4. LVDS Receiver Input Skew Margin VID = 0 RCCD RCIP 1.5V RxCLK OUT RxCLK OUT 2.0V 0.8V 0.8V RCOL RCOH RSRC RHRC 2.0V 0.8V RxOUT_ 2.0V 2.0V Figure 6b. MAX9236/MAX9238 Clock-IN to Clock-OUT Delay 2.0V 0.8V 2V Figure 5a. MAX9234 Output Setup/Hold and High/Low Times PWRDWN 3V RCIP VCC RPLLS RxCLK OUT 2.0V 2.0V 0.8V 0.8V RCOH RSRC RxOUT_ 2.0V 0.8V 0.8V RHRC 2.0V 0.8V Figure 5b. MAX9236/MAX9238 Output Setup/Hold and High/Low Times 8 RxCLK IN RCOL RxCLK OUT HIGH-Z Figure 7. Phase-Locked Loop Set Time _______________________________________________________________________________________ Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers Selection of AC-Coupling Capacitors Voltage droop and the DSV of transmitted symbols cause signal transitions to start from different voltage levels. Because the transition time is finite, starting the signal transition from different voltage levels causes timing jitter. The time constant for an AC-coupled link needs to be chosen to reduce droop and jitter to an acceptable level. 0.8V RxCLK IN RPDD RxOUT_ RxCLK OUT HIGH-Z Figure 8. Power-Down Delay MAX9234/MAX9236/MAX9238 vs. MAX9210/MAX9220/MAX9222 The MAX9234/MAX9236/MAX9238 operate in DC-balance mode only. Pinouts are the same as the MAX9210/MAX9220/MAX9222 except that pin 6 on the MAX9234/MAX9236/MAX9238 is no connect (N.C.). DC balance allows AC-coupling with series capacitors. The MAX9234/MAX9236/MAX9238 are hot-swappable and the input frequency can be changed on the fly, but otherwise the specifications and functionality are the same as the MAX9210/MAX9220/MAX9222 operating in DCbalance mode. See Table 1. The RC network for an AC-coupled link consists of the LVDS receiver termination resistor (RT), the LVDS driver output resistor (RO), and the series AC-coupling capacitors (C). The RC time constant for two equal-value series capacitors is (C x (RT + RO)) / 2 (Figure 10). The RC time constant for four equal-value series capacitors is (C x (RT + RO)) / 4 (Figure 11). RT is required to match the transmission line impedance (usually 100Ω) and RO is determined by the LVDS driver design (the minimum differential output resistance of 78Ω for the MAX9209/MAX9211/MAX9213/ MAX9215 serializers is used in the following example). This leaves the capacitor selection to change the system time constant. + RxCLK IN CYCLE N - 1 DCA2 CYCLE N CYCLE N + 1 DCB2 TxIN20 TxIN19 TxIN18 TxIN17 TxIN16 TxIN15 TxIN14 DCA2 DCB2 TxIN20 TxIN19 TxIN18 TxIN17 TxIN16 TxIN15 TxIN14 DCB1 TxIN13 TxIN12 TxIN11 TxIN10 TxIN9 TxIN8 TxIN7 DCA1 DCB1 TxIN13 TxIN12 TxIN11 TxIN10 TxIN9 TxIN8 TxIN7 DCB0 TxIN6 TxIN5 TxIN4 TxIN3 TxIN2 TxIN1 TxIN0 DCA0 DCB0 TxIN6 TxIN5 TxIN4 TxIN3 TxIN2 TxIN1 TxIN0 RxIN2 DCA1 RxIN1 DCA0 RxIN0 TxIN_, DCA_, AND DCB_ ARE DATA FROM THE SERIALIZER. Figure 9. Deserializer Serial Input _______________________________________________________________________________________ 9 MAX9234/MAX9236/MAX9238 Applications Information PWRDWN MAX9234/MAX9236/MAX9238 Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers MAX9209 MAX9211 MAX9213 MAX9215 HIGH-FREQUENCY, CERAMIC SURFACE-MOUNT CAPACITORS CAN ALSO BE PLACED AT THE SERIALIZER INSTEAD OF THE DESERIALIZER. TxOUT MAX9234 MAX9236 MAX9238 RxIN 7 7 (7 + 2):1 100Ω 1:(9 - 2) (7 + 2):1 100Ω 1:(9 - 2) (7 + 2):1 100Ω 1:(9 - 2) PLL 100Ω PLL 7 7 TxIN RxOUT 7 7 PWRDWN PWRDWN RxCLK OUT TxCLK IN TxCLK OUT RxCLK IN 21:3 SERIALIZER 3:21 DESERIALIZER Figure 10. Two Capacitors per Link, AC-Coupled MAX9209 MAX9211 MAX9213 MAX9215 MAX9234 MAX9236 MAX9238 HIGH-FREQUENCY CERAMIC SURFACE-MOUNT CAPACITORS TxOUT RxIN 7 7 (7 + 2):1 100Ω 1:(9 - 2) (7 + 2):1 100Ω 1:(9 - 2) (7 + 2):1 100Ω 1:(9 - 2) PLL 100Ω PLL 7 7 TxIN RxOUT 7 7 PWRDWN PWRDWN RxCLK OUT TxCLK IN TxCLK OUT 21:3 SERIALIZER RxCLK IN 3:21 DESERIALIZER Figure 11. Four Capacitors per Link, AC-Coupled 10 ______________________________________________________________________________________ Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers C = 0.0773µF Jitter due to droop is proportional to the droop and transition time: tJ = tT x D (Eq 2) where: tJ = jitter (s). tT = transition time (s) (0 to 100%). D = droop (% of signal amplitude). Jitter due to 2% droop and assumed 1ns transition time is: tJ = 1ns x 0.02 tJ = 20ps The transition time in a real system depends on the frequency response of the cable driven by the serializer. The capacitor value decreases for a higher frequency parallel clock and for higher levels of droop and jitter. Use high-frequency, surface-mount ceramic capacitors. Equation 1 altered for four series capacitors (Figure 11) is: C = - (4 x tB x DSV) / (ln (1 - D) x (RT + RO)) (Eq 3) Input Bias and Frequency Detection The inverting and noninverting LVDS inputs are internally connected to +1.2V through 42kΩ (min) to provide biasing for AC-coupling (Figure 1). A frequency-detection circuit on the clock input detects when the input is not switching, or is switching at low frequency. In this case, all outputs are driven low. To prevent switching due to noise when the clock input is not driven, bias the clock input to differential +15mV by connecting a 10kΩ ±1% pullup resistor between the noninverting input and VCC, and a 10kΩ ±1% pulldown resistor between the inverting input and ground. These bias resistors, along with the 100Ω ±1% tolerance termination resistor, provide +15mV of differential input. Unused LVDS Data Inputs At each unused LVDS data input, pull the inverting input up to VCC using a 10kΩ resistor, and pull the noninverting input down to ground using a 10kΩ resistor. Do not connect a termination resistor. The pullup and pulldown resistors drive the corresponding outputs low and prevent switching due to noise. PWRDWN Driving PWRDWN low puts the outputs in high impedance, stops the PLL, and reduces supply current to 50µA or less. Driving PWRDWN high drives the outputs low until the PLL locks. The outputs of two deserializers can be bused to form a 2:1 mux with the outputs controlled by PWRDWN. Wait 100ns between disabling one deserializer (driving PWRDWN low) and enabling the second one (driving PWRDWN high) to avoid contention of the bused outputs. Input Clock and PLL Lock Time There is no required timing sequence for the application or reapplication of the parallel rate clock (RxCLK IN) relative to PWRDWN, or to a power-supply ramp for proper PLL lock. The PLL lock time is set by an internal counter. The maximum time to lock is 32,800 clock periods. Power and clock should be stable to meet the lock-time specification. When the PLL is locking, the outputs are low. Power-Supply Bypassing There are separate on-chip power domains for digital circuits, outputs, PLL, and LVDS inputs. Bypass each VCC, VCCO, PLL VCC, and LVDS VCC pin with high-frequency, surface-mount ceramic 0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin. Cables and Connectors Interconnect for LVDS typically has a differential impedance of 100Ω. Use cables and connectors that have matched differential impedance to minimize impedance discontinuities. Twisted-pair and shielded twisted-pair cables offer superior signal quality compared to ribbon cable and tend to generate less EMI due to magnetic field canceling effects. Balanced cables pick up noise as common mode, which is rejected by the LVDS receiver. ______________________________________________________________________________________ 11 MAX9234/MAX9236/MAX9238 In the following example, the capacitor value for a droop of 2% is calculated. Jitter due to this droop is then calculated assuming a 1ns transition time: C = - (2 x tB x DSV) / (ln (1 - D) x (RT + RO)) (Eq 1) where: C = AC-coupling capacitor (F). tB = bit time (s). DSV = digital sum variation (integer). ln = natural log. D = droop (% of signal amplitude). RT = termination resistor (Ω). RO = output resistance (Ω). Equation 1 is for two series capacitors (Figure 10). The bit time (tB) is the period of the parallel clock divided by 9. The DSV is 10. See equation 3 for four series capacitors (Figure 11). The capacitor for 2% maximum droop at 8MHz parallel rate clock is: C = - (2 x tB x DSV) / (ln (1 - D) x (RT + RO)) C = - (2 x 13.9ns x 10) / (ln (1 - 0.02) x (100Ω + 78Ω)) MAX9234/MAX9236/MAX9238 Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers Board Layout Keep the LVTTL/LVCMOS outputs and LVDS input signals separated to prevent crosstalk. A four-layer PC board with separate layers for power, ground, LVDS inputs, and digital signals is recommended. ESD Protection The MAX9234/MAX9236/MAX9238 ESD tolerance is rated for IEC 61000-4-2 Human Body Model and ISO 10605 standards. IEC 61000-4-2 and ISO 10605 specifiy ESD tolerance for electronic systems. The Human Body Model discharge components are CS = 100pF and RD = 1.5kΩ (Figure 12). For the Human Body Model, all pins are rated for ±5kV contact discharge. The ISO 10605 discharge components are CS = 330pF and RD = 2kΩ (Figure 13). For ISO 10605, the LVDS outputs are rated for ±8kV contact and ±25kV air discharge. The IEC 61000-4-2 discharge components are CS = 150pF and RD = 330Ω (Figure 14). For IEC 61000-4-2, the LVDS inputs are rated for ±8kV Contact Discharge and ±15kV Air-Gap Discharge. 5V Tolerant Input PWRDWN is 5V tolerant and is internally pulled down to GND. R1 1MΩ CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE CS 100pF R2 1.5kΩ DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST Figure 12. Human Body ESD Test Circuit R1 50Ω TO 100Ω CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE CS 330pF R2 2kΩ DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST Skew Margin (RSKM) Skew margin (RSKM) is the time allowed for degradation of the serial data sampling setup and hold times by sources other than the deserializer. The deserializer sampling uncertainty is accounted for and does not need to be subtracted from RSKM. The main outside contributors of jitter and skew that subtract from RSKM are interconnect intersymbol interference, serializer pulse position uncertainty, and pair-to-pair path skew. VCCO Output Supply and Power Dissipation The outputs have a separate supply (VCCO) for interfacing to systems with 1.8V to 5V nominal input-logic levels. The DC Electrical Characteristics table gives the maximum supply current for VCCO = 3.6V with 8pF load at several switching frequencies with all outputs switching in the worst-case switching pattern. The approximate incremental supply current for VCCO other than 3.6V with the same 8pF load and worst-case pattern can be calculated using: II = CTVI 0.5fC x 21 (data outputs) + CTVIfC x 1 (clock output) where: II = incremental supply current. CT = total internal (CINT) and external (CL) load capacitance. VI = incremental supply voltage. fC = output clock-switching frequency. 12 Figure 13. ISO 10605 Contact Discharge ESD Test Circuit 50Ω TO 100Ω CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE CS 150pF RD 330Ω DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST Figure 14. IEC 61000-4-2 Contact Discharge ESD Test Circuit The incremental current is added to (for VCCO > 3.6V) or subtracted from (for VCCO < 3.6V) the DC Electrical Characteristics table maximum supply current. The internal output buffer capacitance is CINT = 6pF. The worst-case pattern-switching frequency of the data outputs is half the switching frequency of the output clock. In the following example, the incremental supply current is calculated for VCCO = 5.5V, fC = 34MHz, and CL = 8pF: VI = 5.5V - 3.6V = 1.9V CT = CINT + CL = 6pF + 8pF = 14pF ______________________________________________________________________________________ Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers II = (14pF x 1.9V x 0.5 x 34MHz x 21) + (14pF x 1.9V x 34MHz). II = 9.5mA + 0.9mA = 10.4mA. The maximum supply current in DC-balanced mode for VCC = VCCO = 3.6V at fC = 34MHz is 106mA (from the DC Electrical Characteristics table). Add 10.4mA to get the total approximate maximum supply current at VCCO = 5.5V and VCC = 3.6V. If the output supply voltage is less than VCCO = 3.6V, the reduced supply current can be calculated using the same formula and method. At high switching frequency, high supply voltage, and high capacitive loading, power dissipation can exceed the package power-dissipation rating. Do not exceed the maximum package power-dissipation rating. See the Absolute Maximum Ratings for maximum package power-dissipation capacity and temperature derating. Functional Diagram DATA CHANNEL 0 LVDS DATA RECEIVER 0 RxIN0+ STROBE RxIN0- RxIN1+ STROBE RxIN2+ STROBE SERIAL-TOPARALLEL CONVERTER LVDS CLOCK RECEIVER RxCLK IN+ RxCLK IN- PWRDWN RxOUT7–13 DATA CHANNEL 2 LVDS DATA RECEIVER 2 RxIN2- SERIAL-TOPARALLEL CONVERTER RxOUT14–20 RxCLK OUT 9x PLL REFERENCE CLOCK GENERATOR Pin Configuration TOP VIEW RxOUT17 1 48 VCCO RxOUT18 2 47 RxOUT16 GND 3 46 RxOUT15 RxOUT19 4 45 RxOUT14 RxOUT20 5 44 GND N.C. 6 43 RxOUT13 LVDS GND 7 42 VCC RxIN0- 8 41 RxOUT12 RxIN0+ 9 40 RxOUT11 RxIN1- 10 RxIN1+ 11 DATA CHANNEL 1 LVDS DATA RECEIVER 1 RxIN1- SERIAL-TOPARALLEL CONVERTER RxOUT0–6 Rising- or Falling-Edge Output Strobe The MAX9234 has a rising-edge output strobe, which latches the parallel output data into the next chip on the rising edge of RxCLK OUT. The MAX9236/MAX9238 have a falling-edge output strobe, which latches the parallel output data into the next chip on the falling edge of RxCLK OUT. The deserializer output strobe polarity does not need to match the serializer input strobe polarity. A deserializer with rising- or fallingedge output strobe can be driven by a serializer with a rising-edge input strobe. MAX9234 MAX9236 MAX9238 39 RxOUT10 38 GND RxOUT9 LVDS VCC 12 37 LVDS GND 13 36 VCCO RxIN2- 14 35 RxOUT8 RxIN2+ 15 34 RxOUT7 RxCLK IN- 16 33 RxOUT6 RxCLK IN+ 17 32 GND LVDS GND 18 31 RxOUT5 19 30 RxOUT4 PLL VCC 20 29 RxOUT3 PLL GND 21 28 VCCO PWRDWN 22 27 RxOUT2 23 26 RxOUT1 RxOUT0 24 25 GND PLL GND RxCLK OUT TSSOP Chip Information MAX9234 TRANSISTOR COUNT: 14,104 MAX9236 TRANSISTOR COUNT: 14,104 MAX9238 TRANSISTOR COUNT: 14,104 PROCESS: CMOS ______________________________________________________________________________________ 13 MAX9234/MAX9236/MAX9238 where: II = CTVI 0.5FC x 21 (data outputs) + CTVIfC x 1 (clock output). Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 48L TSSOP.EPS MAX9234/MAX9236/MAX9238 Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers N MARKING AAA A E H 1 2 3 TOP VIEW BOTTOM VIEW SEE DETAIL A b A1 A2 A CL e D c END VIEW SEATING PLANE SIDE VIEW ( b ) PARTING LINE 0.25 L b1 WITH PLATING DETAIL A NOTES: 1. DIMENSIONS D & E ARE REFERENCE DATUMS AND DO NOT INCLUDE MOLD FLASH. 2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED 0.15MM ON D SIDE, AND 0.25MM ON E SIDE. 3. CONTROLLING DIMENSION: MILLIMETERS. 4. THIS PART IS COMPLIANT WITH JEDEC SPECIFICATION MO-153, VARIATIONS, ED (48L), EE (56L). 5. "N" REFERS TO NUMBER OF LEADS. 6. THE LEAD TIPS MUST LIE WITHIN A SPECIFIED ZONE. THIS TOLERANCE ZONE IS DEFINED BY TWO PARALLEL PLANES. ONE PLANE IS THE SEATING PLANE, DATUM (-C-), THE OTHER PLANE IS AT THE SPECIFIED DISTANCE FROM (-C-) IN THE DIRECTION INDICATED. 7. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY. 8. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY. c1 BASE METAL SECTION C-C PACKAGE OUTLINE, 48 & 56L TSSOP, 6.1mm BODY 21-0155 14 c ______________________________________________________________________________________ C 1 1 Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers REVISION NUMBER REVISION DATE 0 4/05 Initial release 1 10/07 Added IEC 61000-4-2 ESD Performance; various style changes DESCRIPTION PAGES CHANGED — 1, 2, 4, 5, 6, 12 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15 © 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc. MAX9234/MAX9236/MAX9238 Revision History