March 1997 ML4668 Low Power Single Chip 10BASE-FL Transceiver GENERAL DESCRIPTION FEATURES The ML4668 single-chip 10BASE-FL transceiver is a low power, high output current, plug-compatible version of the industry standard ML4663. The ML4668 offers a standard IEEE 802.3 AU interface that allows it to be directly connected to industry standard manchester encoder/ decoder chips or an AUI connector. ■ The ML4668 provides a highly integrated solution that requires a minimal number of external components, and is compliant to the IEEE 802.3 10BASE-FL standard. The transmitter offers a 100mA maximum current drive output that directly drives a fiber optic LED transmitter. The receiver offers a highly stable fiber optic data quantizer capable of accepting input signals as low as 2mVP-P with a 55dB dynamic range. ■ ■ ■ ■ ■ ■ ■ Single chip solution for 10BASE-FL internal or external Medium Attachment Units (MAUs) Incorporates an AU interface Highly stable data quantizer with 55dB input dynamic range Input sensitivity as low as 2mVP-P Up to 100mA maximum current driven fiber optic LED driver for accurate launch power Single +5 volt supply No crystal or clock required Five network status LED outputs The transmitter automatically inserts 1MHz signal during idle time and removes this signal on reception. Low Light is continuously monitored for both activity as well as power level. Five LED status indicators monitor error conditions as well as transmissions, receptions and collisions. BLOCK DIAGRAM +5V VCCTx (+5V) SQEN/JABD 5 Tx+ 10 12 20 27 FIBER OPTIC LED DRIVER AUI RECEIVER Tx– 11 AVCC GND RTSET 17 18 TxOUT 15 XMT Tx SQUELCH 1MHz IDLE SIGNAL JABBER LED DRIVERS 16 RCV 1 CLSN 28 JAB 14 LMON SQE BIAS RECEIVE SQUELCH COL+ 2 AUI DRIVER COL– 3 10MHz GATED OSCILLATOR 26 V + IN AMP 25 VIN– Tx Rx+ 6 LOOPBACK MUX AUI DRIVER Rx– 7 Rx CMP 21 VDC ∫ VREF LINK DETECT 19 GND 9 VCC (+5V) 13 8 RRSET LBDIS 24 AGND 22 VREF 23 VTHADJ 4 CTIMER +5V 1 ML4668 PIN CONNECTION 2 VIN+ AVCC JAB 28 6 24 AGND Rx– 7 23 VTHADJ LBDIS 8 22 VREF VCC 9 21 VDC Tx+ 10 20 GND Tx– 11 12 13 14 15 16 19 17 18 GND TxOUT Rx+ VCCTx 27 26 25 RCV CLSN 1 XMT COL+ 2 LMON COL– 3 5 RTSET 4 SQEN/JABD RRSET CTIMER ML4668 28-Pin PLCC (Q28) VIN– ML4668 PIN DESCRIPTION PIN NAME FUNCTION PIN NAME FUNCTION 1 CLSN Indicates that a collision is taking place. Active low LED driver, open collector. Event is extended with internal timer for visibility. 15 XMT Indicates that transmission is taking place. Active low LED driver, open collector. Event is extended with internal timer for visibility. 2 3 COL+ COL– Gated 10MHz oscillation used to indicate a collision, SQE test, or jabber. Balanced differential line driver outputs that meet AUI specifications. 16 RCV Indicates that the transceiver is receiving a frame from the optical input. Active low LED driver, open collector. Event is extended with internal timer for visibility. 4 CTIMER A capacitor from this pin to VCC determines the Link Monitor response time. 17 VCC Tx +5 volt supply for fiber optic LED driver. 18 TxOUT Fiber optic LED driver output. 19 GND Ground Reference. 20 GND Ground Reference. 21 VDC An external capacitor on this pin integrates an error signal which nulls the offset of the input amplifier. If the DC feedback loop is not being used, this pin should be connected to VREF. 22 V REF A 2.5V reference with respect to GND. 23 VTHADJ This input pin sets the link monitor threshold. 24 AGND Analog Filtered Ground. 25 VIN– This input pin should be capacitively coupled to the input source or to filtered AVCC. (The input resistance is approximately 1.3kΩ.) 26 VIN+ This input pin should be capacitively coupled to the input source or to filtered AVCC. (The input resistance is approximately 1.3kΩ.) 27 AVCC Analog Filtered +5 volts. 28 JAB 5 SQEN/JABD SQE Test Enable, Jabber Disable. When tied low, SQE test is disabled, when tied high SQE test is enabled. When tied to 2.0V both SQE test and Jabber are disabled. 6 7 Rx+ Rx– 8 LBDIS Manchester encoded receive data output to the local device. Balanced differential line driver outputs that meet AUI specifications. Loopback Disable. When this pin is tied to VCC , the AUI transmit pair data is not looped back to the AUI receive pair, and collision is disabled. When this pin is tied to GND (normal operation) or left floating, the AUI transmit pair data is looped back to the AUI receiver pair, except during collision. 9 VCC +5 volt power input. 10 11 Tx+ Tx– Balanced differential line receiver inputs that meet AUI specifications. These inputs may be transformer or capacitively coupled. The Tx input pins are internally DC biased for AC coupling. 12 RTSET Sets the current driven output of the transmitter. 13 RRSET A 1% 61.9kΩ resistor tied from this pin to VCC sets the biasing currents for internal nodes. 14 LMON Link Monitor “Low Light” LED status output. This pin is pulled low when the voltage on the VIN+, VIN– inputs exceed the minimum threshold set by the VTHADJ pin, and there are transitions on VIN+, VIN– indicating an idle signal or active data. If either the voltage on the VIN+, VIN– inputs fall below the minimum threshold or transitions cease on VIN+, VIN–, LMON will go high. Active low LED driver, open collector. Jabber network status LED. When in the Jabber state, this pin will be low and the transmitter will be disabled. In the Jabber “OK” state this pin will be high. Active low LED, open collector. 3 ML4668 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Power Supply Voltage Range VCC ..................................................... GND –0.3 to 6V Input Voltage Range Digital Inputs (SQEN, LBDIS) ... GND –0.3 to VCC +0.3V Tx+, Tx–, VIN+, VIN– ............... GND –0.3 to VCC +0.3V Input Current RRSET, RTSET, JAB, CLSN, XMT, RCV, LMON ...... 60mA Output Current TxOUT .............................................................. 120mA Junction Temperature .............................................. 150°C Storage Temperature Range ...................... –65°C to 150°C Lead Temperature (Soldering) .................................. 260°C Thermal Resistance (θJA) ....................................... 68°C/W OPERATING CONDITIONS Supply Voltage (VCC) ........................................... 5V ± 5% LED on Current ....................................................... 10mA RRSET .......................................................... 61.9kΩ ± 1% RTSET ............................................................. 115Ω ± 1% ELECTRICAL CHARACTERISTICS Unless otherwise specified, TA = Operating Temperature Range, VCC = VCCTx = 5V ± 5% (Note 1) SYMBOL ICC CONDITIONS MIN TYP MAX UNITS Power Supply Current ICC: While Transmitting VCC = 5V, RTSET = 115Ω (Note 2) 140 mA VOL LED Drivers: VOL IOL = 10mA (Note 3) 0.8 V IOUT Transmit Peak Output Current RTSET = 115Ω (Note 4) VSQ 44 52 57 mA Transmit Squelch Voltage Level (Tx+, Tx–) –300 –250 –200 mV VDO Differential Output Voltage (Rx±, COL±) ±550 ±1200 mV VCM Common Mode Output Voltage (Rx±, COL±) VDOO VSQE VLBTH 4 PARAMETER 4.0 Differential Output Voltage Imbalance (Rx±, COL±) SQE/JABD LBDIS Threshold SQE Test Disable Both Disabled Both Enabled Disabled Enabled 1.5 VCC – 0.5 V ±40 mV 0.3 VCC – 2 V V V VCC – 0.1 1 V V VTXCM Common Mode Voltage (Tx+, Tx–) 3.5 V VINCM Common Mode Voltage (VIN+, VIN–) 1.65 V VREF Reference Voltage IREF VREF Output Source Current AV Amplifier Gain VISR Input Signal Range VTHADJ External Voltage at VTHADJ to Set VTH VOFF Input Offset VDC = VREF (DC loop inactive) 3 mV VN Input Referred Noise 50MHz BW 25 µV RIN Input Resistance VIN+, VIN– ITH Input Bias Current of VTHADJ VTH Input Threshold Voltage H Hysteresis 2.30 2.45 2.60 V 5 mA 100 VTHADJ = VREF (Note 5) V/V 2 1600 mVP–P 0.5 2.7 V 0.8 1.3 2.0 kΩ –200 10 +200 µA 5 6 7 mVP–P 20 % ML4668 AC ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER MIN TYP MAX UNITS Transmit FTXIDF Transmit Idle Frequency 0.85 1.25 MHz PTXDC Transmit Idle duty Cycle 45 55 % tTXNPW Transmit Turn-On Pulse Width tTXODY Transmit Turn-On Delay 200 ns tTXLP Transmit loopback Start-up Delay 500 ns tTXFPW Transmit Turn-Off Pulse Width tTXSOI Transmit Turn-Off Start of Idle tTXSDY Transmit Steady State Propagation Delay tTXJ Transmit Jitter into 31Ω Load 20 ns 180 400 15 ns 2100 ns 50 ns ±1.5 ns 4.5 MHz 285 ns Receive FRXSFT Receive Squelch Frequency Threshold 2.51 tRXODY Receive Turn-On Delay tRXFX Last Bit Received to Slow Decay Output tRXSDY Receive Steady State Propagation Delay tRXJ Receive Jitter tAR Differential Output Rise Time 20% to 80% (Rx±, COL±) 4 ns tAF Differential Output Fall Time 20% to 80% (Rx±, COL±) 4 ns 230 300 15 ns 50 ns ±1.5 ns Collision tCPSQE Collision Present to SQE Assert 0 350 ns tSQEXR Time for SQE to Deactivate After Collision 0 700 ns FCLF Collision Frequency 8.5 11.5 MHz PCLPDC Collision Pulse Duty Cycle 40 60 % tSQEDY SQE Test Delay (Tx Inactive to SQE) 0.6 1.6 µs tSQETD SQE Test Duration 0.5 1.0 1.5 µs 50 Jabber and LED Timing tJAD Jabber Activation Delay 20 70 150 ms tJRT Jabber Reset Unjab Time 250 450 750 ms tJSQE Delay from Outputs Disabled to Collision Oscillator On tLED RCV, CLSN, XMT On Time 8 16 32 ms tLLPH Low Light Present to LMON High 3 5 10 µs tLLCL Low Light Present to LMON Low 250 750 ms Note 1: Note 2: Note 3: Note 4: Note 5: 100 ns Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. This dose not include the current from the AUI pull-down resistors, or LED status outputs. LED drivers can sink up to 20mA, but VOL will be higher. Does not include pre-bias current for fiber optic LED which would typically be 3mA. Threshold for switching from Link Fail to Link Pass (Low Light). 5 6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 AULRX– AULRX+ AULPWR+ AULPWR– AULCP– AULCP+ AULTX– AULTX+ CHASSIS REF Figure 1. ML4668 Schematic Diagram +5V 33µ + +5V 3KΩ 8 COL– 0.1 0.1µ IN D1 RP1 510Ω VCC 9 Q1 OUT LM340 GND VR1 5 SQE 360Ω 6 Rx+ 7 Rx– 360Ω 39Ω 10 Tx+ 11 Tx– 39Ω 0.1µF 5KΩ 9 10 7 13 12 D1 360Ω 3 360Ω 15 2 COL+ 16 5 D0 4 2 CI 1 + 4.7µ 19, 20 + ML4668 ALL 510Ω RP1 15 16 1 28 14 XMT RCV CLSN JAB LMON 0.1µ 4.7µH 0.1 0.05 4.7 + 0.1 +VRF –VRF 4.7µH 27 23 22 25 26 21 4 8 17 24 VTHADJ VREF VIN– VIN+ VDC CTIMER LBDIS TxVCC TxOUT 18 115Ω 13 12 RRSET RTSET 61.9k –VRF +VRF +5V 0.01 –VRF +VRF –VRF 0.01 1k R17 10Ω 6 +VRF FIBER OPTIC TRANSMITTER HP HFBR1414 OR OPTEK OPC1414 4 –VRF 7 3 –VRF FIBER OPTIC CABLE FIBER OPTIC CABLE 0.1µF 0.1µF FIBER OPTIC RCVR HP HFBR2416 OR 5 OPTEK OPC2416 8 1 2 3 2,6,7 +5V ML4668 ML4668 SYSTEM DESCRIPTION Figure 1 shows a schematic diagram of the ML4668 in an internal or external 10BASE-FL MAU. On one side of the transceiver is the AU interface and the other is the fiber optic interface. The AU interface is AC coupled when used in an external transceiver or an internal transceiver. The AU interface for an external transceiver includes isolation transformers, some biasing resistors, and a voltage regulator for power. The fiber optic side of the transceiver requires an external fiber optic transmitter and fiber optic receiver. The transmitter uses a current driven output that directly drives the fiber optic transmitter. The receive side of the transceiver accepts the data after passing through a fiber optic receiver, which consists of a module containing a pin diode and a transimpedance amplifier. AU INTERFACE The AU interface consists of 3 pairs of signals: DO, CI and DI (Figure 1). The DO pair contains transmit data from the DTE which is received by the transceiver and sent out onto the fiber optic cable. The DI pair contains valid data that has been either received from the fiber optic cable or looped back from the DO, and output through the DI pair to the DTE. The CI pair indicates whether a collision has occurred. It is an output that oscillates at 10MHz if a collision, Jabber or SQE Test has taken place, otherwise it remains idle. When the transceiver is external, these three pairs are AC coupled through isolation transformers, while an internal transceiver may be capacitively coupled. Tx+, Tx– is internally DC biased (shifted up in voltage) for the proper common mode input voltage. The two 39Ω 1% resistors (or one 78Ω 1% resistor) tied to the Tx+ and Tx– pins will provide the proper termination. The CI and DI pair, which are output from the transceiver to the AUI cable, require 360Ω pull down resistors when terminated with a 78Ω load. However, on a DTE card, CI and DI do not need 78Ω terminating resistors. This also means that the pull down resistors on CI and DI can be 1kΩ or greater depending upon the particular Manchester encoder/decoder chip used. Using higher value pull down resistors as in a DTE card will save power. Refer to Application Note 13 for a more detailed explanation of the AUI pull-down resistors. The AUI drivers are capable of driving the full 50 meters of cable length and have a rise and fall time of typically 4ns. In the idle state, the outputs go to the same voltage to prevent DC standing current in the isolation transformers. Before data will be transmitted onto the fiber optic cable from the AUI interface, it must exceed the squelch requirements for the DO pair. The Tx squelch circuit serves the function of preventing any noise from being transmitted onto the fiber. This circuit rejects signals with pulse widths less than typically 20ns (negative going), or with levels less than –250mV. Once Tx squelch circuit has unsquelched, it looks for the start of idle signal to turn on the squelch circuit again. The transmitter turns on the squelch again when it receives an input signal at Tx+, Tx– that is more positive than –250mV for more than approximately 180ns. At the start of a packet transmission, no more than 2 bits are received from the DO circuit, and are not transmitted onto the fiber optic cable. The difference between start-up delays (bit loss plus steady-state propagation delay) for any two packets that are separated by 9.6µs or less will not exceed 200ns. FIBER OPTIC LED DRIVER The output stage of the transmitter is a current mode switch which develops the output light by sinking current through the LED into the TxOUT pin. Once the current requirement for the LED is determined, the RTSET resistor is selected. The following equation is used to select the correct RTSET resistor: RTSET= 52mA 115Ω IOUT The ML4668 transmitter output will drive up to 100mA, which requires RTSET to equal 60Ω. The transmitter enters the idle state when it detects start of idle on Tx+ and Tx– input pins. After detection, transmitter switches to a 1MHz output idle signal. The output current is switched through the TxOUT pin during the on cycle and the VCC Tx pin during the off cycle as shown in figure 2. Since the sum of the current in these two pins is constant, VCC Tx should be connected as close as possible to the VCC connection for the LED. If not driving an optical LED directly, a differential output can be generated by tying resistors from VCCTx and TxOUT to VCC as shown in figure 3. The minimum voltage on these two pins should not be less than VCC – 2V. VCCTx TxOUT TRANSMISSION The transmit function consists of detecting the presence of data from the AUI DO input (Tx+, Tx–) and driving that data onto the fiber optic LED transmitter. A positive signal on the Tx+ lead relative to the Tx– lead of the DO circuit will result in no current, hence the fiber optic LED is in a low light condition. When Tx+ is more negative than Tx–, the ML4668 will sink current into the chip and the fiber optic LED will light up. IOUT Figure 2. Fiber Optic LED Driver Structure. 7 ML4668 SQE TEST FUNCTION (SIGNAL QUALITY ERROR) VCC 51Ω 51Ω 51Ω RTSET = 560Ω IOUT = 15.9mA ECL VCCTx TxOUT Figure 3. Converting Optical LED Driver Output to Differential ECL. RECEPTION The input to the transceiver comes from a fiber optic receiver (Figure 1). At the start of packet reception no more than 2.7 bits are received from the fiber cable, and are not transmitted onto the DI circuit. The receive squelch will reject frequencies lower than 2.51MHz. While in the unsquelch state, the receive squelch circuit looks for the start of idle signal at the end of the packet. Start of idle occurs when the input signal remains idle for more than 160ns. When start of idle is detected, the receive squelch circuit returns to the squelch state and the start of idle signal is output on the DI circuit (Rx+, Rx–). COLLISION Whenever the receiver and the transmitter are active at the same time the chip will activate the collision output, except when loopback is disabled (LBDIS = VCC ). The collision output is a differential square wave matching the AUI specifications and capable of driving a 78Ω load. The frequency of the square wave is 10MHz ± 15% with a 60/ 40 to 40/60 duty cycle. The collision oscillator also is activated during SQE Test and Jabber. LOOPBACK The loopback function emulates a 10BASE-T transceiver whereby the transmit data sent by the DTE is looped back over the AUI receive pair. Some LAN controllers use this loopback information to determine whether a MAU is connected by monitoring the carrier sense while transmitting. The software can use this loopback information to determine whether a MAU is connected to the DTE by checking the status of carrier sense after each packet transmission. When data is received by the chip while transmitting, a collision condition exits. This will cause the collision oscillator to turn on and the data on the DI pair will follow VIN+, VIN–. After a collision is detected, the collision oscillator will remain on until either DO or VIN+, VIN– go idle. Loopback can be disabled by strapping LBDIS to VCC. In this mode the chip operates as a full duplex transmitter and receiver, and collision detection is disabled. A loopback through the transceiver can be accomplished by tying the fiber transmitter to the receiver. 8 The SQE test function allows the DTE to determine whether the collision detect circuitry is functional. After each transmission, during the inter packet gap time, the collision oscillator will be activated for typically 1µs. The SQE test will not be activated if the chip is in the low light state, or the jabber on state. For SQE to operate, the SQEN pin must be tied to VCC. This allows the MAU to be interfaced to a DTE. The SQE test can be disabled by tying the SQEN pin to ground, for a repeater interface. JABBER FUNCTION REQUIREMENTS The Jabber function prevents a babbling transmitter from bringing down the network. Within the transceiver is a Jabber timer that starts at the beginning of each transmission and resets at the end of each transmission. If the transmission last longer than 20ms the Jabber logic disables the transmitter and turns on the collision signal COL+, COL–. When Tx+ and Tx– finally go idle, a second timer measures 0.5 seconds of idle time before the transmitter is enabled and collision is turned off. Even though the transmitter is disabled during Jabber, the 1MHz idle signal is still transmitted. LED DRIVERS The ML4668 has five LED drivers. The LED driver pins are active low, and the LEDs are normally off (except for LMON). The LEDs are tied to their respective pins through a 500Ω resistor to 5V. The XMT, RCV and CLSN pins have pulse stretchers on them which enables the LEDs to be visible. When transmission or reception occurs, the LED XMT, RCV or CLSN status pins will activate low for several milliseconds. If another transmit, receive or collision conditions occurs before the timer expires, the LED timer will reset and restart the timing. Therefore rapid events will leave the LEDs continuously on. The JAB and LMON LEDs do not have pulse stretchers on them since their conditions occur long enough for the eye to see. LOW LIGHT CONDITION The LMON LED output is used to indicate a low light condition. LMON is activated low when both the receive power exceeds the Link Monitor threshold and there are transitions on VIN+, VIN– less than 3µs apart. If either one of these conditions do not exist, LMON will go high. INPUT AMPLIFIER The VIN+, VIN– input signal is fed into a limiting amplifier with a gain of about 100 and input resistance of 1.3kΩ. Maximum sensitivity is achieved through the use of a DC restoration feedback loop and AC coupling the input. When AC coupled, the input DC bias voltage is set by an on-chip network at about 1.7V. These coupling capacitors, in conjunction with the input impedance of the amplifier, establish a high pass filter with 3dB corner frequency, fL, at 1 fL = (1) 2π1300C ML4668 Since the amplifier has a differential input, two capacitors of equal value are required. If the signal driving the input is single ended, one of the coupling capacitors can be tied to AVCC (Figure 1). The internal amplifier has a lowpass filter built-in to band limit the input signal which in turn will improve the signal to noise ratio. Although the input is AC coupled, the offset voltage within the amplifier will be present at the amplifier’s output. This is represented by VOS in Figure 4. In order to reduce this error, a DC feedback loop is incorporated. This negative feedback loop nulls the offset voltage, forcing VOS to be zero. Although the capacitor on VDC is non-critical, the pole it creates can effect the stability of the feedback loop. To avoid stability problems, the value of this capacitor should be at least 10 times larger than the input coupling capacitors. VOUT+ VOS VOUT– Figure 4. The comparator is a high-speed, differential zero crossing detector that slices and accurately digitizes the receive signal. The output of the comparator is fed in parallel into both the receive squelch circuit and the loopback MUX. LINK DETECT CIRCUIT AND LOW LIGHT The link detect circuit monitors the input signal and determines when the input falls below a preset voltage level. When the input falls below a preset voltage, the ML4668 goes into the Low Light state. In the Low Light state the transmitter is disabled, but continues sending the 1MHz idle signal, the loopback is disabled, the receiver is disabled, and the LMON LED pin goes to high shutting off the LMON LED. To return to the Link Pass state, the optical receiver power must be 20% higher than the shutoff state. This built-in hysteresis adds stability to the Link Monitor circuit. Once the receiver power threshold is exceeded, the ML4668 waits 250ms to 750ms, then checks to see that Tx+. Tx– is idle and no data is being received before re-enabling the transmitter, receiver, loopback circuit, and lighting up the LMON LED. The threshold generator shifts the reference voltage at VTHADJ through a circuit which has a temperature coefficient matching that of the limiting amplifier. The relationship between the VTHADJ and the VTH (the peak to peak input threshold) is: VTHADJ = 408VTH (2) In a 10BASE-FL receiver there must be less than 1 x 10–10 bit errors at a receive power level of –32.5dBm average. One procedure to determine the sensitivity of a receiver is to start at the lowest optical power level and gradually increase the optical power until the BER is met. In this case the Link Detect circuit must not disable the receiver (i.e. VTHADJ should be tied to Ground). Once the sensitivity of the receiver is determined, VTHADJ can be set just above the power level that meets the BER specification. This way the receiver will shut-off before the BER is exceeded. For 10BASE-FL VTHADJ can be tied directly to VREF. However if greater sensitivity is required the circuit in figure 5 can be used to adjust the VTHADJ voltage. Even if VREF is tied to VTHADJ, it is a good idea to layout a board with these two resistors available. This will allow potential future adjustments without board revisions. The response time of the Link Detect circuit is set by the CTIMER pin. Starting from the link off state the link can be switched on if the input exceeds the set threshold for a time given by: T= CTIMER × 0.7V 700µA (3) To switch the link from on to off, the above time will be doubled. A value of 0.05µF will meet to 10BASE-FL specifications. VREF R1 R2 VTHADJ REF THRESH GEN Figure 5. The VTHADJ pin is used to adjust the sensitivity of the receiver. The ML4668 is capable of exceeding the 10BASE-FL specifications for sensitivity. The sensitivity is dependent on the layout of the PC board. A good low noise layout will exceed the 10BASE-FL specifications, while a poor layout will fail to meet the sensitivity and BER spec. 9 ML4668 TIMING DIAGRAMS tTXNPW Tx+ VALID DATA Tx– tTXODY tTXSDY tTXSOI TxOUT IDLE VALID DATA IDLE tTXLP Rx+ VALID DATA Rx– Figure 6. Transmit and Loopback Timing VIN+ VIN– VALID tROXDY DATA tRXSDY tAR tRXFX tAF Rx+ VALID DATA Rx– Figure 7. Receive Timing Tx+ VALID Tx– DATA VIN+ VALID VIN– DATA tCPSQE COL+ CS0 COL– Rx+ Tx Tx Rx Rx Rx Rx– Figure 8. Collision Timing 10 1 FTXIDF tTXFPW ML4668 TIMING DIAGRAMS VIN+ VALID DATA VALID DATA VIN– Tx+ Tx– tCPSQE COL+ CS0 COL– Figure 9. Collision Timing VIN+ VIN– Tx+ VALID Tx– DATA tSQEXR COL+ CS0 COL– Rx+ Rx Rx– Rx Rx Tx Tx Tx Figure 10. Collision Timing Tx+ Tx– VIN+ VALID VIN– DATA tSQEXR COL+ CS0 COL– Rx+ Rx– RxIN RxIN RxIN RxIN RxIN Figure 11. Collision Timing 11 ML4668 TIMING DIAGRAMS 1 FCLF COL+ COL– Figure 12. Collision Timing TxOUT VALID DATA tSQEDY tSQETD COL+ CS0 COL– Figure 13. SQE Timing Tx+ VALID DATA Tx – tJAD TxOUT tJRT VALID DATA tJSQE COL+ CS0 COL– Figure 14. Jabber Timing 12 ML4668 Tx+ Tx– tLED XMT Figure 15. LED Timing VIN+ VIN– tLED RCV Figure 16. LED Timing VIN+ VIN– LMON tLLPH tLLCL Figure 17. LED Timing 13 ML4668 PHYSICAL DIMENSIONS inches (millimeters) Package: Q28 28-Pin PLCC 0.485 - 0.495 (12.32 - 12.57) 0.042 - 0.056 (1.07 - 1.42) 0.450 - 0.456 (11.43 - 11.58) 0.025 - 0.045 (0.63 - 1.14) (RADIUS) 1 0.042 - 0.048 (1.07 - 1.22) PIN 1 ID 8 22 0.300 BSC (7.62 BSC) 0.450 - 0.456 0.485 - 0.495 (11.43 - 11.58) (12.32 - 12.57) 0.390 - 0.430 (9.90 - 10.92) 15 0.009 - 0.011 (0.23 - 0.28) 0.050 BSC (1.27 BSC) 0.026 - 0.032 (0.66 - 0.81) 0.013 - 0.021 (0.33 - 0.53) 0.165 - 0.180 (4.06 - 4.57) 0.148 - 0.156 (3.76 - 3.96) 0.099 - 0.110 (2.51 - 2.79) SEATING PLANE ORDERING INFORMATION PART NUMBER TEMPERATURE PACKAGE ML4668CQ 0°C to 70°C 28-Pin PLCC (Q28) © Micro Linear 1997 is a registered trademark of Micro Linear Corporation Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946. Other patents are pending. Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application. 14 2092 Concourse Drive San Jose, CA 95131 Tel: 408/433-5200 Fax: 408/432-0295 DS4668-01