FAIRCHILD 74ABT2244CSJ

Revised November 1999
74ABT2244
Octal Buffer/Line Driver with
25Ω Series Resistors in the Outputs
General Description
Features
The ABT2244 is an octal buffer and line driver designed to
drive the capacitive inputs of MOS memory drivers,
address drivers, clock drivers, and bus-oriented transmitters/receivers.
■ Guaranteed latchup protection
■ High impedance glitch-free bus loading during entire
power up and power down cycle
■ Nondestructive hot insertion capability
The 25Ω series resistors in the outputs reduce ringing and
eliminate the need for external resistors.
Ordering Code:
Order Number
74ABT2244CSC
74ABT2244CSJ
Package Number
Package Description
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
M20D
74ABT2244CMSA
MSA20
74ABT2244CMTC
MTC20
74ABT2244CPC
N20A
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices are also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
Schematic of Each Output
Description
OE1, OE2
Output Enable Input
(Active LOW)
I0–I7
Inputs
O0–O7
Outputs
Truth Table
OE1
I0–3
O0–3
OE2
I4–7
O4–7
H
X
Z
H
X
Z
L
H
H
L
H
H
L
L
L
L
L
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
© 1999 Fairchild Semiconductor Corporation
DS010991
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74ABT2244 Octal Buffer/Line Driver with 25Ω Series Resistors in the Outputs
May 1992
74ABT2244
Absolute Maximum Ratings(Note 1)
Storage Temperature
−65°C to +150°C
Recommended Operating
Conditions
Ambient Temperature under Bias
−55°C to +125°C
Free Air Ambient Temperature
Junction Temperature under Bias
−55°C to +150°C
Supply Voltage
−0.5V to +7.0V
VCC Pin Potential to Ground Pin
Input Voltage (Note 2)
−0.5V to +7.0V
Input Current (Note 2)
−30 mA to +5.0 mA
−40°C to +85°C
+4.5V to +5.5V
Minimum Input Edge Rate (∆V/∆t)
Data Input
50 mV/ns
Enable Input
20 mV/ns
Voltage Applied to Any Output
in the Disabled or
Power-off State
−0.5V to 5.5V
in the HIGH State
−0.5V to VCC
Current Applied to Output
in LOW State (Max)
twice the rated IOL (mA)
DC Latchup Source Current
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
−300 mA
(Across Comm Operating Range)
Over Voltage Latchup (I/O)
10V
DC Electrical Characteristics
Symbol
Parameter
Min
Typ
Max
2.0
Units
VCC
V
Conditions
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
0.8
V
VCD
Input Clamp Diode Voltage
−1.2
V
Min
IIN = −18 mA
VOH
Output HIGH
V
Min
IOH = −3 mA
V
Min
IOH = −32 mA
VOL
Output LOW Voltage
0.8
V
Min
IIH
Input HIGH Current
1
2.5
2.0
1
IBVI
Input HIGH Current Breakdown Test
7
IIL
Input LOW Current
−1
VID
Input Leakage Test
−1
IOZH
Output Leakage Current
IOZL
Output Leakage Current
IOS
Output Short-Circuit Current
ICEX
475
10
Recognized HIGH Signal
Recognized LOW Signal
µA
Max
µA
Max
µA
Max
V
0.0
IOL = 15 mA
VIN = 2.7V (Note 4)
VIN = VCC
VIN = 7.0V
VIN = 0.5V (Note 4)
VIN = 0.0V
IID = 1.9 µA
All Other Pins Grounded
µA
0 − 5.5V VOUT = 2.7V; OEn = 2.0V
0 − 5.5V VOUT = 0.5V; OEn = 2.0V
−10
µA
−275
mA
Max
VOUT = 0.0V
Output HIGH Leakage Current
50
µA
Max
VOUT = VCC
IZZ
Bus Drainage Test
100
µA
0.0
VOUT = 5.5V; All Others GND
ICCH
Power Supply Current
50
µA
Max
All Outputs HIGH
ICCL
Power Supply Current
30
mA
Max
All Outputs LOW
ICCZ
Power Supply Current
50
µA
Max
OEn = V CC
ICCT
Additional
Outputs Enabled
2.5
mA
Outputs 3-STATE
2.5
mA
Outputs 3-STATE
50
µA
−100
All Others at VCC or GND
ICC/Input
VI = VCC − 2.1V
Max
Enable Input VI = VCC − 2.1V
Data Input VI = VCC − 2.1V
All Others at VCCor GND
ICCD
Dynamic ICC
No Load
mA/
(Note 4)
0.1
MHz
Max
Outputs OPEN
OEn = GND (Note 3)
One Bit Toggling, 50% Duty Cycle
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Note 3: For 8 bits toggling, ICCD < 0.8 mA/MHz.
Note 4: Guaranteed, but not tested.
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2
(SOIC and SSOP Package)
Symbol
Parameter
TA = +25°C
TA = −40°C to +85°C
VCC = +5V
VCC = 4.5V–5.5V
CL = 50 pF
CL = 50 pF
Min
Typ
Max
Min
tPLH
Propagation
1.0
2.2
3.9
1.0
3.9
tPHL
Delay Data to Outputs
1.0
2.9
4.4
1.0
4.4
tPZH
Output Enable
1.5
3.7
6.0
1.5
6.0
tPZL
Time
2.1
4.3
7.0
2.1
7.0
tPHZ
Output Disable
1.7
3.5
5.8
1.7
5.8
tPLZ
Time
1.7
3.7
5.8
1.7
5.8
Units
Max
ns
ns
ns
Capacitance
Symbol
Parameter
Typ
Units
Conditions
TA = 25°C
CIN
Input Capacitance
5.0
pF
VCC = 0V
COUT (Note 5)
Output Capacitance
9.0
pF
VCC = 5.0V
Note 5: COUT is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.
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74ABT2244
AC Electrical Characteristics
74ABT2244
AC Loading
*Includes jig and probe capacitance
FIGURE 2. Test Input Signal Levels
FIGURE 1. Standard AC Test Load
Amplitude
Rep. Rate
tw
tr
tf
3.0V
1 MHz
500 ns
2.5 ns
2.5 ns
FIGURE 3. Test Input Signal Requirements
AC Waveforms
FIGURE 4. Propagation Delay Waveforms for
Inverting and Non-Inverting Functions
FIGURE 6. Propagation Delay,
Pulse Width Waveforms
FIGURE 5. 3-STATE Output HIGH
and LOW Enable and Disable Times
FIGURE 7. Setup Time, Hold Time
and Recovery Time Waveforms
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74ABT2244
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
Package Number M20B
5
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74ABT2244
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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6
74ABT2244
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
Package Number MSA20
7
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74ABT2244
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
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8
74ABT2244 Octal Buffer/Line Driver with 25Ω Series Resistors in the Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
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to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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