E2L0015-17-Y1
¡ Semiconductor
MSM518122
¡ Semiconductor
This version:MSM518122
Jan. 1998
Previous version: Dec. 1996
131,072-Word ¥ 8-Bit Multiport DRAM
DESCRIPTION
The MSM518122 is an 1-Mbit CMOS multiport DRAM composed of a 131,072-word by 8-bit
dynamic RAM and a 256-word by 8-bit SAM. Its RAM and SAM operate independently and
asynchronously.
The MSM518122 supports three types of operation : random access to RAM port, high speed
serial access to SAM port and bidirectional transfer of data between any selected row in the
RAM port and the SAM port. In addition to the conventional multiport DRAM operating
modes, the MSM518122 features the block write and flash write functions on the RAM port and
a split data transfer capability on the SAM port. The SAM port requires no refresh operation
because it uses static CMOS flip-flops.
FEATURES
• Single power supply: 5 V ±10%
• Full TTL compatibility
• Multiport organization
RAM: 128K word ¥ 8 bits
SAM: 256 word ¥ 8 bits
• Fast page mode
• Write per bit
• Masked flash write
• Masked block write
• RAS only refresh
• CAS before RAS refresh
• Hidden refresh
• Serial read/write
• 256 tap location
• Bidirectional data transfer
• Split transfer
• Masked write transfer
• Refresh: 512 cycles/8 ms
• Package options:
40-pin 475 mil plastic ZIP (ZIP40-P-475-1.27)
40-pin 400 mil plastic SOJ (SOJ40-P-400-1.27)
(Product : MSM518122-xxZS)
(Product : MSM518122-xxJS)
xx indicates speed rank.
PRODUCT FAMILY
Family
Access Time
Cycle Time
Power Dissipation
RAM
SAM
RAM
SAM
Operating
Standby
MSM518122-70
70 ns
25 ns
140 ns
30 ns
120 mA
8 mA
MSM518122-80
80 ns
25 ns
150 ns
30 ns
110 mA
8 mA
MSM518122-10
100 ns
25 ns
180 ns
30 ns
100 mA
8 mA
1/45
¡ Semiconductor
MSM518122
PIN CONFIGURATION (TOP VIEW)
W5/IO5
1
W7/IO7
3
SE
5
SIO6
7
SIO8
9
SC 11
SIO2 13
SIO4 15
W1/IO1 17
W3/IO3 19
W4/IO4 21
WB/WE 23
A8 25
VSS2 27
A5 29
NC 31
A7 33
A2 35
A0 37
CAS 39
SC 1
2
W6/IO6
4
W8/IO8
6
SIO5
8
SIO7
SIO1 2
SIO2 3
SIO3 4
SIO4 5
10 VSS1
DT/OE 6
12 SIO1
W1/IO1 7
14 SIO3
W2/IO2 8
16 DT/OE
W3/IO3 9
18 W2/IO2
20 NC
W4/IO4 10
VCC1 11
22 VCC1
WB/WE 12
24 RAS
NC 13
26 A6
RAS 14
28 NC
NC 15
30 A4
32 VCC2
34 A3
36 A1
38 QSF
40 DSF
39 SIO8
38 SIO7
37 SIO6
36 SIO5
35 SE
34 W8/IO8
33 W7/IO7
32 W6/IO6
31 W5/IO5
30 VSS2
29 DSF
28 NC
27 CAS
26 QSF
A8 16
25 A0
A6 17
24 A1
A5 18
23 A2
A4 19
22 A3
VCC2 20
21 A7
40-Pin Plastic ZIP
Pin Name
40 VSS1
40-Pin Plastic SOJ
Function
Pin Name
Function
Address Input
SC
Serial Clock
W1/IO1 - W8/IO8
RAM Inputs/Outputs
SE
SAM Port Enable
SIO1 - SIO8
SAM Inputs/Outputs
DSF
Special Function Input
RAS
Row Address Strobe
QSF
Special Function Output
CAS
Column Address Strobe
VCC
Power Supply (5 V)
WB/WE
Write per Bit/Write Enable
VSS
Ground (0 V)
DT/OE
Transfer/Output Enable
NC
No Connection
A0 - A8
Note :
The same power supply voltage must be provided to every VCC pin, and the same GND
voltage level must be provided to every VSS pin.
2/45
Refresh
Counter
Block Write
Control
Column Mask
Register
Sense Amp.
I/O Control
Color Register
RAM Input
Buffer
W1/IO1
- W8/IO8
Mask Register
512 ¥ 256 ¥ 8
RAM ARRAY
Gate
Gate
SAM
SAM
Serial Decoder
¡ Semiconductor
A0 - A8
Row Decoder
Row
Address
Buffer
Column Decoder
BLOCK DIAGRAM
Column
Address
Buffer
RAM Output
Buffer
Flash Write
Control
SAM Input
Buffer
SAM Output
Buffer
RAS
SIO1
- SIO8
CAS
Timing
Generator
DT/OE
WB/WE
DSF
SAM
Address
Buffer
SAM Address
Counter
QSF
SC
SE
VCC
3/45
MSM518122
VSS
¡ Semiconductor
MSM518122
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
(Note: 16)
Symbol
Condition
Rating
Unit
Input Output Voltage
VT
Ta = 25°C
–1.0 to 7.0
V
Output Current
IOS
Ta = 25°C
50
mA
Power Dissipation
PD
Ta = 25°C
1
W
Operating Temperature
Topr
—
0 to 70
°C
Storage Temperature
Tstg
—
–55 to 150
°C
Recommended Operating Condition
Parameter
(Ta = 0°C to 70°C) (Note: 17)
Symbol
Min.
Typ.
Max.
Unit
Power Supply Voltage
VCC
4.5
5.0
5.5
V
Input High Voltage
VIH
2.4
—
6.5
V
Input Low Voltage
VIL
–1.0
—
0.8
V
Capacitance
Parameter
Input Capacitance
Input/Output Capacitance
Output Capacitance
Note:
(VCC = 5 V ±10%, f = 1 MHz, Ta = 25°C)
Symbol
Min.
Max.
Unit
CI
—
7
pF
CI/O
—
9
pF
CO(QSF)
—
9
pF
This parameter is periodically sampled and is not 100% tested.
DC Characteristics 1
Parameter
Symbol
Condition
Min.
Max.
Output "H" Level Voltage
VOH
IOH = –2 mA
2.4
—
Output "L" Level Voltage
VOL
IOL = 2 mA
—
0.4
–10
10
Unit
V
0 £ VIN £ VCC
Input Leakage Current
ILI
All other pins not
mA
under test = 0 V
Output Leakage Current
ILO
0 £ VOUT £ 5.5 V
Output Disable
–10
10
4/45
¡ Semiconductor
MSM518122
DC Characteristics 2
Item (RAM)
Operating Current
(RAS, CAS Cycling, tRC = tRC min.)
Standby Current
(RAS, CAS = VIH)
RAS Only Refresh Current
(RAS Cycling, CAS = VIH, tRC = tRC min.)
Page Mode Current
(RAS = VIL, CAS Cycling, tPC = tPC min.)
CAS before RAS Refresh Current
(RAS Cycling, CAS before RAS, tRC = tRC min.)
Data Transfer Current
(RAS, CAS Cycling, tRC = tRC min.)
Flash Write Current
(RAS, CAS Cycling, tRC = tRC min.)
Block Write Current
(RAS, CAS Cycling, tRC = tRC min.)
(VCC = 5 V ±10%, Ta = 0°C to 70°C)
SAM
Symbol
-70
-80
-10
Max. Max. Max.
Unit Note
Standby
ICC1
85
75
65
1, 2
Active
ICC1A
120
110
100
1, 2
Standby
ICC2
8
8
8
3
Active
ICC2A
50
45
40
1, 2
Standby
ICC3
85
75
65
1, 2
Active
ICC3A
120
110
100
1, 2
Standby
ICC4
70
65
60
1, 2
Active
ICC4A
120
110
100
Standby
ICC5
85
75
65
mA
1, 2
1, 2
Active
ICC5A
120
110
100
1, 2
Standby
ICC6
85
75
65
1, 2
Active
ICC6A
120
110
100
1, 2
Standby
ICC7
85
75
65
1, 2
Active
ICC7A
120
110
100
1, 2
Standby
ICC8
85
75
65
1, 2
Active
ICC8A
120
110
100
1, 2
5/45
¡ Semiconductor
MSM518122
AC Characteristics (1/3)
Parameter
(VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 4, 5, 6
Symbol
-70
-80
-10
Min. Max. Min. Max. Min. Max.
Unit Note
tRC
140
—
150
—
180
—
ns
tRWC
195
—
195
—
235
—
ns
tPC
45
—
50
—
55
—
ns
tPRWC
90
—
90
—
100
—
ns
tRAC
—
70
—
80
—
100
ns
7, 13
Access Time from Column Address
tAA
—
35
—
40
—
55
ns
7, 13
Access Time from CAS
tCAC
—
20
—
25
—
25
ns
7, 14
Access Time from CAS Precharge
tCPA
—
40
—
45
—
50
ns
7, 14
Output Buffer Turn-off Delay
tOFF
0
20
0
20
0
20
ns
9
6
Random Read or Write Cycle Time
Read Modify Write Cycle Time
Fast Page Mode Cycle Time
Fast Page Mode Read Modify Write Cycle Time
Access Time from RAS
Transition Time (Rise and Fall)
tT
3
35
3
35
3
35
ns
RAS Precharge Time
tRP
60
—
60
—
70
—
ns
RAS Pulse Width
tRAS
70
10k
80
10k
100
10k
ns
RAS Pulse Width (Fast Page Mode Only)
tRASP
70
100k
80
100k 100 100k
ns
RAS Hold Time
tRSH
20
—
25
CAS Hold Time
tCSH
70
—
CAS Pulse Width
tCAS
20
10k
RAS to CAS Delay Time
tRCD
20
50
RAS to Column Address Delay Time
tRAD
15
35
—
25
—
ns
80
—
100
—
ns
25
10k
25
10k
ns
20
55
20
75
ns
13
15
40
20
50
ns
13
Column Address to RAS Lead Time
tRAL
35
—
40
—
55
—
ns
CAS to RAS Precharge Time
tCRP
10
—
10
—
10
—
ns
CAS Precharge Time
tCPN
10
—
10
—
10
—
ns
CAS Precharge Time (Fast Page Mode)
tCP
10
—
10
—
10
—
ns
Row Address Set-up Time
tASR
0
—
0
—
0
—
ns
Row Address Hold Time
tRAH
10
—
10
—
10
—
ns
Column Address Set-up Time
tASC
0
—
0
—
0
—
ns
Column Address Hold Time
tCAH
15
—
15
—
15
—
ns
Column Address Hold Time referenced to RAS
tAR
55
—
55
—
70
—
ns
Read Command Set-up Time
tRCS
0
—
0
—
0
—
ns
Read Command Hold Time
tRCH
0
—
0
—
0
—
ns
10
10
Read Command Hold Time referenced to RAS
tRRH
0
—
0
—
0
—
ns
Write Command Hold Time
tWCH
15
—
15
—
15
—
ns
Write Command Hold Time referenced to RAS
tWCR
55
—
55
—
70
—
ns
Write Command Pulse Width
tWP
15
—
15
—
15
—
ns
Write Command to RAS Lead Time
tRWL
20
—
20
—
25
—
ns
Write Command to CAS Lead Time
tCWL
20
—
20
—
25
—
ns
6/45
¡ Semiconductor
MSM518122
AC Characteristics (2/3)
Parameter
Data Set-up Time
(VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 4, 5, 6
Symbol
-70
-80
-10
Min. Max. Min. Max. Min. Max.
Unit Note
—
0
—
ns
11
15
—
15
—
ns
11
55
—
70
—
ns
tDS
0
—
0
Data Hold Time
tDH
15
—
Data Hold Time referenced to RAS
tDHR
55
—
Write Command Set-up Time
tWCS
0
—
0
—
0
—
ns
12
RAS to WE Delay Time
tRWD
100
—
100
—
130
—
ns
12
Column Address to WE Delay Time
tAWD
65
—
65
—
80
—
ns
12
CAS to WE Delay Time
tCWD
45
—
45
—
55
—
ns
12
Data to CAS Delay Time
tDZC
0
—
0
—
0
—
ns
Data to OE Delay Time
tDZO
0
—
0
—
0
—
ns
Access Time from OE
tOEA
—
20
—
20
—
25
ns
7
Output Buffer Turn-off Delay from OE
tOEZ
0
10
0
10
0
20
ns
9
OE to Data Delay Time
tOED
10
—
10
—
20
—
ns
OE Command Hold Time
tOEH
10
—
10
—
20
—
ns
RAS Hold Time referenced to OE
tROH
15
—
15
—
15
—
ns
CAS Set-up Time for CAS before RAS Cycle
tCSR
10
—
10
—
10
—
ns
CAS Hold Time for CAS before RAS Cycle
tCHR
10
—
10
—
10
—
ns
RAS Precharge to CAS Active Time
tRPC
0
—
0
—
0
—
ns
Refresh Period
tREF
—
8
—
8
—
8
ms
WB Set-up Time
tWSR
0
—
0
—
0
—
ns
WB Hold Time
tRWH
15
—
15
—
15
—
ns
DSF Set-up Time referenced to RAS
tFSR
0
—
0
—
0
—
ns
DSF Hold Time referenced to RAS (1)
tRFH
15
—
15
—
15
—
ns
DSF Hold Time referenced to RAS (2)
tFHR
55
—
55
—
70
—
ns
DSF Set-up Time referenced to CAS
tFSC
0
—
0
—
0
—
ns
DSF Hold Time referenced to CAS
tCFH
15
—
15
—
15
—
ns
Write Per Bit Mask Data Set-up Time
tMS
0
—
0
—
0
—
ns
Write Per Bit Mask Data Hold Time
tMH
15
—
15
—
15
—
ns
DT High Set-up Time
tTHS
0
—
0
—
0
—
ns
DT High Hold Time
tTHH
15
—
15
—
15
—
ns
DT Low Set-up Time
tTLS
0
—
0
—
0
—
ns
DT Low Hold Time
tTLH
15
10k
15
10k
15
10k
ns
tRTH
60
10k
65
10k
80
10k
ns
tATH
25
—
30
—
30
—
ns
tCTH
20
—
25
—
25
—
ns
SE Set-up Time referenced to RAS
tESR
0
—
0
—
0
—
ns
SE Hold Time referenced to RAS
tREH
15
—
15
—
15
—
ns
DT Low Hold Time referenced to RAS
(Real Time Read Transfer)
DT Low Hold Time referenced to Column Address
(Real Time Read Transfer)
DT Low Hold Time referenced to CAS
(Real Time Read Transfer)
7/45
¡ Semiconductor
MSM518122
AC Characteristics (3/3)
Parameter
DT to RAS Precharge Time
(VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 4, 5, 6
Symbol
tTRP
-70
-80
-10
Min. Max. Min. Max. Min. Max.
60
—
60
—
Unit Note
70
—
ns
DT Precharge Time
tTP
20
—
20
—
30
—
ns
RAS to First SC Delay Time (Read Transfer)
tRSD
70
—
80
—
100
—
ns
Column Address to First SC Delay Time (Read Transfer)
tASD
45
—
45
—
50
—
ns
CAS to First SC Delay Time (Read Transfer)
tCSD
20
—
25
—
25
—
ns
Last SC to DT Lead Time (Real Time Read Transfer)
tTSL
5
—
5
—
5
—
ns
DT to First SC Delay Time (Read Transfer)
tTSD
15
—
15
—
15
—
ns
Last SC to RAS Set-up Time (Serial Input)
tSRS
25
—
25
—
30
—
ns
RAS to First SC Delay Time (Serial Input)
tSRD
20
—
20
—
25
—
ns
RAS to Serial Input Delay Time
tSDD
40
—
40
—
50
—
ns
tSDZ
10
40
10
40
10
50
ns
SC Cycle Time
tSCC
30
—
30
—
30
—
ns
SC Pulse Width (SC High Time)
tSC
10
—
10
—
10
—
ns
SC Precharge Time (SC Low Time)
tSCP
10
—
10
—
10
—
ns
Access Time from SC
tSCA
—
25
—
25
—
25
ns
Serial Output Hold Time from SC
tSOH
5
—
5
—
5
—
ns
Serial Input Set-up Time
tSDS
0
—
0
—
0
—
ns
Serial Input Hold Time
tSDH
15
—
15
—
15
—
ns
Access Time from SE
tSEA
—
25
—
25
—
25
ns
SE Pulse Width
tSE
25
—
25
—
25
—
ns
SE Precharge Time
tSEP
25
—
25
—
25
—
ns
Serial Output Buffer Turn-off Delay from SE
tSEZ
0
20
0
20
0
20
ns
Serial Input to SE Delay Time
tSZE
0
—
0
—
0
—
ns
Serial Input to First SC Delay Time
tSZS
0
—
0
—
0
—
ns
Serial Output Buffer Turn-off Delay from RAS
(Pseudo Write Transfer)
Serial Write Enable Set-up Time
tSWS
5
—
5
—
5
—
ns
Serial Write Enable Hold Time
tSWH
15
—
15
—
15
—
ns
Serial Write Disable Set-up Time
tSWIS
5
—
5
—
5
—
ns
Serial Write Disable Hold Time
tSWIH
15
—
15
—
15
—
ns
Split Transfer Set-up Time
tSTS
25
—
30
—
30
—
ns
Split Transfer Hold Time
tSTH
25
—
30
—
30
—
ns
SC-QSF Delay Time
tSQD
—
20
—
25
—
25
ns
DT-QSF Delay Time
tTQD
—
20
—
25
—
25
ns
CAS-QSF Delay Time
tCQD
—
30
—
35
—
35
ns
RAS-QSF Delay Time
tRQD
—
70
—
75
—
85
ns
9
8
8
9
8/45
¡ Semiconductor
Notes:
MSM518122
1. These parameters depend on output loading. Specified values are obtained with
the output open.
2. These parameters are masured at minimum cycle test.
3. ICC2 (Max.) are mesured under the condition of TTL input level.
4. VIH (Min.) and VIL (Max.) are reference levels for measuring timing of input signals.
Also, transition times are measured between VIH and VIL.
5. An initial pause of 200 ms is required after power-up followed by any 8 RAS cycles
(DT/OE “high”) and any 8 SC cycles before proper divice operation is achieved. In
the case of using an internal refresh counter, a minimum of 8 CAS before RAS
initialization cycles in stead of 8 RAS cycles are required.
6. AC measurements assume tT = 5 ns.
7. RAM port outputs are mesured with a load equivalent to 1 TTL load and 100 pF.
Output reference levels are VOH/VOL = 2.4 V/1.0 V.
8. SAM port outputs are measured with a load equivalent to 1 TTL load and 30 pF.
Output reference levels are VOH/VOL = 2.0 V/1.0 V.
9. tOFF (Max.), tOEZ (Max.), tSDZ (Max.) and tSEZ (Max.) difine the time at which the
outputs achieve the open circuit condition and are not reference to output voltage
levels.
10. Either tRCH or tRRH must be satisfied for a read cycle.
11. These parameters are referenced to CAS leading edge of early write cycles and to
WB/WE leading edge in OE controlled write cycles and read modify write cycles.
12. tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are
included in the data sheet as electrical characteristics only.
If tWCS ≥ tWCS (Min.), the cycle is an early write cycle, and the data out pin will
remain open circuit (high impedance) throughout the entire cycle : If tRWD ≥ tRWD
(Min.), tCWD ≥ tCWD (Min.) and tAWD ≥ tAWD (Min.) the cycle is a read-write cycle
and the data out will contain data read from the selected cell : If neither of the above
sets of conditions is satisfied, the condition of the data out (at access time) is
indterminate.
13. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD
(Max.) is specified as a reference point only : If tRCD is greater than the specified tRCD
(Max.) limit, then access time is controlled by tCAC.
14. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD
(Max.) is specified as a reference point only : If tRAD is greater than the specified tRAD
(Max.) limit, then access time is controlled by tAA.
15. Input levels at the AC parameter measurement are 3.0 V/0 V.
16. Stresses greater than those listed under “Absolute Maximum Ratings” may cause
permenent damege to the device.
17. All voltages are referenced to VSS.
9/45
¡ Semiconductor
MSM518122
TIMING WAVEFORM
Read Cycle
tRC
tRAS
RAS
tRP
tAR
VIH –
VIL –
tCSH
,
,
tCRP
CAS
tRSH
VIH –
VIL –
VIH –
VIL –
tCPN
tCAS
tASR
A0 - A8
tRCD
tRAD
tRAH
Row Address
tRAL
tCAH
tASC
Column Address
tRCH
tRRH
tRCS
WB/WE
VIH –
VIL –
tTHS
DT/OE
tROH
tTHH
VIH –
VIL –
tFSR
tFHR
tFSC
tRFH
tCFH
VIH –
DSF
VIL –
tOEA
tDZO
IN
VIH –
VIL –
W1/IO1 W8/IO8
OUT
tCAC
tAA
tRAC
VOH –
VOL –
Open
tOFF
tOEZ
Valid Data-out
"H" or "L"
10/45
¡ Semiconductor
MSM518122
Write Cycle (Early Write)
tRC
tRAS
RAS
tRP
tAR
VIH –
VIL –
tCSH
,,,
,
tCRP
tRCD
tRSH
tRAD
tASR
VIH –
A0 - A8
VIL –
tRAH
tRAL
tASC
tRWH
VIH –
VIL –
tCAH
Column Address
Row Address
tWSR
WB/WE
tWCS
tWCH
tWP
*1
tWCR
tTHS
DT/OE
tCPN
tCAS
VIH –
CAS
VIL –
tTHH
tCWL
tRWL
VIH –
VIL –
tFSR
tRFH
tFHR
tFSC
tMS
tMH
tDS
tCFH
tDH
VIH –
DSF
VIL –
IN
VIH –
VIL –
WM1 Data
tDHR
W1/IO1 W8/IO8
OUT
Valid Data-in
VOH –
VOL –
Open
"H" or "L"
*1 WB/WE
W1/IO1 - W8/IO8
Cycle
0
WM1 data
Write per Bit
1
Don’t Care
Normal Write
WM1 data:
0: Write Disable
1: Write Enable
11/45
¡ Semiconductor
MSM518122
Write Cycle (OE Controlled Write)
tRC
tRAS
RAS
tRP
tAR
VIH –
VIL –
tCSH
,
,
tCRP
CAS
tRCD
tCAS
VIH –
VIL –
tRAD
tRAH
tASR
A0 - A8
VIH –
VIL –
tCPN
tRSH
Row Address
tRAL
tCAH
tASC
Column Address
tCWL
tWSR
VIH –
WB/WE
VIL –
tRWH
tRWL
tWP
*1
tWCR
tTHS
tOEH
VIH –
DT/OE
VIL –
tFHR
tFSR
tRFH
tMS
tMH
tFSC
tCFH
VIH –
DSF
VIL –
IN
VIH –
VIL –
WM1 Data
tDH
Valid Data-in
tDHR
W1/IO1 W8/IO8
OUT
tDS
VOH–
VOL –
Open
"H" or "L"
*1 WB/WE
W1/IO1 - W8/IO8
Cycle
0
WM1 data
Write per Bit
1
Don’t Care
Normal Write
WM1 data:
0: Write Disable
1: Write Enable
12/45
¡ Semiconductor
MSM518122
Read Modify Write Cycle
tRWC
tRAS
RAS
tRP
tAR
VIH –
VIL –
tCSH
,
,
,
tCRP
CAS
tRCD
tRSH
VIH –
VIL –
tCPN
tCAS
tRAD
tASR
VIH –
A0 - A8
VIL –
tASC
tRAH
tCAH
Column Address
Row Address
tCWL
tRWH
tWSR
VIH –
WB/WE
VIL –
tRCS
tCWD
*1
tRWL
tWP
tAWD
tRWD
tTHH
tTHS
DT/OE
tOEH
VIH –
VIL –
tFHR
tFSR
tRFH
tFSC
tMS
tMH
tDZC
tDZO
tCFH
VIH –
DSF
VIL –
IN
VIH –
VIL –
WM1 Data
W1/IO1 W8/IO8
OUT
tDS
tOED
tRAC
VOH–
VOL –
Valid
Data-in
tOEA
tAA
tDH
tCAC
Open
tOEZ
Valid
Data-out
"H" or "L"
*1 WB/WE
W1/IO1 - W8/IO8
Cycle
0
WM1 data
Write per Bit
1
Don’t Care
Normal Write
WM1 data:
0: Write Disable
1: Write Enable
13/45
¡ Semiconductor
MSM518122
Fast Page Mode Read Cycle
tRASP
RAS
tAR
VIH –
VIL –
tRP
tPC
tRSH
tCRP
tRCD
tASR
tRAD
tCSH
tRAH tASC
,,
,
,
CAS
A0 - A8
VIH –
VIL –
VIH –
VIL –
Row
Address
tCP
tCAS
tCP
tCAS
tASC
tCAH
tCPN
tCAS
tASC
tCAH
Column
Address 1
tRAL
tCAH
Column
Address 2
tRCH
Column
Address n
tRCH
tRCH
tRCS
tRCS
tRRH
tRCS
VIH –
WB/WE
VIL –
tTHS
tTHH
VIH –
DT/OE V
IL –
tFSC
tFSR
DSF
VIH –
VIL –
tFSC
tFSC
tCFH
tTHH
tCFH
tCFH
tFHR
tDZO
IN
tCPA
VIH –
VIL –
W1/IO1 W8/IO8
VOH –
OUT V
OL –
tOEA
tCAC
tRAC
Open
tAA
tCPA
tOEA
tOFF
tOEZ
Data-out 1
tCAC
tAA
tOFF
tOEZ
Data-out 2
tOEA
tCAC
tAA
tOFF
tOEZ
Data-out n
"H" or "L"
14/45
¡ Semiconductor
MSM518122
Fast Page Mode Write Cycle (Early Write)
tRASP
RAS
tAR
VIH –
VIL –
tRP
tPC
tRSH
,,,
,
tCRP
CAS
VIH –
VIL –
tASR
A0 - A8
VIH –
VIL –
tRCD
tRAD
tCSH
tRAH tASC
Row
Address
tCP
tCP
tCAS
tCAS
tCAH
tASC
tCAH
Column
Address 1
WB/WE
VIH –
VIL –
tRWH
tWCS
VIH –
VIL –
tWP
tCWL
tRWL
tCWL
tCFH
tFSC
tDS
WM1
Data
tFSC
tFSC
tCFH
tCFH
tMH
VIH –
VIL –
tWP
tFHR
tRFH
tFSR
tMS
IN
tWCH
tTHH
VIH –
DT/OE V
IL –
DSF
Column
Address n
tWCS
tWCS
tCWL
tTHS
tCAH
tWCH
tWCH
tWP
*1
tRAL
tASC
Column
Address 2
tWCR
tWSR
tCPN
tCAS
tDH
tDH
tDH
tDS
Data-in 1
tDS
Data-in 2
Data-in n
tDHR
W1/IO1 W8/IO8
VOH –
OUT V
OL –
Open
"H" or "L"
*1 WB/WE
W1/IO1 - W8/IO8
Cycle
0
WM1 data
Write per Bit
1
Don’t Care
Normal Write
WM1 data:
0: Write Disable
1: Write Enable
15/45
¡ Semiconductor
MSM518122
Fast Page Mode Read Modify Write Cycle
tRASP
tRP
tAR
RAS
VIH –
VIL –
tCSH
tPRWC
tRSH
,
,
CAS
tCAS
VIH –
VIL –
VIH –
A0 - A8
VIL –
Column
Address 1
Column
Address 2
Column
Address n
tWP
tCWD
tCWD
tRWD
tRFH
tFHR
tFSC
tFSC
tFSC
tMS
tDS
tDZO
tDZC
tOED
WM1
Data
tDH
tCAC
tOED
tDZC
tCAC
tDZC
Datain 2
tOED
tCAC
tAA
tOEZ
Dataout 2
tDH
Datain n
tOEA
tAA
Dataout 1
tDS
tDZO
tDH
tOEA
tOEZ
tAA
tRAC
tDS
tDZO
Datain 1
tOEA
W1/IO1 W8/IO8
tCFH
tCFH
tCFH
VIH –
VIL –
VOH –
VOL –
tRWL
tWP
tCWD
tMH
OUT
tCAH
tTHH
tFSR
VIH –
VIL –
tCWL
tWP
*1
VIL –
tCWL
tASC
tCAH
tCWL
tRWH
tWSR
VIH –
tTHS
IN
tCAS
tASC
tCAH
Row
Address
VIH –
DT/OE V
IL –
DSF
tCAS
tASC
tASR tRAH
WB/WE
tCP
tCP
tRCD
tOEZ
Dataout n
"H" or "L"
*1 WB/WE
W1/IO1 - W8/IO8
Cycle
0
WM1 data
Write per Bit
1
Don’t Care
Normal Write
WM1 data:
0: Write Disable
1: Write Enable
16/45
¡ Semiconductor
MSM518122
RAS Only Refresh Cycle
tRC
tRP
tRAS
VIH –
VIL –
,,,
,
RAS
tRPC
tCRP
tCRP
VIH –
CAS
VIL –
tASR
VIH –
A0 - A8
VIL –
WB/WE
DT/OE
tRAH
Row Address
VIH –
VIL –
tTHS
tTHH
tFSR
tRFH
VIH –
VIL –
VIH –
DSF
VIL –
W1/IO1 - VOH–
W8/IO8 VOL –
Open
"H" or "L"
17/45
¡ Semiconductor
MSM518122
CAS before RAS Refresh Cycle
tRC
,,,
tRP
RAS
VIH –
VIL –
tRP
tRAS
tRPC
tCSR
tCPN
tCHR
VIH –
CAS
VIL –
WB/WE
VIH –
VIL –
VIH –
DT/OE V
IL –
DSF
VIH –
VIL –
tOFF
W1/IO1 - VOH–
W8/IO8 VOL –
Open
Note: A0 - A8 = Don't care ("H" or "L")
"H" or "L"
18/45
¡ Semiconductor
MSM518122
Hidden Refresh Cycle
tRC
tRC
tRAS
tRAS
tRP
tRP
tAR
VIH –
VIL –
,
,
,
,
RAS
tCRP
CAS
tCHR
tCPN
VIH –
VIL –
tASR
A0 - A8
tRSH
tRCD
VIH –
VIL –
tRAD
tRAH
tASC
tRAL
tCAH
Column
Address
Row Address
tWSR
tRCS
WB/WE
tRRH
tRWH
VIH –
VIL –
tTHS
tROH
tTHH
VIH –
DT/OE
VIL –
tFSR
tRFH
tFSC
tCFH
tFHR
VIH –
DSF
VIL –
tOEZ
tOFF
W1/IO1 - VOH–
W8/IO8 VOL –
tAA
tOEA
tCAC
tOFF
tOEZ
Valid Data-out
"H" or "L"
19/45
¡ Semiconductor
MSM518122
Load Color Register Cycle
tRC
tRP
tRAS
RAS
VIH –
VIL –
tCSH
,
,
,
tCRP
CAS
tRSH
tASR
tRAH
Row Address
tCWL
tWSR
tRWL
tRWH
tWP
VIH –
VIL –
tWCR
tTHS
DT/OE
tWCH
tOEH
VIH –
VIL –
tFSR
DSF
tCPN
tCAS
VIH –
VIL –
VIH –
A0 - A8
VIL –
WB/WE
tRCD
tRFH
VIH –
VIL –
tDHR
tDS
IN
VIH –
VIL –
W1/IO1 W8/IO8
OUT
Color Data-in
tDS
VOH –
VOL –
tDH
tDH
(Delayed Write)
Color Data-in
(Early Write)
"H" or "L"
20/45
¡ Semiconductor
MSM518122
Read Color Register Cycle
tRC
tRAS
tRP
VIH –
VIL –
,,,
,
RAS
tCSH
tCRP
CAS
tRSH
VIH –
VIL –
tRAH
Row Address
tTHS
tTHH
tROH
VIH –
DT/OE
VIL –
WB/WE
DSF
tCPN
tCAS
VIH –
VIL –
tASR
A0 - A8
tRCD
tRRH
tWSR
tRWH
tFSR
tRFH
tRCS
tRCH
VIH –
VIL –
VIH –
VIL –
tOEA
tCAC
W1/IO1 - VOH–
W8/IO8 VOL –
tOFF
tOEZ
Valid Data-out
tRAC
"H" or "L"
21/45
¡ Semiconductor
MSM518122
Flash Write Cycle
tRC
tRAS
RAS
tRP
VIH –
VIL –
tCSH
,,
,
tCRP
CAS
tRSH
tRCD
tCPN
VIH –
VIL –
tCAS
tASR
VIH –
A0 - A8
VIL –
WB/WE
DT/OE
DSF
IN
VIH –
VIL –
tRAH
Row Address
tWSR
tRWH
tTLS
tTLH
tFSR
tRFH
tMS
tMH
VIH –
VIL –
VIH –
VIL –
VIH –
VIL –
WM1 Data
W1/IO1 W8/IO8
OUT
VOH –
VOL –
Open
"H" or "L"
WM1 Data
Cycle
0
Flash Write Disable
1
Flash Write Enable
22/45
¡ Semiconductor
MSM518122
Block Write Cycle
tRC
tRAS
RAS
tRP
tAR
VIH –
VIL –
tCSH
,,
,
tCRP
CAS
tRCD
VIH –
VIL –
tCAS
tRAD
tASR
A0 - A8
VIH –
VIL –
Column Address
(A2C - A7C)
Row Address
VIH –
VIL –
tRAL
tCAH
tASC
tRAH
tWSR
WB/WE
tCPN
tRSH
tRWH
*1
tTHH
tTHS
VIH –
DT/OE
VIL –
tFHR
DSF
tFSR
tRFH
tMS
tMH
tFSC
VIH –
VIL –
VIH –
IN
VIL –
tDS
tDH
*2
*3
tDHR
W1/IO1 W8/IO8
OUT
tCFH
VOH –
VOL –
Open
"H" or "L"
*1 WB/WE
*2 W1/IO1 - W8/IO8
Cycle
0
WM1 data
Masked Block Write
1
Don’t Care
Block Write (Non Mask)
WM1 data:
0: Write Disable
1: Write Enable
*3) COLUMN SELECT
W1/IO1 - Column 0 (A1C = 0, A0C = 0)
W2/IO2 - Column 1 (A1C = 0, A0C = 1)
W3/IO3 - Column 2 (A1C = 1, A0C = 0)
W4/IO4 - Column 3 (A1C = 1, A0C = 1)
Wn/On
= 0 : Disable
= 1 : Enable
23/45
¡ Semiconductor
MSM518122
Fast Page Mode Block Write Cycle
tRP
tRASP
RAS
tAR
VIH –
VIL –
,
,,,
,,
,
tCRP
CAS
VIH –
VIL –
VIH –
VIL –
tCAS
tASC
tRAL
tCAH
tCPN
A2C A7C
tCAH
A2C A7C
A2C A7C
tTHH
VIH –
VIL –
tRWH
VIH –
VIL –
*1
tFHR
tRFH t
FSC
tFSR
DSF
tASC
tCAH
tASC
Row
Address
tRSH
tCP
tCAS
tRAH
tWSR
WB/WE
tCAS
tRAD
tTHS
DT/OE
tPC
tCP
tRCD
tASR
A0 - A8
tPC
tCSH
VIH –
VIL –
tCFH
tCFH
tFSC
tFSC
tDHR
tMH
tMS
W1/IO1 - VIH –
W8/IO8 VIL –
tCFH
*2
tDH
tDS
tDH
tDH
tDS
*3
tDS
*3
*3
"H" or "L"
*1 WB/WE
*2 W1/IO1 - W8/IO8
Cycle
0
WM1 data
Masked Block Write
1
Don’t Care
Block Write (Non Mask)
WM1 data:
0: Write Disable
1: Write Enable
*3) COLUMN SELECT
W1/IO1 - Column 0 (A1C = 0, A0C = 0)
W2/IO2 - Column 1 (A1C = 0, A0C = 1)
W3/IO3 - Column 2 (A1C = 1, A0C = 0)
W4/IO4 - Column 3 (A1C = 1, A0C = 1)
Wn/On
= 0 : Disable
= 1 : Enable
24/45
,
,,
¡ Semiconductor
MSM518122
Read Transfer Cycle (Previous Transfer is Write Transfer Cycle)
tRC
tRAS
RAS
tRP
tAR
VIH –
VIL –
tCSH
tCRP
CAS
tRCD
VIH –
VIL –
tRAD
tRAH
tASR
A0 - A8
VIH –
VIL –
Row Address
tRAL
tCAH
tASC
SAM Start Address
A0 - A7: TAP
tWSR
WB/WE
tCPN
tRSH
tCAS
tRWH
VIH –
VIL –
tTRP
tTLS
tTLH
tFSR
tRFH
tTP
VIH –
DT/OE V
IL –
tASD
DSF
VIH –
VIL –
tCSD
tOFF
tRSD
W1/IO1 - VOH –
W8/IO8 VOL –
tTSD
tSRS
SC
VIH –
VIL –
VIH –
VIL –
tSCP
Inhibit Rising Transient
tSZS
tSDH
Valid Data-in
SIO1 SIO8
tTQD
OUT
tSC
tSC
tSDS
IN
tSCP
tSCC
tSCA
tCQD
VOH –
VOL –
tSOH
Valid
Data-out
tRQD
VOH –
QSF V
OL –
TAP MSB (A7)
Note: SE = VIL
"H" or "L"
25/45
,,,
,,
,
¡ Semiconductor
MSM518122
Real Time Read Transfer Cycle
tRC
tRAS
RAS
tRP
tAR
VIH –
VIL –
tCSH
tCRP
CAS
tRCD
VIH –
VIL –
tRAL
tRAD
tASR
A0 - A8
VIH –
VIL –
tCPN
tRSH
tCAS
tASC
tRAH
Row Address
tCAH
SAM Start Address
A0 - A7: TAP
tWSR
tRWH
tATH
VIH –
WB/WE
VIL –
tCTH
tTLS
tTRP
tRTH
tTP
VIH –
DT/OE V
IL –
tFSR
tRFH
VIH –
DSF
VIL –
tOFF
W1/IO1 - VOH –
W8/IO8 VOL –
tSCC
tSC
tTSL
tSCP
tTSD
VIH –
SC
VIL –
IN
VIH –
VIL –
SIO1 SIO8
Open
tTQD
tSOH
VOH –
OUT V
OL –
tSCA
tSCA
Valid
Data-out
Valid
Data-out
Valid
Data-out
Valid
Data-out
tSOH
Valid
Data-out
Previous Row Data
VOH –
QSF V
OL –
New Row Data
TAP MSB (A7)
Note: SE = VIL
"H" or "L"
26/45
¡ Semiconductor
MSM518122
,
,
,
Split Read Transfer Cycle
tRC
tRAS
RAS
tRP
tAR
VIH –
VIL –
tCSH
tCRP
CAS
tRSH
tRCD
tCAS
VIH –
VIL –
tRAD
tASR
A0 - A8
WB/WE
VIH –
VIL –
tWSR
tRWH
tTLS
tTLH
tRAL
tASC
tCAH
SAM Start
Address (n)
A0 - A6: TAP
VIH –
VIL –
tRFH
tSTS
VIH –
VIL –
tSTH
tFSR
255
(127)
SC
tRAH
Row Address
VIH –
DT/OE
VIL –
DSF
tCPN
n
n+1
(n+128) (n+129)
n+2
(n+130)
...............
125
(253)
126
(254)
255
(127)
n+1
(n+129)
n+2
(n+130)
...............
125
(253)
127
(255)
n+128
(n)
VIH –
VIL –
SIO1 - VOH –
SIO8 VOL –
254
(126)
n
(n+128)
tSQD
126
(254)
127
(255)
tSQD
VOH –
QSF V
OL –
Lower SAM 0 - 127
Upper SAM 128 - 255
Note: SE = VIL
"H" or "L"
27/45
,
¡ Semiconductor
MSM518122
Pseudo Write Transfer Cycle
tRC
tRAS
RAS
tRP
tAR
VIH –
VIL –
tCSH
tCRP
tRCD
tRSH
tCAS
VIH –
CAS
VIL –
tRAD
tASR
A0 - A8
VIH –
VIL –
tASC
tRAH
Row Address
tCPN
tRAL
tCAH
SAM Start Address
A0 - A7: TAP
WB/WE
tWSR
tRWH
tTLS
tTLH
tFSR
tRFH
VIH –
VIL –
VIH –
DT/OE
VIL –
VIH –
DSF
VIL –
tOFF
W1/IO1 - VOH –
W8/IO8 VOL –
Open
tSRD
tSRS
SC
tSCP
VIH –
VIL –
Inhibit Rising Transient
tESR
SIO1 SIO8
VIH –
VIL –
VOH –
OUT V –
OL
tSCP
tSC
tSWS
tREH
VIH –
SE
VIL –
IN
tSCC
tSC
tSDD
tSDZ
tSDS
tSEZ
Valid
Data-in
tSCA
Valid Data-out
tSDH
Valid
Data-out
tSOH
Open
tCQD
tRQD
QSF
VOH –
VOL –
TAP MSB (A7)
Serial Output Data
Serial Input Data
"H" or "L"
28/45
,
¡ Semiconductor
MSM518122
Write Transfer Cycle
tRC
tRAS
RAS
tRP
tAR
VIH –
VIL –
tCSH
tRCD
tCRP
CAS
tRSH
tCAS
VIH –
VIL –
tRAD
tASR
A0 - A8
VIH –
VIL –
tRAH
Row Address
tASC
tCPN
tRAL
tCAH
SAM Start Address
A0 - A7: TAP
WB/WE
tWSR
tRWH
tTLS
tTLH
tFSR
tRFH
VIH –
VIL –
VIH –
DT/OE
VIL –
VIH –
DSF
VIL –
tMS
tMH
tOFF
W1/IO1 - VOH –
W8/IO8 VOL –
Open
WM1 Data
tSRD
tSRS
SC
VIH –
VIL –
tSCP
SIO1 SIO8
tSCP
Inhibit Rising Transient
tSWS
tREH
VIH –
VIL –
tSDS
IN
tSC
tSC
tESR
SE
tSCC
VIH –
VIL –
tCQD
tSDH
tSDS
tSDH
Valid
Data-in
Valid Data-in
Valid
Data-in
tRQD
VOH –
OUT V –
OL
VOH –
QSF V
OL –
Open
TAP MSB (A7)
Previous
Row Data
WM1 data: 0: Transfer Disable
1: Transfer Enable
New Row Data
"H" or "L"
29/45
¡ Semiconductor
MSM518122
Split Write Transfer Cycle
tRC
tRAS
RAS
tRP
tAR
VIH –
VIL –
tCSH
tCRP
CAS
tRSH
tRCD
VIH –
VIL –
tCPN
tCAS
tRAL
tRAD
,
,,
tASR
A0 - A8
WB/WE
VIH –
VIL –
tRAH
tASC
SAM Start
Address (n)
A0 - A6: TAP
Row Address
tWSR
tRWH
tTLS
tTLH
tCAH
VIH –
VIL –
VIH –
DT/OE V
IL –
tSTS
DSF
VIH –
VIL –
tRFH
tFSR
tMS
tMH
tOFF
W1/IO1 - VOH –
W8/IO8 VOL –
Open
WM1 Data
255
(127)
SC
tSTH
n
(n+128)
n+1
(n+129)
n+2
(n+130)
...............
125
(253)
126
(254)
n+128
(n)
VIH –
VIL –
SIO1 - VIH – 255
SIO8 VIL – (127)
n
(n+128)
n+1
(n+129)
n+2
(n+130)
...............
125
(253)
126
(254)
tSQD
QSF
127
(255)
127
(255)
n+128
(n)
tSQD
VOH –
VOL –
Lower SAM 0 - 127
Upper SAM 128 - 255
Note: SE = VIL
"H" or "L"
30/45
¡ Semiconductor
MSM518122
Serial Read Cycle (SE = VIL)
RAS
VIH –
VIL –
tTHS
DT/OE
tTHH
VIH –
VIL –
tSCC
tSCC
tSC
SC
tSCC
tSC
tSCC
tSC
tSCC
tSC
tSC
VIH –
VIL –
tSCP
tSCA
tSCP
tSOH
SIO1 - VOH –
SIO8 VOL –
Valid
Data-out
tSCP
tSCA
tSCP
tSCA
tSOH
tSOH
Valid
Data-out
tSCP
tSCA
tSOH
Valid
Data-out
tSCP
tSCA
tSOH
Valid
Data-out
Valid
Data-out
Valid
Data-out
Note: SE = VIL
"H" or "L"
Serial Read Cycle (SE Controlled Outputs)
RAS
VIH –
VIL –
tTHS
tTHH
VIH –
DT/OE V
IL –
tSCC
tSCC
tSC
SC
tSCC
tSC
tSCC
tSC
tSC
VIH –
VIL –
tSCP
SE
tSCC
tSC
tSCP
tSEP
tSCP
tSCP
tSCP
tSCP
VIH –
VIL –
tSZE
IN
VIH –
VIL –
SIO1 SIO8
VOH –
OUT
VOL –
tSEA
tSCA
tSOH
Valid
Data-out
tSEZ
Valid
Data-out
tSCA
Open
tSCA
tSOH
Valid
Data-out
tSCA
tSOH
Valid
Data-out
Valid
Data-out
"H" or "L"
31/45
¡ Semiconductor
MSM518122
Serial Write Cycle (SE = VIL)
RAS
VIH –
VIL –
tTHS
DT/OE
VIH –
VIL –
tSCC
tSCC
tSC
SC
tTHH
VIH –
VIL –
tSDH
tSDS
tSCC
tSC
tSDH
tSCP
SIO1 - VIH –
SIO8 VIL –
tSCC
tSC
tSCC
tSC
tSDH
tSC
tSDH
tSDH
tSCP
tSCP
tSCP
tSCP
tSDS
tSDS
tSDS
tSDS
Valid
Data-in
Valid
Data-in
Valid
Data-in
Valid
Data-in
tSCP
Valid
Data-in
Note: SE = VIL
"H" or "L"
Serial Write Cycle (SE Controlled Inputs)
RAS
VIH –
VIL –
tTHS
tTHH
VIH –
DT/OE V
IL –
tSCC
tSC
SC
VIH –
VIL –
tSCP
OUT
VOH –
VOL –
tSEP
tSWH
tSDS
VIH –
VIL –
tSC
tSCP
tSE
tSDH
Valid
Data-in
tSCC
tSC
tSC
tSCP
tSCP
tSWIH
tSWS
tSWH
tSWIS
tSDS
tSCC
tSCP
tSWIH
VIH –
VIL –
IN
tSCC
tSC
tSCP
tSWS
SE
tSCC
tSE
tSDH
Valid
Data-in
tSEP
tSWIS
tSDS
tSWS
tSWH
tSE
tSDH
Valid
Data-in
SIO1 SIO8
Open
"H" or "L"
32/45
¡ Semiconductor
MSM518122
PIN FUNCTION
Address Input : A0 - A8
The 17 address bits decode an 8-bit location of the 1,048,576 locations in the MSM518122
memory array. The address bits are multiplexed to 9 address input pins (A0 - A8) as standard
DRAM. 9 row address bits are latched at the falling edge of RAS. The following 8 column
address bits are latched at the falling edge of CAS.
Row Address Strobe : RAS
RAS is a basic RAM control signal. The RAM port is in standby mode when the RAS level is
“high”. As the standard DRAM’s RAS signal function, RAS is control input that latches the row
address bits and a random access cycle begins at the falling edge of RAS.
In addition to the conventional RAS signal function, the level of the input signals, CAS, DT/OE,
WB/WE, DSF and SE at the falling edge of RAS, determines the MSM518122 operation modes.
Column Address Strobe : CAS
As the standard DRAM’s CAS signal function, CAS is the control input signal that latches the
column address input and the state of the special function input DSF to select, in conjunction
with the RAS control, either read/write operations or the special block write feature on the
RAM port when the DSF is held “low” at the falling edge of RAS.
CAS also acts as a RAM port output enable signal.
Data Transfer/Output Enable : DT/OE
DT/OE is also a control input signal having multiple functions. As the standard DRAM’s OE
signal function, DT/OE is used as an output enable control when DT/OE is “high” at the falling
edge of RAS.
In addition to the conventional OE signal function, a data transfer operation is started between
the RAM port and the SAM port when DT/OE is “low” at the falling edge of RAS.
Write per Bit/Write Enable : WB/WE
WB/WE is a control input signal having multiple functions. As the standard DRAM’s WE
signal function, it is used to write data into the memory on the RAM port when WB/WE is
“high” at the falling edge of RAS.
In addition to the conventional WE signal function, the WB/WE determines the write-per-bit
function when WB/WE is “low” at the falling edge of RAS, during RAM port operations. The
WB/WE also determines the direction of data transfer between the RAM and SAM.
When WB/WE is “high” at the falling edge of RAS, the data is transferred from RAM to SAM
(read transfer). When WB/WE is “low” at the falling edge of RAS, the data is transferred SAM
to RAM (write transfer).
33/45
¡ Semiconductor
MSM518122
Write Mask Data/Data Input and Output : W1/IO1 - W8/IO8
W1/IO1 - W8/IO8 have the functions of both Input/Output and a control input signal. As the
standard DRAM’s I/O pins, input data on the W1/IO1 - W8/IO8 are written into the RAM port
during the write cycle. The input data is latched at the falling edge of either CAS or WB/WE,
whichever occurs later. The RAM data out buffers, which will output read data from the W1/
IO1 - W8/IO8 pins, becomes low impedance state after the specified access times from RAS,
CAS, DT/OE and column address are satisfied and the output data will remain valid as long
as CAS and DT/OE are kept “low”. The outputs will return to the high impedance state at the
rising edge of either CAS or DT/OE, whichever occurs earlier.
In addition to the conventional I/O function, the W1/IO1 - W8/IO8 have the function to set the
mask data, which select mask input pins out of four input pins, W1/IO1 - W8/IO8, at the falling
edge of RAS. Data is written to the DRAM on data lines where the Write-mask data is a logic
“1”. The write-mask data is valid for only one cycle.
Serial Clock : SC
SC is a main serial cycle control input signal. All operations of SAM port are synchronized with
the serial clock SC. Data is shifted in or out of the SAM registers at the rising edge of SC. In a
serial read, the output data becomes valid on the SIO pins after the maximum specified serial
access time tSCA from the rising edge of SC.
The SC also increments the 9 bits serial pointer which is used to select the SAM address. The
pointer address is incremented in a wrap-around mode to select sequential locations after the
setting location which is determined by the column address in the read transfer cycle. When the
pointer reaches the most significant address location (decimal 255), the next SC clock will place
it at the least significant address location (decimal 0).
The SC must be held data constant VIH or VIL level during read/pseudo write/write-transfer
operations and should not be clocked while the SAM port is the standby mode to prevent the
SAM pointer from being increment.
Serial Enable : SE
The SE is a serial access enable control and serial read/write control signal. In a serial read cycle,
SE is used as an output control. In a serial write cycle, SE is used as write enable control. When
SE is “high” , serial access is disable, however, the serial address pointer location is still
incremented when SC is clocked even when SE is “high”.
Special Function Input : DSF
The DSF is latched at the falling edge of RAS and CAS and allows for the selection of several
RAM port and transfer operating modes. In addition to the conventional multiport DRAM, the
special function consisting of flash write, block write, load/read resister and read/write
transfer can be invoked.
34/45
¡ Semiconductor
MSM518122
Special Function Output : QSF
QSF is an output signal which, during split resister mode, indicates which half of the split SAM
is being accessed. QSF “low” indicates that the lower split SAM (0 - 127) is being accessed. QSF
“high” indicates that the upper SAM (128 - 255) is being accessed.
QSF is monitored so that after it toggles and after allowing for a delay of tSTS, split read/write
transfer operation can be performed on the non-active SAM.
Serial Input/Output : SIO1 - SIO8
Serial input/output mode is determined by the most recent read, write or pseudo write transfer
cycle. When a read transfer cycle is performed, the SAM port is in the output mode. When a
write or pseudo write transfer cycle is performed, the SAM port is switched from output mode
to input mode.
35/45
¡ Semiconductor
MSM518122
OPERATION MODES
Table-1 shows the function truth table for a listing of all available RAM ports and transfer
operation of MSM518122.
The RAM port and data transfer operations are determined by the state of CAS, DT/OE, WB/
WE, SE and DSF at the falling edge of RAS and by the level of DSF at the falling edge of CAS.
Table-1. Function Truth Table
RASØ
W/IO
CASØ ADDRESS
Write Register
CAS DT/OE WB/WE DSF SE DSF RASØ CASØ RASØ CASØ CAS/WEØ Mask WM Color
0
*
*
*
*
—
*
—
*
—
—
—
1
0
0
0
0
* Row TAP WM1
*
*
WM1
1
0
0
0
1
* Row TAP
*
*
—
1
0
0
1
*
* Row TAP WM1
—
*
WM1
1
0
1
0
*
* Row TAP
*
*
*
—
1
0
1
1
*
* Row TAP
*
*
*
—
*
1
1
0
0
*
0 Row Column WM1
1
1
0
0
*
1 Row
1
1
0
1
*
* Row
1
1
1
0
*
0 Row Column *
1
1
1
0
*
1 Row
1
1
1
1
*
* Row
Column
A2c-7c
*
Column
A2c-7c
*
WM1
WM1
*
*
Function
—
C.B.R Refresh
—
Masked Write Transfer
—
Pseudo Write Transfer
—
Split Write Transfer
—
—
Read Transfer
—
—
Split Read Transfer
—
Write per Bit
Use
Masked Block Write
Use
Masked Flash Write
—
Load
Use
—
Load
Use
Load
Din
WM1
—
WM1
—
*
WM1
—
Din
—
—
—
Read Write
—
—
—
Use
Block Write
Color
—
—
Load Load Color Register
—
Column
Select
Column
Select
—
Use
Load
Use
Load
Use
If the DSF is 'high" at the falling edge of RAS, special functions such as split transfer, flash write,
and load/read color register can be invoked. If the DSF is "low" at the falling edge of RAS and
"high" at the falling edge of CAS, the block write feature can be invoked.
If the DSF is "low" at the falling edge of RAS and CAS, only the conventional multiport DRAM
operating feature can be invoked.
36/45
¡ Semiconductor
MSM518122
RAM PORT OPERATION
Fast Page Mode
Fast page mode allows data to be transferred into or out of multiple column locations of the
same row by performing multiple CAS cycle during a signal active for a period up to 100m
seconds. For the initial fast page mode access, the output data is valid after the specified access
times from RAS, CAS, column address and DT/OE.
For all subsequent fast page mode read operations, the output data is valid after the specified
access times from CAS, column address and DT/OE. When the write-per bit function is enable,
the mask data latched at the falling edge of RAS is maintained throughout the fast page mode
write or read or read modify write cycle.
RAS Only Refresh
The data in the DRAM requires periodic refreshing to prevent data loss. Refreshing is
accomplished by performing a memory cycle at each of the 512 rows in the DRAM array within
the specified 8ms refresh period.
Although any normal memory cycle will perform the refresh operation, this function is most
easily accomplished with “RAS-only” cycle.
CAS before RAS Refresh
The MSM518122 also offers an internal refresh function. When CAS is held “low” for a specified
period (tCSR) before RAS goes “low”, an internal refresh address counter and on-chip refresh control
clock generators are enable refresh operation take place.
When the refresh operation is completed, the internal refresh address counter is automatically
incremented in preparation for the next CAS before RAS cycle. For successive CAS before RAS
refresh cycle, CAS can remain “low” while cycling RAS.
Hidden Refresh
A hidden refresh is a CAS before RAS refresh performed by holding CAS “low” from a previous read
cycle. This allows for the output data from the previous memory cycle to remain valid while
performing a refresh.
The internal refresh address counter provides the address and the refresh is accomplished by cycling
RAS after the specified RAS precharge period.
Write per Bit Function
The write per bit selectively controls the internal write enable circuits of the RAM port. Write per bit
enabled when WB/WE held “low at the falling edge of RAS in a random write operation. Also, at
the falling edge of RAS, the mask data on the Wi/IOi pins are latched into a write mask register. The
write mask data must be presented at the Wi/IOi pins at every falling edge of RAS. A “0” on any of
the Wi/IOi pins will disable the corresponding write circuits and new data will not be written into
the RAM. A “1” on any of Wi/IOi pins will enable the corresponding write circuits and new data will
be written into the RAM.
37/45
¡ Semiconductor
MSM518122
Load / Read Color Register
The MSM518122 is provided with an on-chip 4 bits color register for use during the flash write
or block write operation. Each bit of the color register corresponds to one of the DRAM I/O
blocks.
The load color register cycle is initiated by holding CAS, WB/WE, DT/OE and DSF “high” at
the falling edge of RAS. The data presented on the Wi/IOi lines is subsequently latched into the
color register at the falling edge of either CAS or WB/WE whichever occurs later.
The read color register cycle is activated by holding CAS, WB/WE, DT/OE and DSF “high” at
the falling edge of RAS and by holding WB/WE “high” at the falling edge of CAS and
throughout the remainder of the cycle. The data in the color register becomes valid on the Wi/
IOi lines after the specified access times from RAS and DT/OE are satisfied.
During the load/read color register cycle, the memory cells on the row address latched at the
falling edge of RAS are refreshed.
Flash Write
Flash write allows for the data in the color register to be written into all the memory locations
of a selected row.
Each bit of the color register corresponds to the DRAM I/O blocks and the flash write operation
can be selectively controlled on an I/O basis in the same manner as the write per bit operation.
A flash write cycle is performed by holding CAS “high” WB/WE “low” and DSF “high” at the
falling edge of RAS. The mask data must also be provided on the Wi/IOi lines at the falling edge
of RAS in order to enable the flash write operation for selected I/O blocks.
Block Write
Block write allows for the data in the color register to be written into 4 consecutive column
address locations starting from a selected row. The block write operation can be selectively
controlled on an I/O basis and a column mask capability is also available.
Block write cycle is performed by holding CAS, DT/OE “high” and DSF “low” at the falling
edge of RAS and by holding DSF “high” at the falling edge of CAS. The state of the WB/WE
input at the falling edge of RAS determines whether or not the I/O data mask is enabled (WB/
WE must be “low” to enable the I/O data mask or “high” to disable mask). At the falling edge
of RAS, a valid row address and I/O mask data are also specified. At the falling edge of CAS,
the starting column address location and column address data mast be provided. During a
block write cycle, the 2 least significant column address locations (A0C, A1C) are internally
controlled and only the 6 most significant column addresses (A2C - A7C) are latched at the
falling edge of CAS.
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¡ Semiconductor
MSM518122
SAM PORT OPERATION
Single Register Mode
High speed serial read or write operation can be reformed through the SAM port independent
of the RAM port operation, except during read/write transfer cycles. The preceding transfer
operation determines the direction of data flow through the SAM port. If the preceding transfer
is a read transfer, the SAM port is in the output mode. If the preceding transfer is write or pseudo
write transfer, the SAM port is in the input mode. The pseudo write transfer only switches the
SAM port from output mode into mode (Data is not transferred from SAM port to RAM port).
Serial data can be read out of the SAM after a read transfer has been performed. The data is
shifted out to the SAM starting at any of the 256 bits locations.
The TAP location corresponds to the column address selected at the falling edge of CAS during
the read or write transfer cycle. The SAM registers are configured as circular data register. The
data is shifted out sequentially starting from the selected TAP location to the most significant
bit (255) and then wraps around to the least significant bit (0).
Split Register Mode
In split register mode, data can be shifted into or out of one half of the SAM while a split read
or split write transfer is being performed on the other half of the SAM.
Conventional (non split) read, write, or pseudo write transfer cycle must precede any split read
or split write transfers. The split read and write transfers will not change the SAM port mode
set by preceding conventional transfer operation. In the split register mode, serial data can be
shifted in or out of the split SAM registers starting from any at the 128 TAP locations, excluding
the last address of each split SAM, data is shifted in or out sequentially starting from the selected
TAP location to the most significant bit (127 or 255) of the first split SAM and, then the SAM
pointer moves to the TAP location selected for the second split SAM to shift data in or out
sequentially starting from this TAP location to the most significant bit (255 or 127) and finally
wraps around to the least significant bit.
TAP
0
1
2
TAP
127
128 129
255
39/45
¡ Semiconductor
MSM518122
DATA TRANSFER OPERATION
The MSM518122 features two types of bidirectional data transfer capability between RAM and
SAM, as shown in Figure 1 below.
1) Conventional (non split) transfer :256 words by 8 bits of data can be loaded from RAM to
SAM (Read transfer) or from SAM to RAM (Write transfer).
2) Split transfer : 128 words by 8 bits of data can be loaded from the lower/upper half of the
RAM to the lower/upper half of the SAM (Split read transfer) or from the lower/upper half
of SAM to the lower/upper half of RAM (Split write transfer).
The conventional transfer and split transfer modes are controlled by the DSF input signal.
512 ¥ 256 ¥ 8
512 ¥ 128 ¥ 8
512 ¥ 128 ¥ 8
Memory
Memory
Memory
Array
Array
Array
256 ¥ 8
128 ¥ 8
128 ¥ 8
1) Conventional Transfer
2) Split Transfer
Figure 1.
The MSM518122 supports five types of transfer operation : Read transfer , Split read transfer,
Write transfer, Pseudo write transfer and Split write transfer as shown in truth table. Data
transfer are invoked by holding the DT/OE signal “low” at the falling edge of RAS. The type
of transfer operation is determined by the state of CAS, WB/WE, SE and DSF latched at the
falling edge of RAS. During conventional transfer operations, the SAM port is switched from
input to output mode (Read transfer) or output to input mode (Write/Pseudo write transfer)
Whereas it remains unchanged during split transfer operation (Split read transfer or Split write
transfer).
40/45
¡ Semiconductor
MSM518122
Read Transfer Operation
Read transfer consists of loading a selected row of data from the RAM into the SAM register.
A read transfer is invoked by holding CAS “high”, DT/OE “low”, WB/WE “high” and DSF
“low” at the falling edge of RAS. The row address selected at the falling edge of RAS determines
the RAM row to be transferred into the SAM. The transfer cycle is completed at the rising edge
of DT/OE. When the transfer is completed, the SAM port is set into the output mode. In a read/
real time read transfer cycle, the transfer of a new row of data is completed at the rising edge
of DT/OE and this data becomes valid on the SIO lines after the specified access time tSCA from
the rising edge of the subsequent SC cycles. The start address of the serial pointer of the SAM
is determined by the column address selected at the falling edge of CAS. In a read transfer cycle
(which is preceded by a write transfer cycle), SC clock must be held at a constant VIL or VIH, after
the SC high time has been satisfied. A rising edge of the SC clock must not occur until after the
specified delay tTSD from the rising edge of DT/OE.
In a real time read transfer cycle (which is preceded by another read transfer cycle), the previous
row data appears on the SIO lines until the DT/OE signal goes “high” and the serial access time
tSCA from the following serial clock is satisfied. This feature allows for the first bit of the new
row of data to appear on the serial output as soon as the last bit of the previous row has been
strobed without any timing loss. To make this continuous data flow possible, the rising edge
of DT/OE must be synchronized with RAS, CAS and the subsequent rising edge of SC (tRTH,
tCTH and tTSL/tTSD must be satisfied).
Write Transfer Operation
Write transfer cycle consists of loading the content of the SAM register into a selected row of the
RAM. If the SAM data to be transferred must first be loaded through the SAM, a pseudo write
transfer operation must precede the write transfer cycles. A write transfer is invoked by holding
CAS “high”, DT/OE “low”, WB/WE “low”, SE “low” at the falling edge of RAS. This write
transfer is selectively controlled per RAM I/O block by setting the mask data on the Wi/IOi
lines at the falling edge of RAS. The row address selected at the falling edge of RAS determines
the RAM row address into which the data will be transferred. The column address selected at
the falling edge of CAS determines the start address of the serial pointer of the SAM. After the
write transfer is completed, the SIO lines are set in the input mode so that serial data
synchronized with the SC clock can be loaded. When consecutive write transfer operation are
performed, new data must not be written into the serial register until the RAS cycle of the
preceding write transfer is completed. Consequently, the SC clock must be held at a constant
VIL or VIH during the RAS cycle. A rising edge of the SC clock is only allowed after the specified
delay tSRD from rising edge of the RAS, at which time a new row of data can be written in the
serial register.
Data transferred to SAM by read transfer cycle or split read transfer cycle can be written to other
address of RAM by write transfer cycle, however, the address to write data must be the same
as that of the read transfer cycle or the split read transfer cycle (row address AX8).
41/45
¡ Semiconductor
MSM518122
Pseudo Write Transfer Operation
Pseudo write transfer cycle must be performed before loading data into the serial register after
a read transfer operation has been excuted. The only purpose of a pseudo write transfer is to
change the SAM port mode from output mode to input mode (A data transfer from SAM to
RAM does not occur). After the serial register is loaded with new data, a write transfer cycle
must be performed to transfer the data from SAM to RAM. A pseudo write transfer is invoked
by holding CAS “high”, DT/OE “low”, WB/WE “low”, SE “high” and DSF “low” at the falling
edge of RAS. The timing conditions are the same as the one for the write transfer cycle except
for the state of SE at the falling edge of RAS.
Split Data Transfer and QSF
The MSM518122 features a bidirectional split data transfer capability between the RAM and
SAM. During split data transfer operation, the serial register is split into two halves which can
be controlled independently. Split read or write transfer operation can be performed to or from
one half of the serial register while serial data can be shifted into or out of the other half of the
register. The most significant column address location (A7C) is controlled internally to
determine which half of the serial register will be reloaded from the RAM. QSF is an output in
which indicates which half of the serial resister is in an active state. QSF changes state when the
last SC clock is applied to active split SAM.
Split Read Transfer Operation
Split read transfer consists of loading 128 words by 8 bits of data from a selected row of the split
RAM into the corresponding non-active split SAM register. Serial data can be shifted out from
of the other half of the split SAM register simultaneously. During split read transfer operation,
the RAM port input clocks do not have to be synchronized with the serial clock SC, thus
eliminating timing restrictions as in the case of real time read transfers. A split read transfer can
be performed after a delay of tSTS, from the change of state of the QSF output, is satisfied.
Conventional (non-split) read transfer operation must precede split read transfer cycles.
Split Write Transfer Operation
Split write transfer consists of loading 128 words by 8 bits of data from the non-active split SAM
register into a selected row of the corresponding split RAM. Serial data can be shifted into the
other half of the split SAM register simultaneously. During split write transfer operation, the
RAM port input clocks do not have to be synchronized with the serial clock SC, thus allowing
for real time transfer. A split write transfer can be performed after a delay of tSTS, from the
change of state of the QSF output, is satisfied.
A pseudo write transfer operation must precede split write transfer. The purpose of the pseudo
write transfer operation is to switch the SAM port from output mode to input mode and to set
the initial TAP location prior to split write transfer operations.
Transfer Operation Without CAS
During all transfer cycles, the CAS clock must be cycled, so that the column addresses are
latched at the falling edge of CAS, to set the SAM TAP location.
42/45
¡ Semiconductor
MSM518122
TAP Location In Split Transfer
1) In a split transfer operation, column address A0C through A6C must be latched at the falling
edge of CAS in order to set the TAP location in one of the split SAM registers. During a split
transfer, column address A7C is controlled internally and therefore it is ignored internally
at the falling edge of CAS. During a split transfer, it is not permissible to set the last address
location (A0C - A6C = 7F), in either the lower SAM or the Upper SAM, as the TAP location.
POWER-UP
Power must be applied to the RAS and DT/OE input signals to pull them “high” before or at
the same time as the VCC supply is turned on. After power-up, a pause of 200 ms minimum is
required with RAS and DT/OE held “high”. After the pause, a minimum of 8 RAS and SC
dummy cycles must be performed to stabilize the internal circuitry, before valid read, write or
transfer operations can begin. During the initialization period, the DT/OE signal must be held
“high”. If the internal refresh counter is used, a minimum 8 CAS before RAS cycles are required
instead of 8 RAS cycles.
43/45
¡ Semiconductor
MSM518122
PACKAGE DIMENSIONS
(Unit : mm)
ZIP40-P-475-1.27
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
3.46 TYP.
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¡ Semiconductor
MSM518122
(Unit : mm)
SOJ40-P-400-1.27
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
1.70 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
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