LH1694 256-output TFT-LCD Gate Driver IC LH1694 DESCRIPTION PIN CONNECTIONS The LH1694 is a 256-output TFT-LCD gate driver IC. TOP VIEW 277-PIN TCP 1 OG1 2 OG2 3 OG3 • Number of LCD drive outputs : 256 • LCD drive output sequence : Output shift direction can be selected OG1/OG256 or OG256/OG1 • Enable chain connection • Usable with both positive/negative power supplies • Output signal masking function • Input signal voltage : +2.7 to +3.6 V • LCD drive voltage : +16.0 to +42.0 V • Operating temperature : –30 to +85 ˚C • Package : 277-pin TCP (Tape Carrier Package) VDD VEE VSS VCC VLS GND SVIO R/L CKV OE1 OE2 OE3 SVOI GND TEST2 TEST1 VLS VCC VSS VEE VDD 277 276 275 274 273 272 271 270 269 268 267 266 265 264 263 262 261 260 259 258 257 CHIP SURFACE FEATURES 254 OG254 255 OG255 256 OG256 NOTE : Doesn't prescribe TCP outline. In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device. 1 LH1694 PIN DESCRIPTION PIN NO. 1 to 256 SYMBOL OG1-OG256 I/O O DESCRIPTION 257, 277 VDD – Power supply pins for LCD drive 258, 276 VEE – Power supply pins for LCD drive 259, 275 VSS – Power supply pins for logic system 260, 274 VCC – Power supply pins for logic system 261, 273 VLS – Power supply pins for logic input/output systems 264, 272 GND – Ground pins for logic input 262, 263 TEST1, TEST2 I 265 266 to 268 SVOI OE3-OE1 I/O I Input pins for output enable 269 270 CKV R/L I I Vertical shift clock input pin Pin for selecting bi-directional shift register and setting cascade sequence 271 SVIO I/O LCD drive output pins IC test pins Vertical scanning start pulse input/output pin Vertical scanning start pulse input/output pin BLOCK DIAGRAM TEST1 262 BI-DIRECTIONAL SHIFT REGISTER TEST2 263 SVOI 265 1 256 OE3 266 CONTROL LOGIC OE2 267 LEVEL SHIFTER OE1 268 1 256 CKV 269 R/L 270 OUTPUT CIRCUIT SVIO 271 1 256 257 277 261 273 264 272 260 274 258 276 259 275 1 256 VLS VLS GND GND VCC VCC VEE VEE OG1 OG256 VDD VDD 2 VSS VSS LH1694 FUNCTIONAL OPERATIONS OF EACH BLOCK BLOCK FUNCTION Used to create signals necessary for mode selecting signal, cascade sequence setting Control Logic Bi-directional Shift signal and for operation of bi-directional shift register. Used as transfer circuit of LCD drive output start signal. It is possible to set LCD drive output sequence of OG1/OG256 direction or OG256/OG1 direction. Used as circuit which shifts LCD drive output signals transferred by bi-directional shift Register Level Shifter , register to VDD-VEE level. Configured with output buffers to output VDD-VEE level. Output Circuit INPUT/OUTPUT CIRCUITS VLS I To Internal Circuit Level Shifter Internal Logic (VLS-GND/VCC-VSS) (VCC-VSS) VSS ¿Applicable pins¡ CKV, R/L, OE1-OE3, TEST1, TEST2 Fig. 1 Input Circuit VLS I Output Signal O VSS VLS Level Shifter (VLS-GND/VCC-VSS) VSS Output Control Signal (VLS-GND) Fig. 2 Input/Output Circuit 3 To Internal Circuit ¿Applicable pins¡ SVIO, SVOI LH1694 VDD O From Internal Circuit (VDD-VEE) ¿Applicable pins¡ OG1-OG256 VEE Fig. 3 Output Circuit FUNCTIONAL DESCRIPTION Pin Functions SYMBOL VDD VLS FUNCTION Used as power supply pin for high level LCD drive. Used as power supply pin for input level shifters. GND Used as power supply pin for input level shifters. VCC Used as power supply pin for logic system, normally connected to VSS + 5.0 V. VEE Used as power supply pin for low level LCD drive. VSS Used as logic system power supply pin. Used as vertical shift clock pulse input pin. CKV Used as vertical scanning start pulse input/output pins. SVIO SVOI Data input/output pins for shift register. During input, data is read at the rising edge of the CKV. During output, data is output at the falling edge of the CKV. • When R/L = "H". SVOI is set to data output pin for next cascade, and SVIO is set to input pin for shift data. • When R/L = "L". SVOI is set to input pin for shift data, and SVIO is set to data output pin for next cascade. Used as input pin for selecting the shift direction of bi-directional shift register and for R/L setting the sequence of cascade connection. LCD drive outputs shift from OG1 to OG256 when set to "H". LCD drive outputs shift from OG256 to OG1 when set to "L". OE1 OE2 OE3 Input pins for output-enable. LCD drive output is set to "L", when OE1, OE2, and OE3 pins are set to "H", and it has no relation with clock input. Relationship between enable control and output pins; OE1 : OG1, OG4 π OG250, OG253, OG256 OE2 : OG2, OG5 π OG251, OG254 OE3 : OG3, OG6 π OG252, OG255 TEST1 Used as input pins for IC testing. TEST2 Must be set to "H". Used as output pins for LCD drive output, and which output data at 2 levels. OG1-OG256 • Selecting data is output at VDD level . • Non-selecting data is output at VEE level . 4 LH1694 Functional Operations cycle of shift clock. Next LCD drive output pins from OG2 to OG256 are sequentially shifted at the rising edge of the CKV for one cycle. Shift signal of OG256 is read at the falling edge of the clock signal, and the input data for the next cascade is output from the SVOI pin. While R/L = "L" input data from SVOI is read at the rising edge of shift clock (CKV), and outputs to LCD drive output pin OG256 at the width for one cycle of shift clock. Next LCD drive output pins from OG255 to OG1 are sequentially shifted at the rising edge of the CKV for one cycle. Shift signal of OG1 is read at the falling edge of the clock signal and the input data for the next cascade is output from the SVIO pin. LH1694 can select the LCD drive output level (OG1 to OG256) by the set of the input signal (CKV, SVIO, SVOI, OE1, OE2, OE3). When the pin for selecting the bi-directional shift register (R/L) is set to "H", LCD drive outputs shift from OG1 to OG256, and when set to "L", LCD drive outputs shift from OG256 to OG1. OE1,OE2 and OE3 are signals for output-enable. Output pins output non-selecting data (VEE level) when OE1 to OE3 pins are set to "H" and it has no relation with input clock. While R/L = "H" input data from SVIO is read at the rising edge of shift clock (CKV), and outputs to LCD drive output pin OG1 at the width for one Example of Input/Output Timing (R/L = "H") 1 2 3 4 5 6 CKV SVIO (Input) OE1 OE2 OE3 OG1 OG2 OG3 OG4 OG5 OG6 • • • • • OG256 SVIO (Output) 5 7 255 256 257 258 LH1694 PRECAUTIONS Logic system power supply (VLS), internal logic system power supply (VSS, VCC; VCC > VSS) and low-level LCD drive power supply (VEE) / logic input / high-level LCD drive power supply (VDD) Precautions when connecting or disconnecting the power supply This IC has a high-voltage LCD driver, so it may be permanently damaged by a high current which may flow if voltage is supplied to the LCD drive power supply while the logic system power supply is floating. Therefore, when connecting the power supply, observe the following sequence. When disconnecting the power supply, follow the reverse sequence. Since the logic state of the internal circuit is unstable immediately after the logic system power is supplied, input CKV and SVIO (or SVOI) while initializing the internal circuit (minimum input clock number is 256 CKV). Logic system power supply (VLS) or internal logic system power supply (VSS, VCC; VCC > VSS) / logic input / LCD drive power supply (VEE, VDD) It is possible to set voltage VEE to the same as VSS. When connecting the power supply when VEE = VSS, observe the following sequence and the recommended sequence figure shown below. VDD VLS Input 0V VCC VSS, VEE Maximum ratings When connecting or disconnecting the power, this IC must be used within the range of the absolute maximum ratings. Input pin setting Input pins other than CKV, SVIO and SVOI must be set to "H" or "L" level. 6 LH1694 ABSOLUTE MAXIMUM RATINGS PARAMETER Supply voltage SYMBOL VDD APPLICABLE PINS VDD RATING –0.3 to +45.0 UNIT V VLS VLS –0.3 to +7.0 V VCC – VSS VCC, VSS –0.3 to +7.0 V VEE – VSS VEE, VSS –0.3 to +45.0 V VDD, VEE, VSS –0.3 to +45.0 V –0.3 to VLS + 0.3 V –45 to +125 ˚C VDD – VEE (VSS) Input voltage VIN Storage temperature CKV, SVIO, SVOI, R/L, OE1-OE3, TEST1, TEST2 TSTG NOTES : 1. TA = +25 ˚C 2. The maximum applicable voltage on any pin with respect to 0 V. RECOMMENDED OPERATING CONDITIONS PARAMETER Supply voltage SYMBOL VDD VLS MIN. +5.5 +2.7 VSS –20.0 Operating temperature MAX. +35.0 UNIT V +3.3 +3.6 V VCC VSS + 4.5 VEE – VSS 0 VDD – VEE +16.0 (VSS) Input voltage TYP. +25.0 –5.0 V VSS + 5.5 +11.0 V V +42.0 V VIN 0 VLS V TOPR –30 +85 ˚C NOTE 1 NOTE : 1. The applicable voltage on any pin with respect to 0 V. Each power supply pin of LH1694 is set as shown below. LCD Drive Output VDD VLS Input SVIO/SVOI Output GND VCC Internal Logic VSS, VEE 7 NOTE 1, 2 LH1694 ELECTRICAL CHARACTERISTICS DC Characteristics (VLS = +2.7 to +3.6 V, VEE = VSS, TOPR = –30 to +85 ˚C) PARAMETER SYMBOL CONDITIONS APPLICABLE PINS VLS = 2.7 to 3.0 V Input "Low" voltage VIL VLS = 3.0 to 3.6 V CKV, SVIO, SVOI, VLS = 2.7 to 3.0 V OE1-OE3, R/L Input "High" voltage VIH VLS = 3.0 to 3.6 V Output "Low" voltage VOL IOL = 0.4 mA OG1-OG256 Output "High" voltage VOH IOH = –0.4 mA Input "Low" current Input "High" current MIN. TYP. UNIT V 0.3VLS V 0.8VLS VEE + 0.4 V V 5.0 5.0 µA µA ILS 100 1.5 µA mA ICC 100 µA IEE 100 µA IIL IIH VI = 0 V VI = VLS VDD – 0.4 V CKV, SVIO, SVOI, OE1-OE3, R/L NOTES : 1. All input pins : 3.3 V 2. CKV : Frequency = 31 kHz, "L" period width tWL = 16.2 µs SVIO : Frequency = 60 Hz OE1 to OE3 : 0 V Other input pins : 3.3 V All output pins are opened. AC Characteristics PARAMETER Clock frequency "H" clock pulse width tCLVH "L" clock pulse width Clock rise time tCKVL tRCKV Clock fall time tFCKV Data setup time tSU Data hold time tH Pulse rise time tRSPV Pulse fall time tFSPV OE enable time Output transfer delay tOEW time 1 Output rise time Output fall time (VLS = +2.7 to +3.6 V, VEE = VSS, TOPR = –30 to +85 ˚C) SYMBOL CONDITIONS fCKV APPLICABLE PINS CKV Output transfer delay time 2 tDOE Output transfer delay time 3 tDSV TYP. MAX. 100 µs 1.0 µs ns 100 CKV, SVIO, SVOI 100 300 CL = 300 pF CL = 50 pF OG1-OG256 SVIO, SVOI 8 ns ns ns 100 100 SVIO, SVOI OE1-OE3 UNIT kHz 1.0 100 tDO tR tF MIN. NOTE V 0.7VLS IDD Supply current MAX. 0.2VLS 1.0 ns ns µs 1.0 µs 1.0 1.0 µs µs 1.0 µs 1.0 µs 1 2 LH1694 Timing Chart tCKVL tCKVH CKV 50% 50% 50% tRCKV 90% 90% 50% 10% tSU SVIO tFCKV fCKV 90% 50% 10% 50% 10% tH 90% 50% 10% tFSPV tRSPV tDO tDO VDD 50% OG1 50% VEE tDO tDO VDD 50% OG2-OG256 50% VEE 50% CKV 50% tR tF VDD 90% 90% OG256 10% 10% VEE tDSV tDSV 50% SVIO 50% tOEW OE1-OE3 50% 50% tDOE tDOE VDD OG1-OG256 50% 50% VEE 9 VSS VDD VEE SVOI OE3 TEST2 GND VLS (TEST1) VCC VDD GND 2.0 (SL) [4.0 (E.L.)] 4.2 (SR) 4.5 (SL) 5.0 (SL) 8.5 (SL) [8.0] 3.4 (SR) 3.5 (SL) 7.0±0.7 [7.0 (E.L.)] [13.9 (E.L.)] 5.4±0.05 [6.9 (E.L.)] 7.6 (SR) UPILEX is a trademark of UBE INDUSTRIES, LTD.. 10 COM2 COM1 COM1 OG254 OG255 OG256 DUMMY COM2 COM1 COM1 0.60±0.02 0.40±0.02 UPILEX S75 E type VLP 25 µm Epoxy resin 5.4MAX. (Resin area) Substrate Adhesive Cu foil [thickness] Solder resist ø Tape Material COM4 48 mm Super wide 4 pitches COM3 [34.0 (E.L.)] [35.8] 16.4 (SR) COM4 P0.12 x (264 – 1) = 31.56±0.05 W0.060±0.02 32.6±0.05 (Mark) 20.4 MAX. (Resin area) 0.40±0.02 16.8 (SL) COM4 COM4 COM3 DUMMY OG1 OG2 OG3 Tape width Tape type Perforation pitch R/L P1.00 x (26 – 1) = 25.0±0.04 W0.40±0.02 SVIO 2-Ø1.9 (PI) 2-Ø2.7 (Cu) 2-Ø1.5 (Cu hole) 2-R1.05 (SR) 1.42±0.05 0.9 (SL) 0.2MAX. Pattern side 4.75±0.05 ø Tape Specification OE2 13.85 (SR) VLS 16.4 (SR) OE1 [30.0 (E.L.)] 29.8±0.05(Holes) 28.0 (SL) VCC 13.85 (SR) CKV 48.175±0.2 44.86 1.42±0.05 0.60±0.02 0.40±0.02 0.9 (SL) Device center VSS 18.0±0.7 16.8 (SL) Film center VEE Ø2.0 (Good device hole) LH1694F 1.1MAX. Total 0.75MAX. Backside Chip center Sprocket center PACKAGES FOR LCD DRIVERS PACKAGE (Unit : mm) 1.5±0.05(Hole) [3.5TYP. (3.2MIN.)] [0.5]