ADC08200 8-Bit, 20 MSPS to 200 MSPS, 1.05 mW/MSPS A/D Converter General Description Key Specifications The ADC08200 is a low-power, 8-bit, monolithic analog-todigital converter with an on-chip track-and-hold circuit. Optimized for low cost, low power, small size and ease of use, this product operates at conversion rates up to 230 MSPS while consuming just 1.05 mW per MHz of clock frequency, or 210 mW at 200 MSPS. Raising the PD pin puts the ADC08200 into a Power Down mode where it consumes 1 mW. The unique architecture achieves 7.3 Effective Bits with 50 MHz input frequency. The ADC08200 is resistant to latch-up and the outputs are short-circuit proof. The top and bottom of the ADC08200’s reference ladder are available for connections, enabling a wide range of input possibilities. The digital outputs are TTL/CMOS compatible with a separate output power supply pin to support interfacing with 3V or 2.5V logic. The digital inputs (CLK and PD) are TTL/CMOS compatible. The ADC08200 is offered in a 24-lead plastic package (TSSOP) and is specified over the industrial temperature range of −40˚C to +85˚C. Features n n n n n Single-ended input Internal sample-and-hold function Low voltage (single +3V) operation Small package Power-down feature j Resolution: j Maximum sampling frequency: 8 bits 200 MSPS (min) ± 0.4 LSB (typ) j DNL: j ENOB (fIN = 50 MHz): 7.3 bits (typ) j THD (fIN = 50 MHz): −61 dB (typ) j No missing codes Guaranteed j Power Consumption Operating Power down 1.05 mW/MSPS (typ) 1 mW (typ) Applications n n n n n n n n n Flat panel displays Projection systems Set-top boxes Battery-powered instruments Communications Medical scan converters X-ray imaging High speed viterbi decoders Astronomy Pin Configuration 20017901 © 2002 National Semiconductor Corporation DS200179 www.national.com ADC08200 8-Bit, 20 MSPS to 200 MSPS, 1.05 mW/MSPS A/D Converter November 2002 ADC08200 Ordering Information ADC08200CIMT TSSOP ADC08200CIMTX TSSOP (tape and reel) Block Diagram 20017902 Pin Descriptions and Equivalent Circuits Pin No. Symbol 6 VIN Analog signal input. Conversion range is VRB to VRT. 3 VRT Analog Input that is the high (top) side of the reference ladder of the ADC. Nominal range is 0.5V to VA. Voltage on VRT and VRB inputs define the VIN conversion range. Bypass well. See Section 2.0 for more information. 9 VRM Mid-point of the reference ladder. This pin should be bypassed to a quiet point in the analog ground plane with a 0.1 µF capacitor. VRB Analog Input that is the low side (bottom) of the reference ladder of the ADC. Nominal range is 0.0V to (VRT – 0.5V). Voltage on VRT and VRB inputs define the VIN conversion range. Bypass well. See Section 2.0 for more information. 10 www.national.com Equivalent Circuit Description 2 Equivalent Circuit ADC08200 Pin Descriptions and Equivalent Circuits (Continued) Pin No. Symbol Description 23 PD Power Down input. When this pin is high, the converter is in the Power Down mode and the data output pins hold the last conversion result. 24 CLK CMOS/TTL compatible digital clock Input. VIN is sampled on the rising edge of CLK input. 13 thru 16 and 19 thru 22 D0–D7 Conversion data digital Output pins. D0 is the LSB, D7 is the MSB. Valid data is output just after the rising edge of the CLK input. 7 VIN GND Reference ground for the single-ended analog input, VIN. 1, 4, 12 VA Positive analog supply pin. Connect to a quiet voltage source of +3V. VA should be bypassed with a 0.1 µF ceramic chip capacitor for each pin, plus one 10 µF capacitor. See Section 3.0 for more information. 18 VDR Power supply for the output drivers. If connected to VA, decouple well from VA. 17 DR GND 2, 5, 8, 11 AGND The ground return for the output driver supply. The ground return for the analog supply. 3 www.national.com ADC08200 Absolute Maximum Ratings (Notes 1, Soldering Temperature, Infrared, 10 seconds (Note 6) 2) Storage Temperature If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VA) −0.3V to VA Reference Voltage (VRT, VRB) VA to AGND CLK, PD Voltage Range −0.05V to (VA + 0.05V) Package Input Current (Note 3) ± 25 mA ± 50 mA Power Dissipation at TA = 25˚C See (Note 4) Input Current at Any Pin (Note 3) ESD Susceptibility (Note 5) Human Body Model Machine Model −40˚C ≤ TA ≤ +85˚C Operating Temperature Range VA +0.3V Voltage on Any Input or Output Pin −65˚C to +150˚C Operating Ratings (Notes 1, 2) 3.8V Driver Supply Voltage (VDR) 235˚C Supply Voltage (VA) +2.7V to +3.6V Driver Supply Voltage (VDR) +2.4V to VA Ground Difference |GND - DR GND| 0V to 300 mV Upper Reference Voltage (VRT) 0.5V to (VA −0.3V) Lower Reference Voltage (VRB) 0V to (VRT −0.5V) VIN Voltage Range VRB to VRT 2500V 200V Converter Electrical Characteristics The following specifications apply for VA = VDR = +3.0VDC, VRT = +1.9V, VRB = 0.3V, CL = 5 pF, fCLK = 200 MHz at 50% duty cycle. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C (Notes 7, 8) Symbol Parameter Conditions Typical (Note 9) Limits (Note 9) Units (Limits) DC ACCURACY INL Integral Non-Linearity +1.0 −0.3 +1.9 −1.2 LSB (max) LSB (min) DNL Differential Non-Linearity ± 0.4 ± 0.95 LSB (max) 0 (max) FSE Full Scale Error 36 50 mV (max) VOFF Zero Scale Offset Error 46 60 mV (max) Missing Codes ANALOG INPUT AND REFERENCE CHARACTERISTICS VRB V (min) VRT V (max) VIN Input Voltage CIN VIN Input Capacitance 4 pF RIN RIN Input Resistance >1 MΩ BW Full Power Bandwidth 500 VRT 1.6 VIN = 0.75V +0.5 Vrms (CLK LOW) (CLK HIGH) Top Reference Voltage VRB Bottom Reference Voltage RREF Reference Ladder Resistance 3 1.9 0.3 VRT to VRB 160 pF MHz VA V (max) 0.5 V (min) VRT − 0.5 V (max) 0 V (min) 120 Ω (min) 200 Ω (max) 2.0 V (min) 0.8 V (max) CLK, PD DIGITAL INPUT CHARACTERISTICS VIH Logical High Input Voltage VDR = VA = 3.6V VIL Logical Low Input Voltage VDR = VA = 2.7V IIH Logical High Input Current VIH = VDR = VA = 3.6V 10 nA IIL Logical Low Input Current VIL = 0V, VDR = VA = 2.7V −50 nA CIN Logic Input Capacitance 3 pF DIGITAL OUTPUT CHARACTERISTICS VOH High Level Output Voltage VA = VDR = 2.7V, IOH = −400 µA 2.6 2.4 V (min) VOL Low Level Output Voltage VA = VDR = 2.7V, IOL = 1.0 mA 0.4 0.5 V (max) www.national.com 4 (Continued) The following specifications apply for VA = VDR = +3.0VDC, VRT = +1.9V, VRB = 0.3V, CL = 5 pF, fCLK = 200 MHz at 50% duty cycle. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C (Notes 7, 8) Symbol Parameter Conditions Typical (Note 9) Limits (Note 9) Units (Limits) DYNAMIC PERFORMANCE ENOB SINAD SNR SFDR THD HD2 HD3 IMD Effective Number of Bits Signal-to-Noise & Distortion Signal-to-Noise Ratio Spurious Free Dynamic Range Total Harmonic Distortion 2nd Harmonic Distortion 3rd Harmonic Distortion Intermodulation Distortion fIN = 4 MHz, VIN = FS − 0.25 dB 7.5 Bits fIN = 20 MHz, VIN = FS − 0.25 dB 7.4 Bits fIN = 50 MHz, VIN = FS − 0.25 dB 7.3 fIN = 70 MHz, VIN = FS − 0.25 dB 7.2 Bits fIN = 100 MHz, VIN = FS − 0.25 dB 7.0 Bits dB fIN = 4 MHz, VIN = FS − 0.25 dB 47 fIN = 20 MHz, VIN = FS − 0.25 dB 46 fIN = 50 MHz, VIN = FS − 0.25 dB 46 fIN = 70 MHz, VIN = FS − 0.25 dB 45 6.9 Bits (min) dB 43.3 dB (min) dB fIN = 100 MHz, VIN = FS − 0.25 dB 44 dB fIN = 4 MHz, VIN = FS − 0.25 dB 47 dB fIN = 20 MHz, VIN = FS − 0.25 dB 46 dB fIN = 50 MHz, VIN = FS − 0.25 dB 46 fIN = 70 MHz, VIN = FS − 0.25 dB 45 fIN = 100 MHz, VIN = FS − 0.25 dB 44 dB fIN = 4 MHz, VIN = FS − 0.25 dB 60 dBc fIN = 20 MHz, VIN = FS − 0.25 dB 58 dBc fIN = 50 MHz, VIN = FS − 0.25 dB 60 dBc fIN = 70 MHz, VIN = FS − 0.25 dB 57 dBc 43.4 dB (min) dB fIN = 100 MHz, VIN = FS − 0.25 dB 54 dBc fIN = 4 MHz, VIN = FS − 0.25 dB −60 dBc fIN = 20 MHz, VIN = FS − 0.25 dB −58 dBc fIN = 50 MHz, VIN = FS − 0.25 dB −60 dBc fIN = 70 MHz, VIN = FS − 0.25 dB -56 dBc fIN = 100 MHz, VIN = FS − 0.25 dB −53 dBc fIN = 4 MHz, VIN = FS − 0.25 dB −66 dBc fIN = 20 MHz, VIN = FS − 0.25 dB -68 dBc fIN = 50 MHz, VIN = FS − 0.25 dB −66 dBc fIN = 70 MHz, VIN = FS − 0.25 dB -60 dBc fIN = 100 MHz, VIN = FS − 0.25 dB −55 dBc fIN = 4 MHz, VIN = FS − 0.25 dB −72 dBc fIN = 20 MHz, VIN = FS − 0.25 dB −58 dBc fIN = 50 MHz, VIN = FS − 0.25 dB −72 dBc fIN = 70 MHz, VIN = FS − 0.25 dB -58 dBc fIN = 100 MHz, VIN = FS − 0.25 dB −60 dBc f1 = 11 MHz, VIN = FS − 6.25 dB f2 = 12 MHz, VIN = FS − 6.25 dB -55 dBc POWER SUPPLY CHARACTERISTICS 86 mA (max) 0.25 0.6 mA (max) DC Input, PD = Low 70 86.6 mA (max) CLK Low, PD = Hi 0.3 Power Consumption DC Input, Excluding Reference 210 260 mW (max) Power Supply Rejection Ratio FSE change with 2.7V to 3.3V change in VA 54 IA Analog Supply Current IDR Output Driver Supply Current IA + IDR Total Operating Current PC PSRR1 DC Input 69.75 fIN = 10 MHz, VIN = FS − 3 dB 69.75 DC Input, PD = Low 5 mA (max) mA dB www.national.com ADC08200 Converter Electrical Characteristics ADC08200 Converter Electrical Characteristics (Continued) The following specifications apply for VA = VDR = +3.0VDC, VRT = +1.9V, VRB = 0.3V, CL = 5 pF, fCLK = 200 MHz at 50% duty cycle. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C (Notes 7, 8) Symbol Parameter Conditions Typical (Note 9) Limits (Note 9) Units (Limits) 200 MHz (min) AC ELECTRICAL CHARACTERISTICS fC1 Maximum Conversion Rate 230 fC2 Minimum Conversion Rate 10 MHz tCL Minimum Clock Low Time 0.87 1.0 ns (min) tCH Minimum Clock High Time 0.65 0.75 ns (min) tOH Output Hold Time CLK to Data Invalid 2.1 tOD Output Delay CLK to Data Transition 3.5 6 Clock Cycles CLK Rise to Acquisition of Data 2.6 ns 2 ps rms Pipeline Delay (Latency) tAD Sampling (Aperture) Delay tAJ Aperture Jitter ns 2.5 ns (min) 5 ns (max) Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: All voltages are measured with respect to GND = AGND = DR GND = 0V, unless otherwise specified. Note 3: When the input voltage at any pin exceeds the power supplies (that is, less than AGND or DR GND, or greater than VA or VDR), the current at that pin should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two. Note 4: The absolute maximum junction temperature (TJmax) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA) / θJA. In the 24-pin TSSOP, θJA is 92˚C/W, so PDMAX = 1,358 mW at 25˚C and 435 mW at the maximum operating ambient temperature of 85˚C. Note that the power consumption of this device under normal operation will typically be about 245 mW (205 mW quiescent power + 16 mW reference ladder power + 24 mW to drive the output bus capacitance). The values for maximum power dissipation listed above will be reached only when the ADC08200 is operated in a severe fault condition (e.g., when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided. Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO Ohms. Note 6: See AN-450, “Surface Mounting Methods and Their Effect on Product Reliability”. Note 7: The analog inputs are protected as shown below. Input voltage magnitudes up to VA + 300 mV or to 300 mV below GND will not damage this device. However, errors in the A/D conversion can occur if the input goes above VDR or below GND by more than 100 mV. For example, if VA is 2.7VDC the full-scale input voltage must be ≤2.8VDC to ensure accurate conversions. 20017907 Note 8: To guarantee accuracy, it is required that VA and VDR be well bypassed. Each supply pin must be decoupled with separate bypass capacitors. Note 9: Typical figures are at TJ = 25˚C, and represent most likely parametric norms. Test limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). www.national.com 6 APERTURE (SAMPLING) DELAY is that time required after the rise of the clock input for the sampling switch to open. The Sample/Hold circuit effectively stops capturing the input signal and goes into the “hold” mode tAD after the clock goes high. PIPELINE DELAY (LATENCY) is the number of clock cycles between initiation of conversion and when that data is presented to the output driver stage. New data is available at every clock cycle, but the data lags the conversion by the Pipeline Delay plus the Output Delay. APERTURE JITTER is the variation in aperture delay from sample to sample. Aperture jitter shows up as input noise. CLOCK DUTY CYCLE is the ratio of the time that the clock wave form is at a logic high to the total time of one clock period. POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well the ADC rejects a change in the power supply voltage. For the ADC08200, PSRR1 is the ratio of the change in Full-Scale Error that results from a change in the dc power supply voltage, expressed in dB. PSRR2 is a measure of how well an a.c. signal riding upon the power supply is rejected from the output. SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal at the output to the rms value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or dc. DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB. Measured at 200 MSPS with a ramp input. EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise and Distortion Ratio, or SINAD. ENOB is defined as (SINAD – 1.76) / 6.02 and says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits. FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input. FULL-SCALE ERROR is a measure of how far the last code transition is from the ideal 11⁄2 LSB below VRT and is defined as: Vmax + 1.5 LSB – VRT SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or SINAD) is the ratio, expressed in dB, of the rms value of the input signal at the output to the rms value of all of the other spectral components below half the clock frequency, including harmonics but excluding dc. SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the input signal at the output and the peak spurious signal, where a spurious signal is any signal present in the output spectrum that is not present at the input. TOTAL HARMONIC DISTORTION (THD) is the ratio expressed in dB, of the rms total of the first nine harmonic levels at the output to the level of the fundamental at the output. THD is calculated as where Vmax is the voltage at which the transition to the maximum (full scale) code occurs. INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from zero scale (1⁄2 LSB below the first code transition) through positive full scale (1⁄2 LSB above the last code transition). The deviation of any given code from this straight line is measured from the center of that code value. The end point test method is used. Measured at 200 MSPS with a ramp input. INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two sinusoidal frequencies being applied to the ADC input at the same time. it is defined as the ratio of the power in the second and thrid order intermodulation products to the power in one of the original frequencies. IMD is usually expressed in dBFS. MISSING CODES are those output codes that are skipped and will never appear at the ADC outputs. These codes cannot be reached with any input value. OUTPUT DELAY is the time delay after the rising edge of the input clock before the data update is present at the output pins. where f1 is the RMS power of the fundamental (output) frequency and f2 through f10 are the RMS power of the first 9 harmonic frequencies in the output spectrum ZERO SCALE OFFSET ERROR is the error in the input voltage required to cause the first code transition. It is defined as VOFF = VZT - VRB where VZT is the first code transition input voltage. 7 www.national.com ADC08200 OUTPUT HOLD TIME is the length of time that the output data is valid after the rise of the input clock. Specification Definitions ADC08200 Timing Diagram 20017931 FIGURE 1. ADC08200 Timing Diagram Typical Performance Characteristics VA = VDR = 3V, fCLK = 200 MHz, fIN = 50 MHz, unless other- wise stated INL INL vs Temperature 20017908 20017914 INL vs Supply Voltage INL vs Sample Rate 20017915 www.national.com 20017910 8 DNL DNL vs Temperature 20017909 20017917 DNL vs Supply Voltage DNL vs Sample Rate 20017911 20017918 SNR vs Temperature SNR vs Supply Voltage 20017920 20017921 9 www.national.com ADC08200 Typical Performance Characteristics VA = VDR = 3V, fCLK = 200 MHz, fIN = 50 MHz, unless otherwise stated (Continued) ADC08200 Typical Performance Characteristics VA = VDR = 3V, fCLK = 200 MHz, fIN = 50 MHz, unless otherwise stated (Continued) SNR vs Sample Rate SNR vs Input Frequency 20017912 20017923 SNR vs Clock Duty Cycle Distortion vs Temperature 20017924 20017925 Distortion vs Supply Voltage Distortion vs Sample Rate 20017926 www.national.com 20017913 10 Distortion vs Input Frequency Distortion vs Clock Duty Cycle 20017928 20017929 SINAD/ENOB vs Temperature SINAD/ENOB vs Supply Voltage 20017930 20017938 SINAD/ENOB vs Sample Rate SINAD/ENOB vs Input Frequency 20017916 20017939 11 www.national.com ADC08200 Typical Performance Characteristics VA = VDR = 3V, fCLK = 200 MHz, fIN = 50 MHz, unless otherwise stated (Continued) ADC08200 Typical Performance Characteristics VA = VDR = 3V, fCLK = 200 MHz, fIN = 50 MHz, unless otherwise stated (Continued) SINAD/ENOB vs Clock Duty Cycle Power Consumption vs Sample Rate 20017940 20017919 Spectral Response @ fIN = 50 MHz Spectral Response @ fIN = 76 MHz 20017946 20017947 Spectral Response @ fIN = 99 MHz Intermodulation Distortion 20017948 www.national.com 20017943 12 The ADC08200 uses a new, unique architecture that achieves over 7 effective bits at input frequencies up to and beyond 100 MHz. The analog input signal that is within the voltage range set by VRT and VRB is digitized to eight bits. Input voltages below VRB will cause the output word to consist of all zeroes. Input voltages above VRT will cause the output word to consist of all ones. Applications Information 1.0 REFERENCE INPUTS The reference inputs VRT and VRB are the top and bottom of the reference ladder, respectively. Input signals between these two voltages will be digitized to 8 bits. External voltages applied to the reference input pins should be within the range specified in the Operating Ratings table (0.5V to (VA − 0.3V) for VRT and −100 mV to (VRT − 0.5V) for VRB). Any device used to drive the reference pins should be able to source sufficient current into the VRT pin and sink sufficient current from the VRB pin. Incorporating a switched capacitor bandgap, the ADC08200 exhibits a power consumption that is proportional to frequency, limiting power consumption to what is needed at the clock rate that is used. This and its excellent performance over a wide range of clock frequencies makes it an ideal choice as a single ADC for many 8-bit needs. Data is acquired at the rising edge of the clock and the digital equivalent of that data is available at the digital outputs 6 clock cycles plus tOD later. The ADC08200 will convert as 20017932 FIGURE 2. Simple, low component count reference biasing. Because of the ladder and external resistor tolerances, the reference voltage can vary too much for some applications. The bottom of the ladder (VRB) may simply be returned to ground if the minimum input signal excursion is 0V. Be sure that the driving source can source sufficient current into the VRT pin and sink enough current from the VRB pin to keep these pins stable. The LMC662 amplifier shown was chosen for its low offset voltage and low cost. VRT should always be at least 0.5V more positive than VRB to minimize noise. The VRM pin is the center of the reference ladder and should be bypassed to a quiet point in the analog ground plane with a 0.1 µF capacitor. DO NOT allow this pin to float. The reference bias circuit of Figure 2 is very simple and the performance is adequate for many applications. However, circuit tolerances will lead to a wide referance voltage range. Better reference stability can be achieved by driving the reference pins with low impedance sources. The circuit of Figure 3 will allow a more accurate setting of the reference voltages. The lower amplifier must have bipolar supplies as its output voltage must go negative to force VRB to any voltage below the VBE of the PNP transistor. Of course, the divider resistors at the amplifier input could be changed to suit your reference voltage needs, or the divider can be replaced with potentiometers for precise settings. 13 www.national.com ADC08200 long as the clock signal is present. The device is in the active state when the Power Down pin (PD) is low. When the PD pin is high, the device is in the power down mode, where the output pins hold the last conversion before the PD pin went high and the device consumes just 1 mW. Functional Description ADC08200 Applications Information (Continued) 20017933 FIGURE 3. Driving the reference to force desired values requires driving with a low impedance source. 2.0 THE ANALOG INPUT The analog input of the ADC08200 is a switch followed by an integrator. The input capacitance changes with the clock level, appearing as 3 pF when the clock is low, and 4 pF when the clock is high. Since a dynamic capacitance is more difficult to drive than is a fixed capacitance, choose an amplifier that can drive this type of load. This will provide optimum SNR performance. Best THD performance is realized when the capacitor and resistor values are both zero. To optimize SINAD, reduce the capacitor value until SINAD performance is optimized. That is, until SNR = −THD. This value will usually be in the range of 20% to 65% of the value calculated with the above formula. An accurate calculation is not possible because of the board material and layout dependence. The circuit of Figure 4 has both gain and offset adjustments. If you eliminate these adjustments normal circuit tolerances may result in signal clipping unless care is exercised in the worst case analysis of component tolerances and the input signal excursion is appropriately limited to account for the worst case conditions. Figure 4 shows an example of an input circuit using the LMH6702. Any input amplifier should incorporate some gain as operational amplifiers exhibit better phase margin and transient response with gains above 2 or 3 than with unity gain. If an overall gain of less than 3 is required, attenuate the input and operate the amplifier at a higher gain, as shown in Figure 4. The RC at the amplifier output filters the clock rate energy that comes out of the analog input due to the input sampling circuit. The optimum time constant for this circuit depends not only upon the amplifier and ADC, but also on the circuit layout and board material. A resistor value should be chosen between 18Ω and 47Ω and the capacitor value chose according to the formula www.national.com 14 ADC08200 Applications Information (Continued) 20017934 FIGURE 4. The input amplifier should incorporate some gain for best performance (see text). 3.0 POWER SUPPLY CONSIDERATIONS A/D converters draw sufficient transient current to corrupt their own power supplies if not adequately bypassed. A 10 µF tantalum or aluminum electrolytic capacitor should be placed within an inch (2.5 cm) of the A/D power pins, with a 0.1 µF ceramic chip capacitor placed within one centimeter of the converter’s power supply pins. Leadless chip capacitors are preferred because they have low lead inductance. While a single voltage source is recommended for the VA and VDR supplies of the ADC08200, these supply pins should be well isolated from each other to prevent any digital noise from being coupled into the analog portions of the ADC. A choke or 27Ω resistor is recommended between these supply lines with adequate bypass capacitors close to the supply pins. As is the case with all high speed converters, the ADC08200 should be assumed to have little power supply rejection. None of the supplies for the converter should be the supply that is used for other digital circuitry in any system with a lot of digital power being consumed. The ADC supplies should be the same supply used for other analog circuitry. No pin should ever have a voltage on it that is in excess of the supply voltage or below ground by more than 300 mV, not even on a transient basis. This can be a problem upon application of power and power shut-down. Be sure that the supplies to circuits driving any of the input pins, analog or digital, do not come up any faster than does the voltage at the ADC08200 power pins. 4.0 THE DIGITAL INPUT PINS The ADC08200 has two digital input pins: The PD pin and the Clock pin. 4.1 The PD Pin The Power Down (PD) pin, when high, puts the ADC08200 into a low power mode where power consumption is reduced to 1 mW. Output data is valid and accurate about 1 millisecond after the PD pin is brought low. The digital output pins retain the last conversion output code when either the clock is stopped or the PD pin is high. 4.2 The ADC08200 Clock Although the ADC08200 is tested and its performance is guaranteed with a 200 MHz clock, it typically will function well with clock frequencies from 10 MHz to 230 MHz. The low and high times of the clock signal can affect the performance of any A/D Converter. Because achieving a precise duty cycle is difficult, the ADC08200 is designed to maintain performance over a range of duty cycles. While it is specified and performance is quaranteed with a 50% clock duty cycle and 200 Msps, ADC08200 performance is typically maintained with clock high and low times of 0.65 ns and 0.87 ns, respectively, corresponding to a clock duty cycle range of 13% to 82.5% with a 200 MHz clock. The CLOCK line should be series terminated at the clock source in the characteristic impedance of that line. If the clock line is longer than 15 www.national.com ADC08200 Applications Information (Continued) where tr is the clock rise time and tprop is the propagation rate of the signal along the trace, the CLOCK pin should be a.c. terminated with a series RC to ground such that the resisitor value is equal to the characteristic impedance of the clock line and the capacitor value is where "L" is the line length in inches, tprop is the signal propagation rate down the clock line and Zo is the characteristic impedance of the clock line. Typical tprop is about 150 ps/inch on FR-4 board material. For FR-4 board material, the value of C becomes 20017936 FIGURE 5. Layout Example Figure 5 gives an example of a suitable layout. All analog circuitry (input amplifiers, filters, reference components, etc.) should be placed together away from any digital components. Where L is the length of the clock line in inches. This termination should be located as close as possible to, but within one centimeter of, the ADC08200 clock pin. 6.0 DYNAMIC PERFORMANCE 5.0 LAYOUT AND GROUNDING The ADC08200 is ac tested and its dynamic performance is guaranteed. To meet the published specifications, the clock source driving the CLK input must exhibit less than 2 ps (rms) of jitter. For best ac performance, isolating the ADC clock from any digital circuitry should be done with adequate buffers, as with a clock tree. See Figure 6. It is good practice to keep the ADC clock line as short as possible and to keep it well away from any other signals. Other signals can introduce jitter into the clock signal. The clock signal can also introduce noise into the analog path. Proper grounding and proper routing of all signals are essential to ensure accurate conversion. A combined analog and digital ground plane should be used. Since digital switching transients are composed largely of high frequency components, total ground plane copper weight will have little effect upon the logic-generated noise because of the skin effect. Total surface area is more important than is total ground plane volume. Capacitive coupling between the typically noisy digital circuitry and the sensitive analog circuitry can lead to poor performance that may seem impossible to isolate and remedy. The solution is to keep the analog circuitry well separated from the digital circuitry. High power digital components should not be located on or near a straight line between the ADC or any linear component and the power supply area as the resulting common return current path could cause fluctuation in the analog input “ground” return of the ADC. Generally, analog and digital lines should cross each other at 90˚ to avoid getting digital noise into the analog path. In high frequency systems, however, avoid crossing analog and digital lines altogether. Clock lines should be isolated from ALL other lines, analog AND digital. Even the generally accepted 90˚ crossing should be avoided as even a little coupling can cause problems at high frequencies. Best performance at high frequencies is obtained with a straight signal path. The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input. Any external component (e.g., a filter capacitor) connected between the converter’s input and ground should be connected to a very clean point in the analog ground plane. www.national.com 20017937 FIGURE 6. Isolating the ADC Clock from Digital Circuitry 7.0 COMMON APPLICATION PITFALLS Driving the inputs (analog or digital) beyond the power supply rails. For proper operation, all inputs should not go more than 300 mV below the ground pins or 300 mV above the supply pins. Exceeding these limits on even a transient basis may cause faulty or erratic operation. It is not uncommon for high speed digital circuits (e.g., 74F and 74AC 16 input alternates between 3 pF and 4 pF with the clock. This dynamic capacitance is more difficult to drive than is a fixed capacitance, and should be considered when choosing a driving device. Driving the VRT pin or the VRB pin with devices that can not source or sink the current required by the ladder. As mentioned in Section 1.0, care should be taken to see that any driving devices can source sufficient current into the VRT pin and sink sufficient current from the VRB pin. If these pins are not driven with devices than can handle the required current, these reference pins will not be stable, resulting in a reduction of dynamic performance. Using a clock source with excessive jitter, using an excessively long clock signal trace, or having other signals coupled to the clock signal trace. This will cause the sampling interval to vary, causing excessive output noise and a reduction in SNR performance. The use of simple gates with RC timing is generally inadequate as a clock source. (Continued) devices) to exhibit undershoot that goes more than a volt below ground. A 51Ω resistor in series with the offending digital input will usually eliminate the problem. Care should be taken not to overdrive the inputs of the ADC08200. Such practice may lead to conversion inaccuracies and even to device damage. Attempting to drive a high capacitance digital data bus. The more capacitance the output drivers must charge for each conversion, the more instantaneous digital current is required from VDR and DR GND. These large charging current spikes can couple into the analog section, degrading dynamic performance. Buffering the digital data outputs (with a 74AF541, for example) may be necessary if the data bus capacitance exceeds 5 pF. Dynamic performance can also be improved by adding 33Ω to 47Ω series resistors at each digital output, reducing the energy coupled back into the converter input pins. Using an inadequate amplifier to drive the analog input. As explained in Section 2.0, the capacitance seen at the 17 www.national.com ADC08200 Applications Information ADC08200 Physical Dimensions inches (millimeters) unless otherwise noted NOTES: UNLESS OTHERWISE SPECIFIED REFERENCE JECED REGISTRATION mo-153, VARIATION AD, DATED 7/93. 24-Lead Package TC Order Number ADC08200CIMT NS Package Number MTC24 www.national.com 18 ADC08200 8-Bit, 20 MSPS to 200 MSPS, 1.05 mW/MSPS A/D Converter Notes LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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