CMLMICRO FX613DW

CML Semiconductor Products
PRODUCT INFORMATION
FX613 Universal Call Progress Decoder
Publication D/613/3 December 1995
Features
Covers Worldwide Call Progress
Frequencies (300Hz to 2,150Hz)
3 Volt <1mA Requirement
Decodes Single or Modulated
Tones
Analogue In/Serial Data Out
Speech Discrimination Ability
µProcessor Compatible Outputs
Telephone/Telecoms, Radio and
Fax/Modem Applications
Mixed Analogue/Digital
Technology
SERIAL CLOCK
SERIAL OUTPUT
PORT (6-BITS)
DATA OUT
0 1 2 3 4 5
CHIP SELECT
V DD
CS
LATCH
TIME
COUNT
f
SIGNAL IN
FILTER &
BAND SELECTOR
FREQUENCY
COUNTER
f/4
HI / LO BAND
LEVEL IN
RESET
LEVEL
DETECTOR
DECODE
ON / OFF
VBIAS
HI / LO
V SS
f/4
SIGNAL QUALITY
ASSESSOR
GOOD/BAD
FX613
LOGIC
RESET
RESET
CS
HI / LO
TIME
XTAL/CLOCK
3.579545MHz
CLOCK
GENERATOR
TIMER
LO = 39.4ms
HI = 13.16ms
IRQ
XTAL
Fig.1 Functional Block Diagram
Brief Description
The FX613 is a wide-band, ‘N-Tone’, non-predictive
tone decoder to measure telephone system call progress
tones in PABX, Pay/Feature-Phone, Fax and Modem
systems.
Adhering to Must/Must-Not Decode limits and able to
measure inband frequencies in outband modulation, this
decoder measures the frequency of input signals in the
range 300Hz to 2,150Hz; the result of each
measurement is presented to a system µProcessor, as a
6-bit serial word.
The decode frequency range, which covers the
World's call progress application spectrum, is processed
internally as two bands: LO = 300Hz to 660Hz and HI =
900Hz to 2150Hz. Frequency measurement is achieved
by counting the number of cycles in a set time period
(LO = 39.47ms or HI = 13.16ms). Bad signal/level quality
or NOTONE results in a count-abort, timing-reset and no
output from the decoder.
Current frequency information is output for the
µProcessor using a Serial Data, Clock and Interrupt
interface.
Data from the FX613 should be processed by a
µProcessor whose algorithms are able to recognize the
frequency, sequence and/or cadence of input signals as
national call progress information; e.g.: ‘Dial’, ‘Busy’,
‘Number-Unobtainable’, ‘Ringing’ and automatic tones
employed by Fax, Modem systems. Software can be
simply configured to reject speech frequencies.
Due to its ‘N-Tone’, non-predictive decoding capability,
units employing the FX613 can be redeployed under a
new national standard by a simple software amendment.
Available in 16-pin plastic S.O.I.C. SMD and 14-pin
plastic DIL packages, this low-cost, mixed analogue/digital
microcircuit has a typical power requirement of less than
1mA at 3 volts and utilizes a telecom-system clock input
of 3.579545MHz to maintain frequency accuracy.
Pin Number
Function
FX613DW
FX613P
1
1
Xtal/Clock: The input to the on-chip clock oscillator inverter. A 3.579545MHz Xtal or
externally derived telephone system clock (fXTAL) should be connected here.
Note - The operation of the FX613 without a suitable Xtal/Clock input may cause
device damage.
2
2
Xtal: The output of the on-chip clock oscillator inverter. See Figure 2.
3
3
No internal connection.
4
4
VBIAS: The internal circuitry bias line, held at VDD/2 this pin must be decoupled to VSS.
5
5
Level In: The input for level discrimination. This input is internally biased to VBIAS,
signals must be a.c. coupled. The audio signal must be fed to both this pin and the
Signal In pin. Correct level detection determines the operation of this device (see
Principles of Decoder Operation), however to disregard the amplitude of the input
levels the FX613 may be permanently enabled by pulling this pin to VDD and disabled
by pulling to VSS.
6
6
Signal In: The input for frequency discrimination and decoding. This input is internally
biased to VBIAS, signals must be a.c. coupled. The audio signal must be fed to both this
pin and the Level In pin.
No internal connection.
7
8
7
VSS: Negative supply rail. Signal ground.
9
8
No internal connection.
No internal connection.
10
11
9
IRQ: This Interrupt Request output from the FX613 is ‘wire-OR able’ allowing the
interrupt outputs of other peripherals to be combined and connected to the Interrupt
input of a µProcessor. This input has a low-impedance pulldown to VSS when active and
a high-impedance when inactive. An interrupt is produced on completion of a HI or LO
frequency measurement.
12
10
Serial Clock: The serial clock from the µProcessor. Data Out is clocked into the
µProcessor on the rising edge of the Serial Clock. See Data-Read Timing diagram.
13
11
Chip Select: A logic “0” at this input will select this device.
14
12
Data Out: The serial data output. Under the control of the Chip Select and Serial
Clock inputs, data should be read from this output in 6-bit blocks MSB (Bit-5) first.
If 8 serial clock pulses are applied, two additional logic “0s” will be output after Bit-0.
15
13
No internal connection.
16
14
VDD: Positive supply rail. A single, stable supply is required. Levels and voltages within
the FX613 are dependent upon this supply. This pin should be decoupled to VSS by a
capacitor located close to the FX613 pins.
2
Application Information
VDD
C4
1
R2
VSS
X1
XTAL/CLOCK
C5
XTAL
2
C6
VSS
VBIAS
C2
AUDIO SIGNAL
LEVEL IN
16
2
15
3
14
4
13
5
SIGNAL IN
C1
C3
1
VSS
FX613DW
VDD
DATA OUT
CHIP SELECT
SERIAL CLOCK INPUT
12
6
11
7
10
8
9
R1
IRQ
VSS
Notes
(1) The Xtal/Clock input may be driven from the host telephone
system's 3.579545MHz clock; if a Xtal drive is required, the
configuration shown INSET is recommended.
(2) The audio signal should be input to both Signal In and Level In pins
via separate coupling capacitors. If it is wished to operate the
device with disregard to on-chip level thresholds and permanently
enable the FX613, the Level In pin should be held at VDD.
To disable the FX613 the Level In pin should be held at VSS. Level
thresholds are preset internally.
Component
Value
R1
R2
C1
C2
C3
C4
C5
C6
X1
22.0kΩ
1.0MΩ
0.01µF
0.1µF
1.0µF
1.0µF
33.0pF
33.0pF
3.579545MHz
Tolerances: C = ± 20% R = ± 10%
Fig.2 External Component Connections
VDD
775mVrms
0
Level (dB)
-10
Low Band
(LO)
-20
High Band
(HI)
Must
Decode
-30
-40
Must-Not
Decode
-50
0
200
400
600
800
1000
1200
1400
1600
1800
2000
Frequency (Hz)
Fig.3 HI/LO Decode Bands
3
2200
Application Information ......
Principles of Decoder Operation
Level Detection
NOTONE Recognition
As level and frequency discrimination operations
take place in parallel the audio signal should, under
normal circumstances, be input to both Signal In and
Level In pins via coupling capacitors.
If the input signal level (Level In) is outside the
preset ‘Must/Must Not Decode’ thresholds
(Specification Page), the Universal Call Progress
Decoder will be disabled.
The NOTONE condition can be recognized using
µProcessor software timing as below.
a. Set the µP timer period to a period greater than
the relevant frequency-band measurement
period (13.16ms or 39.47ms).
b. Each ‘Tone Measurement Complete’ interrupt
from the FX613 must reset the µP timer.
c. With NOTONE or white noise at the decoder input,
the FX613 on-chip timer will be continually reset.
ii No ‘Tone Measurement Complete’ interrupt
will occur - the µP timer will run.
ii The µP Timer time-out can be considered as
a NOTONE indication.
If it is wished to disregard signal input levels at the
Level In pin and attempt to decode under all
conditions, the decoder may be permanently enabled
by holding the Level In pin at V DD.
The device can disabled by pulling Level In to VSS.
Level In
Timer
In Limits
Running
Enabled
Enabled
Reset
Disabled
Disabled (frozen to previous bit-5 level
VDD
Running/Reset
Enabled/Disabled
VSS
Reset
Disabled
Out of Limits
IRQ
Data Out
Enabled (dependent upon Quality measurement)
Disabled (frozen to previous bit-5 level)
Frequency Band Discrimination
On-Chip Timer Operation ......
The input signal is amplified by a self-biased (zerocrossing) inverting amplifier and then ‘filtered’ to
remove high-frequency noise and jitter.
High (HI) and Low (LO) counters are employed to
determine the input frequency band (HI = 900Hz to
2150Hz, LO = 300Hz to 660Hz).
If the input frequency is in the LO Band, the device
will operate as a LO Band decoder and will remain so
until a HI frequency signal is detected. If the input
frequency is in the HI Band, the device will operate as
a HI Band decoder and will remain so until a LO
frequency signal is detected.
Frequency band monitoring is continuous with the
band selection taking place every 9.8ms. It will
therefore take 9.8ms from Power-Up to set up the
initial correct decode frequency band.
When the timer expires the following actions take
place:
a. A HI or LO (“1” or “0”) band indication bit is
latched into Bit-5 of the Serial Output Port.
b. The Frequency Counter count of 5-bits is latched
into the Serial Output Port (Bit-4 [MSB] to Bit-0).
The Serial Output Port Contains 6-bits, if 8 Serial
Clock edges are employed, two extra “0s”, which
should be ignored, will be output last.
c. An interrupt is generated (IRQ) to the
µProcessor. The contents of the Serial Output
Port should be read before the next interrupt is
expected; if not data will be overwritten.
When the Chip Select input is set to “0” the
interrupt is reset.
The On-Chip Timer and Frequency Counter will be
reset in mid-count, and therefore unable to allow a
valid measurement, under the following conditions:
a. A change of decode frequency band.
On-Chip Timer Operation
For frequency measurement, the FX613 counts
the number of input cycles in a fixed time period. This
fixed period, measured by the continuous on-chip
timer, is set to 13.16ms for HI Band inputs and
39.47ms for LO Band inputs.
b. Decoder disabled; signal input level out of
specification or Level Detect input set to VSS.
c. Signal Quality Assessment considered ‘Bad’.
d. Input signal frequency outside limits.
4
Application Information ......
N = int (Frequency x Measurement Period)
Measurement Period
= 39.47ms for Low Band
= 13.16ms for High Band
(300Hz to 660Hz)
(900Hz to 2150Hz)
Note: For input frequencies of between 661Hz and 899Hz the FX613 will give no reliable output.
Bit 5
Band Bit (5)
Output
HI-“1”/LO-“0”
First
MSB (4)
(3)
(2)
(1)
Bits
0 to 4
=N
LSB (0)
Bits 0 to 4 represent the measured frequency in the selected band
When a ‘correct’ decode has been allowed and an interrupt generated, a 6-bit data word will be presented at the
Serial Output Port. This 6-bit word indicates the input frequency's band and value as described below.
As an example, the following binary-word presented at the Serial Output Port (1 1 0 1
frequency in the HI Band of between 1680Hz and 1740Hz (Bit-5 = “1” = HI, ‘N’ = 22).
LO Band
HI Band
N
B5
B4 B3 B2 B1 B0
280
285
290
295
300
305
310
315
320
325
330
335
340
345
350
355
360
365
370
375
380
385
390
395
400
405
410
415
420
425
430
435
440
445
450
455
460
465
470
475
480
485
490
495
500
840
855
870
885
900
915
930
945
960
975
990
1005
1020
1035
1050
1065
1080
1095
1110
1125
1140
1155
1170
1185
1200
1215
1230
1245
1260
1275
1290
1305
1320
1335
1350
1365
1380
1395
1410
1425
1440
1455
1470
1485
1500
11
11
11
11
11
12
12
12
12
12
13
13
13
13
13
14
14
14
14
14
14
15
15
15
15
15
16
16
16
16
16
17
17
17
17
17
18
18
18
18
18
19
19
19
19
H/L
0
1
0
1
1
H/L
0
1
1
0
0
H/L
H/L
0
0
1
1
1
1
0
1
1
0
H/L
0
1
1
1
1
H/L
1
0
0
0
0
H/L
1
0
0
0
1
H/L
1
0
0
1
0
H/L
1
0
0
1
1
Table 1 Decode Frequency Data
5
1 0) will indicate a
LO Band
HI Band
N
B5 B4 B3 B2 B1 B0
505
510
515
520
525
530
535
540
545
550
555
560
565
570
575
580
585
590
595
600
605
610
615
620
625
630
635
640
645
650
655
660
665
670
675
680
685
690
695
700
705
710
715
720
725
1515
1530
1545
1560
1575
1590
1605
1620
1635
1650
1665
1680
1695
1710
1725
1740
1755
1770
1785
1800
1815
1830
1845
1860
1875
1890
1905
1920
1935
1950
1965
1980
1995
2010
2025
2040
2055
2070
2085
2100
2115
2130
2145
2160
2175
19
20
20
20
20
20
21
21
21
21
21
22
22
22
22
22
23
23
23
23
23
24
24
24
24
24
25
25
25
25
25
26
26
26
26
26
27
27
27
27
27
28
28
28
28
H/L
H/L
1
1
0
0
0 1
1 0
1
0
H/L
1
0
1 0
1
H/L
1
0
1 1
0
H/L
1
0
1 1
1
H/L
1
1
0 0
0
H/L
1
1
0 0
1
H/L
1
1
0 1
0
H/L
1
1
0 1
1
H/L
1
1
1 0
0
Application Information ......
Decoder Timing
CHIP SELECT
tCSE
tCYC
tCSH
SERIAL CLOCK
tPWL
tDE
tPWH
tCDS
tDH
tHIZ
DATA OUT
BIT 5
TRI-STATE
BIT 0
BIT 4
tIR
IRQ
Fig.4 Data-Read Timing
Decoder Timing Characteristics
With reference to Figure 4, Data-Read Timing.
tPWH
tPWL
tCYC
tCSE
tCSH
tDH
tCDS
tIR
tDE
tHIZ
Characteristics
Min.
Typ.
Max.
Unit
Serial Clock “High” Pulse Width
Serial Clock “Low” Pulse Width
Serial Clock-Cycle Time
Chip Select Low to Clock “High” Edge
Last Clock “High” Edge to CS “High”
Data Out Hold Time
Clock Edge to Data Out Set Time
Interrupt (IRQ) Reset Time
Chip Select “Low” to Data Enable
Chip Select “High” to Output Tri-State
250
250
600
450
600
0
-
-
200
200
200
1000
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1 Data is output bit 5 first. Bit 5 can be clocked into the µProcessor by the first Serial Clock rising edge.
If 8 Serial Clock pulses are employed the last 2 data-bits will be “0” and should be ignored by the
software.
2 Chip Select should be used to react to Interrupts and then returned to a logic “1”.
If Chip Select stays low there will be no further Interrupts and no Data Output update.
6
Specification
Absolute Maximum Ratings
Exceeding the maximum rating can result in device damage. Operation of the device outside the operating limits is
not implied.
Supply voltage
-0.3 to 7.0V
Input voltage at any pin (ref VSS = 0V)
-0.3 to (VDD + 0.3V)
Sink/source current (supply pins)
+/- 30mA
(other pins)
+/- 20mA
Total device dissipation @ TAMB 25°C
800mW Max.
Derating
10mW/°C
Storage temperature range:
FX613DW/P
-40°C to +85°C (plastic)
Operating Limits ......
Min.
Max.
Unit
Supply Voltage (VDD)
3.0
5.5
V
at 25°C
Operating Temperature ......
-40
+85
°C
All device characteristics are measured under the following conditions unless otherwise specified:
VDD = 3.3V, TOP = -40 to +85 °C. Audio Level 0dB ref: = 775mVrms. Xtal/Clock Frequency = 3.579545MHz
Characteristics
See Note
Static Values
Supply Current
Input Logic “1”
Input Logic “0”
Output Logic “1”
1
Output Logic “0”
1
Impedances
Chip Select and Serial Clock Input
Signal Input
Level Input
IRQ Output (logic “0”)
Data Output (logic “0”)
(Logic “1”)
Dynamic Values
On-Chip Xtal Oscillator
RIN
ROUT
DC Voltage Gain
Bandwidth at Unity Gain
Single Tone Operation
Must-Decode Input Level
2
Must-Not Decode Input Level
2
LO Band Frequency Range
4
HI Band Frequency Range
4
Frequency Resolution (Table 1)
LO Band
HI Band
Input Signal/White-Noise Ratio (HI & LO Bands)
Interrupt Rate (LO Band)
3
(HI Band)
3
False Decodes Due to Noise
6
Outband modulation level limits
for correct decode (fIN = 340Hz to 620Hz)
5
Min.
Typ.
Max.
Unit
70.0
0
90.0
-
0.3
-
1.0
100
30.0
100
10.0
mA
% VDD
% VDD
% VDD
% VDD
10.0
-
50.0
210
500
-
500
2.5
MΩ
kΩ
kΩ
Ω
Ω
kΩ
10.0
25.0
5.0
230
42.0
11.0
825
-
MΩ
kΩ
V/V
MHz
-25.2
300
900
-
-46.0
660
2150
dB
dB
Hz
Hz
19.0
57.0
-
18.0
1.0
25.0
75.0
-
Hz
Hz
dB
/sec
/sec
/2 secs
-
-
10.0
%
Notes
1.
2.
3.
4.
5.
6.
Into a high-impedance load (>1.0MΩ).
Must decode signal above -25.2dB; Must Not decode signal below -46.0dB.
If a supply other than 3.3 volts is used, levels will change pro-rata.
Under ‘Pure Tone’ input conditions.
For input frequencies of between 661Hz and 899Hz the FX613 will provide no reliable output.
With an amplitude modulating frequency of between 16.0Hz and 100Hz.
Test noise input = 5.0kHz at 100mVrms
7
Package Outlines
Handling Precautions
The FX613 is available in the package styles outlined
below. Mechanical package diagrams and specifications
are detailed in Section 10 of this document.
Pin 1 identification marking is shown on the relevant
diagram and pins on all package styles number
anti-clockwise when viewed from the top.
The FX613 is a CMOS LSI circuit which includes input
protection. However precautions should be taken to
prevent static discharges which may cause damage.
FX613DW 16-pin plastic S.O.I.C.
FX613P
(D4)
NOT TO SCALE
14-pin plastic DIL
(P2)
NOT TO SCALE
Max. Body Length
Max. Body Width
10.49mm
7.59mm
Max. Body Length
Max. Body Width
Ordering Information
FX613DW
16-pin plastic S.O.I.C.
(D4)
FX613P
14-pin plastic DIL
(P2)
CML does not assume any responsibility for the use of any circuitry described. No circuit patent licences are implied
and CML reserves the right at any time without notice to change the said circuitry.
20.57mm
6.60mm
CML Microcircuits
COMMUNICATION SEMICONDUCTORS
CML Product Data
In the process of creating a more global image, the three standard product semiconductor
companies of CML Microsystems Plc (Consumer Microcircuits Limited (UK), MX-COM, Inc
(USA) and CML Microcircuits (Singapore) Pte Ltd) have undergone name changes and, whilst
maintaining their separate new names (CML Microcircuits (UK) Ltd, CML Microcircuits (USA)
Inc and CML Microcircuits (Singapore) Pte Ltd), now operate under the single title CML Microcircuits.
These companies are all 100% owned operating companies of the CML Microsystems Plc
Group and these changes are purely changes of name and do not change any underlying legal
entities and hence will have no effect on any agreements or contacts currently in force.
CML Microcircuits Product Prefix Codes
Until the latter part of 1996, the differentiator between products manufactured and sold from
MXCOM, Inc. and Consumer Microcircuits Limited were denoted by the prefixes MX and FX
respectively. These products use the same silicon etc. and today still carry the same prefixes.
In the latter part of 1996, both companies adopted the common prefix: CMX.
This notification is relevant product information to which it is attached.
Company contact information is as below:
CML Microcircuits
(UK)Ltd
CML Microcircuits
(USA) Inc.
CML Microcircuits
(Singapore)PteLtd
COMMUNICATION SEMICONDUCTORS
COMMUNICATION SEMICONDUCTORS
COMMUNICATION SEMICONDUCTORS
Oval Park, Langford, Maldon,
Essex, CM9 6WG, England
Tel: +44 (0)1621 875500
Fax: +44 (0)1621 875600
[email protected]
www.cmlmicro.com
4800 Bethania Station Road,
Winston-Salem, NC 27105, USA
Tel: +1 336 744 5050,
0800 638 5577
Fax: +1 336 744 5054
[email protected]
www.cmlmicro.com
No 2 Kallang Pudding Road, 09-05/
06 Mactech Industrial Building,
Singapore 349307
Tel: +65 7450426
Fax: +65 7452917
[email protected]
www.cmlmicro.com
D/CML (D)/1 February 2002