CXD2409R Timing Controller for ICX076/077AL Description The CXD2409R is a timing controller for CCD camera systems which use the ICX076/077AL black-and-white CCD image sensors. Features • Supports EIA/CCIR standards • Electronic iris (electronic shutter) function • Sync signal generation function • Backlight compensation function • AGC flickerless circuit • Electronic iris power on reset function • Oscillator frequency: 13.5 MHz Applications • Doorphones • Small sized surveillance cameras Structure Silicon gate CMOS IC Absolute Maximum Ratings (Ta = 25°C) • Supply voltage VDD VSS – 0.5 to +7.0 V • Input voltage VI VSS – 0.5 to VDD + 0.5 V • Output voltage VO VSS – 0.5 to VDD + 0.5 V • Operating temperature Topr –20 to +75 °C • Storage temperature Tstg –55 to +150 °C Recommended Operating Conditions • Supply voltage VDD 5.0 ± 0.25 • Operating temperature Topr –20 to +75 64 pin LQFP (Plastic) V °C CCD Image Sensors Used ICX076/077AL Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E94847A52-PP TEST3 41 TEST2 36 TEST1 35 SVSS1 WND WND FL 33 19 17 25 22 37 40 52 61 COMP COMP 27 63 60 62 UP/DOWN ADDER 59 54 SELECT 43 53 LIMIT 44 16 COUNT 15 13 DECODE 10 57 GATE 11 58 TEST TG 14 EIA FLD 47 IRIS /SHUTTER CLK GEN. 12 FL CBLK 46 VD SSG AVSS XSUB SYNC 45 1/525 1/625 SHD 39 XSG1 ENB 8 SHP 38 XSG2 POWER VSS RG 7 XV1 HLIM1 VSS 55 OSCI 1/429 1/432 H2 5 XV2 HLIM2 9 4 XV3 LLIM VDD H1 6 XV4 IRENB VDD 56 OSCO 1/2 3 CLP1 VSS X'tal AVDD 49 CLP2 VSS 13.5MHz 48 WSEL1 CVDD 64 50 CL 1 WSEL2 CVSS CKI HD 2 SVDD1 SVDD2 –2– SVSS2 Block Diagram 23 24 SPDNV/ED2 SPUPV/ED0 21 Vreg 18 DETC4 20 IRIN/ED1 51 PS 26 AGCI1 28 AGCO1 29 AGCI2 30 DETC1 31 DETC2 32 DETC3 34 AGCO2 42 WND CXD2409R CXD2409R 34 33 SVSS1 AGCO2 35 VSS 38 37 36 SHP SHD VSS 41 40 39 TEST1 43 42 TEST3 WND CLP2 CLP1 SYNC 46 45 44 TEST2 48 47 CBLK FLD CL Pin Configuration (Top View) VD 49 32 DETC3 HD 50 31 DETC2 PS 51 30 DETC1 29 AGCI2 IRENB 52 28 AGCO1 ENB 53 POWER 54 27 SVDD1 VSS 55 26 AGCI1 VDD 56 25 CVSS FL 57 24 SPUPV/ED0 EIA 58 23 SPDNV/ED2 WSEL1 59 22 CVDD WSEL2 60 21 Vreg LLIM 61 20 IRIN/ED1 HLIM1 62 19 SVSS2 HLIM2 63 18 CKI 64 7 8 9 10 OSCI AVDD H1 H2 AVSS RG VSS VDD XV2 11 12 13 14 15 16 Symbol I/O Description 1 OSCO O Oscillation inverter output 2 OSCI I Oscillation inverter input 3 AVDD — Power supply (for H1, H2) 4 H1 O Clock output for CCD horizontal register drive 5 H2 O Clock output for CCD horizontal register drive 6 AVSS — GND (for H1, H2) 7 RG O Reset gate pulse output 8 VSS — GND 9 VDD — Power supply 10 XV2 O Clock output for CCD vertical register drive 11 XV1 O Clock output for CCD vertical register drive 12 XSG1 O CCD sensor charge readout pulse output –3– XSUB 6 XV4 5 XSG2 4 XV3 3 XSG1 2 XV1 1 OSCO 17 SVDD2 Pin Description Pin No. DETC4 CXD2409R Pin No. Symbol I/O Description 13 XV3 O Clock output for CCD vertical register drive 14 XSG2 O CCD sensor charge readout pulse output 15 XV4 O Clock output for CCD vertical register drive 16 XSUB O CCD discharge pulse output 17 SVDD2 — Power supply (for the iris window switch) 18 DETC4 O Capacitor for iris detection 19 SVSS2 — GND (for the iris window switch) 20 IRIN/ED1 I Iris signal input/shutter speed setting; clock input in serial mode 21 Vreg I Bias current supply for the comparator 22 CVDD — 23 SPDNV/ED2 I Shutter speed down reference voltage/ shutter speed setting; data input in serial mode 24 SPUPV/ED0 I Shutter speed up reference voltage/ shutter speed setting; strobe input in serial mode 25 CVSS 26 Power supply (for the comparator) — GND (for the comparator) AGCI1 I AGC detection signal input 27 SVDD1 — Power supply (for the AGC window switch) 28 AGCO1 O AGC detection signal output 29 AGCI2 I AGC flickerless circuit input 30 DETC1 O AGC detection capacitor 1 31 DETC2 O AGC detection capacitor 2 32 DETC3 O AGC detection capacitor 3 33 SVSS1 — GND (for the AGC window switch) 34 AGCO2 O AGC flickerless circuit output 35 TEST1 I Test input (with the pull-down resistor) 36 TEST2 I Test input (with the pull-down resistor) 37 VSS — GND 38 SHP O Precharge level sample-and-hold pulse 39 SHD O Data sample-and-hold pulse 40 VSS — GND 41 TEST3 I Test input (with the pull-down resistor) 42 WND O Window pulse output 43 CLP2 O Pulse output for clamp 44 CLP1 O Pulse output for clamp 45 SYNC O Composite sync output 46 CBLK O Composite blanking output 47 FLD O Field pulse output –4– CXD2409R Pin No. Symbol I/O Description 48 CL O Master clock output 49 VD O Vertical sync signal output 50 HD O Horizontal sync signal output 51 PS I Electronic shutter speed input switchover Low: serial input; high: parallel input (with the pull-up resistor) 52 IRENB I Low: electronic shutter mode; high: electronic iris mode (with the pull-up resistor) 53 ENB I Low: XSUB pulse stop; high: XSUB pulse output (with the pull-up resistor) 54 POWER I Electronic iris power on reset 55 VSS — GND 56 VDD — Power supply 57 FL I Low: normal mode; high:AGC flickerless mode (with the pull-down resistor) 58 EIA I Low: EIA; high: CCIR (with the pull-down resistor) 59 WSEL1 I Window pulse output switchover (with the pull-down resistor) 60 WSEL2 I Window pulse output switchover (with the pull-down resistor) 61 LLIM I Electronic iris low speed limiter switchover Low: limiter OFF; high: limiter ON (with the pull-down resistor) 62 HLIM1 I Electronic iris high speed limiter switchover (with the pull-down resistor) 63 HLIM2 I Electronic iris high speed limiter switchover (with the pull-down resistor) 64 CKI I 2 fck clock input –5– CXD2409R Electrical Characteristics DC Characteristics Item Supply voltage Pins 3, 9, 17, 22, 27, and 56 Input voltage 1 All input pins except Pins 20, 21, 23, 24, 26, and 29 Input voltage 2 Pins 20, 21, 23, 24, 26, and 29 (VDD = 4.75 to 5.25V, Topr = –20 to +75°C) Symbol Conditions Min. Typ. Max. Unit VDD 4.75 5.0 5.25 V VIH 0.7VDD V VIL 1.9 VIN 0.3VDD V 5.0 V Output voltage 1 Pins 4, 5, and 7 VOH1 IOH = –7mA VOL1 IOL = 20mA Output voltage 2 Pins 38 and 39 VOH2 IOH = –4mA VOL2 IOL = 8mA Output voltage 3 Pins 18, 28, 30, 31, 32, and 34 VOH3 V VOL3 V Output voltage 4 Pin 48 VOH4 IOH = –4mA VOL4 IOL = 8mA VDD – 0.8 V 0.4 VDD – 0.8 V 0.4 VDD – 0.8 IOL = 4mA Feedback resistance RFB VIN = VSS or VDD Pull-up resistance IOH = –2mA V V 0.4 Output voltage 5 VOH5 Pins 10, 11, 12, 13, 14, 15, 16, 42, 43, VOL5 44, 45, 46, 47, 49, and 50 V VDD – 0.8 V V 0.4 V 250k 1M 2.5M Ω RPU 20k 50k 125k Ω Pull-down resistance RPD 20k 50k 125k Ω Analog switch ON resistance RON 200 Ω Current consumption IDD 125k mA Input/Output Capacitance Item VIN = 2.5V ± 1V 20k 50k (VDD = VSS = 0V, VI or VO = 0V, fM = 1MHz) Symbol Min. Typ. Max. Unit Input pin capacitance CIN 9 pF Output pin capacitance COUT 11 pF –6– CXD2409R Mode Control Pin No. Symbol I/O Low High Remarks 52 IRENB I Electronic shutter Electronic iris Valid when ENB is high. 53 ENB I XSUB stop XSUB output 58 EIA I EIA CCIR 59 WSEL1 I 60 WSEL2 I 61 LLIM I 62 HLIM1 I 63 HLIM2 I 57 FL I AGC flickerless OFF AGC flickerless ON 51 PS I Serial input Parallel input Four types of window settings can be selected by combining WSEL1 and WSEL2. The minimum shutter speed can be selected during electronic iris mode. Valid when ENB is high and IRENB is high. The maximum shutter speed can be selected during electronic iris mode by combining HLIM1 and HLIM2. Valid when ENB is high and IRENB is high. Valid when AGC is used. Valid when ENB is high and IRENB is low. • The functions of the pins (Pins 20, 23, and 24) listed below change according to the IRENB (Pin 52) mode setting. (Valid when ENB is high.) IRENB Pin No. Symbol 20 IRIN /ED1 I Electronic shutter speed setting; clock input in serial mode IRIS signal input 23 SPDNV /ED2 I Electronic shutter speed setting; data input in serial mode Comparator reference voltage input (shutter speed down side) 24 SPUPV /ED0 I Electronic shutter speed setting; strobe input in serial mode Comparator reference voltage input (shutter speed up side) I/O Low High –7– CXD2409R Description of Operation Electronic Shutter/Electronic Iris By setting the ENB pin (Pin 53) high, the XSUB pulse is output for a specific period to activate the electronic shutter and electronic iris. Electronic Shutter Parallel input (IRENB = low, PS = high) Mode OFF EIA ENB IRENB SPUPV IRIN SPDNV EIA L L × × × × 1/60 (s) CCIR H L × × × × 1/50 (s) L H L H H H 1/100 (s) L H L L H H 1/250 (s) L H L H L H 1/500 (s) L H L L L H 1/1000 (s) L H L H H L 1/2000 (s) L H L L H L 1/5000 (s) L H L H L L 1/10000 (s) L H L L L L 1/100000 (s) H H L H H H 1/120 (s) H H L L H H 1/250 (s) H H L H L H 1/500 (s) H H L L L H 1/1000 (s) H H L H H L 1/2000 (s) H H L L H L 1/5000 (s) H H L H L L 1/10000 (s) H H L L L L 1/70000 (s) EIA Electronic shutter CCIR –8– Shutter speed CXD2409R Serial input (IRENB = low, PS = low) By inputting 8-bit data to the ED2 pin (Pin 23), the electronic shutter speed can be controlled. Serial input data format D7 SPDNV/ED2 D6 D5 D4 D3 D2 D1 D0 IRIN/ED1 SPUPV/ED0 The ED2 (Pin 23) data is latched in the register at the ED1 (Pin 20) rise, and retrieved internally at the ED0 (Pin 24) rise. Typical shutter speeds EIA Shutter speed (s) DATA (ED0: 8bit) CCIR Shutter speed (s) DATA (ED0: 8bit) 1/60 11111111 (0 step) 1/50 11111111 (0 step) 1/100 11110110 (9 step) 1/120 11110001 (14 step) 1/250 11100101 (26 step) 1/250 11100011 (28 step) 1/500 11010010 (45 step) 1/500 11010000 (47 step) 1/1000 11000010 (61 step) 1/1000 11000000 (63 step) 1/2000 10111000 (71 step) 1/2000 10110111 (72 step) 1/5000 10101000 (87 step) 1/5000 10100110 (89 step) 1/10000 10011011 (100 step) 1/10000 10011000 (103 step) 1/30000 10000010 (125 step) 1/30000 01111101 (130 step) 1/100000 01101010 (149 step) 1/100000 01100011 (156 step) –9– CXD2409R AC Characteristics SPDNV/ED2 ts2 th2 IRIN/ED1 ts1 ts0 SPUPV/ED0 tw0 Symbol Min. Max. ts2 th2 ts1 tw0 SPDNV (ED2) setup time for IRIN (ED1) rise 20ns — SPDNV (ED2) hold time for IRIN (ED1) rise 20ns — IRIN (ED1) setup time for SPUPV (ED0) rise 20ns — SPUPV (ED0) pulse width 20ns 50µs ws0 SPUPV (ED0) setup time for IRIN (ED1) rise 20ns — Electronic Iris Pin No. (ENB = high, IRENB = high) Symbol Function 20 IRIN/ED1 Iris signal input 23 SPDNV/ED2 Comparator reference voltage input for shutter speed down 24 SPUPV/ED0 Comparator reference voltage input for shutter speed up (a) Electronic iris characteristics Shutter speed : 1/60 to 1/100000 (s) (EIA) 1/50 to 1/70000 (s) (CCIR) Iris steps : 149 steps (EIA) 151 steps (CCIR) Contraction ratio for one iris step : average 6% Note) When LLIM = low, HLIM1 = low, and HLIM2 = low (b) LLIM (low speed shutter limiter) By setting the LLIM pin (Pin 61) high, the minimum shutter speed can be changed. (ENB = high, IRENB = high) LLIM Minimum shutter speed EIA CCIR L 1/60 1/50 H 1/100 1/120 – 10 – CXD2409R (c) HLIM (high speed shutter limiter) By combining the HLIM1 pin (Pin 62) and the HLIM2 pin (Pin 63), the maximum shutter speed can be changed. (ENB = high, IRENB = high) Maximum shutter speed HLIM1 HLIM2 L L 1/100000 (s) 1/70000 (s) H L 1/30000 (s) 1/30000 (s) H H 1/10000 (s) 1/10000 (s) L H 1/5000 (s) 1/5000 (s) EIA CCIR (d) Power on reset During electronic iris mode (IRENB = high), the initial settings for the iris are made in the instant the POWER pin (Pin 54) switches from low to high. The initial setting shutter speed is 1/1000 (s). By applying the circuit shown below, the shutter speed can be initialized when the power is turned on. +5 V power supply 100k 54 POWER 0.68µ 55 VSS 56 VDD – 11 – CXD2409R (e) Backlight compensation By applying the window pulse to the electronic iris detection signal (IRIS) input to IRIN (Pin 20) and the AGC detection signal (DET OUT) input to AGCI1 (Pin 26), backlight compensation can be performed. Compensation is achieved by detecting a limited area with the built-in analog switch for the window and the external sample-and-hold capacitor. In addition, four types of backlight compensation areas can be selected by combining the WSEL1 pin (Pin 59) and WSEL2 pin (Pin 60) as shown in the table below. The basic circuit to perform the window operations is shown in the figure below, and window pulse timing charts are shown on the following pages. Window types WSEL1 WSEL2 L L Minimum shutter speed Full measurement∗1 H L Lower measurement L H Center measurement H H Lower center measurement ∗1 The signal is masked during blanking. Basic Circuit Configuration Comparator for iris DETC4 27 IRIS +5V 18 2SC2785 39k 10k 1µ 10k Iris window switch 20 IRIN 10k Window pulse (WND) 2SC2785 10k CXA1310Q 10k GND 19 OP+ CXD2409R AGCO1 13 DET OUT 28 AGC window switch GND 10k 26 100k AGCI1 – 12 – 1k WSEL1 = L / WSEL2 = L 1. Full measurement Window Pulse Response Chart – 13 – H direction timing V direction timing CCIR H direction timing V direction timing EIA WND CL 6.75MHz XV1 WND XV1 XSG1 WND CL 6.75MHz XV1 WND XV1 XSG1 395 CL 45 CL 294 XV1 10 XV1 394 CL 40 CL 249 XV1 11 XV1 CXD2409R AAAAAA AAAAAA AAAAAA AAAAAA WSEL1 = H / WSEL2 = L 2. Lower measurement – 14 – H direction timing V direction timing CCIR H direction timing V direction timing EIA WND CL 6.75MHz XV1 WND XV1 XSG1 WND CL 6.75MHz XV1 WND XV1 XSG1 395 CL 45 CL 294 XV1 223 XV1 394 CL 40 CL 249 XV1 189 XV1 CXD2409R AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA WSEL1 = L / WSEL2 = H 3. Center measurement – 15 – H direction timing V direction timing CCIR H direction timing V direction timing EIA WND CL 6.75MHz XV1 WND XV1 XSG1 WND CL 6.75MHz XV1 WND XV1 XSG1 288 CL 170 CL 223 XV1 152 XV1 276 CL 158 CL 189 V1 70 XV1 CXD2409R WSEL1 = H / WSEL2 = H AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA 4. Lower center measurement – 16 – H direction timing V direction timing CCIR H direction timing V direction timing EIA WND CL 6.75MHz XV1 WND XV1 XSG1 WND CL 6.75MHz XV1 WND XV1 XSG1 288 CL 170 CL 294 XV1 223 XV1 276 CL 158 CL 249 XV1 189 XV1 CXD2409R CXD2409R AGC Flickerless By setting the FL pin (Pin 57) of the CXD2409R high when using the CXA1310Q AGC, the fluorescent light flicker component generated by differences between the fluorescent light emission cycle and the EIA field cycle can be controlled. Basic Circuit Configuration AGCO2 34 16 AGC CONT 17 OP OUT 18 OP– DETC1 30 DETC2 Flickerless circuit +5V 50k 31 DETC3 32 2.7k 1M 10k 1k AGCI2 2k 29 CXA1310Q CXD2409R AGCO1 28 AGC window switch 10k 26 AGCI1 100k GND – 17 – 1k 19 OP+ 13 DET OUT – 18 – CLP2 CLP1 CCD OUT XV4 XV3 XV2 XV1 XSG2 XSG1 SYNC HD VD BLK FLD 484 486 488 490 492 483 485 487 489 491 EVEN FIELD Timing Chart (1) 9H 11H ODD FIELD 20H EIA Vertical Direction 1 3 2 4 5 6 7 483 485 487 489 491 482 484 486 488 490 492 ODD FIELD 10.5H 9H EVEN FIELD 20H 2 1 3 4 6 5 8 7 9 10 CXD2409R – 19 – CLP2 CLP1 CCD OUT XV4 XV3 XV2 XV1 XSG2 XSG1 SYNC HD VD BLK FLD 7.5H 15.5H ODD FIELD 25H CCIR Vertical Direction 573 575 577 579 581 583 574 576 578 580 582 EVEN FIELD Timing Chart (2) 1 3 2 5 4 7 6 575 577 579 581 583 574 576 578 580 582 ODD FIELD 7.5H 15H EVEN FIELD 25H 1 2 3 4 5 6 7 8 9 10 CXD2409R – 20 – VD FLD VSYNC EQ HSYNC CLP2 CLP1 XSUB XV4 XV3 XV2 XV1 SHD SHP RG H2 H1 (CL) MCK BLK HD Timing Chart (3) 0 5 10 10 16 17 17 20 EIA Horizontal Direction 21 26 25 29 30 36 33 37 41 40 42 42 45 49 51 50 55 60 65 70 74 80 CL = 6.75MHz : 148.148ns 90 CXD2409R – 21 – VD FLD VSYNC EQ HSYNC CLP2 CLP1 XSUB XV4 XV3 XV2 XV1 SHD SHP RG H2 H1 (CL) MCK BLK HD 0 Timing Chart (4) 5 10 10 16 20 20 20 CCIR Horizontal Direction 24 26 28 30 32 40 39 36 40 42 44 42 48 50 52 58 60 63 70 73 81 80 CL = 6.75MHz : 148.148ns 90 CXD2409R – 22 – XV4 XV3 XV2 XV1 XV4 XV3 XV2 XV1 EVEN ODD XSG2 XSG1 HD Timing Chart (5) 0 17 17 21 21 25 25 29 29 33 37 37 33 41 41 45 45 42 429CK EIA Charge Readout Timing 259 257 259 257 268 296 68CK (10.1µs) 285 313 327 208CK (30.8µs) 208CK (30.8µs) 327 14CK (2.07µs) 17CK (2.52µs) 11CK (1.63µs) 17CK (2.52µs) 9CK (1.33µs) 2CK (0.296µs) CL = 6.75MHz : 148.148ns CXD2409R – 23 – XV4 XV3 XV2 XV1 EVEN XV4 XV3 XV2 XV1 ODD XSG2 XSG1 HD Timing Chart (6) 0 20 24 20 32 32 28 28 24 36 44 40 40 36 48 48 44 42 432CK CCIR Charge Readout Timing 261 259 261 259 270 9CK (1.33µs) 68CK (10.1µs) 298 287 329 212CK (31.4µs) 212CK (31.4µs) 329 14CK (2.07µs) 17CK (2.52µs) 11CK (1.63µs) 2CK (0.296µs) 17CK (2.52µs) CL = 6.75MHz : 148.148ns CXD2409R CCIR EIA – 24 – FLD VD VSYNC EQ HSYNC BLKO HDO FLD VD VSYNC EQ HSYNC BLKO HDO Timing Chart (7) 16CK (2.370µs) 32CK (4.74µs) 16CK (2.370µs) 32CK (4.74µs) 81CK (12.000µs) 42CK (6.222µs) 32CK (4.74µs) 32CK (4.74µs) 74CK (10.963µs) AAAA 42CK (6.222µs) 10CK (1.484µs) H Effective Period 1/2H 10CK CL = 6.75MHz : 148.148ns 10CK CXD2409R CXD2409R Timing Chart (8) TS + SG High Speed Phase Timing Chart 74.074ns for both EIA and CCIR CK 148.148ns for both EIA and CCIR H1 H2 RG CCD OUT SHP SHD – 25 – – 26 – 10k 10k 1000P 0.1µ 64 63 62 61 60 59 58 57 12P 1 3 20P 0.1µ 2 5 6 4.7µ/10V AA 4 7 9 4.7µ/10V 8 CXD2409R 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 15µ 26 55 56 27 0.68µ 10µ 54 33 28 34 53 35 4.7µ/10V 0.1µ 3.9k 2k 1k 2.7k SPDNV 50k AA AA 50k 4.7µ/10V 0.1µ 36k SPUPV 4.7µ/10V 0.1µ 50k 39k 10k 10k 10k 1M 180K-pixel B/W CCD 10k 10k 2SC2785 2SC2785 +5V Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. 4.7µ/10V 100k 36 29 39 38 37 52 40 30 41 51 43 42 10µ 44 10µ 45 31 46 2.2k 32 47 47P 47P 47P 47P 2.2k 2.2k 2.2k 50 48 GND +5V 100 100 49 • Electronic iris mode • High speed shutter limit: 1/30000s • Full measurement • AGC flickerless mode Application Circuit -EIA- 4 10k 1k 13 CCD out VSUB ADJ 100k 10k 19 29 CXA1310AQ 24 25 30 CXD1267N VIDEO OUT 27 IRIS OP+ DET OUT 18 17 16 21 20 CXD2409R CXD2409R Package Outline Unit: mm 64PIN LQFP (PLASTIC) 12.0 ± 0.2 ∗ 10.0 ± 0.1 48 33 32 64 17 (0.22) 0.5 ± 0.2 (11.0) 49 A 1 0.5 ± 0.08 + 0.08 0.18 – 0.03 16 + 0.2 1.5 – 0.1 + 0.05 0.127 – 0.02 0.1 0° to 10° 0.5 ± 0.2 0.1 ± 0.1 NOTE: Dimension “∗” does not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE LQFP-64P-L01 LEAD TREATMENT SOLDER/PALLADIUM PLATING EIAJ CODE LQFP064-P-1010 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 0.3g JEDEC CODE – 27 –