AD ADP3088

a
1 MHz, 750 mA Buck Regulator
ADP3088
FUNCTIONAL BLOCK DIAGRAM
FEATURES
1 MHz PWM Frequency
Automatic PWM to Power Saving Mode at Light Load
Fully Integrated 1 A Power Switch
3% Output Regulation Accuracy over Temperature,
Line, and Load
100% Duty Cycle Operation
Simple Compensation
Output Voltage: 1.25 V to 10.5 V
Small Inductor and MLC Capacitors
Low Quiescent Current while Pulse Skipping
Thermal Shutdown
Fully Integrated Soft Start
Cycle-by-Cycle Current Limit
SW
IN
CURRENT
SENSE
PWM
1MHz
AMP
COMPARATOR
IN
S Q
TE
R
PROTECTION
LOGIC
(ILIM, OT)
GND
GND
B
SO
The ADP3088 is a high frequency, nonsynchronous PWM stepdown dc-to-dc regulator with an integrated 1 A power switch
in a space-saving MSOP-8 package. It provides high efficiency
and excellent dynamic response and is very simple to use.
The ADP3088’s 1 MHz switching frequency allows for small,
inexpensive external components, and the current mode control
loop is simple to compensate and eases noise filtering. The device
operates in PWM current mode under heavy loads and saves
energy at lighter loads by switching automatically into power
saving mode. Soft start is integrated completely on-chip, as is
the cycle-by-cycle current limit.
VIN
3.3V
10F
+ REF
1.245V
ADP3088
LE
GENERAL DESCRIPTION
RUN/STOP
COMPARATORS
ERROR
AMP
gm
COMP
APPLICATIONS
PDAs and Palmtop Computers
Notebook Computers
PCMCIA Cards
Bus Products
Portable Instruments
DRV
ADP3088
IN
0.1F
IN
DRV
GND
COMP
SOFT START
TIMER
3.3H
VOUT
1.8V
SW
GND
FB
10.0k
1N5817
10F
FB
22.4k
4.7pF
220pF
20k
Figure 1. Typical Application
O
Capable of operating from 2.5 V to 11 V input, the ADP3088 is
ideal for many applications, including portable, battery-powered
applications where local point-of-use power regulation is
required. Supporting output voltages down to 1.25 V, the
ADP3088 is ideal for generating low voltage rails, providing
the optimal solution in its class for delivering power efficiently,
responsively, and simply with a minimal printed circuit board area.
The device is specified over the industrial temperature range of
–40∞C to +85∞C.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2004 Analog Devices, Inc. All rights reserved.
ADP3088–SPECIFICATIONS1 (V
IN
= 3.3 V, TA = –40C to +85C, unless otherwise noted.)
Parameter
Symbol
Conditions
Min
SUPPLY
Input Voltage Range
Ground Current, Operating
VIN
IGND2
DRV = GND
VIN = 10 V, IL = 500 mA,
DRV = GND
DRV = 2 V
No Load
VCOMP = 0 V
2.5
OSCILLATOR
Oscillator Frequency
Minimum Sleep Duty Cycle
Maximum Duty Cycle
Wake-Up Hysteresis
fSW
DPSM
DMAX
VHYST
OUTPUT SWITCH
Switch-On Voltage
VIO3
Current Limit Threshold
Leakage Current
ERROR AMPLIFIER
Reference Voltage Accuracy
Reference Voltage Line
Regulation
Feedback Input Bias Current
Sink/Source Current
Short Circuit Current
FB Voltage Drops below VREF
ILIM
VIN = 12 V
VREF
IFB
ICOMP
ICOMP, SD
gm, EA
MODULATOR
Transconductance
Control Offset Voltage
Soft Start Time
Shutdown Threshold Voltage
Slope Compensation
gm, MOD
VPWM, OS
tSS
VCOMP, SD
mSC
100
20
IL = 500 mA, FB = GND, and
DRV = GND
FB = COMP
FB = COMP,
VIN = 3 V to 12 V
Soft Start Expired
Unit
11
V
3.6
250
40
mA
mA
mA
mA
∞C
1
14
1.25
30
40
0.4
V
1.0
1.2
0.5
1.4
A
mA
1.222
1.245
0.02
1.265
V
%/V
–50
35
+1
60
20
+50
85
40
nA
mA
mA
VCOMP to IL
Effectively Summed to ISW
MHz
%
%
mV
0.25
VCOMP = 0 V, Activating
Shutdown
FB = COMP
B
SO
Transconductance
0.75
IL = 500 mA
Max
TE
IQ
ISD
TSD
6
2.5
150
15
160
LE
Quiescent Current, Operating
Shutdown
Thermal Shutdown Threshold
Typ
480
mA/V
1
0.90
250
A/V
V
ms
mV
A/ms
340
0.7
600
750
NOTES
1
All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).
2
For higher efficiency operation, tie the DRV pin to the output for I L < 250 mA and V IN > 3 V.
3
VIN – VSW includes voltage drop across internal current sensor.
O
Specifications subject to change without notice.
–2–
REV. C
ADP3088
ABSOLUTE MAXIMUM RATINGS *
PIN CONFIGURATION
*Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability. Only one absolute maximum
rating may be applied at any one time.
IN 2
GND
Temperature
Range
Package
Option Branding
ADP3088
5 FB
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Function
1, 2
IN
Power Supply Input. Both pins must
be connected.
3, 6
GND
Ground. Both pins must be
connected.
4
5
COMP
Feedback Loop Compensation and
Shutdown Input. An open drain or
collector used to pull the pin to
ground will shut down the device.
FB
Feedback Voltage Sense Input. This
pin senses the voltage via an external
resistor divider.
LE
ADP3088ARM-REEL –40∞C to +85∞C MSOP-8 P0A
ADP3088ARM-REEL7 –40∞C to +85∞C MSOP-8 P0A
DRV
This pin provides a separate path for
the drive current to be connected to
ground.
8
SW
Switching Output.
B
SO
7
O
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADP3088 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. C
7 DRV
TOP VIEW
3 (Not to Scale) 6 GND
COMP 4
ORDERING GUIDE
Model
8 SW
IN 1
TE
Input Supply Voltage . . . . . . . . . . . . . . . . . . . –0.3 V to +12 V
Voltage on Any Pin with Respect to GND . . . –0.3 V to +12 V
(Voltage on Any Pin May Not Exceed VIN)
Operating Ambient Temperature Range . . . . –40∞C to +85∞C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . 125∞C
qJA (4-Layer Board) . . . . . . . . . . . . . . . . . . . . . . . . . . 116∞C/W
qJA (2-Layer Board) . . . . . . . . . . . . . . . . . . . . . . . . . . 159∞C/W
Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300∞C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215∞C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220∞C
–3–
ADP3088–Typical Performance Characteristics
200.00
100
VOUT = 3.3V
STANDBY QUIESCENT CURRENT (A)
90
80
70
EFFICIENCY (%)
VOUT = 2.5V
60
VOUT = 1.5V
50
40
30
VIN = 5V, CIN = COUT = 10F, L = 10H
20
TA = 25C
10
100
200
300
400
160.00
140.00
120.00
100.00
–40
0
0
180.00
500
–15
85
5.00
VOUT = 5V
90
60
VOUT = 3.3V
VOUT = 2.5V
50
VOUT = 1.5V
40
30
VIN = 10V, CIN = COUT = 10F, L = 10H
20
0
B
SO
TA = 25C
10
100
200
300
4.00
LE
70
GROUND CURRENT (mA)
80
EFFICIENCY (%)
60
TPC 4. Standby Quiescent Current vs. Temperature
100
400
500
ILOAD = 500mA
3.00
VDRV = 2V
2.00
1.00
–40
–15
TPC 2. Efficiency vs. Load Current and Output Voltage
10
35
60
85
TEMPERATURE (C)
LOAD CURRENT (mA)
100
35
TE
TPC 1. Efficiency vs. Load Current and Output Voltage
0
10
TEMPERATURE (C)
LOAD CURRENT (mA)
TPC 5. Ground Current vs. Temperature
1.2438
FEEDBACK VOLTAGE (V)
10
O
QUIESCENT CURRENT (mA)
IL = 500mA
VOUT = 1.5V, CIN = COUT = 10F, DRV = GND
TA = 25C
1
1.2433
1.2428
1.2423
IL = 0mA
1.2418
–40
0
0
2
4
6
8
10
12
–15
10
35
60
85
TEMPERATURE (C)
INPUT VOLTAGE (V)
TPC 3. Quiescent Current vs. Input Voltage
TPC 6. Feedback Voltage vs. Temperature
–4–
REV. C
ADP3088
20.00
SHUTDOWN SUPPLY CURRENT (A)
OUTPUT VOLTAGE (V)
1.515
1.505
VIN = 5V, CIN = COUT = 10F, L = 10H
TA = 25C
1.495
100
200
300
400
16.00
14.00
12.00
10.00
–40
1.485
0
18.00
500
–15
OUTPUT CURRENT (mA)
10
35
60
85
TE
TEMPERATURE (C)
TPC 7. Load Regulation
TPC 10. Shutdown Supply Current vs. Temperature
0.300
1.10
0.280
SWITCH VOLTAGE (V)
LE
FREQUENCY (MHz)
1.05
1.00
0.95
0.260
ILOAD = 500mA
0.240
0.90
–40
B
SO
0.220
–15
10
35
60
0.200
–40
85
–15
1.20
CURRENT LIMIT (A)
O
1.15
1.10
1.05
35
60
85
TPC 11. Switch-Sense Resistor Voltage vs. Temperature
1.000
TA = 25C
0.900
SWITCH SATURATION VOLTAGE (V)
TPC 8. Oscillator Frequency vs. Temperature
10
TEMPERATURE (C)
TEMPERATURE (C)
0.800
0.700
0.600
VIN = 12V
0.500
VIN = 5V
0.400
0.300
VIN = 3.3V
0.200
VIN = 2.5V
0.100
1.00
–40
0.00
–15
10
35
60
TEMPERATURE (C)
0.50
0.75
TPC 12. Switch Saturation Voltage vs. Load
Current and Input Voltage
TPC 9. Current Limit vs. Temperature
REV. C
0.25
OUTPUT CURRENT (A)
85
–5–
1.00
ADP3088
CH 1: INPUT VOLTAGE, 2V/DIV
CH 1: INPUT VOLTAGE, 10mv/DIV,
AC-COUPLED
CH 2: OUTPUT VOLTAGE, 500mV/DIV
VIN = 5V, VOUT = 1.5V, LOAD CURRENT = 0mA,
CIN = COUT = 10F, L = 10H
TA= 25C
TE
VIN = 5V, VOUT = 1.5V, LOAD CURRENT = 500mA,
CIN = COUT = 10F, L = 10H
TA = 25C
TPC 13. Start-Up Waveform
TPC 16. VOUT Ripple
CH 2: OUTPUT VOLTAGE, 500mV/DIV
B
SO
VIN = 5V, VOUT = 1.5V, LOAD CURRENT = 500mA,
CIN = COUT = 10F, L = 10H
TA = 25C
LE
CH 1: INPUT VOLTAGE, 2V/DIV
TPC 14. Start-Up Waveform
TA = 25C
VIN = 5V, V OUT = 1.5V, LOAD CURRENT = 10mA, C IN = C OUT = 10F, L = 10H
TPC 17. Power-Saving Mode Waveforms*
O
CH 1: INPUT VOLTAGE, 2V/DIV
CH 2: OUTPUT VOLTAGE,
500mV/DIV
VIN = 2.5V, VOUT = 1.25V, LOAD CURRENT = 250mA,
CIN = COUT = 10F, L = 10H, TA = 25C
TA = 25C
VIN = 5V, VOUT = 1.5V, LOAD CURRENT = 25mA,
CIN = C OUT = 10F, L = 10H
TPC 15. Start-Up Waveform
TPC 18. Steady-State Waveforms*
*NOTES FOR TPCs 17 AND 18
CH 1: Output Voltage, 20mV/DIV, AC-Coupled
CH 2: Switch Node Voltage, 2V/DIV
CH 3: Inductor Current, 100mA/DIV
–6–
REV. C
ADP3088
CH 1: LOAD CURRENT STEP, 167mA/DIV
CH 2: OUTPUT VOLTAGE, 100mV/DIV
VIN = 5V, V OUT = 1.5V, LOAD CURRENT = 100mA,
TA = 25C, CIN = C OUT = 10F, L = 10H
TE
VIN = 5V, VOUT = 1.5V, LOAD CURRENT = 50mA TO 550mA TO 50mA,
TA = 25C, CIN = 10F, COUT = 20F, L = 10H
TPC 22. Load Transient Response
LE
TPC 19. Steady-State Waveforms*
CH 1: INPUT VOLTAGE, 2V/DIV
CH 1: LOAD CURRENT STEP, 167mA/DIV
CH 2: OUTPUT VOLTAGE, 20mV/DIV
B
SO
CH 2: OUTPUT VOLTAGE, 100mV/DIV
VIN = 5V, VOUT = 1.5V, LOAD CURRENT = 50mA TO 550mA,
TA = 25C, CIN = 10F, COUT = 20F, L = 10H
TPC 20. Load Transient Response
O
CH 1: LOAD CURRENT STEP, 167mA/DIV
CH 2: OUTPUT VOLTAGE, 100mV/DIV
VIN = 5V, VOUT = 1.5V, LOAD CURRENT = 550mA TO 50mA,
CIN = COUT = 10F, L = 10H
TA = 25C
TPC 21. Load Transient Response
*NOTES FOR TPC 19
CH 1: Output Voltage, 20mV/DIV, AC-Coupled
CH 2: Switch Node Voltage, 2V/DIV
CH 3: Inductor Current, 100mA/DIV
REV. C
–7–
VIN = 3V TO 5V, VOUT = 1.5V, LOAD CURRENT = 500mA,
TA = 25C, CIN = 10F, COUT = 10F, L = 10H
TPC 23. Line Transient Response
ADP3088
THEORY OF OPERATION
The ADP3088 is a fixed frequency buck switching regulator in
an MSOP-8 package using an external Schottky rectifier. It
features an integrated 1 A power switch and switches at 1 MHz.
The ADP3088 uses PWM operation and incorporates soft start
for controlled start-up sequence and overtemperature switch
protection. The ADP3088 draws low current while running
in power saving mode and even lower current in shutdown.
The current limit protection overrides the PWM comparator; if
this occurs, then the switch pulse will be terminated and the soft
start mode will be reset.
Current Sense Amplifier
The voltage on the internal current sense resistor is sensed and
passed to the ramp input of the PWM comparator. This current
sense signal is also passed to the current limit comparator for
peak current limit shutdown. At the current limit, the soft start
capacitor is reset and soft start is reinitiated. The current limit is
nominally 1.2 A. Slope compensation is added to the ADP3088
to stabilize the loop. A generated ramped signal is summed with
the current sense signal to provide slope compensation. Slope
compensation is needed to close the inner loop so subharmonic
oscillation is avoided. The ramp is reset with each clock cycle so
that the ADP3088 is capable of true 100% duty cycle.
TE
The system shown in the Functional Block Diagram is configured for a 1.8 V output using a 10 mH inductor. At the beginning
of a cycle, the 1 MHz oscillator enables an SR latch, enabling the
internal 1 A power switch. The current sense amplifier and the
protection logic block monitor the current flowing between the
IN and SW pins. The switch is turned off when the current
reaches a level determined by the protection logic block or
PWM comparator, whichever is lower. The error amplifier
measures the output voltage through an external resistor divider
tied to the FB pin. This amplifier servos the switch current to
regulate the FB pin voltage to 1.245 V. An internal regulator
provides power to the control circuitry. The COMP pin can be
used to shut down the ADP3088. When pulled low, it turns off
the internal regulator, thus biasing down the chip, reducing the
input current, and disconnecting the output from the input.
Antisaturation circuitry is used to drive the switch to the edge of
saturation. This allows the driver to quickly switch at 1 MHz
and maintain good efficiency. For improved efficiency, the DRV
pin may be connected to the output provided that the input
voltage is at least 1 V greater than the output.
Run/Stop Comparators
LE
This block creates the 1 MHz signal sent to the SR latch that is
used for the switching frequency. It also takes the FB voltage
and decides when to go into wake-up mode from power saving
mode. The decision to induce the power saving mode is based
on the duty ratio. During steady-state continuous operation, the
duty ratio of a PWM buck regulator is simply a function of the
input/output voltage ratio, with second-order effects including
the voltage drop of the internal switch and the external diode.
Once the load drops to a certain point, discontinuous operation
occurs, and the duty ratio begins to modulate to maintain
regulation. In the ADP3088, the regulator goes to sleep when
the integrated duty ratio measurements drop to less than half of
the minimum expected integrated duty ratio. The minimum
expected duty ratio occurs at the maximum input voltage and
the minimum output voltage in continuous mode operation.
Reference
B
SO
If the output load increases, the error amplifier will detect a
lower voltage on the FB pin via the resistor divider on the output
and send a signal to the PWM comparator to increase the on time
of the switch. This in effect increases the duty cycle and provides
more current to drive the increased load during the transient
event until a new operating point is established.
PWM Comparator
The PWM comparator looks at the signal from the current
sense amplifier and the error amplifier to determine the correct
switch-on time to regulate the output voltage under a given load.
The ADP3088 incorporates an internal band gap reference,
including curvature correction for an extremely low temperature
coefficient. The reference can be disabled by grounding the
COMP pin, which also turns off the bias for the rest of the chip.
Error Amplifier
Soft Start Timer
The soft start will prevent saturating the inductor, which could
cause uncontrolled overshoot of the output voltage and electrical
stress to the system at startup. When first powered up, an internal
soft start capacitor is discharged and the soft start circuitry
provides a gradually decaying offset to the error amplifier to
prevent it from saturating and from commanding the maximum
switch current to charge the output capacitor. The output
voltage approaches the final regulation voltage with a smooth
exponential decay. This will reduce electrical stress to the system.
O
The error amplifier provides a control voltage to the PWM stage
to set the peak inductor current that sets the output current of
the regulator. It is a gm amplifier in that its output is a current to
the COMP pin.
Protection Logic
The protection logic block provides current limit and
overtemperature protection. The overtemperature protection is
enabled when the temperature of the chip exceeds a specified
preset temperature; the switch will be disabled until the temperature drops below a specified level, then normal operation will
resume. The thermal shutdown only stops switching, but it does
not put the chip into power saving mode, nor does it reinitiate soft
start. As the chip cools slightly, it will rapidly cycle in and out of
thermal shutdown, maintaining the die temperature at 160∞C but
allowing the output voltage and current to swing up and down.
Output
The output stage contains the bipolar power switch and the
circuits necessary to switch it on and off quickly. The pass
switch is driven to the edge of saturation, and the result is a fast
switching response and low switch resistance. For improved
efficiency, the DRV pin may be connected to the output, provided
that the input voltage is at least 1 V higher than the output.
This will send the current needed to drive the bipolar switch to
the output load instead of routing it to ground. For some VIN
and ILOAD configurations, the DRV pin must be grounded for
reliable operation.
–8–
REV. C
ADP3088
APPLICATION INFORMATION
Output Voltage Setting
junction to case or ambient, as desired, to determine the internal
temperature rise.
In its standard usage, the output voltage of the ADP3088 is
programmed to a desired fixed value by a resistor divider from
the output voltage into the feedback node, the FB pin, at which
node the control loop ensures regulation at the reference level,
VREF. The divider should be designed to satisfy the formula
If the input voltage were so much higher than the output voltage
that it required an average duty ratio less than an internally
preset threshold, then power savings mode (PSM)—which is
characterized by periodic shutdown and wake-up of the device
that reduces average quiescent current—would be active for all
load conditions rather than only at lighter loads, for which it is
intended. PSM operation is characterized by low frequency
ripple on the output that appears similar to the behavior of a
hysteretic regulator. This is usually not a factor for consideration and may be ignored if PSM operation is acceptable for all
load conditions. But in case it is relevant, the following recommendation is offered:
(1)
where RA is the upper divider resistor (between the output and FB)
and RB is the lower one (between FB and ground). RA and RB
are recommended to have values in the range of 2 kW~200 kW and
are likely to require a 1% tolerance or better to attain acceptable
output voltage tolerance.
VIN <
VO + VF
DPSM( MAX )
(3)
It is not possible to prevent the duty ratio from tending toward
zero in nonsynchronous buck converters below a certain minimum
load current level called “borderline current” or “critical current”
for the power converter. That corresponds to the inductor
ripple current reaching zero at its bottom peak, sometimes called
the “valley current.” If PSM activation strains the lower regulation
limit due to the hysteretic ripple, the output voltage can be offset
slightly upward by readjusting the nominal voltage setpoint with
the resistor divider.
LE
In less conventional applications described separately, the resistor
feedback configuration can be modified or tapped with other
resistors to affect current flow into the FB node that, in turn,
influences the output voltage. Even a switched voltage can be
summed into the FB node as long as it is sufficiently integrated
and does not intolerably compromise the transient response. This
latter application is considered further below, for an application for
powering a DSP.
TE
Ê
R ˆ
VOUT = VREF ¥ Á1 + A ˜
RB ¯
Ë
Input Voltage, Power Dissipation Considerations, and
Power Savings Mode
The input voltage range is not typically considered a critical
parameter for electrical functionality, but there are several
considerations, upon which there is further elaboration below:
B
SO
1. VIN must never exceed the maximum rated voltage.
Even though a buck converter may have a low dropout voltage
that allows the static regulation to be maintained as the input
voltage drops near the output voltage, in buck converters, the
slew rate limitation of the inductor current can compromise the
dynamic regulation in response to the load current step increases.
That is because the maximum rate the current can be increased
to in the inductor is proportional to the voltage available to
impress across it, which is compromised as the input voltage
reduces toward the output voltage. This is not a limitation of
the device but of buck converters in general. The limitation is
considered part of the output filter design, although it could
also be considered in terms of a minimum acceptable input
voltage for a given output filter that will ensure that the dynamic
response is acceptably maintained.
2. VIN must be within the specified operating range when normal
operation is expected.
3. VIN must be greater than VOUT by at least the specified headroom when dc regulation is expected.
4. VIN, if not sufficiently greater than VOUT, may limit the large
signal transient response of a buck converter.
5. VIN, if much greater than VOUT, may give rise to such a low
duty ratio that it activates power savings mode even at static
higher load conditions or upon dynamic load changes when
it is not desired.
O
6. VIN affects the device power dissipation (a lower value causes
higher dissipation), which in turn affects die temperature
that must be kept below a maximum rating.
The lowest input voltage together with the maximum output
voltage and maximum current create the conditions for the
maximum power dissipation in the device, which determine the
maximum temperature rise that should be checked against the
maximum junction temperature rating. The formula for maximum
power dissipation in the device is given by
PDMAX =
VO + VF @ IO , MAX
VIN
¥ IO , MAX ¥ VSW @ IO , MAX
(2)
where VF is the diode forward voltage drop and VSW is the drop
across the internal switch and current sensing resistor that
appears between the VIN and SW pins of the ADP3088 during the
on state of the switch. Both of these variables can be approximated
from a combination of worst-case specifications and typical graphs.
Multiply the power dissipation by the thermal resistance from
REV. C
Output Filter Components
In most applications, it is desirable to use the smallest inductor
value that does not introduce practical problems, since this tends
to yield the lowest cost inductor. One reason for using an even
larger inductor than the minimum tolerable might be to reduce
the output ripple voltage further. But cost being equal, this is
generally better accomplished with a better quality or proportionally larger output capacitor instead, since a larger inductor
degrades the large signal transient performance capability.
A conservative nominal design target value for the inductor of a
typical application circuit is that which creates a peak-to-peak
ripple current, DIL, for the nominal input voltage that is approximately a third of the nominal 500 mA rating of the ADP3088.
The reason for not basing the ripple current on the maximum
load current is concern about the protection. Scaling the ripple
currents with lower load currents would yield higher inductor
values that might give satisfactory operation. However, in order for
overload operation up to the current limit level of the ADP3088
to be satisfactory, it would be necessary to choose an inductor
–9–
ADP3088
rated up to that higher current, which would likely yield an
unsatisfactory inductor size and cost. In any case, having chosen
a target level for DIL, the recommended inductor value is
given by
DIL( MAX ) =
(1 - D) ¥ (VO + VF )
(4)
fSW ¥ DIL
where D is the duty ratio, the suffix indicating continuous
inductor current, and is given by
D=
VO + VF
VIN + VF - VSW
(5)
VIN ( MAX ) - VO – VSW
VIN ( MAX ) + VF – VSW
¥
VO + VF
fSW ¥ L
Performance degradation of the inductor, consisting of some
loss of inductance or excessive power loss, may be encountered
at higher ripple currents, so the ripple current figure, together
with the knowledge of the expected dc current, should be
checked against the specifications of the inductor.
If the ESR of the output capacitor is substantial, as it is likely to
be if an MLC capacitor is not used, then the ripple voltage on
the output, dominated by the ESR, may be substantial and of
concern for regulation specifications. The resistive component
of the output voltage ripple is simply the ripple current multiplied by the ESR, and if it is more than a few millivolts, it will
dominate the output capacitance in contributing to the output
ripple voltage.
VSW and VF are assessed at full load, and fSW is the fixed
switching frequency of the ADP3088. The formula suggests the
calculation of L using a nominal input voltage; for applications
requiring a large range of V IN, the limitations of transient
response at VIN(MIN) versus the higher ripple at VIN(MAX) may
warrant deeper consideration of how to optimize the design. In
applications where load transients are not severe, this conservative
design for L is recommended. A more aggressive minimization of
L is outlined below, but a few restrictions are noted.
The boundary condition of the inductor reaching the borderline
current, IO(BL), can be determined by the formula
VO + VF
VIN - VO - VSW
LE
As inductance becomes smaller, the ripple current becomes
larger. If the ripple becomes particularly large or, as an additional factor, if the load is particularly dynamic, then there is
an increasing possibility that the peak inductor current will
reach the current limit shutdown threshold, ICL, which is not
desirable. This should be avoided by restricting the minimum
inductor value to keep the ripple current moderated. An
alternative way to prevent excessive dynamic overshoot of the
inductor current during a load transient is to reduce the dc
gain of the error amplifier by adding resistive feedback; this
idea is discussed below.
IO(BL ) =
2mH
V + VF
¥ (VO + VF ) ¥ O
– 0.35
V
VIN ( MIN )
(6)
The value used for VIN(MIN) should be only the minimum input
voltage for which normal high performance operation must be
ensured. Note that the value returned for L may be negative, in
which case the restriction does not apply. If the preceding formula
yields a lower inductor value than the conservative recommendation given previously, as is likely for most applications, then
one should consider further limitations to see how low the value
can be minimized.
2 fSW L
¥
(8)
VIN + VF - VSW
Below this output current level, the inductor current will be
discontinuous, and the duty ratio will be modulated to lower
values by factors substantially more than the losses that cause
only a small amount of the modulation in the continuous inductor
current operation. PSM is initiated automatically by a proprietary technique consisting of a duty ratio amplifier with an
internal time constant. As the load current drops well into the
low current region and the duty ratio passes below the threshold
of DPSM for a sufficient time, PSM is activated. The corresponding level of output current is given by
B
SO
O
Another important restriction of the minimum inductor value may
apply. The design should ensure against possible subharmonic
oscillation that can occur in all fixed frequency, current-controlled
switching power supplies when switching at high duty ratios.
The subharmonic oscillation phenomenon will not be explained
here (there are many papers written on the subject) except to
say that it is characterized by alternating high and low duty
ratios, i.e., every other cycle, which produces additional ripple
on the output. To prevent subharmonic oscillation, the following restriction for the minimum inductor value is recommended:
L>
(7)
TE
L=
For a given inductor selection, the earlier formula is rearranged
for convenience and skewed to the worst-case input voltage to
determine the maximum inductor ripple current, DIL.
IO(PSM) =
VIN +VF -VSW VIN -VO -VSW
1
2
¥ DPSM
¥
2
VO +VF
fSW ¥ L
(9)
It can be seen in the formula that this current threshold is inversely
proportional to inductance, so although it is usually not a relevant
concern, it is noted that an aggressively low output inductance
should be avoided to keep the PSM threshold current at a desirably low level.
For the user’s reference, when current is below the borderline
level, the duty ratio is modulated according to the formula
DD = 2 ¥ IO ¥
VO + VF
VIN + VF - VSW
¥
fSW ¥ L
VIN - VO - VSW
(10)
where the suffix indicates that the inductor current is discontinuous.
For controlling the capacitive component of the output ripple
voltage, the following constraint on the minimum output
capacitance should be applied:
CO >
–10–
DIL
8 fSW DVR
(11)
REV. C
ADP3088
where ⌬VR is the tolerable ripple voltage. However, this constraint
is rarely relevant, since the typical capacitance requirement is
driven more by dynamic response requirements than by ripple
concerns. In a typical application circuit, a 10 mF capacitor
produces a capacitive output voltage ripple component of only
about 2 mV. 10 mF is usually sufficient for applications that do not
impose particularly high frequency load transients, and imposes
additional constraints that are elaborated upon in the next section.
Returning to constraints for choosing the output capacitor for
digital loads, another criterion for ensuring sufficient output
capacitance applies.
Load Characterization
where DIO is the maximum high frequency load step. It should
be noted that the formula results strictly from the physical
limitation of the output filter; the compensation must also be
optimized to maximize the response of the control loop to avoid
substantial additional output voltage deviation. The formula
might also be written to describe a maximum inductance for a
given capacitance, but it is generally better practice to choose
the inductor first and add capacitance as needed.
ÈÊ dI L ˆ
˘
ÏV
- VSW - VO
V + VF ¸
and O
, MIN ˙ = < Ì IN ( MIN )
ÍÁ
˝ (12)
˜
dt
L
L MAX ˛
Ë
¯
MAX
ÍÎ
˙˚
Ó
where the < sign indicates a selection of whichever bracket term
is lower.
ÈdIL
˘
MIN ˙
2DVO Í
dt
ÍÎ
˙˚
(13)
The impedance of the output capacitor together with a digital
load also creates some limiting considerations. Series resistance
(ESR) rather than capacitance can be a dominant design
consideration with non-MLC capacitors. If the load is essentially
digital, then the dynamic deviation of the output voltage cannot
be limited to any better than the dynamic load current step
times the ESR. In a formula,
LE
If the slew rate of the load is fast compared to the minimum
inductor slew rate, then the ability of the power converter to
contain the output voltage deviation following a load change is
limited not only by the response of the control loop, i.e., by its
speed to demand zero or maximum duty ratio from the modulator,
but by the power stage as well. In such a case, beginning with
the recognition that output voltage deviation would be substantial
even if the loop response were instantaneous, it can be shown
that one can achieve better overall voltage containment by
degenerating the dc loop gain. As a technical matter, it should be
noted that there will always be some minimum output voltage
deviation downward due to a load step even if the inductor slew is
as fast as the load slew rate. During a switching cycle, the modulator latches its “decision” to turn off the switch. It cannot rescind
that decision, but must instead wait for the next clock cycle to
turn on the switch again and begin slewing the inductor current
upward. This is only a second-order consideration.
2
TE
Optimization of the compensation, as well as the output filter,
requires some knowledge of a fundamental characteristic of the
load. Qualitatively, there are two types of loads with which we
are concerned: fast slew rate and slow slew rate. These slew
rates are assessed with respect to the minimum (absolute)
inductor (current) slew rate, as given by
CO >
DIO
DVO ≥ DIO ¥ ESR
(14)
In such a case, it is often important to choose a capacitor that
controls the ESR to a sufficiently small value. MLC capacitors are
often chosen to practically eliminate the consideration of ESR
entirely.
B
SO
Closing the Loop—Compensation
O
Slow slew rate loads may be referred to simply as conventional
loads, since these have been the more prevalent type of load.
Optimally compensating a conventional load is synonymous
with small signal ac considerations; the objective is to maximize
the ac gain up to the crossover frequency, ensure sufficient
phase margin at the unity gain crossover frequency, and keep
the gain rolling off at higher frequencies to avoid gain margin
problems.
Fast slew rate loads may be referred to as digital loads since,
from the perspective of the power converter, they have a digital
characteristic when changing between two extremes, and also
because such fast slew rates tend to characterize modern digital
circuits, which often feature power management interrupts, i.e.,
interrupt signals used to turn circuitry on and off as needed during
normal system operation. Optimally compensating a digital load
is more a task of impedance matching and dc gain determination than a task of ac loop optimization.
REV. C
The factors determining the response of the power converter
include the feedback input resistor divider, a lead network if
applicable, the transconductance of the error amplifier, its
frequency response limitation (i.e., as adequately modeled by a
capacitance from output to ground), its external termination
impedance (i.e., the compensation that may or may not include
dc feedback), the modulator transconductance, and the power
converter’s termination impedance (i.e., the output capacitor
and load resistance).
Since the ADP3088 has a current-controlled loop, the particular
inductor value does not by first-order consideration affect small
signal stability. However, slew rate limitations, as discussed
earlier, a large signal limitation consideration, set boundaries
that are often relevant for optimizing compensation of the feedback loop. If the compensation of the current control signal, i.e.,
the COMP pin, is designed to promote a current response that is
faster than the inductor current can slew, then when a step load is
applied, the control signal will tend to initially respond in excess
(of the actual current change that is occurring) and then allow an
overshoot of the current and output voltage since it is delayed in
correcting its excess.
For conventional loads, the following describes how the frequency corners (poles and zeros) are positioned or should be
chosen to optimize the loop gain, beginning in the low
frequency spectrum:
–11–
ADP3088
1. The dc loop gain is limited by the applied load resistance and
the output resistance of the error amplifier, but it is not important
to determine how high the dc gain is.
where VOUT is the nominal dc level. This equation together with
the preceding recommendations should suffice to determine
compensation component selection for users familiar with loop
design. This begins with deciding the crossover frequency, fC,
evaluating the impedances at that frequency, and setting the openloop gain, AOL, to unity. By example, fC = 125 kHz is chosen.
2. Two poles in the low frequency spectrum begin to roll off the
gain, one determined by the load resistance and output
capacitor, CO, and the other by the error amplifier’s output
resistance and its termination capacitance, the equivalent
feedback capacitance, and the added compensation capacitance CHF. Determining the location of these poles is not
relevant to the compensation design. It suffices to know that
both are decades below the crossover frequency.
Assuming a well chosen CHF as described previously, in other
words, such that it creates a pole well above crossover or approximately matches the zero of the output capacitor, the following
equation approximates the calculation of the crossover frequency:
fC =
1 + 50k(WA) ¥ f Z ¥ k1
(16)
21k(WA) ¥ k1
TE
where k1 = CO ¥ VOUT/RC and fZ = 1/2p RCCC, the zero frequency
set by the compensation, and the units are shown with the
constants in the equation for clarification.
The preceding equation cannot readily be solved in terms of k1,
but it can be solved closely enough by a few iterations beginning
with values for k1 around 1 ¥ 109 (FA). For the example below, set
the zero about a half-decade below fC as previously advised, that is,
choose fZ ~ fC /÷10 = 40 kHz. Using the previously stated values for
fZ and fC, the value of k1 = 800 p (FA) satisfies the equation. RA
and RB are presumed to be already chosen per earlier guidelines to
set the output voltage. As an example, RA = RB = 10 kW (implying
an output voltage of 2.5 V). Similarly, it is presumed that CO was
chosen; let CO = 15 mF. Then, finally, RC and then also CC can be
determined by rearranging the simple formulas previously given.
The example yields RC ~ 47 kW and CC ~ 82 pF. Assuming an
MLC output capacitor of reasonable quality, the pole setting
capacitor could be chosen to be CHF = 4.7 pF.
LE
3. A lead network is especially desirable for a variable output
voltage application in order to keep a fairly constant crossover
frequency and phase margin for all output voltages. If used,
this lead network simply consists of a capacitor, CFF, in parallel
with the upper feedback divider resistor, RA; this creates a
closely spaced zero/pole pair that provides a gain boost before
crossover so that, above the pole frequency, the loop gain and
phase are similar for all output voltages. If the lead network is
used for a fixed voltage application, the pole should be chosen
to align with the following described zero; for variable voltage
applications, the maximum frequency of the pole should be
placed as high as is comfortable without substantially degrading the phase margin, e.g., not within an octave or, more
conservatively, a half-decade of the crossover frequency.
O
B
SO
4. A zero turns the gain roll-off back to one-pole sufficiently in
advance of the crossover frequency to create ample phase
margin, e.g., half a decade; the zero could feasibly be that of
the output capacitor itself, i.e., the zero formed by the ESR
and the capacitance, CO, but that is both unlikely (since the
zero frequency will likely be higher than where the loop zero is
desired) and generally imprudent (since the loop performance
would depend on the stability of the ESR, which often is
poor or unknown). As recommended, the zero, fZ, is created
by an RC circuit terminating the COMP pin (a resistor, RC, in
series with a capacitor, CC), while the capacitance terminating
the error amplifier, CHF, forms a pole, fP, with RC to cancel
the zero of the output capacitor. Or, if the zero is well above
the crossover frequency, as may be the case when using an
MLC output capacitor, that pole is set high enough above
the crossover frequency, again, for example, half a decade,
so that it doesn’t cut substantially into the phase margin at
crossover but still ensures continued gain roll-off so that the gain
margin is acceptably high; note that the previous guidelines
suggest that CC ≥ 10 ¥ CHF.
5. The gain crosses 0 dB (unity) at a crossover frequency that is
typically a tenth and advisably not greater than a fourth of the
switching frequency; one primary reason for this approximate
upper limit being the extra phase margin loss due to the
switching interval that is not predicted by the linear model.
Assuming no lead network is used, the open-loop gain is given by
AOL
ÊV ˆ
600mÁ 2 ˜ ¥ ZCOMP ¥ ZO
ËW ¯
ª
VOUT
(15)
VIN
5V
1F
MLCC
CHF
4.7pF
ADP3088
IN
IN
GND
COMP
CC
470pF
RC
10k
SW
DRV
GND
6.8H
1A
10F
SCHOTTKY MLCC
VOUT
1.5V
RA
10k
FB
RB
48.7k
Figure 2. 5 V to 1.5 V, General-Purpose Application
Another application circuit features a voltage inversion and
regulation design such that the output voltage is negative (see
Figure 3). Negative output voltages are allowed when the input
plus the output voltage does not exceed the rating of the device.
In the voltage inverting configuration, the ground reference of
the ADP3088 is the negative output voltage, and the conventional
output voltage point is tied to ground. Operation is bootstrapped;
the power converter behaves as if the input voltage were equal to
the actual input voltage plus the magnitude of the output voltage
and as if the output voltage were not inverted. This implies that
it is possible to have the input voltage be less than the magnitude
of the output voltage, provided that the input voltage alone is
sufficient to start the operation of the IC, i.e., before the negative
–12–
REV. C
ADP3088
output voltage has been developed. (The circuit in Figure 3
with a –3.3 V output works well over an input range from 2.5 V
to 7.5 V.) Since the ADP3088 features a current-controlled
loop, the feedback effect of essentially boosting the input voltage
atop the output (with respect to the ground connection of the
ADP3088) is reduced to a negligible second-order effect.
CHF
4.7pF
SW
DRV
GND
COMP
CHF =
1A
10F
SCHOTTKY MLCC
GND
FB
CC
220pF
RC
20k
CO ¥ ESR
RFB
(18)
If an MLC capacitor is used for CO, the value of CHF might be
calculated to be less than a few picofarads, in which case it is
recommended to use a 4.7 pF~10 pF capacitor. The formula is
derived from a patented design technique called ADOPT®,
Analog Devices’ Optimal Positioning Technology. This creates
ac and dc impedance matching, and the increased complexity of
the dc regulation design is moderated by the simplicity of the
frequency compensation.
+
RA
10k
+
RB
6.04k
VOUT
– 3.3V
Figure 3. +5 V to –3.3 V, General-Purpose
Inverting Application
Voltage Positioning Designs
In this design approach, at higher currents the output voltage
will be appreciably lower than at the lower currents. This is equivalent to saying that the load regulation appears to be poor.
But, paradoxically perhaps to the user unfamiliar with voltage positioning, the overall containment of the voltage within a
given window will be improved, and that tends to be of particular importance in many highly dynamic loads.
LE
For digital loads, a different compensation technique is recommended that involves implementing “voltage positioning,”
which is now commonly used on CPUs but is equally applicable
to any dynamic device. Voltage positioning is the intentional
and controlled variation of the output voltage with the load
current, such that the power supply appears to have a substantial output resistance. The key to voltage positioning
optimization for a digital load is to degenerate the loop gain
just enough so that the static load regulation allows a similar
voltage deviation with the current as would be the peak voltage deviation, ⌬VO, that could not be avoided in the event
that a step change of the current were to occur even if the
loop response were instantaneous. The reason for even an
instantaneous response in the control loop allowing an output
voltage deviation is that the slew rate of the current in the
output is limited by the inductor, and a corresponding dynamic
burden is placed on the output capacitor to maintain the output
voltage. Therefore, inductor value minimization is desired both
for concern over its size and cost and also to maximize the slew
rate of the current to the output so that a smaller output capacitor is needed.
TE
1F
MLCC
IN
IN
Having chosen this design approach, the series RC of the compensation network can be removed, and the single remaining
capacitor, CHF, should be increased to approximately
4.7H
ADP3088
VIN
5V
higher than VREF, which would result in a slight downward shift
of the nominal output voltage.
B
SO
The application circuit in Figure 4 features a 3.3 V input and a
2.5 V output at 100 mA~400 mA, which constrains the output
voltage within a ~100 mV range with only a 4.7 mF output
capacitor, even when the load slew rate is extremely fast. This
does not include the initial tolerance of the voltage setting
that is separately accounted with voltage positioning designs.
Note that the lower resistor, RB, of the feedback divider is
reduced from the 10 kW value that one would use for a standard
(nonvoltage-positioned) design that had no voltage positioning
resistor RVP.
O
To implement voltage positioning, a resistor, RVP, should be placed
between the COMP and FB pins according to the formula
RVP =
DIO RA
g MOD ¥ DVO
REV. C
ADP3088
SW
IN
IN
1F
MLCC
CHF
4.7pF
DRV
GND
GND
COMP
3.3H
1A
4.7F
SCHOTTKY MLCC
VOUT
2.5V
100 mA– 400 mA
RA
10k
FB
RB
8.75k
RVP
51k
Figure 4. Application Circuit Using Voltage Positioning, Allowing Small Output Capacitance
(17)
where gMOD is the modulator gain and ⌬IO must be assessed
over the entire operating load range as the difference between
the maximum and minimum load. CO must be chosen at least
large enough to support the targeted ⌬VO according to the previous
formula governing the relationship among the minimum output
capacitance, voltage deviation, and load current. In order to ensure
that the output voltage will be constrained within the limitations
of ⌬VO, the limitations noted earlier for PSM hysteretic ripple are
applicable in the operating load range and ESR. Also, an experimental adjustment downward to the value of RB may be needed,
since the dc bias point of the COMP node is usually a little
VIN
3.3V
Extra-Low Voltage Outputs
Some newer power management applications require voltage levels
below the normal adjustable voltage range of the ADP3088, i.e.,
below 1.25 V. Such applications can be accommodated using
the ADP3088 by modifying the application circuit to sum in a
resistor-weighted portion of another regulated system voltage,
e.g., 3.3 V, to the feedback node (FB). The tolerance of the
ADP3088’s output voltage will increase by an amount proportional to the tolerance of the summed in-system voltage times
the ratio of the conductance from that node to that of the output
voltage. The example in Figure 5 shows an implementation
of this technique together with another special implementation
described in the following section. The resistor RTT sums from a
–13–
ADP3088
2.5 V system voltage to the FB node that will reduce the output voltage according to the formula
DVOUT = (VREF -VTT )
RA
RTT
The design of either parallel bit or PWM type of voltage control
must consider whether the interface node(s), from parallel
switched bits or a single PWM signal, has an active pull-up state
(in which case it must be to a known voltage) or a passive pull-up
(open drain) that floats up to the FB node voltage, 1.25 V, in its
high state. If at least the lower extreme of the desired output
voltage range must be lower than 1.25 V, either technique can
be combined with the technique for lowering the output voltage
below 1.25 V. Such an example of an application having this
requirement is the Blackfin® DSP. Figure 5 shows an implementation of this technique.
(19)
Dynamic Voltage Control
Some newer power management applications also require an
ability to adjust the voltage being delivered to a load during
operation. Although there is no integration of this feature in the
ADP3088, it can readily be accommodated with a few components. Dynamic voltage control can be implemented either by
parallel bus control or by PWM. In both cases, the output voltage
is modified by summing either switched bits with, presumably
binary, weighting resistors or a switched PWM node via a single
resistor into the FB pin. (The switched PWM node refers to an
external PWM control signal, not the switched node of the power
converter itself.) Since the PWM technique modulates a current
into the FB node, it is necessary both to integrate that signal
and to avoid slowing down the response of the power converter
to the output voltage transitions. This can be accomplished by
placing a capacitor between the output voltage and the feedback
node, which serves to provide a zero/pole pair in the main regulation loop and appears as an integration pole to the PWM signal.
Input Voltage: 4.75 V ~ 7.5 V
Output Voltage: 0.9 V ~ 1.5 V
TE
Dynamic voltage control interface technique: PWM, active
high to VIO
System voltage used for lowering output voltage below
1.25 V: VTT = VIO = 2.5 V
LE
Maximum output current: 700 mA
ADP3088
VIN
~5V TO 8V
CHF
10pF
[email protected]
SW
1N5817
IN
GND
DRV
CC
470pF
RC
20k
COMP
310F
MLCC
VOUT
0.9V TO 1.5V
@700 mA
GND
B
SO
2.2F
MLCC
IN
FB
CFF
2.2nF
RA
10.0k
RTT
287k
VTT 2.5V
PWM 0V TO 2.5V
RPWM
41.2k
O
Figure 5. Blackfin DSP Application
–14–
REV. C
ADP3088
OUTLINE DIMENSIONS
8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
3.00
BSC
8
5
4.90
BSC
3.00
BSC
1
4
PIN 1
1.10 MAX
0.15
0.00
0.38
0.22
COPLANARITY
0.10
0.23
0.08
SEATING
PLANE
TE
0.65 BSC
8
0
0.80
0.60
0.40
O
B
SO
LE
COMPLIANT TO JEDEC STANDARDS MO-187AA
REV. C
–15–
ADP3088
Revision History
Location
Page
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Changes to TPC 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Changes to Equation 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Changes to Equation 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Changes to Equation 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4/03—Data Sheet changed from REV. A to REV. B.
TE
Equation 1 edited . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
10/02—Data Sheet changed from REV. 0 to REV. A.
Equation 6 edited . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Equation 16 edited . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
O
B
SO
LE
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
–16–
REV. C
C02832–0–1/04(C)
1/04—Data Sheet changed from REV. B to REV. C.