AN-793 APPLICATION NOTE One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106 • Tel: 781/329-4700 • Fax: 781/461-3113 • www.analog.com ESD/Latch-Up Considerations with iCoupler® Isolation Products by Rich Ghiorse INTRODUCTION Analog Devices iCoupler products offer an alternative isolation solution to optocouplers with superior integration, performance, and power consumption characteristics. An iCoupler isolation channel consists of CMOS input and output circuits and a chip scale transformer (see Figure 1). Because the iCoupler employs CMOS technology, it can be more vulnerable to latch-up or electrostatic discharge (ESD) damage than an optocoupler when subjected to system-level ESD, surge voltage, fast transient, or other overvoltage conditions. Components vs. Systems Simply put, a component is a single integrated device with interconnects while a system is a nonintegrated device built from several interconnected components. In almost all cases the distinction between a component and a system is obvious. However, the differences between component and system tests may not be so obvious. Further, component specifications may not directly indicate how a device will perform in system - level testing. ESD testing is a good example of this. ESD, surge, burst, and fast transient events are facts of life in electronic applications. These events generally consist of high voltage, short duration spikes applied directly or indirectly to a device. These events arise from interaction of the device to real-world phenomena, such as human contact, ac line perturbations, lightning strikes, or common-mode voltage differences between system grounds. Figure 1. ADuM140x Quad Isolator This application note provides guidance for avoiding these problems. Examples are presented for various system-level test configurations showing mechanisms that may impact performance. For each example recommended solutions are given. Later this year, Analog Devices is introducing hardened versions of most iCoupler products that will have improved immunity to latch-up and electrical overstress (EOS). This new product family, the ADuM3xxx series, will be pin - compatible with the existing ADuM1xxx series products and will offer identical performance specifications. Both product families will continue to be made available. REV. 0 Component-level ESD testing is most useful in determining a device’s robustness to handling by humans and automated assembly equipment prior and during assembly into a system. Component-level ESD data is less useful in determining a device’s robustness within a system subjected to system-level ESD events. There are two reasons for this. • System - and component- level ESD testing have different objectives. Component-level testing seeks to address conditions typically endured during component handling and assembly. System-level testing seeks to address conditions typically endured during system operation. • The specific conditions a component is subjected to during system-level testing can be a strong function of the board/module/system design in which it resides. For example, long inductive traces between a system and component ground can actually impose a more severe voltage transient onto a component than is imposed on the system at the test point. AN-793 Table I summarizes the ESD test results for the ADuM140x quad isolator. One might conclude from Table I that iCouplers can only be used in systems with ESD ratings of < 4 kV. In reality it is quite common for iCouplers to be used in systems that pass 15 kV ESD levels per IEC 61000 - 4 -2. VDD1 First Fail Voltage (V) Human Body Model 3,500 4,000 Field Induced Charge Device Model 1,500 2,000 Machine Model 200 400 Latch-Up in CMOS Devices Inherent in a CMOS process are parasitic PNP and NPN transistors configured as silicon control rectifiers (SCR). Latch-up is a condition that comes about when this parasitic SCR is triggered. This causes a low resistance to appear from V DD to ground, and a subsequent large current to be drawn through the device. This excessive current lays open the possibility of damage due to EOS. Damage caused by latch-up can range from complete destruction of the device to parametric degradation. More insidious are latent failures that could affect operation later in a system’s lifetime. An excellent treatise on the subject of latch-up in general can be found in the Analog Dialogue 35 - 05 (2001) article, “Winning the Battle Against Latch- Up in CMOS Switches.” While this article specifically addresses problems with CMOS switches, it is generally applicable to all CMOS devices, including iCouplers. The use of ceramic bypass capacitors to minimize supply noise between VDD and ground is highly recommended in all iCoupler applications. These should have a value between 0.01 F and 0.1 F and be placed as close as possible to the iCoupler device. Even with adequate bypassing, latch-up problems may still occur in some applications. Placing a 200 resistor in series with VDD is also helpful. This limits the supply current to 25 mA in 5 V applications, which is below the latch-up trigger current. However, depending on the supply current being drawn, this series resistance can reduce the supply voltage at the iCoupler to an unacceptable level. This is most likely to be a concern when operating at high data rates that involve high supply currents. Table II. Common System Tests Used in iCoupler Applications Test Voltage (V rms)1 IEC 61000-4-2 ESD 2,000 to 15,000 IEC 61000-4-4 Fast Transient/Burst 500 to 4,000 IEC 61000-4-5 Surge 500 to 4,000 1 C1 L4 Figure 2. iCoupler Model Useful in Analyzing System Designs To accurately predict the performance of iCouplers in a system, the designer needs to understand the nature of the system tests and weigh how they impact the iCoupler at the component level. Table II lists common system-level tests used in iCoupler applications. Several examples of these tests will be discussed later. Purpose GND2 L3 For complete information on Analog Devices ESD testing, refer to the Analog Devices Reliability Handbook. Test Standard VO GND1 Table I. ADuM140x ESD Test Results First Pass Voltage (V) L2 VIN The difference is in the test methods: The component-level tests call for direct application of ESD events to the pins or body of an unpowered device, while system-level tests call for application ESD events to various locations in the system accessible to external ESD occurrences. Furthermore, the specific waveforms used in component-level and system-level testing differ. ESD Model VDD2 L1 IEC 61000-4 tests include compliance levels; the test voltages shown are the ranges for level 1 (lowest) through level 4 (highest) compliance. iCoupler Model for Analyzing System Test Performance Figure 2 shows a circuit model of an iCoupler which is useful to understand the impact of system-level testing. Inductors L1, L2, L3, and L4 are due largely to package pins and bond wires, while capacitor C1 is due to the stray capacitance across the isolation barrier. The inductance values are approximately 0.2 nH. The capacitance value is approximately 0.3 pF per iCoupler channel. Usually the mechanism that causes latch-up is an overvoltage condition beyond the part’s absolute maximum rating (>7.0 V or <–0.5 V for most iCoupler products). Once an iCoupler is integrated into a system the source of the overvoltage is not always clear. However, it is usually manageable once understood. –2– REV. 0 AN-793 IEC 61000-4-2 ESD Testing A block diagram of the IEC 61000- 4-2 ESD test is shown in Figure 3. In this test, ESD contact or air discharges are applied at various points on a system chassis. This gives rise to several mechanisms that can cause latch-up problems for an iCoupler. These include injected current via one of the iCoupler grounds as well as inductive coupling from ESD currents in the system chassis or in printed wiring board traces. instance the chassis impedance, ZCHASSIS, gives rise to an injected current during an ESD discharge. This current flows in the loop formed by L3, C2, L4, and C STRAY. C STRAY is the capacitance from the shield of an output cable to chassis ground. The larger the value of CSTRAY, the larger the injected current and the consequent internal noise voltage appearing across L4. If this voltage forces GND2 beyond its absolute maximum rating, then latch-up could occur. SYSTEM CHASSIS The following measures are recommended to avoid current injection difficulties: • Minimize the chassis impedance to ground. • Minimize CSTRAY, the cross-isolation barrier capacitance. CHASSIS GROUND • If possible place a 200 resistor in series with VDD2 to limit latch-up trigger current. • Place a 50 resistor between chassis ground and GND1. This reduces IINJECTED and ultimately VNOISE. ESD ZAP TO 15kV AIR OR CONTACT DISCHARGE • Place a transient absorbing Zener diode from the connection to chassis ground. This clamps the noise voltage to within the Zener voltage. ESD SOURCE Inductive Coupling from ESD Current One consideration is the possibility of inductive coupling from ESD current present in the iCoupler printed wiring board or system chassis. Inductive pickup on iCoupler transformers from external magnetic fields is not a problem in the vast majority of applications; however, there have been rare instances in IEC 61000- 4-2 ESD testing where this phenomenon has been noted. Solutions to this problem are straightforward. Figure 3. IEC 61000-4-2 ESD Test Injected ESD Current The first possible mechanism for latch- up is one in which excessive ESD current is injected into an iCoupler ground. Figure 4 shows a situation where an iCoupler is used as a floating output (the same mechanism can be present in a floating input configuration). In this ESD ZAP 200 RESISTOR TO LIMIT LATCH-UP TRIGGER CURRENT USE 50 RESISTOR TO DECREASE IINJECTED VDD1 VDD2 DIN 50 GND1 DOUT L4 L3 200 VLOGIC GND2 +VNOISE– ZCHASSIS C2 IINJECTED CSTRAY CHASSIS/EARTH GROUND ADDITION OF TRANSIENT ABSORBER TO CLAMP NOISE VOLTAGE AT GND1 PIN MINIMIZE SIZE OF CSTRAY, COUPLING FROM OUTPUT CABLE SHIELD TO CHASSIS GROUND Figure 4. Injected ESD Current Mechanism and Recommended Solutions REV. 0 –3– AN-793 Figure 5 shows an ESD test setup and the paths of currents IESD and I1 caused by an ESD strike. These currents can be very large, and induce large magnetic fields on the application printed wiring board and chassis. The placement and geometry of ground traces, ground circuit connections, board location, and orientation within the chassis are all critical in minimizing inductive pickup from the radiated magnetic fields. WORST ORIENTATION iCoupler PACKAGE CHIP SCALE TRANSFORMER VDD + VINDUCED – Figure 5a shows a poor layout which uses a thin ground trace near the iCoupler. It also shows a ground loop that allows some of IESD to flow through the board ground circuit as I1. Close proximity and narrow trace widths increase the magnitude of the induced magnetic field. If strong enough, this can cause iCoupler latch-up as discussed above. Figure 5b shows an optimal design using a wide ground plane further away from the iCoupler and a single point ground which prevents IESD from flowing in the board ground circuit. When designing ground circuits, it is always helpful to think in terms of current paths. MAGNETIC FIELD ORIENTATION RIGHT ANGLE TO TRANSFORMER WINDINGS MAXIMIZES VINDUCED BEST ORIENTATION PC BOARD CHIP SCALE TRANSFORMER When designing the chassis for the system, it is important to minimize impedance of the chassis ground connection. It is also helpful to mount printed circuit boards as far away from the edge of the chassis as possible, and to have the board oriented so that iCouplers are parallel to any radiated magnetic fields as depicted in Figure 6. MAGNETIC FIELD ORIENTATION PARALLEL TO TRANSFORMER WINDINGS MINIMIZES VINDUCED iCoupler PACKAGE SYSTEM CHASSIS Figure 6. External Magnetic Field Interaction with iCoupler Tranformers APPLICATION BOARD If inductive coupling is a problem, recommended solutions include the following: FIGURE 5a POOR GROUND LAYOUT iCoupler I1 POOR GROUND TECHNIQUE: 1. GROUND LOOP ALLOWS PART OF THE LESD TO FLOW THROUGH BOARD GROUND 2. THIN GROUND CONDUCTOR WILL RADIATE MAGNETIC FIELD AND CAUSE PICKUP IN iCoupler TRANSFORMERS I2 IESD ESD ZAP POINT APPLICATION BOARD GROUND PLANE I1 IESD Properly design ground system to avoid ground loops. • Use ground plane instead of single narrow traces. • Orient print wiring boards away from chassis boundaries. • If possible, orient the iCoupler parallel to external magnetic fields as depicted in Figure 6. IEC 61000-4-5 Surge Testing Surge testing per IEC 61000 - 4 -5 is another common system - level test in industrial and instrumentation applications. Figure 7 depicts an iCoupler in a surge test configuration showing associated bypass and stray capacitances. V TEST is the surge test voltage appearing between earth ground and the board’s local ground GND1. This test typically has test voltages up to 4 kV. As shown in Figure 7, if excessive stray capacitance exists across the isolation barrier, the voltage at VDD1 can be driven above its absolute maximum rating and damage the iCoupler. SYSTEM CHASSIS iCoupler • FIGURE 5b GOOD GROUND LAYOUT GOOD GROUND TECHNIQUE: 1. USE OF WIDE GROUND PLANE LOWERS INDUCTANCE AND WILL LOWER NOISE 2. NO LOOP SO LESD FLOWS THROUGH THE CHASSIS ONLY ESD ZAP POINT Figure 5. Contrasting Examples of Board Ground Circuits –4– REV. 0 AN-793 ���� CBP1 should be increased to 0.1 F to reduce the coupled voltage to 0.4 V—a much safer value. Do the following for best results: �� • Minimize capacitances between iCoupler floating grounds and system grounds. • Provide adequate bypassing with good quality ceramic bypass capacitors with values large enough to minimize the induced voltage at iCoupler supply pins. • Ensure VDD1 and VDD2 are free from noise spikes. • If possible add a 200 resistor in series with VDD1 to limit parasitic SCR trigger current. • Use a transient-absorbing Zener diode across VDD1. �� ���� �� �� ��� ���� �� ���� ���� ���� �� �� �� �� ����� Figure 7. iCoupler in IEC 61000-4-5 Surge Test Setup Figure 8 shows the model reduced for easier analysis of circuit. The simplified schematic ignores negligible effects of lead inductances and lumps CSTRAY as a computed element (Equation 1). �������������� ��������� �������� �������� IEC 61000-4-4 Fast Transient and Burst Testing Example Fast transient and burst testing per IEC 61000 - 4 - 4 is another common system - level test that can cause problems if good design practice is not followed. This test couples high voltage fast edge signals onto system ac mains. �� ���� i������� ���� ������������� ��������������� ������������� COUPLED TRANSIENT NOISE THROUGH CSTRAY TO VDD1 OR VDD2 ���� �� ���� BOARD WITH iCoupler ������ ���� ���� TRANSFORMER WINDING CAPACITANCE CSTRAY ����� VDD1 SYSTEM POWER SUPPLIES Using Figure 8, and ignoring inductances, CSTRAY is given as CSTRAY × C5 C = C4 + BP2 C BP2 + C5 C STRAY C STRAY + C BP1 (1) Figure 9. IEC 61000-4-4 Fast Transient/Burst Test Setup Figure 9 shows a simplified circuit diagram of a fast transient test setup. The main mechanism for problems here is interwinding capacitance of the system power supplies transformers. This stray capacitance can couple fast transient signals from the ac mains to the iCoupler supply pins. If the voltage impressed on the iCoupler supplies is high enough, then maximum rated supply voltages can be exceeded and latch-up is possible. (2) Equation 2 shows that making CSTRAY small compared to CBP1 can minimize V X. For example, with a test voltage of 4 kV and a bypass capacitance of 0.01 F, even the moderate amount of 10 pF of stray capacitance would create a coupled VDD1 voltage of 4 V. When imposed on top of the normal supply voltage, this would induce latch-up. In such a situation the bypass capacitance REV. 0 COUPLED TRANSIENT NOISE ONTO AC LINE RECOMMENDED SOLUTION TRANSIENT ABSORBER The coupled voltage V X is calculated using a simple capacitor divider VX = VTEST × COUPLING NETWORK AC LINES VDD2 Figure 8. Simplified Equivalent Circuit of Figure 7 EFT/BURST GENERATOR The best preventive measures in this example are: –5– • Use low interwinding capacitance supplies. • Minimize supply noise by using adequate bypassing. • Use Zener diode clamps across the iCoupler supplies to clamp noise voltages. AN-793 New ESD-Hardened iCouplers To better support the use of iCouplers in harsh ESD applications, Analog Devices is introducing a new line of iCoupler products. The ADuM3xxx series takes advantage of improved circuit designs and layouts to increase iCoupler robustness to ESD events. These new products are pin- and specification- compatible with their ADuM1xxx series counterparts. For many installed applications, the standard iCoupler products work just fine. Therefore, both the standard ADuM1xxx and the ESD-hardened ADuM3xxx series will continue to be offered. Inside the ADuM3xxx Series iCoupler Several design enhancements are incorporated into the ADuM3xxx series iCouplers to create a more robust device. Specific improvements include: The part numbering for the ADuM3xxx series is analogous to that of the standard product except that only Pb-free models are provided. Table III gives examples of the part numbering for the two product families. • Areas of high electric field concentration eliminated using 45 corners; on metal traces. • ESD protection cells added to all input/output interfaces. • Key metal trace resistances reduced using wider geometry and paralleling of lines with vias. • The SCR effect inherent in CMOS devices minimized by use of guarding and isolation techniques between PMOS and NMOS devices. • Supply pin overvoltage prevented with larger ESD clamps between each supply pin and its respective ground. Table III. Part Numbering Examples for Various Standard and ESD-Hardened iCoupler Products Standard Products ESD-Hardened Products ADuM1100ARWZ ADuM3100ARWZ ADuM1201ARWZ ADuM3201ARWZ ADuM1301BRWZ ADuM3301BRWZ ADuM1402CRWZ ADuM3402CRWZ CONCLUSION By following the guidelines set forth in this application note, designers can be assured of success in their application of iCouplers at the system level. Problems with system-level tests can be anticipated using the lumped-element circuit model presented for the iCoupler. With this model and a good understanding of the various system tests, designers can avoid problems by employing the preventive techniques suggested in this document. In situations where the recommendations cannot be implemented due to cost, system design, or other considerations, the new ADuM3xxx iCoupler provides an alternative method of avoiding ESD/latch-up problems. –6– REV. 0 –7– AN05547–0–7/05(0) © 2005 Analog Devices, Inc. All rights reserved. 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