Revised September 2000 74F269 8-Bit Bidirectional Binary Counter General Description Features The 74F269 is a fully synchronous 8-stage up/down counter featuring a preset capability for programmable operation, carry lookahead for easy cascading and a U/D input to control the direction of counting. All state changes, whether in counting or parallel loading, are initiated by the rising edge of the clock. ■ Synchronous counting and loading ■ Built-in lookahead carry capability ■ Count frequency 100 MHz ■ Supply current 113 mA typ ■ 300 mil slimline package Ordering Code: Order Number Package Number Package Description 74F269SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F269SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Function Table PE CEP CET U/D L X X X H H X X H X H X H L L H H L L L H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = Transition LOW-to-HIGH CP Function Parallel Load All Flip-Flops Hold Hold (TC Held HIGH) Count Up Count Down © 2000 Fairchild Semiconductor Corporation DS009510 www.fairchildsemi.com 74F269 8-Bit Bidirectional Binary Counter April 1988 74F269 Unit Loading/Fan Out Pin Names U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL Description P0–P7 Parallel Data Inputs 1.0/1.0 20 µA/−0.6 mA PE Parallel Enable Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA U/D Up-Down Count Control Input 1.0/1.0 20 µA/−0.6 mA CEP Count Enable Parallel Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA CET Count Enable Trickle Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA CP Clock Input 1.0/1.0 20 µA/−0.6 mA TC Terminal Count Output (Active LOW) 5.0/33.3 −1 mA/20 mA Q0–Q7 Flip-Flop Outputs 50/33.3 −1 mA/20 mA Logic Diagram www.fairchildsemi.com 2 Recommended Operating Conditions Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +150°C Supply Voltage 0°C to +70°C +4.5V to +5.5V −0.5V to +7.0V VCC Pin Potential to Ground Pin Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Current Applied to Output in LOW State (Max) twice the rated IOL (mA) DC Electrical Characteristics Symbol Parameter Min Typ Max VCC VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V Min V Min 0.5 V Min IOL = 20 mA 5.0 µA Max VIN = 2.7V 7.0 µA Max VIN = 7.0V 50 µA Max VOUT = VCC V 0.0 3.75 µA 0.0 −0.6 mA Max VIN = 0.5V −150 mA Max VOUT = 0V Output HIGH Voltage VOL Output LOW Voltage IIH Input HIGH Current IBVI Input HIGH Current 10% VCC 2.5 5% VCC 2.7 V Conditions Input HIGH Voltage VOH 2.0 Units VIH 10% VCC Breakdown Test ICEX Output HIGH Leakage Current VID IOD Input Leakage Test 4.75 Output Leakage Circuit Current Recognized as a HIGH Signal Recognized as a LOW Signal IIN = −18 mA IOH = −1 mA IOH = −1 mA IID = 1.9 µA, All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded IIL Input LOW Current IOS Output Short-Circuit Current ICCH Power Supply Current 104 125 mA Max VO = HIGH ICCL Power Supply Current 113 135 mA Max VO = LOW −60 3 www.fairchildsemi.com 74F269 Absolute Maximum Ratings(Note 1) 74F269 AC Electrical Characteristics Symbol Parameter Min TA = +25°C TA = 0°C to +70°C VCC = +5.0V VCC = 5.0V CL = 50 pF CL = 50 pF Typ Max Min Units Max fMAX Maximum Clock Frequency 100 85 tPLH Propagation Delay 3.5 8.0 3.5 MHz tPHL CP to Qn (Count-Up) 4.5 10.5 4.5 11.0 tPLH Propagation Delay 3.5 7.5 3.5 10.0 tPHL U/D to TC 4.5 7.5 4.5 11.0 tPLH Propagation Delay 3.5 7.0 3.5 10.5 tPHL CET to TC 3.0 10.5 3.0 11.5 tPLH Propagation Delay 4.5 10.0 4.5 10.5 tPHL CP to TC 5.0 10.0 4.5 10.5 tPLH Propagation Delay 3.5 10.5 3.5 11.0 tPHL CP to Qn (Count-Down) 4.5 10.5 4.5 11.0 tPLH Propagation Delay 3.5 7.0 3.5 10.0 tPHL CP to Qn (Load) 4.0 7.0 4.0 7.0 7.0 ns ns ns ns ns ns AC Operating Requirements TA = +25°C Symbol TA = 0°C to +70°C VCC = +5.0V Parameter Min Max VCC = 5.0V Min tS(H) Setup Time, HIGH or LOW 3.5 4.0 tS(L) Data to CP 3.0 3.0 tH(H) Hold Time, HIGH or LOW 1.0 2.0 tH(L) Data to CP 1.0 1.0 tS(H) Setup Time, HIGH or LOW 5.5 6.5 tS(L) PE to CP 5.5 6.5 tH(H) Hold Time, HIGH or LOW 0 0 tH(L) PE to CP 0 0 tS(H) Setup Time, HIGH or LOW 6.0 6.5 tS(L) CET or CEP to CP 8.0 9.0 tH(H) Hold Time, HIGH or LOW 0 0 tH(L) CET or CEP to CP tW(H) Clock Pulse Width, HIGH or LOW tW(L) 0 0 3.5 3.5 3.5 4.0 tS(H) Setup Time, HIGH or LOW 8.0 9.5 tS(L) U/D to CP 6.0 7.0 tH(H) Hold Time, HIGH or LOW 0.0 0.0 tH(L) U/D to CP 0.0 0.0 www.fairchildsemi.com 4 Units Max ns ns ns ns ns ns 74F269 Physical Dimensions inches (millimeters) unless otherwise noted 28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B 5 www.fairchildsemi.com 74F269 8-Bit Bidirectional Binary Counter Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N24C Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 6