TI TPS5602

TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 – JUNE 1999
D
D
D
D
D
D
D
D
D
D
D
DBT PACKAGE
(TOP VIEW)
Independent Dual Channels
Hysteretic Control for Fast Transient
Response
4.5-V to 25-V Input Voltage Range
Adjustable Output Voltage Down to 1.2 V
Synchronous Rectifier Enables Efficiencies
of >95%
Minimized External Component Count
Separate Standby Control and Over Current
Protection
Low Supply Current . . . 0.8 mA Typ
30-Pin TSSOP
Low Standby Current (1-µA maximum)
EVM Available (TPS5602EVM-121)
INV1
NC
SOFTSTART1
NC
CT
NC
GND
REF
STBY1
STBY2
VCC
COMP
SOFTSTART2
NC
INV2
description
1
30
2
29
3
28
4
27
5
26
6
25
7
24
8
23
9
22
10
21
11
20
12
19
13
18
14
17
15
16
LH1
OUT1_u
LL1
OUT1_d
OUTGND1
TRIP1
VCC SENSE
TRIP2
Vref5
REG5V_IN
OUTGND2
OUT2_d
LL2
OUT2_u
LH2
The TPS5602 is a dual-channel synchronous
NC – No internal connection
buck switch-mode power supply controller
featuring very fast feedback control and minimized component count. By using the hysteretic control method,
it is ideal for high-transient current applications, such as ’C6000 and multiple ’C54x DSPs. The TPS5602 is
designed specifically for DSP applications that require high efficiency. Since both channels are independent,
the up and down power sequencing can be easily achieved by properly setting the standby pins. The wide input
voltage and adjustable output voltage make the TPS5602 suitable for many applications.
typical design
5V
+
C3
D1
GND
R3
R2
C4
L1
C1
OUT1
1.8 V
C7
R5
C2
R6
C8
R1
L2
C5
R4
OUT2
3.3 V
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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• DALLAS, TEXAS 75265
1
TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 – JUNE 1999
AVAILABLE OPTIONS
PACKAGE
TA
TSSOP
(DBT)
TPS5602IDBT
– 40°C to 85°C
TPS5602IDBTR
EVM
TPS5602EVM 121
TPS5602EVM-121
functional block diagram
SFT1
SOFT START1
LH1
INV1
Hysteretic Comp.
OUT1_u
DLY
LL1
1.185 V
Setup trigger
OUT1_d
DLY
OUTGND1
Current Comp.
TRIP1
OSC on
CT
OSC
VccSENSE
Fixed off–time reset
Current
Protection
Trigger
Trigger on
Comp
1.1 V
TRIP2
GND
Setup trigger
Current Comp.
OUTGND2
OUT2_d
UVLO
INV2
DLY
LL2
3.8 V
Hysteretic Comp.
Out2_u
DLY
LH2
1.185 V
VREF5
SFT2
SOFT START2
Vcc
STBY1
Vref
STBY2
REF
2
4.5 V
1.185 V
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• DALLAS, TEXAS 75265
REG5Vin
TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 – JUNE 1999
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
COMP
12
I/O
Voltage monitor comparator input
CT
5
I/O
The oscillator frequency external capacitor connection
GND
7
Control GND
INV1
1
I
CH1 hysteretic comparator inverting input
INV2
15
I
CH2 hysteretic comparator inverting input
LH1
30
I/O
CH2 high-side gate drive boost capacitor input
LH2
16
I/O
CH1 high-side gate drive boost capacitor input
LL1
28
I/O
CH1 high-side drive and current protection
LL2
18
I/O
CH2 high-side drive and current protection
NC
2, 4, 6, 14
OUT1_d
27
I/O
CH1 low-side gate drive output
OUT2_d
19
O
CH2 low-side gate drive output
OUT1_u
29
O
CH1 high-side switch output
OUT2_u
17
O
CH2 high-side switch output
OUTGND1
26
OUTGND2
20
REF
8
O
1.185-V reference voltage output
REG5V_IN
21
I
External 5-V input
SOFTSTART1
3
I/O
CH1 soft start control external capacitor connection
SOFTSTART2
13
I/O
CH2 soft start control external capacitor connection
STBY1
9
I
CH1 standby control
STBY2
10
I
CH2 standby control
TRIP1
25
I
CH1 output current control input
TRIP2
23
I
CH2 output current control input
VCC
Vref5
11
I
Supply voltage input
22
O
5-V internal regulator output
VCCSENSE
24
I
Supply voltage sense input
Output GND 1
Output GND 2
detailed description
vref (1.185 V)
The reference voltage is used for the output voltage setting and the voltage protection (COMP).
vref (5 V)
An internal linear voltage regulator offers a fixed 5-V voltage as the bootstrap voltage so that the design for the
bootstrap is much easier. The tolerance is 6%. The extra current capability can also be used to power external
circuitry.
5-V switch
If the internal 5-V switch senses a 5-V input from REG5V pin, the internal 5-V linear regulator will be
disconnected from the MOSFET drivers. The external 5-V will be used for the low-side driver and the high-side
bootstrap, thus increasing the efficiency.
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3
TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 – JUNE 1999
detailed description (continued)
hysteretic comparator
Each channel has a hysteretic comparator to regulate the output voltage of the synchronous-buck converter.
The hysteresis is set internally and is typically 8.5 mV. The total delay from the comparator input to the driver
output is typically 500 ns from low to high and 350 ns from high to low.
low-side driver
The low-side driver is designed to driver low-Rds(on) n-channel MOSFETs. The maximum drive voltage is 5 V
from Vref5. The current rating of the driver is typically 1 A, source and sink.
high-side driver
The high side driver is designed to drive low-Rds(on) n-channel MOSFETs. The current rating of the driver is
1 A, source and sink. When configured as a floating driver, the bias voltage to the driver is developed from the
Vref5, limiting the maximum drive voltage between OUTxU and LLx to 5 V. The maximum voltage that can be
applied between LHx and OUTGNDx is 30 V.
deadtime control
Deadtime control prevents shoot-through current from flowing through the main power FETs during switching
transitions by actively controlling the turnon time of the MOSFETs drivers. The typical deadtime from
low-side-driver-off to high-side-driver-on is 75 ns and 164 ns from high-side-driver-off to low-side-driver-on.
current protection
The current protection is achieved by sensing the high-side power MOSFET drain-to-source voltage drop during
on-time through VCCSense and LLx pins. An external resistor between Vin and TRIPx pin with the internal
current source connected to the current comparator negative input adjusts the current limit. The typical internal
current source current is 15 µA. When the voltage on the positive pin is lower than the negative pin, the current
comparator turns on the trigger, and then activates the oscillator. This oscillator repeatedly resets the trigger
until the overcurrent condition is removed. The equation for the external resistor selection is:
Rclmt
+ Rds(on)
)
ń
(Itrip Iind(p-p) 2)
0.000015
Where Rds(on) is the MOSFET turnon resistance; Itrip is the required trip current; Iind(p-p) is the peak-to-peak
inductor ripple current. Itrip must be greater than 0.5×Iind(p-p). The tolerance is ±30%.
COMP
COMP is an internal comparator used for any voltage protection such as the output under-voltage protection
for DSP power applications. If the core voltage is lower than the setpoint, the comparator turns off both channels
to prevent the DSP from damage.
SOFT1, SOFT2
Separate soft-start terminals make it possible to set the sequencing of each output for any possibility. The
capacitor value for a start-up time can be calculated by the following equation:
C=2×T
(µF)
Where C is the external capacitor value, T is the required start-up time in (ms).
STBY1, STBY2
Both channels can be switched into standby mode separately by grounding the STBY pin. The standby current
is less than 1 µA. The STBY pins can be used for sequencing.
UVLO
When the input voltage rises to about 3.8 V, the IC is turned on, ready to function. When the input voltage falls
below the turnon value, the IC is turned off. The typical hysteresis is 149 mV.
4
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TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 – JUNE 1999
absolute maximum ratings over operating free-air temperature (see Note 1) (unless otherwise
noted)†
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 27 V
Input voltage, VI, INV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
Softstart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
COMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V
REG5V_IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V
STBY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 15 V
TRIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 15 V
Maximum Driver current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 A
Output voltage, LLx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 27 V
Output voltage, OUTx_u . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 32 V
Output voltage, OUTx_d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
Power dissipation (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Table
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages are with respect to GND terminal.
DISSIPATION RATING TABLE
PACKAGE
TA = 25°C
POWER DISSIPATION
DBT
TA ≥ 25°C
DERATING FACTOR
874 mW
TA = 85°C
POWER DISSIPATION
6.993 mW/°C
454 mW
recommended operating conditions
MIN
Supply voltage, VCC
Input voltage, VI
NOM
4.5
MAX
25
INV1/2
6
COMP
6
SOFTSTART1/2
6
REG5V_IN
5.5
STBY1/STBY2
12
TRIP1/2
VCC_SENCE
25
Operation junction temperature range, TA
–40
85
UNIT
V
V
°C
electrical characteristics over recommended TA = –40°C to 85°C temperature range, VCC = 7 V
(unless otherwise noted)
reference voltage
PARAMETER
Vreff
Reference voltage
VI(Regin)
VI(Regl)
Line regulation
Load regulation
TEST CONDITIONS
TA = 25°C,
VI = 4.5 V to 25 V,
Ivref = 50 µA
I = 1 µA to 1 mA
VCC = 5.5 V to 25 V,
I = 1 µA to 1 mA,
I = 50 µA
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MIN
TYP
MAX
1.167
1.185
1.203
1.155
1.215
UNIT
V
0.2
12
mV
0.5
10
mV
5
TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 – JUNE 1999
quiescent current
PARAMETER
TEST CONDITIONS
ICC
Operating current without switching
Both STBY >2.5 V,
VI = 4.5 V to 25 V
No switching
I(CCS)
Stand-by current
Both STBY <0.5 V,
VI = 4.5 V to 25 V
MIN
TYP
MAX
UNIT
0.8
1.5
mA
1
1000
nA
MIN
TYP
MAX
UNIT
5.5
8.5
11.5
mV
hysteretic comparator
PARAMETER
Vhys†
Hysteresis window
VH(off)
IH(bias)
Offset voltage
TEST CONDITIONS
Bias current
t(HLT), t(LHT)
t(LH)
TTL input signal
Propagation delay from INV to OUTxU‡
2
mV
10
pA
230
10 mV overdrive on hysteretic band signal
t(HI)
† Vhys is assured by design.
‡ The delay time in the table includes the driver.
500
650
350
500
TYP
MAX
ns
driver deadtime
PARAMETER
t(DRVLH)
t(DRVHL)
TEST CONDITIONS
MIN
Low side to high side
90
High side to low side
160
UNIT
ns
standby
PARAMETER
IH
IL
Tturn-on
High-level input voltage
Low-level input voltage
Propagation
Pro
agation delay
TEST CONDITIONS
MIN
TYP
MAX
2.5
STBY1 STBY2
STBY1,
V
0.5
7.2
Staby to driver out
output
ut
Tturn-off
UNIT
V
µs
4.8
5 V regulator
PARAMETER
VO
VI(Regin)
VI(Regl)
IOS
6
TEST CONDITIONS
Output voltage
I = 10 mA
Load regulation
VCC = 5.5 V to 25 V,
I = 1 mA to 10 mA,
Short-circuit output current
Vref = 0 V
POST OFFICE BOX 655303
MIN
TYP
4.7
MAX
5.3
I = 10 mA
20
VCC = 5.5 V
40
80
• DALLAS, TEXAS 75265
UNIT
V
mV
mA
TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 – JUNE 1999
electrical characteristics over recommended free-air temperature range, VCC = 7 V (unless
otherwise noted) (continued)
5-V internal switch
PARAMETER
VTLH
VTHL
Threshold voltage
Rson
On-time resistance
Vhys
Hysteresis
TEST CONDITIONS
MIN
TYP
MAX
4.2
4.9
4.1
4.7
2.5
50
8
UNIT
V
Ω
250
mV
UNIT
current limit
PARAMETER
TEST CONDITIONS
Internal current source
MIN
TYP
MAX
10
15
20
Input offset voltage
2.5
µA
mV
UVLO
PARAMETER
V(TLH)
V(THL)
TEST CONDITIONS
Threshold voltage
Hysteresis
MIN
TYP
MAX
UNIT
3.6
4.2
3.5
4.1
50
250
mV
MAX
UNIT
V
driver output
PARAMETER
TEST CONDITIONS
OUT_u sink current
OUT_u source current
OUT_d sink current
OUT_d source current
Rise time
Fall time
MIN
TYP
VO = 3 V
VO = 2 V
0.5
1.2
–1
–1.7
VO = 3 V
VO = 2 V
0.5
1.2
–1
–1.7
High side driver is GND referenced,
Input:
In
ut: INV = 0 V – 3 V,
V
tr/tf = 10 ns,
Frequency = 200 kHz,
CL = 2200 pF
25.6
CL = 3300 pF
30.8
High side driver is GND referenced,
Input:
In
ut: INV = 0 V – 3 V,
V
tr/tf = 10 ns,
Frequency = 200 kHz,
CL = 2200 pF
23.2
CL = 3300 pF
25.2
A
A
ns
ns
Softstart
PARAMETER
I(CTRL)
TEST CONDITIONS
Softstart current
MIN
TYP
MAX
1.8
2.5
3
Maximum discharge current
0.92
UNIT
µA
mA
COMP†
PARAMETER
TEST CONDITIONS
Threshold voltage
Turn on
Propagation
g
delay
y 50% duty
y cycle,
y ,
No capacitor on COMP or OUT_u pin,
MIN
TYP
MAX
UNIT
1
1.1
1.25
V
452
Frequency = 200 kHz
Turn off
† The delay time in the table includes the drivers.
ns
384
oscillator
PARAMETER
TEST CONDITIONS
Frequency without Ct
Frequency with Ct
Ct = 100 pF
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MIN
TYP
MAX
UNIT
202.4
kHz
67.5
kHz
7
TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 – JUNE 1999
TYPICAL CHARACTERISTICS
QUIESCENT CURRENT (BOTH CHANNEL STANDBY)
vs
SUPPLY VOLTAGE
QUIESCENT CURRENT (BOTH CHANNELS ON)
vs
SUPPLY VOLTAGE
160.0
950
140.0
TJ = 125°C
I (off) – Quiescent Current – nA
I(qon) – Quiescent Current – µ A
900
TJ = 25°C
850
800
TJ = –40°C
750
700
650
120.0
TJ = 125°C
100.0
80.0
60.0
40.0
20.0
0.0
600
4.5
7.0
VCC – Supply Voltage – V
25.0
4.5
15.0
20.0
DRIVE VOLTAGE
vs
DRIVE CURRENT (SINK)
3.5
6
TJ = –40°C
3
5
4
TJ = 25°C
3
TJ = 125°C
2
1
V(snk) – Driver Output Voltage – V
V(src) – Driver Output Voltage – V
10.0
Figure 2
DRIVE OUTPUT VOLTAGE
vs
DRIVE CURRENT (SOURCE)
2.5
2
TJ = 25°C
1.5
TJ = 125°C
1
0.5
0.1
0.5
1
I(src) – Driver Source Current – A
0
TJ = –40°C
0.1
0.5
1
I(sink) – Driver Sink Current – A
Figure 3
8
7.0
VCC – Supply Voltage – V
Figure 1
0
TJ = –40°C
TJ = 25°C
Figure 4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
25.0
TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 – JUNE 1999
TYPICAL CHARACTERISTICS
SOFTSTART CAPACITANCE
vs
SOFTSTART TIMING
CURRENT-PROTECTION SOURCE CURRENT
vs
SUPPLY VOLTAGE
I(trip) – Current-Protection Source Current – µ A
C(start) – Softstart Capacitance – µ F
1
0.1
0.01
0.001
1
13.8
TJ = 125°C
13.6
TJ = 25°C
13.4
13.2
TJ = –40°C
13.0
12.8
12.6
100
10
T(start) – Softstart Timing – ms
14.0
4.5
7.0
15.0
20.0
25.0
Figure 6
Figure 5
STANDBY THRESHOLD VOLTAGE (H–L)
vs
JUNCTION TEMPERATURE
UVLO HYSTERESIS VOLTAGE
vs
JUNCTION TEMPERATURE
2.5
0.20
0.18
2.0
UVOL Hysteresis Voltage – V
V(stby) – Standby Threshold Voltage – V
10.0
VCC(trip) – Supply Voltage – V
1.5
1.0
0.5
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0.0
–40
–20
0
25
50
70
95
TJ – Junction Temperature – °C
125
0.00
–40
–20
0
25
50
70
95
TJ – Junction Temperature – °C
Figure 7
125
Figure 8
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• DALLAS, TEXAS 75265
9
TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 – JUNE 1999
TYPICAL CHARACTERISTICS
STANDBY THRESHOLD (L–H)
vs
JUNCTION TEMPERATURE
UVLO THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
2.5
3.80
V(stby) – Threshold Voltage – V
UVLO Threshold Voltage – V
3.78
3.76
3.74
3.72
3.70
3.68
3.66
2.0
1.5
1.0
0.5
3.64
3.62
3.60
0.0
–40
–20
0
25
50
70
95
TJ – Junction Temperature – °C
–40
125
–20
0
25
50
70
95
TJ – Junction Temperature – °C
Figure 9
Figure 10
VREF5 VOLTAGE
vs
VREF5 CURRENT
SOFT START CHARGE CURRENT
vs
JUNCTION TEMPERATURE
5.1
5.0
–2.5
TJ = 125°C
TJ = 25°C
VREF5 – Voltage – V
Softstart Charge Current – µ A
–3.0
–2.0
–1.5
–1.0
4.9
TJ = –40°C
4.8
4.7
4.6
–0.5
4.5
0.0
–40
–20
0
25
50
70
95
TJ – Junction Temperature – °C
125
0
–10
–20
Figure 12
POST OFFICE BOX 655303
–30
Vref5 – Current – mA
Figure 11
10
125
• DALLAS, TEXAS 75265
–40
–50
Open
LH1
OUTGND2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
LH2
OUT2U
15
R9
R8
15
Figure 13. EVM Schematic Diagram
INV2
NC
COMP
OUT2D
SOFTSTART2
LL2
VCC
5Vin
TRIP2
VREF5
STBY1
STBY2
REF
TRIP1
NC
VCCSENSE
Ct
GND
OUT1D
OUTGND1
NC
LL1
OUT1L
SOFTSTART1
NC
INV1
1.8 V
4A
5–9 V
5A
VI
VO
3A
3.3 V
3.3 V
1.8 V
TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 – JUNE 1999
APPLICATION INFORMATION
11
TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 – JUNE 1999
APPLICATION INFORMATION
application for DSP power
The design shown in this data sheet is a reference design for a DSP application. An evaluation module (EVM),
TPS5602EVM-121 (SLVP121), is available for customer testing and evaluation. The intent is to allow a
customer to fully evaluate the given design using the plug-in EVM supply shown here. The input voltage for this
EVM is from 4.5 V to 9 V. The outputs are 1.8 V at 4 A and 3.3 V at 3 A. By changing few components this EVM
can be used for different operating specifications such as high-input voltage.
This application provides the following power supply sequence: the core power goes up before the I/O supply,
and if the core power is brought down by abnormal condition, the I/O power will be brought down with it.
To help the customers to design the power supply using the TPS5602, key design procedures are shown below:
switching frequency
With hysteretic control, the switching frequency is a function of the input voltage, the output voltage, the
hysteresis window, the delay of the hysteresis comparator and the driver, the output inductance, the resistance
in the output inductor, the output capacitance, the ESR and ESL in the output capacitor, the output current, and
the turn on resistance of high side and low side MOSFET. It is a very complex equation if everything is included.
To make it more useful to the designers, a simplified equation only considers the most influential factors. The
tolerance of this equation is about 30%:
ƒs
+
Vin
ǒ
Vout
( Vin
Vin
ESR
ǒ
* ǒ10 10*7 ) TdǓńCout
10 –7 ) TdǓ ) 0.007 Lout * ESL
* Vout )
ǒ
10
ESR
Ǔ
Vin
Ǔ
Where ƒs is the switching frequency (Hz); Vout is the output voltage (V); Vin is the input voltage (V); Cout is the
output capacitance; ESR is the equivalent series resistance in the output capacitor (Ω); ESL is the equivalent
series inductance in the output capacitor (H); Lout is the output inductance (H); and Td is the output feedback
filter time constant (S).
Example: Vin = 5 V, Vout = 1.8 V, Cout = 680 µF: ESR = 40 mΩ; ESL = 3 nH; Lout = 6 µH; Td = 0.5 µs
Then, the frequency fs = 122 kHz.
output inductor ripple current
The output inductor current ripple can affect not only the efficiency and the inductor saturation, but also the
output capacitor selection. The equation is exhibited below:
Iripple
+
Vin
ǒ
* Vout * Iout
Rdson
) RLǓ
Lout
D
Ts
Where Iripple is the peak-to-peak ripple current through the inductor (A); Vin is the input voltage (V); Vout is the
output voltage (V); Iout is the output current; Rdson is the on-time resistance of MOSFET (Ω); D is the duty cycle;
and Ts is the switching cycle (S). From the equation, it can be seen that the current ripple can be adjusted by
changing the output inductor value.
Example: Vin = 5 V, Vout = 1.8 V, Iout = 5 A: Rdson = 10 mΩ; RL = 5 mΩ; D = 0.36; Ts = 10 mS; Lout = 6 µH
Then, the ripple current Iripple = 2 A.
12
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TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 – JUNE 1999
APPLICATION INFORMATION
application for DSP power (continued)
output capacitor RMS current
Assuming the inductor ripple current totally goes through the output capacitor to ground, the RMS current in the
output capacitor can be calculated as:
Io(rms)
+ ǸD12I
Where Io(rms) is the maximum RMS current in the output capacitor (A); ∆I is the peak–to–peak inductor ripple
current (A).
Example: ∆ I = 2 A, so Io(rms) = 0.58 A
input capacitor RMS current
Assuming the input ripple current totally goes into the input capacitor to the power ground, the RMS current in
the input capacitor can be calculated as:
Ii(rms)
+ Io
ǒ
D
Ǹ(1 * D) ) (1 * D) ǸDǓ
Where Ii(rms) is the input RMS current in the input capacitor (A); Io is the output current (A); D is the duty cycle.
From the equation, it can be seen that the highest input RMS current usually occurs at lowest input voltage.
Example: Io = 5 A; D = 0.36
Then, Ii(rms) = 3.36 A
softstart
The softstart timing can be adjusted by selecting the softstart capacitor value. The equation is
Csoft = 2 × Tsoft
Where Csoft is the softstart capacitance (µF); Tsoft is the start-up time pin (S).
Example: Tsoft = 5 ms, so Csoft = 0.01 µF.
current protection
The current protection in TPS5602 is set using an internal current source and an external resistor to set up the
current limit. The sensed high side MOSFET drain-to-source voltage drop is compared to the set point; if the
voltage drop exceeds the limit, the internal oscillator is activated, and continuously resets the current limit until
the over-current condition is removed. The equation below should be used for calculating the external resistor
value for current protection:
Rclmt
+ Rds(on)
)
ń
(Itrip Iind(p-p) 2)
0.000015
Where Rclmt is the external current limit resistor (R10, R11); Rds(on) is the high side MOSFET on resistance;
Itrip is the required current limit; lind(p-p) is the peak-to-peak output inductor current.
Example: Rds(on) = 10 mΩ, Itrip = 5 A, Lind = 2 A, so Rclmt = 4 kΩ.
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TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 – JUNE 1999
APPLICATION INFORMATION
application for DSP power (continued)
sequencing and under voltage protection
The EVM design uses the standby pins to implement power sequencing. There are two ways to achieve the
protection: one uses a voltage supervisory circuit such as the TI TPS3305-18, the other uses a low cost
comparator, such as the TI TLV1391. The standby pin for the second channel is pulled low by either the
supervisory circuit or the external protection comparator until the first channel output voltage is above the
start-up threshold voltage. With the protection hysteresis, during the power down, if the core voltage is lower
than, for example, 1.3 V, the 3.3 output will be pulled down together. During the normal operation, if the core
voltage is lost, the I/O voltage will be pulled down at the same time. This protection circuit prevents the DSPs
from any damage caused by the malfunctioning power supply. The equation displayed below uses the
comparator for the protection setpoint:
Assuming R16 is much larger than R17, and R19 is 10 kΩ, and the R13 value is adjusted for the turnon setpoint:
R13
+ (Von * 1.2)1.2ǒR16 ø R19 Ǔ
Where Von is the required turn on setpoint. For the turn-off setpoint, R16 is adjusted,
R16
(1.2 * Vin)
+ R19R13(VoffR19
* 1.2) * 1.2 R13
By solving these equations together, or using a spreadsheet to iterate, the setpoints can be easily derived. The
two equations are used for the verification:
Von
+ 1.2 (RǒR1316)ø RǒR1916Ǔ ø R19 Ǔ
and
Voff
+ R13
ǒ
Ǔ
* ) 1.2 ) 1.2
R19 R13
1.2 Vin
R16
Where Von and Voff are the turnon and turnoff setpoints respectively
Example can be found by using the numbers in the bill of materials.
layout considerations
Good power supply results will only occur when care is given to proper design and layout. Layout will affect noise
pickup and generation and can cause a good design to perform with less than expected results. With a range
of currents from milliamps to tens or even hundreds of amps, good power supply layout is much more difficult
than most general PCB designs. The general design should proceed from the switching node to the output, then
back to the driver section and, finally, placing the low-level components. Below are several specific points to
consider before layout of a TPS5602 design begins.
D
D
D
D
14
All sensitive analog components should be referenced to ANAGND. These include components connected
to Vref5, Vref, INV, LH, and COMP.
Analog ground and drive ground should be isolated as much as possible. Ideally, analog ground will connect
to the ground side of the bulk storage capacitors on VO, and drive ground will connect to the main ground
plane close to the source of the low-side FET.
Connections from the drivers to the gate of the power FETs should be as short and wide as possible to
reduce stray inductance. This becomes more critical if external gate resistors are not being used.
The bypass capacitor for VCC should be placed close to the TPS5602.
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TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 – JUNE 1999
APPLICATION INFORMATION
layout considerations (continued)
D
D
D
D
D
D
D
When configuring the high-side driver as a floating driver, the connection from LL to the power FETs should
be as short and as wide as possible.
When configuring the high-side driver as a floating driver, the bootstrap capacitor (connected from LH to
LL) should be placed close to the TPS5602.
When configuring the high-side driver as a ground-referenced driver, LL should be connected to DRVGND.
The bulk storage capacitors across VIN should be placed close to the power FETs. High-frequency bypass
capacitors should be placed in parallel with the bulk capacitors and connected close to the drain of the
high-side FET and to the source of the low-side FET.
High-frequency bypass capacitors should be placed across the bulk storage capacitors on VO.
LH and LL should be connected very close to the drain and source, respectively, of the high-side FET. LH
and LL should be routed very close to each other to minimize differential-mode noise coupling to these
traces. Ceramic decoupling capacitors should be placed close to where HISENSE connects to VIN, to
reduce high-frequency noise coupling on HISENSE.
The output voltage sensing trace should be isolated from the switching node and/or inductor pulses by the
use of a ground trace or plane.
test results
The tests are conducted at TA = 25°C, the input voltage is 5 V (if not specifically noted).
3.3-V OUTPUT EFFICIENCY
1.8-V OUTPUT EFFICIENCY
98
95
96
90
94
85
90
Efficiency – %
Efficiency – %
92
88
86
84
80
75
70
82
80
65
78
76
0.1 0.5
1
1.5 2 2.5 3 3.5 4
IO – Output Current – A
4.5
5
60
0.1 0.5
Figure 14
1
1.5 2 2.5 3 3.5
IO – Output Current – A
4
4.5
5
Figure 15
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15
TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 – JUNE 1999
APPLICATION INFORMATION
COMBINED SYSTEM EFFICIENCY
3.3-V OUTPUT LOAD REGULATION
94
3.32
I(1.8) = 4 A
I(3.3) = 3 A
93
VO – Output Voltage – V
%
92
Efficiency
91
90
89
88
3.315
3.31
3.305
87
86
3.3
10 20 30 40 50 60 70 80 90 100
Percentage of Output Current on Both Channels – %
0 0.1 0.5 1 1.5
2
2.5
3 3.5 4
4.5 5
IO – Output Current – A
Figure 16
Figure 17
3.3-V LINE REGULATION
1.8-V OUTPUT LOAD REGULATION
3.35
1.8
1.795
VO – Output Voltage – V
VO – Output Voltage – V
3.34
1.79
1.785
3.33
3.32
3.31
3.3
3.29
1.78
0
0.1 0.5 1 1.5 2 2.5 3 3.5 4
IO – Output Current – A
4.5
5
4.5 5
9
11 13 15 17 19 21 23 25
VI – Input Voltage – V
Figure 18
16
7
Figure 19
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TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 – JUNE 1999
APPLICATION INFORMATION
1.8-V OUTPUT LINE REGULATION
OUTPUT VOLTAGE RIPPLE
1.805
VO – Output Voltage – V
1.8
50 mV/div
1.795
∆V = 48 mV
1.79
1.785
1.78
1.775
VI = 5 V
5 µs/div
4.5
5
7
9
11 13 15 17 19 21
23 25
VI – Input Voltage – V
Figure 21
Figure 20
POWER-UP SEQUENCING
POWER-DOWN SEQUENCING
3.3 V
200 ms
3.3 V
1 V/div
1 V/div
1.8 V
1.8 V
VI = 5 V
1 ms/div
100 ms/div
Figure 22
Figure 23
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17
TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 – JUNE 1999
APPLICATION INFORMATION
TRANSIENT RESPONSE (OVERSHOOT)
90 A/µs
1 A/div
∆ = 100 mV
100 mV/div
5 µs/div
Figure 24
TRANSIENT RESPONSE (UNDERSHOOT)
6.5 A/µs
1 A/div
∆V = 75 mV
100 mV/div
5 µs/div
Figure 25
18
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TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 – JUNE 1999
APPLICATION INFORMATION
Table 1. SLVP121 Bill of Materials
REF.
C1†
PART NUMBER
MFR.
DESCRIPTION
SIZE
Open
C2
Std
Capacitor, ceramic, 470 pF,16 V, X7R, 20%
805
C3
Std
Capacitor, ceramic, 2200 pF,16 V, X7R, 20%
805
C4
C5†
GRM235Y5V106Z016A
Capacitor, ceramic, 10 µF, 16 V, Y5V
1210
Open
805
C6
Std
Capacitor, ceramic, 1 µF, 16 V, X7R, 20%
1206
C7
Std
Capacitor, ceramic, 2200 pF, 16 V, X7R, 20%
805
C8
Std
Capacitor, ceramic, 2200 pF, 16 V, X7R, 20%
805
C9
GRK316F225ZG
Taiyo Yuden
Capacitor, ceramic, 2.2 µF, 35 V, X7R, 20%
1206
C11
GRK316F225ZG
Taiyo Yuden
Capacitor, ceramic, 2.2 µF, 35 V, X7R, 20%
1206
C12
C13†
GRK316F225ZG
Taiyo Yuden
Capacitor, ceramic, 2.2 µF, 35 V, X7R, 20%
1206
Std
Open
805
C14†
Std
Open
805
C15
10TPB220M
SANYO
Capacitor, electrolytic, 220 µF, 10 V, 20%
10×10 mm
C16
2R5TPB680M
SANYO
Capacitor, POSCAP, 680 µF, 2.5 V, 20%
7.3×4.3 mm
C17
4TPB470M
SANYO
Capacitor, POSCAP, 470 µF, 4 V, 20%
7.3×4.3 mm
C18
GMK325F106ZH
Taiyo Yuden
Capacitor, ceramic, 10 µF, 35 V
1210
C21
GMK325F106ZH
Taiyo Yuden
Capacitor, ceramic, 10 µF, 35 V
1210
D1
SD103-AWDICT-ND
Digikey
Diode, Schottky, 40 mA, 200 mA, 400 mW
3.5×1.5 mm
D2
SD103-AWDICT-ND
Digikey
Diode, Schottky, 40 mA, 200 mA, 400 mW
3.5×1.5 mm
J1
S1132-12-ND
Sullins
Header, right angle, 12-pin, 0.1 ctrs, 0.3” pins
Digikey, S1132–12–ND
L2
DO3316P-682
Coilcraft
Inductor, 6.8 µH, 4.4 A
0.5x0.37 in
L3
DO3316P-103
Coilcraft
Inductor 10 µH, 3.9 A
0.5x0.37 in
Q1–Q4
Si441DY Rev. A
Siliconix
MOSFET, N-Ch, 30 V, 10-A, 0.013 Ω
SO–8
R1
Std
Resistor, SMD, MF, 1.74 kΩ, 1/8W, 1%
805
R4
Std
Resistor, SMD, MF, 680 Ω, 1/8W, 1%
805
R6
Std
Resistor, SMD, MF, 910 Ω, 1/8W, 1%
805
R7
Std
Resistor, SMD, MF, 1.21 kΩ, 1/8W, 1%
805
R8
Std
Resistor, SMD, MF, 15 Ω, 1/8W, 5%
805
R9
Std
Resistor, SMD, MF, 15 Ω, 1/8W, 5%
805
R10
Std
Resistor, SMD, MF, 5.1 kΩ, 1/8W, 5%
805
R11
Std
Resistor, SMD, MF, 5.1 kΩ, 1/8W, 5%
805
R13†
Std
Open, resistor, SMD, MF, 3.3 kΩ, 1/8W, 5%
805
R14
R15†
Std
Open, resistor, SMD, MF, kΩ, 1/8W, 5%
805
Std
Open, resistor, SMD, MF, 1 kΩ, 1/8W, 5%
805
R16†
R17†
Std
Open, resistor, SMD, MF, 200 kΩ, 1/8W, 5%
805
Std
Open, resistor, SMD, MF, 10 kΩ, 1/8W, 5%
805
R18†
R19†
Std
Open, resistor, SMD, MF, 1 kΩ, 1/8W, 5%
805
Std
Open, resistor, SMD, MF, 10 kΩ, 1/8W, 5%
805
R20†
Std
Open, resistor, SMD, MF, 0 kΩ
805
U1
U2†
TPS5602DBT
TI
Dual channel controller
TSSOP 30-pin
TLV1391
TI
Open, single Comparator
SOT-23
U3
TPS3305-18D
TI
Supervisor
D
muRata
NOTE: This table is for 5–9 V input voltage and 3.3 V/1.8 V only.
† Any components with † are for optional test purpose only.
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TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 – JUNE 1999
APPLICATION INFORMATION
To change the EVM operating specifications, several suggestions are shown in the following table.
HIGH INPUT VOLTAGE
(TO 25 V)
2.5 V OUTPUT VOLTAGE
LOW-COST POWER
SEQUENCING
Change R1 to 1 kΩ
Remove U3
Add R15 (1 kΩ)
Change Rt to 1.2 kΩ
Add U2
Change C15 to ELNA
RV-35V221MH10-R (35 V, 220 µF)
Change U3 to TPS3305-25D
Add R13, R16, R17, R19
TOP SIDE
BOTTOM SIDE
20
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COMPONENT SECOND SOURCE
Q1–4
IR7811 for higher efficiency
TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 – JUNE 1999
APPLICATION INFORMATION
BOARD ASSEMBLY
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TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 – JUNE 1999
APPLICATION INFORMATION
Power Supply
Load
5–V, 5–A Supply
–
0–5A
+
Load
0–5A
NOTE: All wire pairs should be twisted.
Figure 26. Test Setup
22
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TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 – JUNE 1999
MECHANICAL DATA
DBT (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
30 PINS SHOWN
0,50
0,27
0,17
30
16
0,08 M
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
15
0°– 8°
0,75
0,50
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
28
30
38
44
50
A MAX
7,90
7,90
9,80
11,10
12,60
A MIN
7,70
7,70
9,60
10,90
12,40
DIM
4073252/D 09/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion.
Falls within JEDEC MO-153 except for pin count and body length
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