Charge Pump, 7-Channel Smart LED Driver with I2C Interface ADP8861 FEATURES TYPICAL OPERATING CIRCUIT D1 D2 D3 D4 D5 D6 D7 VIN CIN 1µF VOUT COUT 1µF VDDIO nRST C1+ VDDIO ADP8861 SDA C1– VDDIO C1 1µF C2+ SCL C2– VDDIO C2 1µF nINT GND1 GND2 08391-001 Charge pump with automatic gain selection of 1×, 1.5×, and 2× for maximum efficiency 7 independent, programmable LED drivers 7 drivers capable of 30 mA (typical) 1 driver also capable of 60 mA (typical) Programmable maximum current limit (128 levels) Standby mode for <1 μA current consumption 16 programmable fade in and fade out times 0.1 sec to 5.5 sec Choose from linear, square, or cubic rates Fading override I2C-compatible interface for all programming Dedicated reset pin and built-in power-on reset (POR) Short-circuit, overvoltage, and overtemperature protection Internal soft start to limit inrush currents Input-to-output isolation during faults or shutdown Operation down to VIN = 2.5 V with undervoltage lockout (UVLO) at VIN = 2.0 V Small lead frame chip scale package (LFCSP) Figure 1. APPLICATIONS Mobile display backlighting Mobile phone keypad backlighting Dual RGB backlighting LED indication General backlighting of small format displays GENERAL DESCRIPTION The ADP8861 provides a powerful charge pump driver with independent control of up to seven LEDs. These seven LEDs can be independently driven up to 30 mA (typical). The seventh LED can also be driven to 60 mA (typical). All LEDs are programmable for maximum current and fade in/out times via the I2C interface. These LEDs can also be combined into groups to reduce the processor instructions during fade in/out. This entire configuration is driven by a two-capacitor charge pump with gains of 1×, 1.5×, and 2×. The charge pump is capable of driving a maximum IOUT of 240 mA from a supply of 2.5 V to 5.5 V. A full suite of safety features, including shortcircuit, overvoltage, and overtemperature protection, allows easy implementation of a safe and robust design. Additionally, input inrush currents are limited via an integrated soft start combined with controlled input-to-output isolation. The ADP8861 is available in a compact lead frame chip scale package (LFCSP). Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved. ADP8861 TABLE OF CONTENTS Features .............................................................................................. 1 Automated Fade In and Fade Out ............................................ 14 Applications ....................................................................................... 1 Backlight Turn On/Turn Off/Dim ........................................... 15 Typical Operating Circuit ................................................................ 1 Automatic Dim and Turn Off Timers ..................................... 15 General Description ......................................................................... 1 Fade Override ............................................................................. 16 Revision History ............................................................................... 2 Independent Sink Control ........................................................ 16 Specifications..................................................................................... 3 Short-Circuit Protection Mode ................................................ 16 I C Timing Diagram .................................................................... 4 Overvoltage Protection .............................................................. 17 Absolute Maximum Ratings............................................................ 5 Thermal Shutdown/Overtemperature Protection ................. 17 Maximum Temperature Ranges ................................................. 5 Interrupts ..................................................................................... 17 Thermal Resistance ...................................................................... 5 Applications Information .............................................................. 19 ESD Caution .................................................................................. 5 Determining the Transition Point of the Charge Pump ....... 19 Pin Configuration and Function Descriptions ............................. 6 Layout Guidelines....................................................................... 19 2 Typical Performance Characteristics ............................................. 7 Example Circuits ........................................................................ 20 Theory of Operation ...................................................................... 11 I C Programming and Digital Control ........................................ 21 Power Stage.................................................................................. 12 Backlight Register Descriptions ............................................... 26 Operating Modes ........................................................................ 13 Independent Sink Register Descriptions................................. 31 Backlight Operating Levels ....................................................... 14 Outline Dimensions ....................................................................... 39 Backlight Maximum and Dim Settings ................................... 14 Ordering Guide .......................................................................... 39 2 REVISION HISTORY 4/10—Revision 0: Initial Version Rev. 0 | Page 2 of 40 ADP8861 SPECIFICATIONS VIN = 3.6 V, SCL = 2.7 V, SDA = 2.7 V, nINT = open, nRST = 2.7 V, VD1:D7 = 0.4 V, Capacitor C1 = 1 μF, Capacitor C2 = 1 μF, COUT = 1 μF, typical values are at TA = 25°C and are not guaranteed, minimum and maximum limits are guaranteed from TA = −40°C to +85°C, unless otherwise noted. Table 1. Parameter SUPPLY Input Voltage Operating Range Start-Up Level Low Level VIN(START) Hysteresis UVLO Noise Filter Quiescent Current Prior to VIN(START) During Standby After Startup and Switching OSCILLATOR Switching Frequency Duty Cycle OUTPUT CURRENT CONTROL Maximum Drive Current Diode1 to Diode 7 TJ = 25°C TJ = −40°C to +85°C Diode 7 Only (60 mA Setting) TJ = 25°C TJ = −40°C to +85°C LED Current Source Matching 1 All Current Sinks Diode 2 to Diode 7 Current Sinks Leakage Current on LED Pins Equivalent Output Resistance Gain = 1× Gain = 1.5× Gain = 2× Regulated Output Voltage AUTOMATIC GAIN SELECTION Minimum Voltage Gain Increases Minimum Current Sink Headroom Voltage Gain Delay FAULT PROTECTION Start-Up Charging Current Source Output Voltage Threshold Exit Soft Start Short-Circuit Protection Symbol VIN VIN(START) VIN(STOP) VIN(HYS) tUVLO IQ IQ(START) IQ(STBY) IQ(ACTIVE) Test Conditions/Comments ID7(60 mA) IMATCH IMATCH7 IMATCH6 ID1:D7(LKG) ROUT Typ 2.5 VIN increasing VIN decreasing After startup 1.75 VIN = VIN(START) − 100 mV VIN = 3.6 V, Bit nSTBY = 0, SCL = SDA = 0 V VIN = 3.6 V, Bit nSTBY = 1, IOUT = 0 mA, gain = 2× Charge pump gain = 2× fSW D ID1:D7(MAX) Min 2.05 1.97 80 10 10 0.3 4.5 Max Unit 5.5 2.30 V V V mV μs 1.0 7.2 μA μA mA 0.8 1 50 1.32 MHz % 26.2 24.4 30 34.1 34.1 mA mA 52.5 48.8 60 67 67 mA mA VD1:D7 = 0.4 V Bit SCR = 0 in the ISC7 register VD7 = 0.4 V, Bit SCR = 1 in the ISC7 register VD1:D7 = 0.4 V VD2:D7 = 0.4 V 2.0 1.5 VIN = 5.5 V, VD1:D7 = 2.5 V, Bit nSTBY = 1 VOUT(REG) VIN = 3.6 V, IOUT = 100 mA VIN = 3.1 V, IOUT = 100 mA VIN = 2.5 V, IOUT = 100 mA VIN = 3 V, gain = 2×, IOUT = 10 mA VHR(UP) VHR(MIN) Decrease VD1:D7 until the gain switches up IDX = IDX(MAX) × 95% tGAIN The delay after gain has changed and before gain is allowed to change again ISS VOUT VOUT(START) VOUT(SC) VIN = 3.6 V, VOUT = 0.8 × VIN VOUT rising VOUT falling Rev. 0 | Page 3 of 40 4.3 162 0.5 3.0 3.8 4.9 200 180 % % 0.5 μA 5.5 Ω Ω Ω V 276 100 2.5 3.75 0.92 × VIN 0.55 × VIN mV mV μs 5.5 mA V V ADP8861 Parameter Output Overvoltage Protection Activation Level OVP Recovery Hysteresis Thermal Shutdown Threshold Hysteresis Isolation from Input to Output During Fault Time to Validate a Fault I2C INTERFACE Operating VDDIO Voltage Logic Low Input 2 Logic High Input 3 2 I C TIMING SPECIFICATIONS Delay from Reset Deassertion to I2C Access SCL Frequency SCL High Time SCL Low Time Setup Time Data Repeated Start Stop Condition Hold Time Data Start/Repeated Start Bus Free Time (Stop and Start Conditions) Rise Time (SCL and SDA) Fall Time (SCL and SDA) Pulse Width of Suppressed Spike Capacitive Load per Bus Line 1 2 3 Symbol VOVP TSD TSD(HYS) IOUTLKG Test Conditions/Comments Min Typ V mV 150 20 °C °C μA 1.5 2 VIN = 2.5 V VIN = 5.5 V Guaranteed by design μs 5.5 0.5 V V V 20 μs 400 1.55 tRESET fSCL tHIGH tLOW 0.6 1.3 kHz μs μs tSU, DAT tSU, STA tSU, STO 100 0.6 0.6 ns μs μs tHD, DAT tHD, STA tBUF 0 0.6 1.3 0.9 μs μs μs tR tF tSP CB 20 + 0.1 CB 20 + 0.1 CB 0 300 300 50 400 ns ns ns pF Current source matching is calculated by dividing the difference between the maximum and minimum currents from the sum of the maximum and minimum. VIL is a function of the input voltage. See Figure 15 in the Typical Performance Characteristics section for typical values over operating ranges. VIH is a function of the input voltage. See Figure 15 in the Typical Performance Characteristics section for typical values over operating ranges. I2C TIMING DIAGRAM SDA tLOW tR tF tSU, DAT tF tHD, STA tSP tBUF tR SCL S Unit 5.8 500 VIN = 5.5 V, VOUT = 0 V, Bit nSTBY = 0 tFAULT VDDIO VIL VIH Max tHD, DAT tHIGH tSU, STA Sr P S 08391-002 S = START CONDITION Sr = REPEATED START CONDITION P = STOP CONDITION tSU, STO Figure 2. I2C Interface Timing Diagram Rev. 0 | Page 4 of 40 ADP8861 ABSOLUTE MAXIMUM RATINGS MAXIMUM TEMPERATURE RANGES Table 2. Parameter VIN, VOUT D1, D2, D3, D4, D5, D6, and D7 nINT, nRST, SCL, and SDA Output Short-Circuit Duration Operating Temperature Range Ambient (TA) Junction (TJ) Storage Temperature Range Soldering Conditions ESD (Electrostatic Discharge) Human Body Model (HBM) Charged Device Model (CDM) 1 Rating −0.3 V to +6 V −0.3 V to +6 V −0.3 V to +6 V Indefinite –40°C to +85°C1 –40°C to +125°C –65°C to +150°C JEDEC J-STD-020 ±3 kV ±1.5 kV The maximum operating junction temperature (TJ(MAX)) takes precedence over the maximum operating ambient temperature (TA(MAX)). See the Maximum Temperature Ranges section for more information. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The maximum operating junction temperature (TJ(MAX)) takes precedence over the maximum operating ambient temperature (TA(MAX)). Therefore, in situations where the ADP8861 is exposed to poor thermal resistance and high power dissipation (PD), the maximum ambient temperature may need to be derated. In these cases, the maximum ambient temperature can be calculated with the following equation: TA(MAX) = TJ(MAX) − (θJA × PD(MAX)) THERMAL RESISTANCE θJA (junction to air) is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. The θJA and θJC (junction to case) are determined according to JESD51-9 on a 4-layer printed circuit board (PCB) with natural convection cooling. For the LFCSP package, the exposed pad must be soldered to the GND1 and/or GND2 terminal on the board. Table 3. Thermal Resistance Package Type 20-Lead LFCSP_WQ ESD CAUTION Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified, all voltages are referenced to ground. Rev. 0 | Page 5 of 40 θJA 49.5 θJC 5.3 Unit °C/W ADP8861 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADP8861 20 19 18 17 16 D4 D5 NA D6 D7 TOP VIEW (Not to Scale) 15 14 13 12 11 1 2 3 4 5 GND1 VIN VOUT C2+ C1+ NOTES 1. CONNECT THE EXPOSED PADDLE TO GND1 AND/OR GND2. 08391-005 nINT 6 SDA 7 GND2 8 C1– 9 C2– 10 D3 D2 D1 SCL nRST Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. 14 3 2 1 20 19 17 16 18 13 11 9 12 10 15 8 6 5 Mnemonic VIN D1 D2 D3 D4 D5 D6 D7 NA VOUT C1+ C1− C2+ C2− GND1 GND2 nINT nRST 7 4 21 SDA SCL EPAD Description Input Voltage, 2.5 V to 5.5 V. LED Sink 1. LED Sink 2. LED Sink 3. LED Sink 4. LED Sink 5. LED Sink 6. LED Sink 7. This pin is not used and must be connected to ground. Charge Pump Output. Charge Pump C1+. Charge Pump C1−. Charge Pump C2+. Charge Pump C2−. Ground. Connect the exposed pad to GND1 and/or GND2. Ground. Connect the exposed pad to GND1 and/or GND2. Processor Interrupt (Active Low). Requires an external pull-up resistor. If this pin is not used, it can be left floating. Hardware Reset (Active Low). This pin resets the device to the default conditions. If not used, this pin must be tied above VIH(MIN). I2C Serial Data. Requires an external pull-up resistor. I2C Clock. Requires an external pull-up resistor. Exposed Paddle. Connect the exposed paddle to GND1 and/or GND2. Rev. 0 | Page 6 of 40 ADP8861 TYPICAL PERFORMANCE CHARACTERISTICS VIN = 3.6 V, SCL = 2.7 V, SDA = 2.7 V, nRST = 2.7 V, VD1:D7 = 0.4 V, CIN = 1 μF, Capacitor C1 = 1 μF, Capacitor C2 = 1 μF, COUT = 1 μF, TA= 25°C, unless otherwise noted. 2.0 1.8 35 VIN = 3.6V ID1:D7 = 30mA IOUT = NO LOAD 30 1.6 25 1.4 IOUT (mA) 1.0 0.8 D1 15 D2 D3 10 –40°C +25°C +85°C +105°C 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 D5 5.5 VIN (V) 0 Figure 4. Typical Quiescent Current, G = 1× D6 D7 0 35 IOUT = NO LOAD 0.8 1.0 1.2 1.4 1.6 1.8 3.5 32 3.0 31 IOUT (mA) 33 2.5 VD1:D7 = 0.4V 30 D1 29 D2 D3 28 1.5 –40°C +25°C +85°C +105°C 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 D4 27 D5 D6 26 5.5 VIN (V) 25 2.0 08391-101 1.0 D7 2.5 6 5 MISMATCH (%) 1 0.1 –40°C +25°C +85°C +105°C 1 2 3 4 VIN (V) Figure 6. Typical Standby IQ vs. VIN 5 4.0 4.5 5.0 5.5 2.0 VIN = 3.6V ID1:D7 = 30mA –40°C +25°C +85°C +105°C 4 3 2 1 6 0 0.2 08391-102 0 3.5 Figure 8. Typical Diode Current vs. VIN SCL = SDA = 0V nRST = 2.7V 0.01 3.0 VIN (V) Figure 5. Typical Quiescent Current, G = 2×, IQ(ACTIVE) 10 2.0 34 2.0 IQ (µA) 0.6 Figure 7. Typical Diode Current vs. Current Sink Headroom Voltage (VHR) 4.0 0.001 0.4 VHR (V) 5.0 4.5 0.2 08391-104 0.2 D4 5 08391-100 0.4 08391-103 0.6 IQ (mA) 20 08391-105 IQ (mA) 1.2 0.4 0.6 0.8 1.0 1.2 VHR (V) 1.4 1.6 1.8 Figure 9. Typical Diode Matching vs. Current Sink Headroom Voltage (VHR) Rev. 0 | Page 7 of 40 ADP8861 35 1.0 VIN = 3.6V ID1:D7 = 30mA IOUT = 100mA 0.9 30 0.8 0.7 20 ROUT (Ω) 15 0.5 0.4 0.3 10 –40°C +25°C +85°C +105°C 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 –40°C +25°C +85°C +105°C 0.2 0.1 2.0 VHR (V) 0 2.0 08391-106 5 0 0.6 3.0 3.5 4.0 4.5 5.0 5.5 VIN (V) Figure 10. Typical Diode Current vs. Current Sink Headroom Voltage (VHR) 1 2.5 08391-109 IOUT (mA) 25 Figure 13. Typical ROUT (G = 1×) vs. VIN 10 VIN = 3.6V VD1:D7 = 0.40V VOUT = 80% OF VIN 9 0 7 IOUT (mA) –2 –3 6 5 4 3 –40°C +25°C +85°C +105°C 2 –5 1 –10 20 50 80 110 JUNCTION TEMPERATURE (°C) 0 2.0 08391-107 –6 –40 4.0 4.5 5.0 5.5 1.4 VIH @ +25°C 6 VIH @ +85°C 1.2 5 VIH @ –40°C THRESHOLD (V) 1.0 G = 2× @ VIN = 2.5V 4 3 G = 1.5× @ VIN = 3V 2 0.8 VIL @ +25°C VIL @ +85°C 0.6 VIL @ –40°C 0.4 1 0.2 G = 1× @ VIN = 3.6V –20 0 20 40 60 TEMPERATURE (°C) 80 100 0 2.5 08391-108 ROUT (Ω) 3.5 Figure 14. Typical Output Soft Start Current, ISS IOUT = 100mA 0 –40 3.0 VIN (V) Figure 11. Typical Change In Diode Current vs. Temperature 7 2.5 08391-110 –4 3.0 3.5 4.0 4.5 5.0 VIN (V) Figure 15. Typical I2C Thresholds, VIH and VIL Figure 12. ROUT vs. Temperature Rev. 0 | Page 8 of 40 5.5 08391-111 IOUT DEVIATION (%) 8 –1 ADP8861 450 90 400 80 5.2 70 EFFICIENCY (%) 5.3 5.1 VOUT (V) 100 5.0 4.9 20 4.6 10 80 110 JUNCTION TEMPERATURE (°C) 150 100 IOUT = 140mA, Vf = 3.85V 0 2.5 08391-113 50 200 40 4.7 20 250 50 30 –10 300 60 4.8 4.5 –40 350 IIN (mA) 5.4 VIN = 3V GAIN = 2× IOUT = 10mA 50 IOUT = 210mA, Vf = 4.25V 3.0 3.5 4.0 4.5 0 5.5 5.0 08391-116 5.5 VIN (V) Figure 19. Typical Efficiency (High Vf Diode) Figure 16. Typical Regulated Output Voltage (VOUT(REG)) 6.0 T VIN (AC-COUPLED) 50mV/DIV 1 5.8 OVP THRESHOLD IIN (AC-COUPLED) 10mA/DIV 5.4 3 CIN = 1µF, COUT = 1µF, C1 = 1µF, C2 = 1µF VIN = 3.6V IOUT = 120mA 5.2 –40 –10 20 50 80 110 JUNCTION TEMPERATURE (°C) 80 400 70 350 60 300 50 250 40 200 30 150 20 100 T VIN (AC-COUPLED) 50mV/DIV 1 VOUT (AC-COUPLED) 50mV/DIV IIN (mA) 450 Figure 20. Typical Operating Waveforms, G = 1× 2 IIN (AC-COUPLED) 10mA/DIV 0 2.5 IOUT = 140mA, Vf = 3.1V IOUT = 210mA, Vf = 3.2V 3.0 3.5 CIN = 1µF, COUT = 1µF, C1 = 1µF, C2 = 1µF VIN = 3.0V IOUT = 120mA 50 4.0 4.5 5.0 VIN (V) 0 5.5 500ns/DIV Figure 21. Typical Operating Waveforms, G = 1.5× Figure 18. Typical Efficiency (Low Vf Diode) Rev. 0 | Page 9 of 40 08391-118 10 3 08391-115 EFFICIENCY (%) Figure 17. Typical Overvoltage Protection (OVP) Threshold 90 500ns/DIV 08391-114 OVP RECOVERY 08391-117 VOUT (V) VOUT (AC-COUPLED) 50mV/DIV 2 5.6 ADP8861 VIN = 3.7V T VIN (AC-COUPLED) 50mV/DIV 1 VOUT (1V/DIV) VOUT (AC-COUPLED) 50mV/DIV 2 2 IIN (10mA/DIV) IIN (AC-COUPLED) 10mA/DIV 500ns/DIV 4 Figure 22. Typical Operating Waveforms, G = 2× IOUT (10mA/DIV) 100µs/DIV Figure 23. Typical Start-Up Waveform Rev. 0 | Page 10 of 40 08391-120 CIN = 1µF, COUT = 1µF, C1 = 1µF, C2 = 1µF VIN = 2.5V IOUT = 120mA 08391-119 3 ADP8861 THEORY OF OPERATION LEDs. A full suite of safety features, including short-circuit, overvoltage, and overtemperature protection with input-tooutput isolation, allows for a robust and safe design. The integrated soft start limits inrush currents at startup, restart attempts, and gain transitions. The ADP8861 provides a powerful charge pump driver with programmable LED control. Up to seven LEDs can be independently driven up to 30 mA (typical) each. The seventh LED can also be driven to 60 mA (typical). All LEDs can be individually programmed or combined into a group to operate backlight D1 ID1 D2 ID2 ID3 D3 ID4 D4 ID5 D5 D6 D7 GAIN SELECT LOGIC ID7 ID6 VIN ISS VIN CIN VIN VIN VOUT IREFS UVLO VDDIO VREFS SOFT START COUT EN STNDBY CLK NOISE FILTER nRST C1+ 50µs RESET CHARGE PUMP (1×, 1.5×, 2×) STANDBY C1 1µF C1– C2+ C2 1µF SCL SDA I2C LOGIC C2– SWITCH CONTROL CURRENT SINK CONTROL nINT GND1 GND2 Figure 24. Detailed Block Diagram Rev. 0 | Page 11 of 40 08391-011 VBAT CHARGE PUMP LOGIC ADP8861 in parallel and are discharged to VOUT in parallel. In certain fault modes, the switches are opened and the output is physically isolated from the input. POWER STAGE Because typical white LEDs require up to 4 V to drive them, some form of boosting is required over the typical variation in battery voltage. The ADP8861 accomplishes this with a high efficiency charge pump capable of producing a maximum IOUT of 240 mA over the entire input voltage range (2.5 V to 5.5 V). Charge pumps use the basic principle that a capacitor stores charge based on the voltage applied to it, as shown in the following equation: Q=C×V Automatic Gain Selection Each LED that is driven requires a current source. The voltage on this current source must be greater than a minimum headroom voltage (180 mV typical) to maintain accurate current regulation. The gain is automatically selected based on the minimum voltage (VDX) at all of the current sources. At startup, the device is placed into G = 1× mode and the output charges to VIN. If any VD1:D7 level is less than the required headroom (180 mV), the gain is increased to the next step (G = 1.5×). A 100 μs delay is allowed for the output to stabilize prior to the next gain switching decision. If there remains insufficient current sink headroom, then the gain is increased again to 2×. Conversely, to optimize efficiency, it is not desirable for the output voltage to be too high. Therefore, the gain reduces when the headroom voltage is great enough. This point (labeled VDMAX in Figure 25) is internally calculated to ensure that the lower gain still results in ample headroom for all the current sinks. The entire cycle is illustrated in Figure 25. (1) By charging the capacitors in different configurations, the charge, and therefore the gain, can be optimized to deliver the voltage required to power the LEDs. Because a fixed charging and discharging combination must be used, only certain multiples of gain are available. The ADP8861 is capable of automatically optimizing the gain (G) from 1×, 1.5×, and 2×. These gains are accomplished with two capacitors (labeled C1 and C2 in Figure 24) and an internal switching network. In G = 1× mode, the switches are configured to pass VIN directly to VOUT. In this mode, several switches are connected in parallel to minimize the resistive drop from input to output. In G = 1.5× and 2× modes, the switches alternatively charge from the battery and discharge into the output. For G = 1.5×, the capacitors are charged from VIN in series and are discharged to VOUT in parallel. For G = 2×, the capacitors are charged from VIN STANDBY EXIT STANDBY Note that the gain selection criteria apply only to active current sources. If current sources have been deactivated through an I2C command (for example only five LEDs are used), then the voltages on the deactivated current sources are ignored. STARTUP: CHARGE VIN TO VOUT 0 EXIT STARTUP 1 VOU T > VOUT(START) 0 WAIT 100µs (TYP) G=1 MIN (VD1:D7) < VHR(UP) 1 G = 1.5 1 WAIT 100µs (TYP) MIN (VD1:D7) < VHR(UP) 1 0 0 MIN (VD1:D7) > VDMAX 0 1 WAIT 100µs (TYP) MIN (VD1:D7) < VDMAX NOTES 1. VDMAX IS THE CALCULATED GAIN DOWN TRANSITION POINT. Figure 25. State Diagram for Automatic Gain Selection Rev. 0 | Page 12 of 40 08391-012 G=2 ADP8861 Soft Start Feature Shutdown Mode At startup (either from UVLO activation or fault/standby recovery), the output is first charged by ISS (3.75 mA typical) until it reaches about 92% of VIN. This soft start feature reduces the inrush current that is otherwise present when the output capacitance is initially charged to VIN. When this point is reached, the controller enters G = 1× mode. If the output voltage is not sufficient, then the automatic gain selection determines the optimal point as defined in the Automatic Gain Selection section. Shutdown mode disables all circuitry, including the I2C receivers. Shutdown occurs when VIN is below the undervoltage thresholds. When VIN rises above VIN(START) (2.05 V typical), all registers are reset and the part is placed into standby mode. Reset Mode In reset mode, all registers are set to their default values and the part is placed into standby. There are two ways to reset the part: by power-on reset (POR) or using the nRST pin. POR is activated any time that the part exits shutdown mode. After a POR sequence is complete, the part automatically enters standby mode. OPERATING MODES There are four different operating modes: active, standby, shutdown, and reset. After startup, the part can be reset by pulling the nRST pin low. As long as the nRST pin is low, the part is held in a standby state but no I2C commands are acknowledged (all registers are kept at their default values). After releasing the nRST pin, all registers remain at their default values, and the part remains in standby; however, the part does accept I2C commands. Active Mode In active mode, all circuits are powered up and in a fully operational state. This mode is entered when Bit nSTBY (in Register MDCR) is set to 1. Standby Mode The nRST pin has a 50 μs (typical) noise filter to prevent inadvertent activation of the reset function. The nRST pin must be held low for this entire time to activate reset. Standby mode disables all circuitry except for the I2C receivers. Current consumption is reduced to less than 1 μA. This mode is entered when the nSTBY bit is set to 0 or when the nRST pin is held low for more than 100 μs (maximum). When standby is exited, a soft start sequence is performed. The operating modes function according to the timing diagram in Figure 26. SHUTDOWN VIN CROSSES ~2.05V AND TRIGGERS POWER-ON RESET VIN nRST MUST BE HIGH FOR 20µs (MAX) BEFORE SENDING I2C COMMANDS BIT nSTBY IN REGISTER MDCR GOES LOW ~100µs DELAY BETWEEN POWER-UP AND WHEN I2C COMMANDS CAN BE RECEIVED STANDBY nRST IS LOW, WHICH FORCES STANDBY LOW AND RESETS ALL I2C REGISTERS 25µs TO 100µs NOISE FILTER nRST VIN ~3.75mA CHARGES VOUT TO VIN LEVEL SOFT START 1.5× 2× 1× GAIN CHANGES OCCUR ONLY WHEN NECESSARY, BUT HAVE A MIN TIME BEFORE CHANGING 10µs 100µs Figure 26. Typical Timing Diagram Rev. 0 | Page 13 of 40 SOFT START 08391-013 VOUT ADP8861 30 BACKLIGHT OPERATING LEVELS 30mA 0 20 15 LINEAR 10 SQUARE 0 0 32 64 CODE 96 128 08391-015 5 Figure 28. Backlight Current vs. Input Code BACKLIGHT_DIM AUTOMATED FADE IN AND FADE OUT 08391-014 BACKLIGHT CURRENT BACKLIGHT_MAX 25 BACKLIGHT CURRENT (mA) The backlight can be operated at either the maximum level (Register 0x09) or the dim level (Register 0x0A). The backlight maximum and dim current settings are determined by a 7-bit code programmed by the user into these registers. The 7-bit resolution allows the user to set the backlight to one of 128 different levels between 0 mA and 30 mA. Figure 27. Backlight Operating Levels The maximum and dim settings can be set between 0 mA and 30 mA; therefore, it is possible to program a dim setting that is greater than a maximum setting. For normal expected operation, ensure that the dim setting is programmed to be less than the maximum setting. BACKLIGHT MAXIMUM AND DIM SETTINGS The ADP8861 can implement two distinct algorithms to achieve a linear and a nonlinear relationship between input code and backlight current. The law bits in Register 0x04 are used to change between these algorithms. By default, the ADP8861 uses a linear algorithm (law = 00), where the backlight current increases linearly for a corresponding increase in input code. Backlight current (in milliamperes) is determined by the following equation: Backlight Current (mA) = Code × (Full-Scale Current/127) (2) where: Code is the input code programmed by the user. Full-Scale Current is the maximum sink current allowed per LED (typically 30 mA). The ADP8861 can also implement a nonlinear (square approximation) relationship between input code and backlight current level. In this case (law = 01), the backlight current (in milliamperes) is determined by the following equation: ⎛ Full − Scale Current Backlight Current (mA) = ⎜ Code × ⎜ 127 ⎝ The LED drivers are easily configured for automated fade in and fade out. Sixteen fade in and fade out rates can be selected via the I2C interface. Fade in and fade out rates range from 0.1 sec to 5.5 sec (per full-scale current, either 30 mA or 60 mA). Table 5. Available Fade In and Fade Out Rates Code 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 The fade profile is based on the transfer law selected (linear, square, Cubic 10, or Cubic 11) and the delta between the actual current and the target current. Smaller changes in current reduce the fade time. For linear and square law fades, the fade time is given by 2 ⎞ ⎟ (3) ⎟ ⎠ Figure 28 shows the backlight current level vs. input code for both the linear and square law algorithms. Fade Rate (in sec per Full-Scale Current) 0.1 (disabled) 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.5 4.0 4.5 5.0 5.5 Fade Time = Fade Rate × (Code/127) (4) where the Fade Rate is shown in Table 5. The Cubic 10 and Cubic 11 laws also use the square law backlight currents derived from Equation 3; however, the time between each step is varied to produce a steeper slope at higher currents and a shallower slope at lower currents (see Figure 29). Rev. 0 | Page 14 of 40 ADP8861 30 AUTOMATIC DIM AND TURN OFF TIMERS The user can program the backlight to dim automatically by using the DIMT bits in Register 0x07. The dim timer has 127 settings ranging from 1 sec to 127 sec. Program the dim timer (DIMT) before turning on the backlight. If BL_EN = 1, the backlight turns on to its maximum setting and the dim timer starts counting. When the dim timer expires, the internal state machine sets DIM_EN = 1, and the backlight enters its dim setting. 25 CURRENT (mA) LINEAR 20 15 SQUARE 10 CUBIC 11 BACKLIGHT CURRENT 5 CUBIC 10 0 0.25 0.50 0.75 08391-016 0 1.00 UNIT FADE TIME DIM TIMER RUNNING DIM TIMER RUNNING MAX Figure 29. Comparison of the Dimming Transfers Laws BACKLIGHT TURN ON/TURN OFF/DIM DIM BL_EN = 1 DIM_EN = 1 DIM_EN = 0 DIM_EN = 1 BL_EN = 0 08391-019 With the device in active mode (nSTBY = 1), the backlight can be turned on using the BL_EN bit in Register 0x01. Before turning on the backlight, the user should ensure that the maximum and dim settings are programmed. The backlight turns on when BL_EN = 1. The backlight turns off when BL_EN = 0. SET BY USER SET BY INTERNAL STATEMACHINE BACKLIGHT CURRENT Figure 32. Dim Timer If the user clears the DIM_EN bit, the backlight reverts to its maximum setting and the dim timer begins counting again. When the dim timer expires, the internal state machine again sets DIM_EN = 1, and the backlight enters its dim setting. The backlight can be turned off at any point during the dim timer countdown by clearing BL_EN. BL_EN = 1 08391-017 MAX BL_EN = 0 Figure 30. Backlight Turn On/Turn Off While the backlight is on (BL_EN = 1), the user can change to the dim setting by programming DIM_EN = 1 in Register 0x01. If DIM_EN = 0, the backlight reverts to its maximum setting. The user can also program the backlight to turn off automatically by using the OFFT bits in Register 0x06. The off timer has 127 settings ranging from 1 sec to 127 sec. Program the off timer (OFFT) before turning on the backlight. If BL_EN = 1, the backlight turns on to its maximum setting and the off timer starts counting. When the off timer expires, the internal state machine clears the BL_EN bit, and the backlight turns off. BACKLIGHT CURRENT BACKLIGHT CURRENT OFF TIMER RUNNING MAX MAX DIM_EN = 1 DIM_EN = 0 BL_EN = 0 BL_EN = 1 BL_EN = 0 SET BY USER SET BY INTERNAL STATE MACHINE Figure 31. Backlight Turn On/Dim/Turn Off Figure 33. Off Timer The backlight can be turned off at any point during the off timer countdown by clearing BL_EN. Rev. 0 | Page 15 of 40 07967-020 BL_EN = 1 08391-018 DIM ADP8861 The dim timer and off timer can be used together for sequential maximum-to-dim-to-off functionality. With both the dim and off timers programmed, and BL_EN asserted, the backlight turns on to its maximum setting, and when the dim timer expires, the backlight changes to its dim setting. When the off timer expires, the backlight turns off. The ISCs have additional timers to facilitate blinking functions. A shared on timer (SCON) used in conjunction with the off timers of each ISC (SC1_OFF, SC2_OFF, SC3_OFF, and SC4_OFF in Register 0x12, and SC5_OFF, SC6_OFF, and SC7_OFF in Register 0x11) allows the LED current sinks to be configured in various blinking modes. The on timer can be set to one of four different settings: 0.2 sec, 0.6 sec, 0.8 sec, or 1.2 sec. The off timers have four different settings: disabled, 0.6 sec, 1.2 sec, and 1.8 sec. Blink mode is activated by setting the off timers to any setting other than disabled. DIM TIMER RUNNING MAX OFF TIMER RUNNING BL_EN = 1 DIM_EN = 1 BL_EN = 0 08391-021 DIM SET BY USER SET BY INTERNAL STATE MACHINE Figure 34. Dim and Off Timers Used Together FADE OVERRIDE A fade override feature (FOVR in Register CFGR (0x04)) enables the host to override the preprogrammed fade in or fade out settings. If FOVR is set and the backlight is enabled in the middle of a fade out process, the backlight instantly (within approximately 100 ms) returns to its prefade brightness level. Alternatively, if the backlight is fading in, reasserting BL_EN overrides the programmed fade in time, and the backlight instantly goes to its final fade value. This is useful for situations where a key is pressed during a fade sequence. However, if FOVR is cleared and the backlight is enabled in the middle of a fade process, the backlight gradually brightens from where it was interrupted (it does not go down to 0 and then comes back on). BACKLIGHT CURRENT Each of the seven LEDs can be configured (in Register 0x05) to operate as either part of the backlight or to operate as an independent sink current (ISC). Each ISC can be enabled independently and has its own current level. All ISCs share the same fade in rates, fade out rates, and fade law. Program all fade, on, and off timers before enabling any of the LED current sinks. If ISCx is on during a blink cycle and SCx_EN is cleared, the LED turns off (or fades to off if fade out is enabled). If ISCx is off during a blink cycle and SCx_EN is cleared, it stays off. ISCx ON TIME FADE-IN ON TIME FADE-OUT FADE-IN FADE-OUT MAX OFF TIME OFF TIME ISCx_EN SET BY USER FADE-IN OVERRIDDEN 08391-026 BACKLIGHT CURRENT INDEPENDENT SINK CONTROL Figure 36. Independent Sink Blink Mode with Fading FADE-OUT OVERRIDDEN SHORT-CIRCUIT PROTECTION MODE BL_EN = 1 BL_EN = 1 (REASSERTED) BL_EN = 0 BL_EN = 1 BL_EN = 0 Figure 35. Fade Override Function (FOVR Is High) 08391-022 MAX The ADP8861 can protect against short circuits on the output (VOUT). Short-circuit protection (SCP) is activated at the point when VOUT < 55% of VIN. Note that SCP sensing is disabled during both startup and restart attempts (fault recovery). SCP sensing is reenabled 4 ms (typical) after activation. During a short-circuit fault, the device enters a low current consumption state and an interrupt flag is set. The device can be restarted at any time after receiving a short-circuit fault by simply rewriting nSTBY = 1. It then repeats another complete soft start sequence. Note that the value of the output capacitance (COUT) should be small enough to allow VOUT to reach approximately 55% (typical) of VIN within the 4 ms (typical) time. If COUT is too large, the device inadvertently enters short-circuit protection. Rev. 0 | Page 16 of 40 ADP8861 OVERVOLTAGE PROTECTION Overvoltage protection (OVP) is implemented on the output. There are two types of overvoltage events: normal (no fault) and abnormal (from a fault or sudden load change). Normal Overvoltage In a normal (no fault) overvoltage, the output voltage approaches VOUT(REG) (4.9 V typical) during normal operation. This is not caused by a fault or load change, but it is simply a consequence of the input voltage times the gain reaching the same level as the clamped output voltage (VOUT(REG)). To prevent this type of overvoltage, the ADP8861 detects when the output voltage rises to VOUT(REG). It then increases the effective ROUT of the gain stage to reduce the voltage that is delivered. This effectively regulates VOUT to VOUT(REG); however, there is a limit to the effect that this system can have on regulating VOUT. It is designed only for normal operation and it is not intended to protect against faults or sudden load changes. When the output voltage is regulated to VOUT(REG), no interrupt is set and the operation is transparent to the LEDs and the overall application. pump resumes operation. If the fault or load event recurs, the process may repeat. An interrupt flag is set at each OVP instance. THERMAL SHUTDOWN/OVERTEMPERATURE PROTECTION If the die temperature of the ADP8861 rises above a safe limit (150°C typical), the controllers enter thermal shutdown (TSD) protection mode. In this mode, most of the internal functions shut down, the part enters standby, and the TSD_INT interrupt (Register 0x02) is set. When the die temperature decreases below ~130°C, the part can be restarted. To restart the part, simply remove it from standby. No interrupt is generated when the die temperature falls below 130°C. However, if the software clears the pending TSD_INT interrupt and the temperature remains above 130°C, another interrupt is generated. The complete state machine for these faults (SCP, OVP, and TSD) is shown in Figure 37. INTERRUPTS There are three interrupt sources available on the ADP8861 in Register 0x02. Abnormal Overvoltage Because of the open-loop behavior of the charge pump as well as how the gain transitions are computed, a sudden load change or fault can abnormally force VOUT beyond 6 V. This causes an abnormal overvoltage situation. If the event happens slowly enough, the system first tries to regulate the output to 4.9 V as in a normal overvoltage scenario. However, if this is not sufficient, or if the event happens too quickly, then the ADP8861 enters OVP mode when VOUT exceeds the OVP threshold (typically 5.8 V). In OVP mode, only the charge pump is disabled to prevent VOUT from rising too high. The current sources and all other device functionality remain intact. When the output voltage falls by about 500 mV (to 5.3 V typical), the charge • • • Overvoltage protection: The OVP_INT interrupt is generated when the output voltage exceeds 5.8 V (typical). Thermal shutdown circuit: An interrupt (TSD_INT) is generated when entering overtemperature protection. Short-circuit detection: SHORT_INT is generated when the device enters short-circuit protection mode. The interrupt (if any) that appears on the nINT pin is determined by the bits mapped in Register INTR_EN (0x03). To clear an interrupt, write a 1 to the interrupt in the MDCR2 register (0x02) or reset the part. Reading the interrupt, or writing a 0, has no effect. Rev. 0 | Page 17 of 40 ADP8861 STANDBY 0 EXIT STANDBY 1 TSD FAULT DIE TEMP > TSD EXIT STANDBY 0 1 STARTUP: CHARGE VIN TO VOUT DIE TEMP < TSD – TSD(HYS) SCP FAULT 0 VOUT > VOUT(START) 1 0 EXIT STARTUP VOUT < VOUT(SC) 0 1 VOUT < VOVP – VOVP(HYS) 0 0 G=1 WAIT 100µs (TYP) MIN (VD1:D7 ) < VHR(UP) 1 VOUT > VOVP 1 OVP FAULT 1 1 0 VOUT < VOVP – VOVP (HYS) 0 G = 1.5 WAIT 100µs (TYP) MIN (VD1:D7 ) < VHR(UP) 0 0 MIN (VD1:D7 ) > VDMAX VOUT > VOUT(REG) 1 1 1 0 OVP FAULT TRY TO REGULATE VOUT TO VOUT(REG) 1 VOUT > VOVP 0 1 VOUT < VOVP – VOVP (HYS) 0 0 1 WAIT 100µs (TYP) MIN (VD1:D7 ) > VDMAX VOUT > VOUT(REG) 1 0 OVP FAULT G=2 TRY TO REGULATE VOUT TO VOUT(REG) NOTES 1. VDMAX IS THE CALCULATED GAIN DOWN TRANSITION POINT. 08391-027 VOUT > VOVP Figure 37. Fault State Machine Rev. 0 | Page 18 of 40 ADP8861 APPLICATIONS INFORMATION The ADP8861 allows the charge pump to operate efficiently with a minimum of external components. Specifically, the user must select an input capacitor (CIN), output capacitor (COUT), and two charge pump fly capacitors (C1 and C2). CIN should be 1 μF or greater. The value must be high enough to produce a stable input voltage signal at the minimum input voltage and maximum output load. A 1 μF capacitor for COUT is recommended. Larger values are permissible, but care must be exercised to ensure that VOUT charges above 55% (typical) of VIN within 4 ms (typical). See the Short-Circuit Protection Mode section for more details. For best practice, it is recommended that the two charge pump fly capacitors be 1 μF; larger values are not recommended, and smaller values may reduce the ability of the charge pump to deliver maximum current. For optimal efficiency, the charge pump fly capacitors should have low equivalent series resistance (ESR). Low ESR X5R or X7R capacitors are recommended for all four components. The use of fly capacitors sized 0402 and smaller is allowed, but the GDWN_DIS bit in Register 0x01 must be set. Minimum voltage ratings should adhere to the guidelines in Table 6. VOUT is also equal to the largest Vf of the LEDs used plus the voltage drop across the regulating current source. This gives VOUT = Vf(MAX) + VDX Combining Equation 5 and Equation 6 gives VIN = (Vf(MAX) + VDX + IOUT × ROUT(G))/G DETERMINING THE TRANSITION POINT OF THE CHARGE PUMP Consider the following design example where: Vf(MAX) = 3.7 V IOUT = 140 mA (7 LEDs at 20 mA each) ROUT (G = 1.5×) = 3 Ω (obtained from Figure 12) At the point of a gain transition, VDX = VHR(UP). Table 1 gives the typical value of VHR(UP) as 0.2 V. Therefore, the input voltage level when the gain transitions from 1.5× to 2× is VIN = (3.7 V + 0.2 V + 140 mA × 3 Ω)/1.5 = 2.88 V LAYOUT GUIDELINES Note the following layout guidelines: Capacitor CIN COUT C1 C2 Gain = 1.5× VIN VIN × 1.5 (max of 5.5 V) VIN/2 VIN/2 Gain = 2× VIN VIN × 2.0 (max of 5.5 V) VIN VIN Any color LED can be used if the Vf (forward voltage) is less than 4.1 V. However, using lower Vf LEDs reduces the input power consumption by allowing the charge pump to operate at lower gain states. The equivalent circuit model for a charge pump is shown in Figure 38. VOUT ROUT COUT VDX 08391-140 G × VIN IOUT Figure 38. Charge Pump Equivalent Circuit Model The input voltage is multiplied by the gain (G) and delivered to the output through an effective resistance (ROUT). The output current flows through ROUT and produces an IR drop to yield: VOUT = G ×VIN − IOUT × ROUT(G) (5) (7) Equation 7 is useful for calculating approximate bounds for the charge pump design. Table 6. Capacitor Stress in Each Charge Pump Gain State Gain = 1× VIN VIN None None (6) The ROUT term is a combination of the RDSON resistance for the switches used in the charge pump and a small resistance, which accounts for the effective dynamic charge pump resistance. The ROUT level changes based upon the gain (the configuration of the switches). Typical ROUT values are given in Table 1, Figure 12, and Figure 13. Rev. 0 | Page 19 of 40 For optimal noise immunity, place the CIN and COUT capacitors as close to their respective pins as possible. These capacitors should share a short ground trace. If the LEDs are a significant distance from the VOUT pin, another capacitor on VOUT, placed closer to the LEDs, is advisable. For optimal efficiency, place the charge pump fly capacitors (C1 and C2) as close to the part as possible. The ADP8861 does not distinguish between power ground and analog ground. Therefore, both ground pins can be connected directly together. It is recommended that these ground pins be connected at the ground for the input and output capacitors. Unused diode pins (Pin D1 to Pin D7) can be connected to ground or to VOUT, or remain floating. However, the unused diode current sinks must be disabled by setting them as independent sinks in Register 0x05 and then disabling them in Register 0x10. If they are not disabled, the charge pump efficiency may suffer. If the interrupt pin (nINT) is not used, connect it to ground or leave it floating. Never connect it to a voltage supply, except through a ≥1 kΩ series resistor. The ADP8861 has an integrated noise filter on the nRST pin. Under normal conditions, it is not necessary to filter the reset line. However, if the part is exposed to an unusually noisy signal, it is beneficial to add a small RC filter or bypass capacitor on this pin. If the nRST pin is not used, it must be pulled well above the VIH(MIN) level (see Table 1). Do not allow the nRST pin to float. ADP8861 EXAMPLE CIRCUITS D1 D2 D3 D4 D5 D6 D7 VIN 1µF VOUT VDDIO 1µF nRST C1+ VDDIO ADP8861 SDA C1– VDDIO C1 1µF C2+ SCL C2– VDDIO C2 1µF GND1 08391-202 nINT GND2 Figure 39. Generic Application Schematic KEYPAD LIGHT UP TO 10 LEDs (6mA EACH) 60mA MAX TOTAL CURRENT DISPLAY BACKLIGHT DL1 DL2 DL3 DL4 D1 D2 D3 DL7 DL8 DL17 R5 R6 R15 ACCESSORY LIGHTS OR SUB-DISPLAY BL DL5 DL6 D4 D5 D6 D7 VIN VIN C2 C1 R1 nRST GND2 GND1 VDDIO R2 R3 VOUT ADP8861 R4 nRST C1+ SDA C1– SCL C2+ nINT C2– C4 nINT Figure 40. Application Schematic with Keypad Light Control Rev. 0 | Page 20 of 40 08391-029 C3 I2C CONTROL SIGNALS ADP8861 I2C PROGRAMMING AND DIGITAL CONTROL Table 7 through Table 55 provide register and bit descriptions. The reset value for all bits in the bit map tables is all 0s, except in Table 9 (see Table 9 for its unique reset value). Wherever the acronym N/A appears in the tables, it means not applicable. The ADP8861 provides full software programmability to facilitate its adoption in various product architectures. The default I2C address is 0101010x (x = 0 during write, x = 1 during read). Therefore, the default write address is 0x54 and the read address is 0x55. Note the following general behavior of registers: SELECT REGISTER TO WRITE B0 1 0 1 0 1 B7 0 R/W ACK DEVICE ID FOR READ OPERATION B0 REGISTER VALUE ACK ST 8-BIT VALUE TO WRITE IN THE ADDRESSED REGISTER STOP ACK RS 0 08391-200 DEVICE ID FOR WRITE OPERATION B7 B0 REGISTER ADDRESS FROM MASTER B7 0 R/W ACK FROM ADP8861 1 READ = 1 0 WRITE = 0 1 FROM ADP8861 0 REPEATED START B0 1 FROM ADP8861 B7 ST 0 SLAVE TO MASTER MASTER TO SLAVE Figure 41. I2C Read Command Sequence DEVICE ID FOR WRITE OPERATION 1 0 B7 R/W ACK B0 REGISTER ADDRESS SELECT REGISTER TO WRITE B7 ACK B0 REGISTER VALUE 8-BIT VALUE TO WRITE IN THE ADDRESSED REGISTER ACK ST 08391-201 0 STOP 1 FROM ADP8861 0 FROM ADP8861 B0 1 FROM ADP8861 0 WRITE = 0 B7 ST START • • All registers are set to their default values during reset or after a UVLO event. All registers are read/write unless otherwise specified. Unused bits are read as zero. START • SLAVE TO MASTER MASTER TO SLAVE Figure 42. I2C Write Command Sequence Rev. 0 | Page 21 of 40 ADP8861 Table 7. Register Set Definitions Address (Hex) 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B to 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A Register Name MFDVID MDCR MDCR2 INTR_EN CFGR BLSEN BLOFF BLDIM BLFR BLMX BLDM Reserved ISCFR ISCC ISCT1 ISCT2 ISCF ISC7 ISC6 ISC5 ISC4 ISC3 ISC2 ISC1 Description Manufacturer and device ID Device mode and status Device mode and Status Register 2 Interrupts enable Configuration register Sink enable, backlight or independent Backlight off timeout Backlight dim timeout Backlight fade in and fade out rates Backlight maximum current Backlight dim current Independent sink current fade control register Independent sink current control register Independent Sink Current Timer Register, LED[7:5] Independent Sink Current Timer Register, LED[4:1] Independent sink current fade register Independent Sink Current, LED7 Independent Sink Current, LED6 Independent Sink Current, LED5 Independent Sink Current, LED4 Independent Sink Current, LED3 Independent Sink Current, LED2 Independent Sink Current, LED1 Rev. 0 | Page 22 of 40 ADP8861 Table 8. Register Map Address (Hex) 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B to 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A Register Name MFDVID MDCR MDCR2 INTR_EN CFGR BLSEN BLOFF BLDIM BLFR BLMX BLDM N/A ISCFR ISCC ISCT1 ISCT2 ISCF ISC7 ISC6 ISC5 ISC4 ISC3 ISC2 ISC1 Bit 7 Reserved Reserved Reserved Reserved Bit 6 Bit 5 Manufacturer ID INT_CFG nSTBY Reserved Reserved Reserved D7EN D6EN Bit 4 Bit 3 DIM_EN SHORT_INT SHORT_IEN GDWN_DIS TSD_INT TSD_IEN D5EN D4EN OFFT DIMT Bit 2 Bit 1 Bit 0 Device ID SIS_EN Reserved BL_EN OVP_INT Reserved OVP_IEN Reserved Law FOVR D3EN D2EN D1EN BL_FO BL_FI Reserved Reserved Reserved SC7_EN SCON SC4_OFF BL_MC BL_DC Reserved SC6_EN Reserved SC5_EN SC7_OFF SC3_OFF SC4_EN SC3_EN SC6_OFF SC2_OFF SCFO SC2_EN SCFI SCR Reserved Reserved Reserved Reserved Reserved Reserved SCD7 SCD6 SCD5 SCD4 SCD3 SCD2 SCD1 Rev. 0 | Page 23 of 40 SC_LAW SC1_EN SC5_OFF SC1_OFF ADP8861 Manufacturer and Device ID (MFDVID)—Register 0x00 Multiple device revisions are tracked by the device ID field. This is a read-only register. Table 9. MFDVID Bit Map Bit 7 Bit 6 0 Bit 5 Manufacturer ID 1 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 Device ID 0 Bit 0 0 0 Mode Control Register (MDCR)—Register 0x01 Table 10. MDCR Bit Map Bit 7 Reserved Bit 6 INT_CFG Bit 5 nSTBY Bit 4 DIM_EN Bit 3 GDWN_DIS Bit 2 SIS_EN Bit 1 Reserved Bit 0 BL_EN Table 11. Bit Descriptions for the MDCR Register Bit Name N/A INT_CFG Bit No. 7 6 nSTBY 5 DIM_EN 4 GDWN_DIS 3 SIS_EN 2 N/A BL_EN 1 0 Description Reserved. Interrupt configuration. 1 = processor interrupt deasserts for 50 μs and reasserts with pending events. 0 = processor interrupt remains asserted if the host tries to clear the interrupt while there is a pending event. 1 = device is in active mode. 0 = device is in standby mode; only the I2C interface is enabled. DIM_EN is set by the hardware after a dim timeout. The user can also force the backlight into dim mode by asserting this bit. Dim mode can only be entered if BL_EN is also enabled. 1 = backlight is operating at the dim current level (BL_EN must also be asserted). 0 = backlight is not in dim mode. 1 = the charge pump does not switch down in gain until all LEDs are off. The charge pump switches up in gain as needed. This feature is useful if the ADP8861 charge pump is used to drive an external load. This feature must be used when utilizing small fly capacitors (0402 or smaller). 0 = the charge pump automatically switches up and down in gain. This provides optimal efficiency, but is not suitable for driving loads that are not connected through the ADP8861 diode drivers. Additionally, the charge pump fly capacitors should be low ESR and sized 0603 or greater. Synchronous independent sinks enable. 1 = enables all LED current sinks designated as independent sinks. This bit has no effect if any of the SCx_EN bits in Register 0x10 are set. 0 = disables all LED current sinks designated as independent sinks. This bit has no effect if any of the SCx_EN bits in Register 0x10 are set. Reserved. 1 = backlight is enabled (nSTBY must also be asserted). 0 = backlight is disabled. Rev. 0 | Page 24 of 40 ADP8861 Mode Control Register 2 (MDCR2)—Register 0x02 Table 12. MDCR2 Bit Map Bit 7 Bit 6 Reserved Bit 5 Bit 4 SHORT_INT Bit 3 TSD_INT Bit 2 OVP_INT Bit 1 Bit 0 Reserved Table 13. Bit Descriptions for the MDCR2 Register Bit Name N/A SHORT_INT Bit No. [7:5] 4 TSD_INT 3 OVP_INT 2 N/A 1:0 1 Description 1 Reserved Short-circuit error interrupt. 1 = a short-circuit or overload condition on VOUT has been detected. 0 = no short-circuit or overload condition has been detected. Thermal shutdown interrupt. 1 = the device temperature has exceeded 150°C (typical). 0 = no overtemperature condition has been detected. Overvoltage interrupt. 1 = VOUT has exceeded VOVP. 0 = VOUT has not exceeded VOVP. Reserved. Interrupt bits are cleared by writing a 1 to the flag; writing a 0 or reading the flag has no effect. Interrupt Enable (INTR_EN)—Register 0x03 Table 14. INTR_EN Bit Map Bit 7 Bit 6 Reserved Bit 5 Bit 4 SHORT_IEN Bit 3 TSD_IEN Bit 2 OVP_IEN Bit 1 Bit 0 Reserved Table 15. Bit Descriptions for the INTR_EN Register Bit Name N/A SHORT_IEN Bit No. [7:5] 4 TSD_IEN 3 OVP_IEN 2 N/A [1:0] Description Reserved. Short-circuit interrupt is enabled. When the SHORT_INT status bit is set after an error condition, an interrupt is raised to the host if the SHORT_IEN flag is enabled. 1 = the short-circuit interrupt is enabled. 0 = the short-circuit interrupt is disabled (the SHORT_INT flag continues to assert). Thermal shutdown interrupt is enabled. When the TSD_INT status bit is set after an error condition, an interrupt is raised to the host if the TSD_IEN flag is enabled. 1 = the thermal shutdown interrupt is enabled. 0 = the thermal shutdown interrupt is disabled (the TSD_INT flag continues to assert). Overvoltage interrupt enabled. When the OVP_INT status bit is set after an error condition, an interrupt is raised to the host if the OVP_IEN flag is enabled. 1 = the overvoltage interrupt is enabled. 0 = the overvoltage interrupt is disabled (the OVP_INT flag continues to assert). Reserved. Rev. 0 | Page 25 of 40 ADP8861 BACKLIGHT REGISTER DESCRIPTIONS Configuration Register (CFGR)—Register 0x04 Table 16. CFGR Bit Map Bit 7 Bit 6 Bit 5 Reserved Bit 4 Bit 3 Bit 2 Bit 1 Law Bit 0 FOVR Bit 1 D2EN Bit 0 D1EN Table 17. Bit Descriptions for the CFGR Register Bit Name N/A Law Bit No. [7:3] [2:1] FOVR 0 Description Reserved Backlight transfer law 00 = linear law DAC, linear time steps 01 = square law DAC, linear time steps 10 = square law DAC, nonlinear time steps (Cubic 10) 11 = square law DAC, nonlinear time steps (Cubic 11) Backlight fade override 1 = the backlight fade override is enabled 0 = the backlight fade override is disabled Backlight Sink Enable (BLSEN)—Register 0x05 Table 18. BLSEN Bit Map Bit 7 Reserved Bit 6 D7EN Bit 5 D6EN Bit 4 D5EN Bit 3 D4EN Bit 2 D3EN Table 19. Bit Descriptions for the BLSEN Register Bit Name N/A D7EN Bit No. 7 6 D6EN 5 D5EN 4 D4EN 3 D3EN 2 D2EN 1 D1EN 0 Description Reserved Diode 7 backlight sink enable 1 = selects LED7 as an independent sink 0 = connects LED7 sink to backlight enable (BL_EN) Diode 6 backlight sink enable 1 = selects LED6 as an independent sink 0 = connects LED6 sink to backlight enable (BL_EN) Diode 5 backlight sink enable 1 = selects LED5 as an independent sink 0 = connects LED5 sink to backlight enable (BL_EN) Diode 4 backlight sink enable 1 = selects LED4 as an independent sink 0 = connects LED4 sink to backlight enable (BL_EN) Diode 3 backlight sink enable 1 = selects LED3 as an independent sink 0 = connects LED3 sink to backlight enable (BL_EN) Diode 2 backlight sink enable 1 = selects LED2 as an independent sink 0 = connects LED2 sink to backlight enable (BL_EN) Diode 1 backlight sink enable 1 = selects LED1 as an independent sink 0 = connects LED1 sink to backlight enable (BL_EN) Rev. 0 | Page 26 of 40 ADP8861 Backlight Off Timeout (BLOFF)—Register 0x06 Table 20. BLOFF Bit Map Bit 7 Reserved Bit 6 Bit 5 Bit 4 Bit 3 OFFT Bit 2 Bit 1 Bit 0 Table 21. Bit Descriptions for the BLOFF Register Bit Name N/A OFFT Bit No. 7 [6:0] Description Reserved. Backlight off timeout. After the off timeout (OFFT) period, the backlight turns off. If the dim timeout (DIMT) is enabled, the off timeout starts after the dim timeout. 0000000 = timeout disabled 0000001 = 1 sec 0000010 = 2 sec 0000011 = 3 sec … 1111111 = 127 sec Backlight Dim Timeout (BLDIM)—Register 0x07 Table 22. BLDIM Bit Map Bit 7 Reserved Bit 6 Bit 5 Bit 4 Bit 3 DIMT Bit 2 Bit 1 Bit 0 Table 23. Bit Descriptions for the BLDIM Register Bit Name N/A DIMT Bit No. 7 [6:0] Description Reserved. Backlight dim timeout. After the dim timeout (DIMT) period, the backlight is set to the dim current value. The dim timeout starts after backlight reaches the maximum current. 0000000 = timeout disabled 0000001 = 1 sec 0000010 = 2 sec 0000011 = 3 sec … 1111111 = 127 sec Rev. 0 | Page 27 of 40 ADP8861 Backlight Fade (BLFR)—Register 0x08 Table 24. BLFR Bit Map Bit 7 Bit 6 Bit 5 BL_FO Bit 4 Bit 3 Bit 2 Bit 1 BL_FI Bit 0 Table 25. Bit Descriptions for the BLFR Register Bit Name BL_FO Bit No. [7:4] BL_FI [3:0] 1 Description Backlight fade out rate. If fade out is disabled (BL_FO = 0000), the backlight changes instantly (within 100 ms). If the fade out rate is set, the backlight fades from its current value to the dim or the off value. The times listed for BL_FO are for a full-scale fade out (30 mA to 0 mA). Fades between closer current values reduce the fade time. See the Automated Fade In and Fade Out section for more information. 0000 = 0.1 sec (fade out disabled) 1 0001 = 0.3 sec 0010 = 0.6 sec 0011 = 0.9 sec 0100 = 1.2 sec 0101 = 1.5 sec 0110 = 1.8 sec 0111 = 2.1 sec 1000 = 2.4 sec 1001 = 2.7 sec 1010 = 3.0 sec 1011 = 3.5 sec 1100 = 4.0 sec 1101 = 4.5 sec 1110 = 5.0 sec 1111 = 5.5 sec Backlight fade in rate. If fade in is disabled (BL_FI = 0000), the backlight changes instantly (within 100 ms). If the fade in rate is set, the backlight fades from its current value to its maximum value when the backlight is turned on. The times listed for BL_FI are for a full-scale fade in (0 mA to 30 mA). Fades between closer current values reduce the fade time. See the Automated Fade In and Fade Out section for more information. 0000 = 0.1 sec (fade in disabled)1 0001 = 0.3 sec 0010 = 0.6 sec 0011 = 0.9 sec … 1111 = 5.5 sec When fade in and fade out are disabled, the backlight does not instantly fade, but instead, fades rapidly within about 100 ms. Rev. 0 | Page 28 of 40 ADP8861 Backlight Maximum Current Register (BLMX)—Register 0x09 Table 26. BLMX Bit Map Bit 7 Reserved Bit 6 Bit 5 Bit 4 Bit 3 BL_MC Bit 2 Bit 1 Bit 0 Table 27. Bit Descriptions for the BLMX Register Bit Name N/A BL_MC Bit No. 7 [6:0] Description Reserved. Backlight maximum current. The backlight maximum current can be set according to the linear or square law function (see Table 28 for a complete list of values). DAC Linear Law (mA) Square Law (mA) 0000000 0 0.000 0000001 0.236 0.002 0000010 0.472 0.007 0000011 0.709 0.017 … … … 1111111 30 30 Table 28. Linear and Square Law Currents Per DAC Code (SCR = 0) DAC Code 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 Linear Law (mA) 0 0.236 0.472 0.709 0.945 1.181 1.417 1.654 1.890 2.126 2.362 2.598 2.835 3.071 3.307 3.543 3.780 4.016 4.252 4.488 4.724 4.961 5.197 5.433 5.669 5.906 6.142 6.378 6.614 6.850 7.087 7.323 7.559 7.795 Square Law (mA) 1 0.000 0.002 0.007 0.017 0.030 0.047 0.067 0.091 0.119 0.151 0.186 0.225 0.268 0.314 0.365 0.419 0.476 0.538 0.603 0.671 0.744 0.820 0.900 0.984 1.071 1.163 1.257 1.356 1.458 1.564 1.674 1.787 1.905 2.026 DAC Code 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 0x40 0x41 0x42 0x43 Rev. 0 | Page 29 of 40 Linear Law (mA) 8.031 8.268 8.504 8.740 8.976 9.213 9.449 9.685 9.921 10.157 10.394 10.630 10.866 11.102 11.339 11.575 11.811 12.047 12.283 12.520 12.756 12.992 13.228 13.465 13.701 13.937 14.173 14.409 14.646 14.882 15.118 15.354 15.591 15.827 Square Law (mA) 1 2.150 2.279 2.411 2.546 2.686 2.829 2.976 3.127 3.281 3.439 3.601 3.767 3.936 4.109 4.285 4.466 4.650 4.838 5.029 5.225 5.424 5.627 5.833 6.043 6.257 6.475 6.696 6.921 7.150 7.382 7.619 7.859 8.102 8.350 ADP8861 DAC Code 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F 0x60 0x61 Linear Law (mA) 16.063 16.299 16.535 16.772 17.008 17.244 17.480 17.717 17.953 18.189 18.425 18.661 18.898 19.134 19.370 19.606 19.842 20.079 20.315 20.551 20.787 21.024 21.260 21.496 21.732 21.968 22.205 22.441 22.677 22.913 Square Law (mA) 1 8.601 8.855 9.114 9.376 9.642 9.912 10.185 10.463 10.743 11.028 11.316 11.608 11.904 12.203 12.507 12.814 13.124 13.439 13.757 14.078 14.404 14.733 15.066 15.403 15.743 16.087 16.435 16.787 17.142 17.501 DAC Code 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F 1 Linear Law (mA) 23.150 23.386 23.622 23.858 24.094 24.331 24.567 24.803 25.039 25.276 25.512 25.748 25.984 26.220 26.457 26.693 26.929 27.165 27.402 27.638 27.874 28.110 28.346 28.583 28.819 29.055 29.291 29.528 29.764 30.000 Square Law (mA) 1 17.863 18.230 18.600 18.974 19.351 19.733 20.118 20.507 20.899 21.295 21.695 22.099 22.506 22.917 23.332 23.750 24.173 24.599 25.028 25.462 25.899 26.340 26.784 27.232 27.684 28.140 28.599 29.063 29.529 30.000 Cubic 10 and Cubic 11 laws use the square law DAC setting but vary the time step per DAC code (see Figure 29). Rev. 0 | Page 30 of 40 ADP8861 Backlight Dim Current Register (BLDM)—Register 0x0A Table 29. BLDM Bit Map Bit 7 Reserved Bit 6 Bit 5 Bit 4 Bit 3 BL_DC Bit 2 Bit 1 Bit 0 Table 30. Bit Descriptions for the BLDM Register Bit Name N/A BL_DC Bit No. 7 [6:0] Description Reserved. Backlight dim current. The backlight is set to the dim current value after a dim timeout or if the DIM_EN flag is set by the user (see Table 28 for a complete list of values). DAC Linear Law (mA) Square Law (mA) 0000000 0 0.000 0000001 0.236 0.002 0000010 0.472 0.007 0000011 0.709 0.017 … … … 1111111 30 30 INDEPENDENT SINK REGISTER DESCRIPTIONS Independent Sink Current Fade Control Register (ISCFR)—Register 0x0F Table 31. ISCFR Bit Map Bit 7 Bit 6 Bit 5 Bit 4 Reserved Bit 3 Bit 2 Bit 1 Bit 0 SC_LAW Table 32. Bit Descriptions for the ISCFR Bit Name N/A SC_LAW Bit No. [7:2] [1:0] Description Reserved Independent sink current fade transfer law 00 = linear law DAC, linear time steps 01 = square law DAC, linear time steps 10 = square law DAC, nonlinear time steps (Cubic 10) 11 = square law DAC, nonlinear time steps (Cubic 11) Independent Sink Current Control (ISCC)—Register 0x10 Table 33. ISCC Bit Map Bit 7 Reserved Bit 6 SC7_EN Bit 5 SC6_EN Bit 4 SC5_EN Bit 3 SC4_EN Table 34. Bit Descriptions for the ISCC Register Bit Name N/A SC7_EN Bit No. 7 6 SC6_EN 5 SC5_EN 4 Description Reserved This enable acts upon LED7 1 = SC7 is turned on 0 = SC7 is turned off This enable acts upon LED6 1 = SC6 is turned on 0 = SC6 is turned off This enable acts upon LED5 1 = SC5 is turned on 0 = SC5 is turned off Rev. 0 | Page 31 of 40 Bit 2 SC3_EN Bit 1 SC2_EN Bit 0 SC1_EN ADP8861 Bit Name SC4_EN Bit No. 3 Description This enable acts upon LED4 1 = SC4 is turned on 0 = SC4 is turned off SC3_EN 2 SC2_EN 1 SC1_EN 0 This enable acts upon LED3 1 = SC3 is turned on 0 = SC3 is turned off This enable acts upon LED2 1 = SC2 is turned on 0 = SC2 is turned off This enable acts upon LED1 1 = SC1 is turned on 0 = SC1 is turned off Independent Sink Current Time (ISCT1)—Register 0x11 Table 35. ISCT1 Bit Map Bit 7 Bit 6 SCON Bit 5 Bit 4 SC7_OFF Bit 3 Bit 2 SC6_OFF Bit 1 Bit 0 SC5_OFF Table 36. Bit Descriptions for the ISCT1 Register Bit Name SCON Bit No. [7:6] Description 1 SC on time. If the SCx_OFF time is not disabled and the independent current sink is enabled (Register 0x10), the LED(s) remains on for the on time selected (per the following list) and then turns off. 00 = 0.2 sec 01 = 0.6 sec 10 = 0.8 sec 11 = 1.2 sec SC7_OFF [5:4] SC6_OFF [3:2] SC5_OFF [1:0] 1 SC7 off time. When the SC off time is disabled, the ISC remains on while enabled. When the SC off time is set to any other value, then the ISC turns off for the off time (per the following listed times) and then turns on according to the SCON setting. 00 = off time disabled 01 = 0.6 sec 10 = 1.2 sec 11 = 1.8 sec SC6 off time. When the SC off time is disabled, the ISC remains on while enabled. When the SC off time is set to any other value, then the ISC turns off for the off time (per the following listed times) and then turns on according to the SCON setting. 00 = off time disabled 01 = 0.6 sec 10 = 1.2 sec 11 = 1.8 sec SC5 off time. When the SC off time is disabled, the ISC remains on while enabled. When the SC off time is set to any other value, then the ISC turns off for the off time (per the following listed times) and then turns on according to the SCON setting. 00 = off time disabled 01 = 0.6 sec 10 = 1.2 sec 11 = 1.8 sec Each current sink remains on continuously when its enable is set to 1 and its off time is set to 00 (disabled). Rev. 0 | Page 32 of 40 ADP8861 Independent Sink Current Time (ISCT2)—Register 0x12 Table 37. ISCT2 Bit Map Bit 7 Bit 6 SC4_OFF Bit 5 Bit 4 SC3_OFF Bit 3 Bit 2 SC2_OFF Bit 1 Bit 0 SC1_OFF Table 38. Bit Descriptions for the ISCT2 Register Bit Name SC4_OFF Bit No. [7:6] SC3_OFF [5:4] SC2_OFF [3:2] SC1_OFF [1:0] 1 Description 1 SC4 off time. When the SC off time is disabled, the ISC remains on while enabled. When the SC off time is set to any other value, then the ISC turns off for the off time (per the following listed times) and then turns on according to the SCON setting. 00 = off time disabled 01 = 0.6 sec 10 = 1.2 sec 11 = 1.8 sec SC3 off time. When the SC off time is disabled, the ISC remains on while enabled. When the SC off time is set to any other value, then the ISC turns off for the off time (per the following listed times) and then turns on according to the SCON setting. 00 = off time disabled 01 = 0.6 sec 10 = 1.2 sec 11 = 1.8 sec SC2 off time. When the SC off time is disabled, the ISC remains on while enabled. When the SC off time is set to any other value, then the ISC turns off for the off time (per the following listed times) and then turns on according to the SCON setting. 00 = off time disabled 01 = 0.6 sec 10 = 1.2 sec 11 = 1.8 sec SC1 off time. When the SC off time is disabled, the ISC remains on while enabled. When the SC off time is set to any other value, then the ISC turns off for the off time (per the following listed times) and then turns on according to the SCON setting. 00 = off time disabled 01 = 0.6 sec 10 = 1.2 sec 11 = 1.8 sec Each current sink remains on continuously when its enable is set to 1 and its off time is set to 00 (disabled). Rev. 0 | Page 33 of 40 ADP8861 Independent Sink Current Fade (ISCF)—Register 0x13 Table 39. ISCF Bit Map Bit 7 Bit 6 Bit 5 SCFO Bit 4 Bit 3 Bit 2 Bit 1 SCFI Bit 0 Table 40. Bit Descriptions for the ISCF Register Bit Name SCFO Bit No. [7:4] SCFI [3:0] Description Sink current fade out rate. The following times listed are for a full-scale fade out (30 mA to 0 mA). Fades between closer current values reduce the fade time. See the Automated Fade In and Fade Out section for more information. 0000 = disabled 0001 = 0.30 sec 0010 = 0.60 sec 0011 = 0.90 sec 0100 = 1.2 sec 0101 = 1.5 sec 0110 = 1.8 sec 0111 = 2.1 sec 1000 = 2.4 sec 1001 = 2.7 sec 1010 = 3.0 sec 1011 = 3.5 sec 1100 = 4.0 sec 1101 = 4.5 sec 1110 = 5.0 sec 1111 = 5.5 sec Sink current fade in rate. The following times listed are for a full-scale fade in (0 mA to 30 mA). Fades between closer current values reduce the fade time. See the Automated Fade In and Fade Out section for more information. 0000 = disabled 0001 = 0.30 sec 0010 = 0.60 sec 0011 = 0.90 sec 0100 = 1.2 sec 0101 = 1.5 sec 0110 = 1.8 sec 0111 = 2.1 sec 1000 = 2.4 sec 1001 = 2.7 sec 1010 = 3.0 sec 1011 = 3.5 sec 1100 = 4.0 sec 1101 = 4.5 sec 1110 = 5.0 sec 1111 = 5.5 sec Rev. 0 | Page 34 of 40 ADP8861 Sink Current Register LED7 (ISC7)—Register 0x14 Table 41. ISC7 Bit Map Bit 7 SCR Bit 6 Bit 5 Bit 4 Bit 3 SCD7 Bit 2 Bit 1 Bit 0 Table 42. Bit Descriptions for the ISC7 Register Bit Name SCR Bit No. 7 SCD7 [6:0] Description 1 = Sink Current 1. 0 = Sink Current 0. For Sink Current 0, use the following DAC code schedule (see Table 28 for a complete list of values): DAC Linear Law (mA) Square Law (mA) 0000000 0 0.000 0000001 0.236 0.002 0000010 0.472 0.007 0000011 0.709 0.017 … … … 1111111 30 30 For Sink Current 1, use the following DAC code schedule (see Table 43 for a complete list of values): DAC Linear Law (mA) Square Law (mA) 0000000 0.000 0 0000001 0.472 0.004 0000010 0.945 0.014 0000011 1.417 0.034 … … … 1111111 60 60 Table 43. Linear and Square Law Currents for LED7 (SCR = 1) DAC Code 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 Linear Law (mA) 0.000 0.472 0.945 1.42 1.89 2.36 2.83 3.31 3.78 4.25 4.72 5.20 5.67 6.14 6.61 7.09 7.56 8.03 8.50 8.98 9.45 9.92 10.39 10.87 11.34 Square Law (mA) 1 0 0.004 0.014 0.034 0.06 0.094 0.134 0.182 0.238 0.302 0.372 0.45 0.536 0.628 0.73 0.838 0.952 1.076 1.206 1.342 1.488 1.64 1.8 1.968 2.142 DAC Code 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 Rev. 0 | Page 35 of 40 Linear Law (mA) 11.81 12.28 12.76 13.23 13.70 14.17 14.65 15.12 15.59 16.06 16.54 17.01 17.48 17.95 18.43 18.90 19.37 19.84 20.31 20.79 21.26 21.73 22.20 22.68 23.15 Square Law (mA) 1 2.326 2.514 2.712 2.916 3.128 3.348 3.574 3.81 4.052 4.3 4.558 4.822 5.092 5.372 5.658 5.952 6.254 6.562 6.878 7.202 7.534 7.872 8.218 8.57 8.932 ADP8861 DAC Code 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 Linear Law (mA) 23.62 24.09 24.57 25.04 25.51 25.98 26.46 26.93 27.40 27.87 28.35 28.82 29.29 29.76 30.24 30.71 31.18 31.65 32.13 32.60 33.07 33.54 34.02 34.49 34.96 35.43 35.91 36.38 36.85 37.32 37.80 38.27 38.74 39.21 39.69 40.16 40.63 41.10 41.57 Square Law (mA) 1 9.3 9.676 10.058 10.45 10.848 11.254 11.666 12.086 12.514 12.95 13.392 13.842 14.3 14.764 15.238 15.718 16.204 16.7 17.202 17.71 18.228 18.752 19.284 19.824 20.37 20.926 21.486 22.056 22.632 23.216 23.808 24.406 25.014 25.628 26.248 26.878 27.514 28.156 28.808 DAC Code 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F 1 Linear Law (mA) 42.05 42.52 42.99 43.46 43.94 44.41 44.88 45.35 45.83 46.30 46.77 47.24 47.72 48.19 48.66 49.13 49.61 50.08 50.55 51.02 51.50 51.97 52.44 52.91 53.39 53.86 54.33 54.80 55.28 55.75 56.22 56.69 57.17 57.64 58.11 58.58 59.06 59.53 60 Square Law (mA) 1 29.466 30.132 30.806 31.486 32.174 32.87 33.574 34.284 35.002 35.726 36.46 37.2 37.948 38.702 39.466 40.236 41.014 41.798 42.59 43.39 44.198 45.012 45.834 46.664 47.5 48.346 49.198 50.056 50.924 51.798 52.68 53.568 54.464 55.368 56.28 57.198 58.126 59.058 60 Cubic 10 and Cubic 11 laws use the square law DAC setting but vary the time step per DAC code (see Figure 29). Rev. 0 | Page 36 of 40 ADP8861 Sink Current Register LED6 (ISC6)—Register 0x15 Table 44. ISC6 Bit Map Bit 7 Reserved Bit 6 Bit 5 Bit 4 Bit 3 SCD6 Bit 2 Bit 1 Bit 0 Table 45. Bit Descriptions for the ISC6 Register Bit Name N/A SCD6 Bit No. 7 [6:0] Description Reserved. Sink current. Use the following DAC code schedule (see Table 28 for a complete list of values). DAC Linear Law (mA) Square Law (mA) 0000000 0 0.000 0000001 0.236 0.002 0000010 0.472 0.007 0000011 0.709 0.017 … … … 1111111 30 30 Sink Current Register LED5 (ISC5)—Register 0x16 Table 46. ISC5 Bit Map Bit 7 Reserved Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SCD5 Table 47. Bit Descriptions for the ISC5 Register Bit Name N/A SCD5 Bit No. 7 [6:0] Description Reserved. Sink current. Use the following DAC code schedule (see Table 28 for a complete list of values): DAC Linear Law (mA) Square Law (mA) 0000000 0 0.000 0000001 0.236 0.002 0000010 0.472 0.007 0000011 0.709 0.017 … … … 1111111 30 30 Sink Current Register LED4 (ISC4)—Register 0x17 Table 48. ISC4 Bit Map Bit 7 Reserved Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 SCD4 Table 49. Bit Descriptions for the ISC4 Register Bit Name N/A SCD4 Bit No. 7 [6:0] Description Reserved. Sink current. Use the following DAC code schedule (see Table 28 for a complete list of values): DAC Linear Law (mA) Square Law (mA) 0000000 0 0 0000001 0.236 0.002 0000010 0.472 0.007 0000011 0.709 0.017 … … … 1111111 30 30 Rev. 0 | Page 37 of 40 Bit 0 ADP8861 Sink Current Register LED3 (ISC3)—Register 0x18 Table 50. ISC3 Bit Map Bit 7 Reserved Bit 6 Bit 5 Bit 4 Bit 3 SCD3 Bit 2 Bit 1 Bit 0 Table 51. Bit Descriptions for the ISC3 Register Bit Name N/A SCD3 Bit No. 7 [6:0] Description Reserved. Sink current. Use the following DAC code schedule (see Table 28 for a complete list of values): DAC Linear Law (mA) Square Law (mA) 0000000 0 0.000 0000001 0.236 0.002 0000010 0.472 0.007 0000011 0.709 0.017 … … … 1111111 30 30 Sink Current Register LED2 (ISC2)—Register 0x19 Table 52. ISC2 Bit Map Bit 7 Reserved Bit 6 Bit 5 Bit 4 Bit 3 SCD2 Bit 2 Bit 1 Bit 0 Table 53. Bit Descriptions for the ISC2 Register Bit Name N/A SCD2 Bit No. 7 [6:0] Description Reserved. Sink current. Use the following DAC code schedule (see Table 28 for a complete list of values): DAC Linear Law (mA) Square Law (mA) 0000000 0 0.000 0000001 0.236 0.002 0000010 0.472 0.007 0000011 0.709 0.017 … … … 1111111 30 30 Sink Current Register LED1 (ISC1)—Register 0x1A Table 54. ISC1 Bit Map Bit 7 Reserved Bit 6 Bit 5 Bit 4 Bit 3 SCD1 Bit 2 Bit 1 Table 55. Bit Descriptions for the ISC1 Register Bit Name N/A SCD1 Bit No. 7 [6:0] Description Reserved. Sink current. Use the following DAC code schedule (see Table 28 for a complete list of values): DAC Linear Law (mA) Square Law (mA) 0000000 0 0.000 0000001 0.236 0.002 0000010 0.472 0.007 0000011 0.709 0.017 … … … 1111111 30 30 Rev. 0 | Page 38 of 40 Bit 0 ADP8861 OUTLINE DIMENSIONS PIN 1 INDICATOR 4.10 4.00 SQ 3.90 0.30 0.25 0.20 0.50 BSC 20 16 15 PIN 1 INDICATOR 1 EXPOSED PAD 2.65 2.50 SQ 2.35 5 11 0.80 0.75 0.70 0.50 0.40 0.30 10 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 6 0.25 MIN BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 061609-B TOP VIEW COMPLIANT TO JEDEC STANDARDS MO-220-WGGD. 08391-203 Figure 43. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 4 mm × 4 mm Body, Very Thin Quad (CP-20-10) Dimensions shown in millimeters Figure 44. Tape and Reel Orientation for LFCSP Units ORDERING GUIDE Model1 ADP8861ACPZ-RL ADP8861DBCB-EVALZ ADP886XMB1-EVALZ 1 Temperature Range −40°C to +85°C Package Description 20-Lead LFCSP_WQ, 7” Tape and Reel Daughter Card USB-to-I2C Adapter Board Z = RoHS Compliant Part. Rev. 0 | Page 39 of 40 Package Option CP-20-10 ADP8861 NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08391-0-4/10(0) Rev. 0 | Page 40 of 40