Philips Semiconductors Product specification PowerMOS transistor Logic level FET GENERAL DESCRIPTION N-channel enhancement mode logic level field-effect power transistor in a plastic envelope suitable for surface mount applications. The device is intended for use in automotive and general purpose switching applications. PINNING - SOT404 PIN BUK565-60H QUICK REFERENCE DATA SYMBOL PARAMETER VDS ID Ptot Tj RDS(ON) Drain-source voltage Drain current (DC) Total power dissipation Junction temperature Drain-source on-state resistance; VGS = 5 V PIN CONFIGURATION MAX. UNIT 60 41 125 175 38 V A W ˚C mΩ SYMBOL DESCRIPTION d mb 1 gate 2 drain 3 source g mb drain 2 1 s 3 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS VDS VDGR ±VGS ±VGSM Drain-source voltage Drain-gate voltage Gate-source voltage Non-repetitive gate-source voltage Drain current (DC) Drain current (DC) Drain current (pulse peak value) Total power dissipation Storage temperature Junction temperature ID ID IDM Ptot Tstg Tj MIN. MAX. UNIT RGS = 20 kΩ tp ≤ 50 µs - 60 60 15 20 V V V V Tmb = 25 ˚C Tmb = 100 ˚C Tmb = 25 ˚C Tmb = 25 ˚C - - 55 - 41 29 164 125 175 175 A A A W ˚C ˚C THERMAL RESISTANCES SYMBOL PARAMETER Rth j-mb Thermal resistance junction to mounting base Thermal resistance junction to ambient Rth j-a June 1995 CONDITIONS minimum footprint, FR4 board (see Fig. 18) 1 TYP. MAX. UNIT - 1.2 K/W 50 - K/W Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level FET BUK565-60H STATIC CHARACTERISTICS Tmb = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS V(BR)DSS Drain-source breakdown voltage Gate threshold voltage Zero gate voltage drain current Zero gate voltage drain current Gate source leakage current Drain-source on-state resistance VGS(TO) IDSS IDSS IGSS RDS(ON) MIN. TYP. MAX. UNIT VGS = 0 V; ID = 0.25 mA 60 - - V VDS = VGS; ID = 1 mA VDS = 60 V; VGS = 0 V; Tj = 25 ˚C VDS = 60 V; VGS = 0 V; Tj =125 ˚C VGS = ±15 V; VDS = 0 V VGS = 5 V; ID = 20 A 1.0 - 1.5 1 0.1 10 25 2.0 10 1.0 100 38 V µA mA nA mΩ MIN. TYP. MAX. UNIT 11 20 - S DYNAMIC CHARACTERISTICS Tmb = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS gfs Forward transconductance VDS = 25 V; ID = 20 A Ciss Coss Crss Input capacitance Output capacitance Feedback capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 1200 470 180 1750 600 275 pF pF pF td on tr td off tf Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time VDD = 30 V; ID = 3 A; VGS = 5 V; RGS = 50 Ω; Rgen = 50 Ω - 25 120 160 110 40 150 220 145 ns ns ns ns Ld Internal drain inductance - 3.5 - nH Ld Internal drain inductance - 4.5 - nH Ls Internal source inductance Measured from contact screw on tab to centre of die Measured from drain lead 6 mm from package to centre of die Measured from source lead 6 mm from package to source bond pad - 7.5 - nH MIN. TYP. MAX. UNIT REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tmb = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS IDR - - - 41 A IDRM VSD Continuous reverse drain current Pulsed reverse drain current Diode forward voltage IF = 41 A ; VGS = 0 V - 0.95 164 2.0 A V trr Qrr Reverse recovery time Reverse recovery charge IF = 41 A; -dIF/dt = 100 A/µs; VGS = 0 V; VR = 30 V - 60 0.30 - ns µC MIN. TYP. MAX. UNIT - - 90 mJ AVALANCHE LIMITING VALUE Tmb = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS WDSS Drain-source non-repetitive unclamped inductive turn-off energy ID = 41 A ; VDD ≤ 25 V ; VGS = 5 V ; RGS = 50 Ω June 1995 2 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level FET 120 BUK565-60H Normalised Power Derating PD% 10 Zth j-mb / (K/W) BUKx55-lv 110 100 90 1 D= 0.5 80 0.1 0.2 0.1 0.05 0.02 0.01 0 70 60 50 40 30 tp PD D= 20 10 0 0 20 40 60 80 100 Tmb / C 120 140 160 180 Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Tmb) 120 1E-05 1E-03 t/s 1E-01 1E+01 Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T Normalised Current Derating ID% t T 0.001 1E-07 tp T ID / A 100 BUK5Y5-60H 10 15 110 100 6 5 80 90 4.5 80 60 70 4 60 50 40 3.5 40 30 3 20 20 10 VGS / V = 2.5 0 0 20 40 60 80 100 Tmb / C 120 140 160 0 180 ID / A = 6 8 10 0.2 RDS(ON) / Ohm 2.5 3 BUK5Y5-60H 3.5 4 4.5 ID S/ N) 4 Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS); parameter VGS BUK555-60H 100 2 VDS / V Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V 1000 0 0.15 tp = VD VGS / V = 5 10 us O S( RD 0.1 100 us 10 10 1 ms DC 0.05 10 ms 100 ms 6 15 0 1 1 10 VDS / V 100 20 40 60 80 100 ID / A Fig.3. Safe operating area. Tmb = 25 ˚C ID & IDM = f(VDS); IDM single pulse; parameter tp June 1995 0 Fig.6. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(ID); parameter VGS 3 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level FET 100 BUK565-60H ID / A VGS(TO) / V BUK5Y5-60H max. 2 80 typ. 60 20 Tj / C = -40 25 150 0 0 1 2 3 4 VGS / V 5 6 7 0 8 -60 Fig.7. Typical transfer characteristics. ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj gfs / S 40 min. 1 40 -20 20 60 Tj / C 100 140 180 Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS BUK5Y5-60H 1E-01 SUB-THRESHOLD CONDUCTION ID / A 1E-02 30 2% 1E-03 98 % typ 20 1E-04 10 1E-05 Tj / C = -40 25 150 0 0 20 40 60 80 1E-06 100 0 0.4 0.8 ID / A Fig.8. Typical transconductance, Tj = 25 ˚C. gfs = f(ID); conditions: VDS = 10 V 2.0 a 1.2 VGS / V 1.6 2 2.4 Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS Normalised RDS(ON) = f(Tj) 10000 BUK5Y5-60H C / pF Ciss Coss Crss 1.5 1.0 1000 0.5 0 -60 -20 20 60 Tj / C 100 140 100 0.1 180 10 100 VDS / V Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 20 A; VGS = 5 V June 1995 1 Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz 4 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level FET BUK565-60H BUK5Y5-60H VGS / V 15 120 WDSS% 110 100 90 VDD / V = 12 80 10 48 70 60 50 40 5 30 20 10 0 0 10 20 30 40 50 60 70 0 80 20 40 QG / nC Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG); conditions: ID = 41 A; parameter VDS IS / A 100 60 80 100 120 Tmb / C 160 180 Fig.15. Normalised avalanche energy rating. WDSS% = f(Tmb); conditions: ID = 41 A BUKXY5-60H Tj / C = VDD + -40 25 150 80 140 L VDS - 60 VGS -ID/100 40 T.U.T. 0 20 0 RGS 0 0.5 1 R 01 shunt 1.5 VSDS / V Fig.16. Avalanche energy test circuit. WDSS = 0.5 ⋅ LID2 ⋅ BVDSS /(BVDSS − VDD ) Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj June 1995 5 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level FET BUK565-60H MECHANICAL DATA Dimensions in mm 4.5 max 1.4 max 10.3 max Net Mass: 1.4 g 11 max 15.4 2.5 0.85 max (x2) 0.5 2.54 (x2) Fig.17. SOT404 : centre pin connected to mounting base. MOUNTING INSTRUCTIONS Dimensions in mm 11.5 9.0 17.5 2.0 3.8 5.08 Fig.18. SOT404 : soldering pattern for surface mounting. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Epoxy meets UL94 V0 at 1/8". June 1995 6 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level FET BUK565-60H DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 1996 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. June 1995 7 Rev 1.000 Error Log 565-60.H 1) Level: Format Error Message: Word is wider than column Location: Document Body Page: 1 Distance from TOF: 7.14cm Level: 1 Section: 1 Block: Text #1 Column: 6 level field-effect power transistor in Page E1 96-11-11 04:15 pm