E2U0057-38-21 ¡ Semiconductor MSM7617 ¡ Semiconductor This version: Feb. 1999 MSM7617 Previous version: Aug. 1998 2-Channel Echo Canceler GENERAL DESCRIPTION The MSM7617 cancels echoes (acoustic or line echoes) generated in voice channels. It is a lowpower CMOS LSI device with two channels. MSM7617 echo canceling is performed by digital signal processing. It negates echoes by estimating the echo channel and then generating a pseudo-echo signal. When used as an acoustic echo canceler, the MSM7617 can cancel acoustic echoes between speaker and microphone that occur during hands-free speaking with car phones, conferencing system phones, etc. When used as a line echo canceler, the MSM7617 can cancel line echoes returned by hybrid impedance mismatches. By setting its mode for use as a single cross-connected channel, the MSM7617 can cancel both acoustic and line echoes. Also, the MSM7617 can improve voice communication by using its howling detection, doubletalk detection, attenuation, and gain control functions to prevent and suppress howling levels, and by using its center clipping function to suppress low level noise. Furthermore, the MSM7617 can disable echo canceling during data communication with its 2100 Hz tone detector and 2100 Hz phase reversal detector. It also provides the ability to attenuate SIN levels, to amplify SOUT levels, and to adjust input/output levels. An economical and highly efficient echo canceler unit can be constructed by using a 2-channel single-chip CODEC like the MSM7533 together with the MSM7617. 1/28 ¡ Semiconductor MSM7617 FEATURES •Echo canceler has two channels, which can be used for acoustic and line echoes. Set as a single cross-connected channel, it can be used for both acoustic and line echoes. •ITU-T G164/G165 standard tone disabler. •PCM line level adjustment possible with SIN level attenuator (SA pin) and SOUT level amplifier (SG pin). Can also be used for ERL amplification with the SIN level attenuator (SA pin). •RGC pin provides input/output adjustment mode (±6LR mode) that can prevent malfunction due to excessive inputs without changing the RIN-ROUT input/output levels. •Cancelable echo delay time: 55 ms (max.) •Echo attenuation: 30 dB (typ.) •Clock frequency: 18 to 20 MHz 19.2 MHz if using internal clock signal •Power supply voltage: 4.5 to 5.5 V •Package: 64-pin plastic QFP (QFP64-P-1414-0.80-BK) •Product name: MSM7617-001GS-BK (m-law) 2/28 ¡ Semiconductor MSM7617 BLOCK DIAGRAM RIN1 Non-linear/ Linear S/P –6LR ATT GC Linear/ Non-linear +6LR P/S ROUT1 DF1 Howling Detector Double Talk Detector Power Calculator Adaptive FIR Filter (AFF) 2100 Hz Tone, Phase Reverse Detector CH1 WDT1 – SOUT1 RIN2 Linear/ Non-linear P/S Non-linear/ Linear S/P Center Clip SG –6LR + ATT +6LR –6LR SA + ATT GC +6LR Non-linear/ Linear S/P SIN1 Linear/ Non-linear P/S ROUT2 DF2 Howling Detector Double Talk Detector Power Calculator Adaptive FIR Filter (AFF) 2100 Hz Tone, Phase Reverse Detector CH2 WDT2 – SOUT2 Linear/ Non-linear P/S SG Center Clip +6LR + ATT –6LR SA + Non-linear/ Linear S/P SIN2 SYNCO EC-A Controller EC-B Controller I/O Controller IOM0,1 SCK SYNC1 SYNC2 NLP2 HCL2 ADP2 RST2 HD2 ATT2 SG20,21 SA20,21 GC20,21 ECDM0,1 ECM PLL CLKIN VSS (PLL) VSS NLP1 HCL1 ADP1 RST1 HD1 ATT1 SG10,11 SA10,11 RGC1011 VDD (PLL) VDD Clock Generator PWDWN SCKO The above diagram shows internal connections for 2-channel parallel mode. The internal connections for 2-channel serial I/O mode and 1-channel cross-connected mode are shown below. 2-channel parallel I/O mode 2-channel serial I/O mode CH1 RIN1 RIN ROUT ROUT1 RIN1 RIN AFF SOUT1 SOUT + RIN SIN1 SOUT1 SOUT SOUT2 + ROUT1 RIN + ROUT2 RIN SIN1 SOUT SIN2 SOUT + ROUT1 + SIN SIN1 CH2 ROUT RIN AFF SIN ROUT AFF SIN CH2 ROUT AFF SOUT CH1 ROUT AFF SIN CH2 RIN2 1-channel cross-connected mode CH1 ROUT ROUT2 AFF SIN SOUT + SIN SIN2 3/28 ¡ Semiconductor MSM7617 49 WDT2 50 DF2 51 RGC20 52 RGC21 53 VDD 54 SA20 55 SA21 56 SG20 57 SG21 58 RIN2 59 ROUT2 60 VSS 61 SIN2 62 SOUT2 63 ATT2 64 HD2 PIN CONFIGURATION (TOP VIEW) RST2 1 48 VSS(PLL) ADP2 2 47 VDD(PLL) HCL2 3 46 CLKIN SYNC2 4 45 VSS VDD 5 44 VSS NLP2 6 43 TST IOM0 7 42 PWDWN IOM1 8 41 ECDM1 SCK 9 40 ECDM0 ECM 10 39 SCKO NLP1 11 38 SYNCO DF1 31 WDT1 32 RGC10 30 RGC11 29 VSS 28 SA10 27 SA11 26 SG10 25 RIN1 23 33 VDD SG11 24 34 VDD RST1 16 VDD 21 ADP1 15 ROUT1 22 35 VDD SIN1 20 36 VDD HCL1 14 SOUT1 19 SYNC1 13 HD1 17 37 VDD ATT1 18 VSS 12 64-Pin Plastic QFP 4/28 ¡ Semiconductor MSM7617 PIN DESCRIPTIONS Pin Symbol Type 1 RST2 I Description Reset signal input pin for channel 2. "L": Reset "H": Normal operation Input signals are invalid for 100 ms after reset (after RST returns to "H" from "L") for setting initial values. Input the basic clock during reset. Output pins will be placed in the following states during reset. Hi-Z: ROUT2, SOUT2 No effect: SYNCO, SCKO, ROUT1, SOUT1, DF1, WDT1 Previous state: DF2, WDT2 2 ADP2 I AFF coefficient control pin for channel 2. This pin stops coefficient variation of the adaptive FIR filter (AFF), fixing the coefficients. It allows once acquired AFF coefficients to be saved. "H": Fixed coefficient mode "L": Normal mode (variable coefficients) 3 HCL2 I Echo canceler disable pin for channel 2. This pin disables the echo canceler and enables data from SIN to SOUT to be output in "through mode". The input and output levels of SIN and SOUT are changed by the setting of the SG and SA pins; therefore, to output data from SIN to SOUT in "through mode", set the SA and SG pins to "0 dB". It simultaneously clears the adaptive FIR filter coefficients. "H": Disable mode "L": Normal mode (echo canceller enabled) 4 SYNC2 I Sync signal input pin for channel 2 transmit/receive PCM data while in parallel I/O mode. Input the transmit/receive sync signal (8 kHz) of the PCM CODEC connected to channel 2. Input "L" if not in parallel I/O mode. 6 NLP2 I NLP control pin for channel 2. This pin controls center clipping, forcing SOUT2 output to the minimum positive value when it is below –54 dBm0. It is effective for reducing uncanceled echoes and low-level noise. "H": Center clipping on "L": Center clipping off 7 IOM0 8 IOM1 I Sets I/O mode of PCM data. IOM1 IOM0 Mode Setting 0 0 2-channel parallel I/O mode 0 1 2-channel serial I/O mode 1 0 1-channel cross-connected mode 1 1 Inhibited 5/28 ¡ Semiconductor MSM7617 PIN DESCRIPTIONS (Continued) Pin Symbol Type 9 SCK I Description Common pin for channel 1 and channel 2. Clock input pin for PCM data transmission. Input the same clock as the transmit/receive clock of the PCM CODEC. Frequencies below 128 kHz cannot be used in serial mode. 10 ECM I Not used. Fix input to "H". 11 NLP1 I NLP control pin for channel 1. This pin controls center clipping, forcing SOUT1 output to the minimum positive value when it is below –54 dBm0. It is effective for reducing uncancelled echoes and low-level noise. "H": Center clipping on "L": Center clipping off 13 SYNC1 I Sync signal input pin for channel 1 transmit/receive PCM data while in 2channel parallel I/O mode, 2-channel serial I/O mode, or 1-channel crossconnected mode. Input the transmit/receive sync signal (8 kHz) of the PCM CODEC. 14 HCL1 I Echo canceler disable control pin for channel 1. This pin disables the echo canceler and enables data from SIN to SOUT to be output in "through mode". The input and output levels of SIN and SOUT are changed by the setting of the SG and SA pins; therefore, to output data from SIN to SOUT in "through mode", set the SA and SG pins to "0 dB". It simultaneously clears the adaptive FIR filter coefficients. "H": Disable mode "L": Normal mode (echo canceler enabled) 15 ADP1 I AFF coefficient control pin for channel 1. This pin stops coefficient variation of the adaptive FIR filter (AFF), fixing the coefficients. It allows once acquired AFF coefficients to be saved. "H": Fixed coefficient mode "L": Normal mode (variable coefficients) 16 RST1 I Reset signal input pin for channel 1. "L": Reset "H": Normal operation Input signals are invalid for 100 ms after reset (after RST returns to "H" from "L") for setting initial values. Input the base clock during reset. Output pins will be placed in the following states during reset. Hi-Z: ROUT1, SOUT1 No effect: SYNCO, SCKO, ROUT2, SOUT2, DF2, WDT2 Previous state: DF1, WDT1 6/28 ¡ Semiconductor MSM7617 PIN DESCRIPTIONS (Continued) Pin Symbol Type 17 HD1 I Description Howling detection control pin for channel 1. This pin controls detection and canceling of howling generated by the acoustics of handsfree telephones. "L": Howling detector on "H": Howling detector off 18 ATT1 I ATT control pin for channel 1. This pin controls the ATT function for preventing howling with the attenuators (ATT) provided on RIN and SOUT. When input is only on RIN, the SOUT attenuator is activated. When there is no input on RIN or there is input on both SIN and RIN, the RIN input attenuator is activated. Either the ATT for the RIN output or the ATT for the SOUT is always activated in all cases, and the attenuation of ATT is 6 dB. "H": Attenuator off "L": Attenuator on Because the attenuator is inserted opposite the speaker, it is effective for further reducing echo. 19 SOUT1 O PCM data output pin. Output signal changes depending on the setting of the IOM pins (refer to the block diagram). Data is always output on the rising edge of SCK. This pin is put in high impedance state while there is no data or during reset. In 2-channel parallel I/O mode, this pin becomes SOUT for channel 1 and outputs the PCM signal synchronous with SYNC1. In 2-channel serial I/O mode, this pin outputs the SOUT signal as a multiplexed PCM signal of SOUT signal for channel 1 and channel 2 synchronous with SYNC1. In 1-channel cross-connected mode, this pin becomes high impedance. 7/28 ¡ Semiconductor MSM7617 PIN DESCRIPTIONS (Continued) Pin Symbol Type 20 SIN1 I Description PCM data input pin. Pin use changes depending on the setting of the IOM pins (refer to the block diagram). In 2-channel parallel I/O mode, this pin becomes SIN for channel 1 and inputs the PCM signal synchronous with SYNC1. In 2-channel serial I/O mode, this pin sequentially inputs SIN as a multiplexed PCM signal from channel 1 and channel 2 synchronous with SYNC1. In 1-channel crossconnected mode, this pin becomes the cross-connected SIN pin for channel 1, and inputs the PCM signal synchronous with SYNC1. Data is captured on the falling edge of SCK. 22 ROUT1 O PCM data output pin. Output signal changes depending on the setting of the IOM pins (refer to the block diagram). Data is always output on the rising edge of SCK. This pin becomes high impedance while there is no data or during reset. In 2-channel parallel I/O mode, this pin becomes ROUT for channel 1 and outputs the PCM signal synchronous with SYNC1. In 2-channel serial I/O mode, this pin outputs the ROUT signal as a multiplexed PCM signal of ROUT signals for channel 1 and channel 2 synchronous with SYNC1. In 1-channel cross-connected mode, this pin becomes the cross-connected ROUT pin for channel 1, and outputs the PCM signal synchronous with SYNC1. 23 RIN1 I PCM data input pin. Pin use changes depending on the setting of the IOM pins (refer to the block diagram). In 2-channel parallel I/O mode, this pin becomes RIN for channel 1 and inputs the PCM signal synchronous with SYNC1. In 2-channel serial I/O mode, this pin sequentially inputs RIN as a multiplexed PCM signal from channel 1 and channel 2 synchronous with SYNC1. In 1-channel crossconnected mode, this pin is not used, and should be fixed at "L". Data is captured on the falling edge of SCK. 8/28 ¡ Semiconductor MSM7617 PIN DESCRIPTIONS (Continued) Pin Symbol Type 24 SG11 I 25 SG10 Description S output gain control pins for channel 1 (refer to the block diagram). These pins amplify the output level of SOUT. The gain level can be set even during the echo canceler disable mode. 26 SA11 27 SA10 I SG11 SG10 0 0 0 dB 0 1 +6 dB 1 0 +12 dB 1 1 Not used Gain Level S input attenuator control pins for channel 1 (refer to the block diagram). These pins attenuate the input level of SIN. Use them if ERL is large. The attenuation level can be set even during the echo canceler disable mode. 29 RGC11 30 RGC10 I SA11 SA10 0 0 0 dB 0 1 –6 dB 1 0 –12 dB 1 1 Not used Attenuation Level R input level control pins for channel 1 (refer to the block diagram). Excessive input (PCM level is at maximum value) causes a malfanction. Use these pins when there is a possibility of excessive input. RGC11 RGC10 Level Control Mode 0 0 Off 0 1 GC: On (control level = –20 dBm0) By the R gain controller, levels from –20 to –11.5 dBm0 will be suppressed to –20 dBm0 and those above –11.5 dBm0 will always be attenuated by 8.5 dB. This is effective to prevent excessive input and howling for hands-free applications. 1 0 Inhibited 1 1 ±6LR: On Applies –6 dB to excessive inputs using the level adjuster provided on R and S I/O. Since +6 dB also is applied at the output, the total level will not change, making this effective against line echo. 9/28 ¡ Semiconductor MSM7617 PIN DESCRIPTIONS (Continued) Pin Symbol Type 31 DF1 O Description Tone disabler flag output pin for channel 1. This pin outputs a disable flag when the ECDM pins are used for tone disabler mode. "H": Echo canceler disabled "L": Echo canceler enabled 32 WDT1 O Not used. Leave this pin open. 38 SYNCO O Output pin for internal SYNC signal (8 kHz). This pin is used as the transmit/receive synchronization signal for PCM signals. Connect it to the SYNC pin and PCM CODEC’s synchronization signal pin. Leave this pin open if using an external SYNC. 39 SCKO O Output pin for internal SCK signal (256 kHz). This pin is used for the transfer clock of PCM signals. Connect it to the PCM CODEC’s synchronization signal pin. Leave open if using an external SYNC. 40 ECDM0 41 ECDM1 I Tone disabler control pin common to channel 1 and channel 2. These pins detect answer tones generated by modems (2100 Hz), and then disable the echo canceler. ECDM1 ECDM0 Tone Disabler Mode 42 PWDWN I 0 0 Off 0 1 2100 Hz tone detection: On 1 0 2100 Hz and phase reversal detection: On 1 1 Inhibited Common pin for channel 1 and channel 2. This pin controls the power-down mode to reduce current consumption when the device is not being used. "L": Power down "H": Normal operation During power-down mode all input pins are invalid, and output pins will enter the following states. Hi-Z: SOUT1, SOUT2, ROUT1, ROUT2 "L": SYNCO, SCKO Previous state: DF1, WDT1, DF2, WDT2 Reset the device after power-down mode is released. 10/28 ¡ Semiconductor MSM7617 PIN DESCRIPTIONS (Continued) Pin Symbol Type Description 43 TST O Not used. Leave this pin open. 46 CLKIN I Basic clock input pin. Input a clock 18 to 20 MHz. Use 19.2 MHz if using internal synchronization signals (SYNCO, SCKO). 47 VDD I (PLL) Power supply for PLL circuit that uses the basic clock. Insert a 0.1mF capacitor with excellent high frequency characteristics between VDD (PLL) and VSS (PLL). 48 VSS I (PLL) Ground for PLL circuit that uses the basic clock. Insert a 0.1mF capacitor with excellent high frequency characteristics between VDD (PLL) and VSS (PLL). 49 WDT2 O Not used. Leave this pin open. 50 DF2 O Tone disabler flag output pin for channel 2. This pin outputs a disable flag when the ECDM pins are used for tone disabler. "H": Echo canceler disabled "L": Echo canceler enabled 51 RGC20 52 RGC21 I R input level control pins for channel 2 (refer to the block diagram). Excessive input (PCM level is at maximum value) causes a malfunction. Use these pins when there is a possibility of excessive input. RGC21 RGC20 Level Control Mode 0 0 Off 0 1 GC: On (control level = –20 dBm0) By the R gain controller, levels from –20 to –11.5 dBm0 will be suppressed to –20 dBm0 and those above –11.5 dBm0 will always be attenuated by 8.5 dB. This is effective to prevent excessive input and howling for hands-free applications. 1 0 Inhibited 1 1 ±6LR: On Apply –6 dB to excessive inputs using the level adjuster provided on R and S I/O. Since +6 dB also is applied at the output, the total level will not change, making this effective against line echo. 11/28 ¡ Semiconductor MSM7617 PIN DESCRIPTIONS (Continued) Pin Symbol Type 54 SA20 I 55 SA21 Description S input attenuator control pins for channel 2 (refer to the block diagram). These pins attenuate the input level of SIN. Use them if ERL is large. The attenuation level can be set even during the echo canceler disable mode. 56 SG20 57 SG21 I SA21 SG20 0 0 0 dB 0 1 –6 dB 1 0 –12 dB 1 1 Not used Attenuation Level S output gain control pins for channel 2 (refer to the block diagram). These pins amplify the output level of SOUT. The gain level can be set even during the echo canceler disable mode. 58 RIN2 I SG21 SG20 0 0 0 dB 0 1 +6 dB 1 0 +12 dB 1 1 Not used Gain Level PCM data input pin. Pin use changes depending on the setting of the IOM pins (refer to the block diagram). In 2-channel parallel I/O mode, this pin becomes RIN for channel 2 and inputs the PCM signal synchronous with SYNC2. Data is captured on the falling edge of SCK. In other modes, this pin is not used, and should be fixed at "L". 59 ROUT2 O PCM data output pin. Output signal changes depending on the setting of the IOM pins (refer to the block diagram). Data is always output on the rising edge of SCK. This pin becomes high impedance while there is no data. In 2-channel parallel I/O mode, this pin becomes ROUT for channel 2 and outputs the PCM signal synchronous with SYNC2. In 2-channel serial I/O mode, this pin is not used and should be left open. In 1-channel crossconnected mode, this pin becomes the cross-connected ROUT pin for channel 2, and outputs the PCM signal synchronous with SYNC1. 12/28 ¡ Semiconductor MSM7617 PIN DESCRIPTIONS (Continued) Pin Symbol Type 61 SIN2 I Description PCM data input pin. Pin use changes depending on the setting of the IOM pins (refer to the block diagram). Data is captured on the falling edge of SCK. In 2-channel parallel I/O mode, this pin becomes SIN for channel 2 and inputs the PCM signal synchronous with SYNC2. In 2-channel serial I/O mode, this pin is not used and should be fixed at "L". In 1-channel crossconnected mode, this pin becomes the cross-connected SIN pin for channel 2, and inputs the PCM signal synchronous with SYNC1. 62 SOUT2 O PCM data output pin. Output signal changes depending on the setting of the IOM pins (refer to the block diagram). Data is always output on the rising edge of SCK. This pin becomes high impedance while there is no data. In 2-channel parallel I/O mode, this pin becomes SOUT for channel 2 and outputs the PCM signal synchronous with SYNC2. In other modes, this pin is not used and should be left open. 63 ATT2 I ATT control pin for channel 2. This pin controls the ATT function for preventing howling with the attenuators (ATT) provided on RIN and SOUT. When input is only on RIN, the SOUT attenuator is activated. When there is no input on SIN or there is input on both SIN and RIN, the RIN input attenuator is activated. Either the ATT for the RIN output or the ATT for the SOUT is always activated in all cases, and the attenuation of ATT is 6 dB. "H": Attenuator off "L": Attenuator on Because the attenuator is activated opposite the speaker, it is effective for further reducing echo. 64 HD2 I Howling detection control pin for channel 2. This pin controls detection and canceling of howling generated by the acoustics of handsfree telephones. "L": Howling detector on "H": Howling detector off 13/28 ¡ Semiconductor MSM7617 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Power Supply Voltage VDD Input Voltage VIN Power Dissipation Storage Temperature Condition Rating Unit –0.3 to + 7 V Ta = 25°C –0.3 to VDD + 0.3 V 1 W — –55 to +150 °C PD TSTG RECOMMENDED OPERATING CONDITIONS (VDD = 4.5 V to 5.5 V) Symbol Condition Min. Typ. Max. Unit Power Supply Voltage VDD — 4.5 5 5.5 V Power Supply Voltage VSS — — 0 — V Parameter High Level Input Voltage VIH — 2.4 — VDD V Low Level Input Voltage VIL — 0 — 0.8 V Operating Temperature Ta — –40 +25 +85 °C ELECTRICAL CHARACTERISTICS DC Characteristics (VDD = 4.5 V to 5.5 V, Ta = –40°C to +85°C) Symbol Condition Min. Typ. Max. Unit High Level Output Voltage Parameter VOH IOH = 40 µA 4.2 — VDD V Low Level Output Voltage VOL IOL = 1.6 mA 0 — 0.4 V High Level Input Current IIH VIH = VDD — 0.1 10 µA IIL VIL = VSS –10 –0.1 — µA High Level Output Leakage Current IOZH VOH = VDD — 0.1 10 µA Low Level Output Leakage Current IOZL VOL = VSS –10 –0.1 — µA Power Supply Current (operation mode) IDDO — — 80 130 mA Power Supply Current (power-down mode) IDDS PWDWN = "L" — 0.5 2 mA CI — — — 15 pF CLOAD — — — 20 pF Low Level Input Current Input Capacitance Output Load Capacitance 14/28 ¡ Semiconductor MSM7617 Echo Canceler Characteristics (refer to characteristics diagram) Parameter Condition Symbol Min. Typ. Max. Unit — 30 — dB — — 55 ms RIN = –10 dBm0 (5 kHz white noise band) Echo Reduction LRES (Common to Channel 1 and E. R. L. = 6 dB TD = 50 ms Channel 2) ATT, GC, NLP: OFF RIN = –10 dBm0 Cancelable Echo Delay Time TD (Common to Channel 1 and (5 kHz white noise band) E. R. L. = 6 dB ATT, GC, NLP: OFF Channel 2) Tone Disabler Characteristics Parameter Tone Detection Min. Typ. Max. Unit Detection frequency 2075 2100 2125 Hz Detection level –32 — — dBm0 380 — — ms Detection time Detection condition Phase Reversal Detection Release 2100Hz. 180° out-of-phase detected before and after 450±25ms. Detection frequency 2075 2100 2125 Hz Detection level –32 — — dBm0 Phase reversal 135 180 225 ° Detection level — — –32 dBm0 Release time — 250 — ms 15/28 ¡ Semiconductor MSM7617 AC Characteristics (VDD = 4.5 V to 5.5 V, Ta = –40°C to +85°C) Parameter Clock Frequency If Used Without Internal Sync Signal Clock Cycle Time If Used Without Internal Sync Signal Symbol fC tMCK Min. Typ. Max. — 19.2 — 18 — 20 — 52.08 — 50 — 55.56 Unit MHz ns Clock Duty Cycle tDMC 40 — 60 % Clock High Level Pulse Width tMCH tMCK ¥ 0.4 — tMCK ¥ 0.6 ns Clock Low Level Pulse Width tMCL tMCK ¥ 0.4 — tMCK ¥ 0.6 ns tr — — 5 ns — 5 ns Clock Rise Time Clock Fall Time tf — tDCM — — 40 ns fCO — 256 — kHz Internal Sync Clock Cycle Time tCO — 3.9 — µs Internal Sync Clock Duty Cycle tDCO — 50 — % Internal Sync Signal Output Time tDCC — — 5 ns Internal Sync Signal Period tCYO — 125 — µs Internal Sync Signal Pulse Width tWSO — tCO — µs 64 — 2048 128 — 2048 0.488 — 15.62 0.488 — 7.81 Internal Sync Clock Output Time Internal Sync Clock Frequency Transmit/Receive Sync Clock Frequency In Serial I/O Mode Transmit/Receive Sync Clock Cycle Time In Serial I/O Mode fSCK tSCK kHz µs Transmit/Receive Sync Clock Duty Cycle tDSC 40 50 60 % Transmit/Receive Sync Signal Period tCYC — 125 — µs tXS 45 — — ns tSX 45 — — ns Sync Timing tWSY tSCK — tCYC–tSCK µs Receive Signal Setup Time tDS 45 — — ns Receive Signal Hold Time tDH 45 — — ns Receive Signal Input Time tID — 7tSCK — µs In 2-Channel Serial Mode tID2 — 15tSCK — µs Sync Signal Width 16/28 ¡ Semiconductor MSM7617 AC Characteristics (Continued) (VDD = 4.5 V to 5.5 V, Ta = –40°C to +85°C) Parameter Serial Output Delay Time Symbol Min. Typ. Max. Unit tSD — — 90 ns tXD — — 90 ns Reset Signal Input Width tWR 1 — — µs Reset Start Time tDRS 5 — — ns Reset End Time tDRE — — 52 ns Process Operation Start Time tDIT 100 — — µs Power-Down Start Time tDPS — — 111 ns Power-Down End Time tDPE — — 15 ns RST Width After Power-Down tWPR 10 — — ms RST Control Pin Setup Time tDSR 20 — — ns RST Control Pin Hold Time tDHR 20 — — ns SCK Control Pin Setup Time tDCS 120 — — ns SCK Control Pin Hold Time tDCH 120 — — ns 17/28 ¡ Semiconductor MSM7617 TIMING DIAGRAMS Clock Timing fC, tMCK, tDMC tMCH tMCL tr tf CLKIN tDCM tDCM SCKO tDCO fCO, tCO SCKO tDCC tDCC tCYO SYNCO tWSO 18/28 ¡ Semiconductor MSM7617 Serial Data Input Timing (Parallel Mode, FTF Mode) fSCK, tSCK tDSC SCK tSX tXS tCYC SYNC tWSY tDH tDS SIN RIN MSB 7 6 5 4 3 2 1 LSB 0 MSB 7 1 7 tID Serial Data Input Timing (Serial Mode) Note: Refer to parallel mode for detailed timing fSCK, tSCK SCK tCYC tWSY SYNC1 RIN1 SIN1 tID2 tDH tDS 7 6 5 4 3 CH1 data 2 1 0 7 6 5 4 3 2 0 CH2 data 19/28 ¡ Semiconductor MSM7617 Serial Data Output Timing (Parallel Mode, FTF Mode) fSCK, tSCK tDSC SCK tXS tSX tCYC SYNC tWSY tXD tXD tSD SOUT ROUT High-Z tXD MSB 7 6 5 4 3 2 LSB 0 1 High-Z MSB 7 Serial Data Output Timing (Serial Mode) Note: Refer to parallel mode for detailed timing fSCK, tSCK SCK tCYC tWSY SYNC1 ROUT1 High-Z 7 SOUT1 6 5 4 3 2 1 0 7 CH1 data 6 5 4 3 2 1 0 High-Z 7 CH2 data Operation Timing After Reset tWR RST Note: Reset timing can be asynchronous. tDRS Internal operation tDIT tDRE Reset Initial setting Proccessing starts 20/28 ¡ Semiconductor Power-Down Timing ,, MSM7617 Note: All inputs are invalid during power-down. Always reset the device after power-down. PWDWN tDPS Internal operation RST tDPE Power-down tWPR Capture Timing of Control Pins Control pin states are captured during reset and during each period’s serial data capture. tWR RST tDHR tDSR Control Pin SCK tID2 tID SYNC tDCH Channel 1 Control Pin tDCS Channel 2 Control Pin (when not in serial mode) tDCH tDCS Channel 2 Control Pin (when in serial mode) 21/28 ¡ Semiconductor MSM7617 HOW TO USE THE MSM7617 The echo canceler cancels the echo on the RIN signal as returned by SIN. Connect the original signal to the R side, and the signal generating the echo to the S side. Connection Methods According to Echoes Example 1. Cancel Acoustic Echo (applies to acoustic echo from line input) ROUT RIN Input Acoustic echo AFF CODEC SIN + – SOUT + H CODEC Example 2. Cancel Line Echo (applies to line echo from microphone input) SOUT Input CODEC RIN + AFF SIN ROUT H CODEC Line echo Example 3. Cancel Both Acoustic Echo And Line Echo MSM7617 ROUT1 Input + Acoustic echo CODEC Input SIN2 AFF SIN1 AFF + CH1 ROUT2 CODEC H Line echo CH2 22/28 ¡ Semiconductor MSM7617 ECHO CANCELER CHARACTERISTICS DIAGRAM Characteristics of m-law and A-law are identical. (Characteristic graphs below are reference data.) RIN Input Level vs. Echo Attenuation ERL vs. Echo Attenuation 40 40 Echo Attenuation [dB] Echo Attenuation [dB] 30 20 10 0 30 20 10 0 40 30 20 10 0 –10 –50 –40 –30 –20 –10 0 RIN Input level [dBm0] E. R. L. [dB] Measuring Conditions: RIN input level = –10 dBm0 white noise Echo delay time = 50 ms ATT, GC, NLP, LR all off 10 Measuring Conditions: RIN input = white noise Echo delay time = 50 ms E.R.L. = 6 [dB] ATT, GC, NLP, LR all off Echo Delay Time vs. Echo Attenuation Measuring Conditions: RIN input level = –10 dBm0 white noise Echo delay time = 50 ms E.R.L = 6 dB ATT, GC, NLP, LR all off 40 Echo Attenuation [dB] 30 20 10 0 0 10 20 30 40 50 60 Echo Delay Time [ms] Note: regarding dBm0: The "dBm0" unit used in the characteristic graphs is a unit that expresses PCM CODEC digital values. Therefore, be aware that the same value 0 [dBm0] might correspond to different analog input levels depending on the PCM CODEC being used. Please check the data sheet of the PCM CODEC being used. Example MSM7533 0 [dBm0] = 0.85 [Vrms] = 2.4 [Vp-p] = 0.8 [dBm] 600 W –10 [dBm0] = 0.27 [Vrms] = 0.76 [Vp-p] = –9.2 [dBm] 600 W MSM7543 0 [dBm0] = 0.6007 [Vrms] = 1.7 [Vp-p] = –2.2 [dBm] 600 W –10 [dBm0] = 0.19 [Vrms] = 0.54 [Vp-p] = –12.2 [dBm] 600 W 23/28 ¡ Semiconductor MSM7617 Measurement System Block Diagram White noise generator MSM7617 L. P. F. 5 kHz RIN ROUT Echo Delay Time Delay CH1 or CH2 Level Meter SOUT SIN ATT E. R. L. 2ch CODEC MSM7533 24/28 ¡ Semiconductor MSM7617 NOTES ON USE 1. Set echo return loss (E. R. L) to be attenuated. If the echo return loss is set to be amplified, the echo cannot be canceled. (Refer to the "E. R. L vs Echo Attenuation" characteristic graph.) When the echo return loss is amplified, adjust the input level to be attenuated by setting the mode with the SA pin. If the level from the SA pin is too low by setting the mode with the SA pin, then amplify the output level by setting the mode with the SG pin. 2. Set RIN input so that there is not excessive input (above 0 dBm0) from the PCM CODEC. Echo cancellation is not possible with excessive input. (Refer to the "RIN vs Echo Attenuation" characteristic graph.) Recommended input levels are –10 to –20 dBm0. If there is a possibility of excessive input, then set GC mode or 6LR mode with the RGC pins. 3. Applying the tone signals to this echo canceler will decrease echo attenuation. 4. For changes in the echo path (retransmit, circuit switching during transmission, and so on), convergence may be difficult. Perform a reset to make it converge. If the state of the echo path changes after a reset, convergence may again be difficult. In cases such as a change in the echo path, perform a reset each time. 5. If a clock is not input after power is applied, then the internal circuits will not stabilize, possibly damaging the device. When power is applied, set the PWDWN pin to "H" and input the basic clock. If the device is put into PWDWN immediately after power has been applied, be sure to input 10 or more clocks of the basic clock before setting to the power down mode. 6. Always reset after power is applied or power-down is released. For power-on reset operation, an external oscillator may require a certain setting time after powered on. Allow 10 ms for a reset time after the oscillator has settled. 7. When the device is used as an acoustic echo canceler, equipment noise and environment noise from the microphone amp may be amplified, and echo attenuation may be below 30 dB. 25/28 19 58 62 13 ch1 SYNC 9 32 31 +5 V 11 14 15 17 18 CH1 24 25 26 27 29 30 16 ch1 RST GND 41 40 43 46 CLOCK 42 +5 V GND 47 48 5 21 33 34 36 26/28 ch2 RST ch3 RST ch4 RST MSM7617 ROUT1 SIN1 ROUT2 SIN2 SYNC2 22 23 20 19 59 58 61 62 4 13 WDT2 DF2 NLP2 HCL2 ADP2 HD2 ATT2 SG21 SG20 SA21 SA20 RGC21 RGC20 RST2 IOM1 IOM0 ECM SYNCO SCKO VSS VSS VSS VSS VSS 49 32 50 31 6 11 9 3 +5 V +5 V 14 2 15 64 17 63 18 57 CH2 CH3 24 56 25 55 26 54 27 52 29 51 30 1 16 8 7 GND GND 41 40 10 43 38 46 39 42 12 +5 V GND 28 44 45 48 5 21 60 VDD 37 VDD 53 47 + GND 33 +5 V 35 34 36 RIN1 SOUT1 RIN2 SOUT2 SYNC1 SCK WDT1 DF1 NLP1 HCL1 ADP1 HD1 ATT1 SG11 SG10 SA11 SA10 RGC11 RGC10 RST1 ECDM1 ECDM0 TST CLKIN PWDWN VDD(PLL) VSS(PLL) VDD VDD VDD VDD VDD VDD ROUT1 SIN1 ROUT2 SIN2 SYNC2 22 WDT2 DF2 NLP2 HCL2 ADP2 HD2 ATT2 SG21 SG20 SA21 SA20 RGC21 RGC20 RST2 IOM1 IOM0 ECM SYNCO SCKO VSS VSS VSS VSS VSS 49 20 59 61 4 50 6 3 +5 V 2 64 63 57 CH4 56 55 54 52 51 1 8 7 GND 10 38 39 12 28 44 45 60 VDD 37 VDD 53 GND + +5 V MSM7617 35 RIN1 SOUT1 RIN2 SOUT2 SYNC1 SCK WDT1 DF1 NLP1 HCL1 ADP1 HD1 ATT1 SG11 SG10 SA11 SA10 RGC11 RGC10 RST1 ECDM1 ECDM0 TST CLKIN PWDWN VDD(PLL) VSS(PLL) VDD VDD VDD VDD VDD VDD ¡ Semiconductor MSM7617 23 APPLICATION CIRCUITS Terminal side ROUT Bus SIN Bus RIN Bus SOUT Bus ch3 SYNC SCK 4-Channel Serial Interface Line Echo Canceler Example Line side ¡ Semiconductor MSM7617 Cross-Connection Example 2ch CODEC MSM7533VGS-K Microphone Input C1 R1 R2 DV Speaker Output R3 DV 21 AIN1 22 GSX1 4 AOUT1 13 12 15 10 16 19 5 6 DOUT1 DIN1 XSYNC RSYNC BCLK A/m PDN CHP R5 24 AIN2 GSX2 23 AOUT2 2 Line Input Line Output R7 DV 14 DOUT2 DIN2 11 VDD 8 1 SGC AG DG 18 C2 R6 AV + C3 C4 C5 (AG) 9 DV R4 DV MSM7617 23 RIN1 19 SOUT1 58 RIN2 62 SOUT2 13 SYNC1 9 SCK 32 WDT1 31 DF1 11 NLP1 14 HCL1 15 ADP1 17 HD1 18 ATT1 24 25 26 27 29 DV 30 RST DG CLK PWDWN DV DG C6 SG11 SG10 SA11 SA10 RGC11 RGC10 16 RST1 41 ECDM1 40 ECDM0 43 TST 46 CLKIN 42 PWDWN 47 VDD(PLL) 48 VSS(PLL) 5V DD 21 VDD 33 VDD 34 V DD 35 V DD 36 VDD ROUT1 22 20 SIN1 59 ROUT2 61 SIN2 4 SYNC2 WDT2 DF2 NLP2 HCL2 ADP2 HD2 49 50 6 3 2 R8 DV R1 = 20 kW 64 63 ATT2 SG21 57 56 SG20 SA21 55 SA20 54 52 RGC21 51 RGC20 RST2 1 8 IOM1 IOM0 7 R2 = 20 kW R3 = 2.2 kW R4 = 10 kW R5 = 20 kW R6 = 20 kW R7 = 2.2 kW R8 = 10 kW DG ECM 10 38 SYNC0 39 SCK0 12 VSS 28 VSS V 44 C1 = 1 mF C2 = 1 mF C3 = 0.1 mF C4 = 10 mF SS VSS 45 60 C7 VDD 37 VDD 53 C5 = 0.1 mF + DG C8 C6 = 0.1 mF DV C7 = 0.1 mF C8 = 10 mF 27/28 ¡ Semiconductor MSM7617 PACKAGE DIMENSIONS (Unit : mm) QFP64-P-1414-0.80-BK Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.87 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 28/28 E2Y0002-29-11 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents cotained herein may be reprinted or reproduced without our prior permission. 9. MS-DOS is a registered trademark of Microsoft Corporation. Copyright 1999 Oki Electric Industry Co., Ltd. Printed in Japan