MOTOROLA MPC9448D

MOTOROLA
Freescale
SEMICONDUCTOR TECHNICAL
DATA Semiconductor, Inc.
3.3V/2.5V LVCMOS 1:12 Clock
Fanout Buffer
Freescale Semiconductor, Inc...
The MPC9448 is a 3.3V or 2.5V compatible, 1:12 clock fanout buffer
targeted for high performance clock tree applications. With output
frequencies up to 350 MHz and output skews less than 150 ps, the device
meets the needs of most demanding clock applications.
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12 LVCMOS compatible clock outputs
Selectable LVCMOS and differential LVPECL compatible clock inputs
Order Number: MPC9448/D
Rev 3, 04/2003
MPC9448
LOW VOLTAGE
3.3V/2.5V LVCMOS 1:12
CLOCK FANOUT BUFFER
Maximum clock frequency of 350 MHz
Maximum clock skew of 150 ps
Synchronous output stop in logic low state eliminates output runt pulses
High--impedance output control
3.3V or 2.5V power supply
Drives up to 24 series terminated clock lines
Ambient temperature range --40°C to +85°C
32--Lead LQFP packaging
Supports clock distribution in networking, telecommunication and
computing applications
• Pin and function compatible to MPC948
FA SUFFIX
32--LEAD LQFP PACKAGE
CASE 873A
Functional Description
The MPC9448 is specifically designed to distribute LVCMOS
compatible clock signals up to a frequency of 350 MHz. Each output
provides a precise copy of the input signal with a near zero skew. The
outputs buffers support driving of 50Ω terminated transmission lines on
the incident edge: each output is capable of driving either one parallel
terminated or two series terminated transmission lines.
Two selectable, independent clock inputs are available, providing support of LVCMOS and differential LVPECL clock
distribution systems. The MPC9448 CLK_STOP control is synchronous to the falling edge of the input clock. It allows the start
and stop of the output clock signal only in a logic low state, thus eliminating potential output runt pulses. Applying the OE control
will force the outputs into high--impedance mode.
All inputs have an internal pull--up or pull--down resistor preventing unused and open inputs from floating. The device supports
a 2.5V or 3.3V power supply and an ambient temperature range of --40°C to +85°C. The MPC9448 is pin and function compatible
but performance--enhanced to the MPC948.
© Motorola, Inc. 2003
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MPC9448
GND
Q6
VCC
22
21
20
19
18
Q7
Q5
23
Q3
Q3
25
17
16
Q4
VCC
26
15
Q8
Q2
27
14
VCC
GND
28
13
Q9
Q6
Q1
29
12
GND
Q7
VCC
30
11
Q10
Q0
31
10
VCC
9
Q11
Q9
Q10
VCC
Q11
32
1
2
3
4
5
6
7
8
GND
GND
VCC
Q8
OE
SYNC
MPC9448
CLK_STOP
VCC
PCLK
Q5
CLK_SEL
Freescale Semiconductor, Inc...
24
Q2
VCC
CLK_STOP
VCC
CLK
STOP
PCLK
1
CCLK
CCLK
CLK_SEL
0
Q4
Q1
PCLK
PCLK
GND
Q0
VCC
GND
(all input resistors have a value of 25kΩ)
OE
Figure 1. Logic Diagram
Figure 2. 32--Lead Package Pinout
(Top View)
Table 1. FUNCTION TABLE
Control
CLK_SEL
Default
1
0
1
PECL differential input selected
CCLK input selected
state)1
OE
1
Outputs disabled (high-impedance
CLK_STOP
1
Outputs synchronously stopped in logic low state
Outputs enabled
Outputs active
1. OE=0 will high-impedance tristate all outputs independent on CLK_STOP.
Table 2. PIN CONFIGURATION
Pin
I/O
Type
Function
PCLK, PCLK
Input
LVPECL
Clock signal input
CCLK
Input
LVCMOS
Alternative clock signal input
CLK_SEL
Input
LVCMOS
Clock input select
CLK_STOP
Input
LVCMOS
Clock output enable/disable
OE
Input
LVCMOS
Output enable/disable (high--impedance tristate)
Q0--11
Output
LVCMOS
Clock outputs
GND
Supply
Ground
Negative power supply (GND)
VCC
Supply
VCC
Positive power supply for I/O and core. All VCC pins must be connected to
the positive power supply for correct operation
MOTOROLA
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TIMING SOLUTIONS
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MPC9448
Table 3. ABSOLUTE MAXIMUM RATINGS*
Symbol
Parameter
Min
Max
Unit
VCC
Supply Voltage
--0.3
3.9
V
VIN
DC Input Voltage
--0.3
VCC + 0.3
V
VOUT
DC Output Voltage
--0.3
VCC + 0.3
V
IIN
DC Input Current
±20
mA
IOUT
DC Output Current
±50
mA
TStor
Storage Temperature Range
125
°C
--65
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or
conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute--maximum--rated conditions is
not implied.
Freescale Semiconductor, Inc...
Table 4. GENERAL SPECIFICATIONS
Symbol
Characteristic
Min
Typ
Max
Unit
VCC ­ 2
Condition
VTT
Output Termination Voltage
MM
ESD Protection (Machine Model)
200
V
V
HBM
ESD Protection (Human Body Model)
2000
V
LU
Latch--up Immunity
200
mA
CPD
Power Dissipation Capacitance
10
pF
Per Output
CIN
Input Capacitance
4.0
pF
Inputs
Table 5. DC CHARACTERISTICS (VCC = 3.3V ±5%, TA = --40°C to +85°C)
Symbol
Characteristic
Min
Typ
Max
Unit
Condition
VIH
Input HIGH Voltage
2.0
VCC + 0.3
V
LVCMOS
VIL
Input LOW Voltage
--0.3
0.8
V
LVCMOS
mV
LVPECL
VCC -- 0.6
V
LVPECL
300
µA
VIN = VCC or GND
V
IOH = --24mAc
V
V
IOL = 24mAc
IOL = 12mA
VPP
VCMR
a
Peak--to--Peak Input Voltage
PCLK
250
Common Mode Range
PCLK
1.1
Currentb
IIN
Input
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
ZOUT
d
ICCQ
2.4
0.55
0.30
Output Impedance
17
Maximum Quiescent Supply Current
Ω
2.0
mA
All VCC Pins
a. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (DC) specification.
b. Input pull-up / pull-down resistors influence input current.
c. The MPC9448 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated
transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50Ω series terminated transmission lines (for
VCC=3.3V) or one 50Ω series terminated transmission line (for VCC=2.5V).
d. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open.
TIMING SOLUTIONS
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Freescale Semiconductor, Inc.
MPC9448
Table 6. AC CHARACTERISTICS (VCC = 3.3V ±5%, TA = --40°C to +85°C)a
Symbol
Characteristics
fref
Typ
0
Max
Unit
350
MHz
Condition
fMAX
Maximum Output Frequency
0
350
MHz
VPP
Peak-to-peak input voltage
PCLK
400
1000
mV
LVPECL
VCMRb
Common Mode Range
PCLK
1.3
VCC-0.8
V
LVPECL
tP, REF
Reference Input Pulse Width
tr, tf
Freescale Semiconductor, Inc...
Min
Input Frequency
1.4
ns
CCLK Input Rise/Fall Time
PCLK to any Q
CCLK to any Q
1.6
1.3
1.0c
ns
3.6
3.3
ns
ns
tPLH/HL
tPLH/HL
Propagation delay
tPLZ, HZ
Output Disable Time
11
ns
tPZL, LZ
Output Enable Time
11
ns
tS
Setup time
CCLK to CLK_STOP
PCLK to CLK_STOP
0.0
0.0
ns
ns
tH
Hold time
CCLK to CLK_STOP
PCLK to CLK_STOP
1.0
1.5
ns
ns
tsk(O)
Output-to-output Skew
tsk(PP)
Device-to-device Skew
tSK(P)
0.8 to 2.0V
150
ps
PCLK or CCLK to any Q
2.0
ns
Output pulse skewd
Using CCLK
Using PCLK
300
400
ps
ps
DCQ
Output Duty Cycle
fQ<170 MHz
55
%
DCREF = 50%
tr, tf
Output Rise/Fall Time
1.0
ns
0.55 to 2.4V
45
50
0.1
a. AC characteristics apply for parallel output termination of 50Ω to VTT.
b. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts tPLH/HL and tSK(PP).
c. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input
pulse width, output duty cycle and maximum frequency specifications.
d. Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |.
Table 7. DC CHARACTERISTICS (VCC = 2.5V ±5%, TA = --40°C to +85°C)
Symbol
Characteristics
Min
Max
Unit
1.7
VCC + 0.3
V
LVCMOS
-0.3
0.7
VIH
Input high voltage
VIL
Input low voltage
VPP
Peak-to-peak input voltage
PCLK
250
Common Mode Range
PCLK
1.0
VCMR
a
IIN
Typ
Input currentb
VOH
Output High Voltage
V
LVCMOS
mV
LVPECL
VCC-0.7
V
LVPECL
300
µA
VIN=GND or VIN=VCC
V
IOH= -15 mAc
V
IOL= 15 mAc
1.8
VOL
Output Low Voltage
ZOUT
Output impedance
ICCQd
Maximum Quiescent Supply Current
Condition
0.6
19
Ω
2.0
mA
All VCC Pins
a. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (DC) specification.
b. Input pull-up / pull-down resistors influence input current.
c. The MPC9448 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated
transmission line to a termination voltage of VTT. Alternatively, the device drives one 50Ω series terminated transmission lines at
VCC=2.5V.
d. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open.
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MPC9448
Table 8. AC CHARACTERISTICS (VCC = 2.5V ±5%, TA = --40°C to +85°C)a
Symbol
fref
Min
Typ
0
Max
Unit
350
MHz
Condition
fMAX
Maximum Output Frequency
0
350
MHz
VPP
Peak-to-peak input voltage
PCLK
400
1000
mV
LVPECL
Common Mode Range
PCLK
1.2
VCC-0.8
V
LVPECL
VCMR
b
tP, REF
tr, tf
Freescale Semiconductor, Inc...
Characteristics
Input Frequency
Reference Input Pulse Width
1.4
ns
CCLK Input Rise/Fall Time
PCLK to any Q
CCLK to any Q
1.5
1.7
1.0c
ns
4.2
4.4
ns
ns
tPLH/HL
tPLH/HL
Propagation delay
tPLZ, HZ
Output Disable Time
11
ns
tPZL, LZ
Output Enable Time
11
ns
tS
Setup time
CCLK to CLK_STOP
PCLK to CLK_STOP
0.0
0.0
ns
ns
tH
Hold time
CCLK to CLK_STOP
PCLK to CLK_STOP
1.0
1.5
ns
ns
tsk(O)
Output-to-output Skew
tsk(PP)
Device-to-device Skew
tSK(p)
Output pulse skewd
DCQ
Output Duty Cycle
tr, tf
Output Rise/Fall Time
0.8 to 2.0V
150
ps
PCLK or CCLK to any Q
2.7
ns
Using CCLK
Using PCLK
200
300
ps
ps
55
55
%
%
DCREF = 50%
1.0
ns
0.6 to 1.8V
fQ< 350 MHz and using CCLK
fQ<200 MHz and using PCLK
45
45
50
50
0.1
a. AC characteristics apply for parallel output termination of 50Ω to VTT.
b. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts tPLH/HL and tSK(PP).
c. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input
pulse width, output duty cycle and maximum frequency specifications.
d. Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |.
TIMING SOLUTIONS
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MPC9448
APPLICATIONS INFORMATION
Figure 3. Output Clock Stop (CLK_STOP) Timing
Diagram
3.0
CCLK or
PCLK
2.5
VOLTAGE (V)
CLK_STOP
Freescale Semiconductor, Inc...
Q0 to Q11
Driving Transmission Lines
The MPC9448 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user, the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of 17Ω (VCC=3.3V), the
outputs can drive either parallel or series terminated
transmission lines. For more information on transmission
lines, the reader is referred to Motorola application note
AN1091. In most high performance clock networks,
point--to--point distribution of signals is the method of choice.
In a point--to--point scheme, either series terminated or
parallel terminated transmission lines can be used. The
parallel technique terminates the signal at the end of the line
with a 50Ω resistance to VCC÷2.
17Ω
MPC9448
OUTPUT
BUFFER
IN
RS = 33Ω
ZO = 50Ω
RS = 33Ω
ZO = 50Ω
RS = 33Ω
ZO = 50Ω
2.0
In
1.5
0.5
0
2
4
6
8
TIME (nS)
10
12
14
Figure 5. Single versus Dual Line Termination
Waveforms
The waveform plots in Figure 5 “Single versus Dual Line
Termination Waveforms” show the simulation results of an
output driving a single line versus two lines. In both cases,
the drive capability of the MPC9448 output buffer is more
than sufficient to drive 50Ω transmission lines on the incident
edge. Note from the delay measurements in the simulations
a delta of only 43ps exists between the two differently loaded
outputs. This suggests that the dual line driving need not be
used exclusively to maintain the tight output--to--output skew
of the MPC9448. The output waveform in Figure 5 “Single
versus Dual Line Termination Waveforms” shows a step in
the waveform; this step is caused by the impedance
mismatch seen looking into the driver. The parallel
combination of the 33Ω series resistor plus the output
impedance does not match the parallel combination of the
line impedances. The voltage wave launched down the two
lines will equal:
OutA
OutB0
17Ω
OutB1
Figure 4. Single versus Dual Transmission Lines
VL
Z0
RS
R0
VL
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each
output of the MPC9448 clock driver. For the series
terminated case, however, there is no DC current draw; thus,
the outputs can drive multiple series terminated lines.
Figure 4 “Single versus Dual Transmission Lines” illustrates
an output driving a single series terminated line versus two
series terminated lines in parallel. When taken to its extreme,
the fanout of the MPC9448 clock driver is effectively doubled
due to its capability to drive multiple lines at VCC=3.3V.
MOTOROLA
OutB
tD = 3.9386
1.0
MPC9448
OUTPUT
BUFFER
IN
OutA
tD = 3.8956
= VS ( Z0 ÷ (RS+R0 +Z0))
= 50Ω || 50Ω
= 33Ω || 33Ω
= 17Ω
= 3.0 ( 25 ÷ (16.5+17+25)
= 1.28V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.5V. It will then increment
towards the quiescent 3.0V in steps separated by one round
trip delay (in this case 4.0ns).
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Since this step is well above the threshold region it will not
cause any false clock triggering; however, designers may be
uncomfortable with unwanted reflections on the line. To
better match the impedances when driving multiple lines, the
situation in Figure 6 “Optimized Dual Line Termination”
should be used. In this case, the series terminating resistors
are reduced such that when the parallel combination is added
to the output buffer impedance the line impedance is
perfectly matched.
MPC9448
OUTPUT
BUFFER
RS = 16Ω
ZO = 50Ω
RS = 16Ω
ZO = 50Ω
Table 9. Die junction temperature and MTBF
Freescale Semiconductor, Inc...
Figure 6. Optimized Dual Line Termination
Power Consumption of the MPC9448 and Thermal
Management



C
M
20.4
110
9.1
120
4.2
130
2.0
Where Rthja is the thermal impedance of the package
(junction to ambient) and TA is the ambient temperature.
According to Table 9, the junction temperature can be used to
estimate the long-term device reliability. Further, combining
equation 1 and equation 2 results in a maximum operating
frequency for the MPC9448 in a series terminated
transmission line system, equation 4.
I CCQ + V CC ⋅ f CLOCK ⋅ N ⋅ C PD +
I CCQ + V CC ⋅ f CLOCK ⋅ N ⋅ C PD +
100
In equation 2, P stands for the number of outputs with a
parallel or thevenin termination, VOL, IOL, VOH and IOH are a
function of the output termination technique and DCQ is the
clock signal duty cyle. If transmission lines are used ΣCL is
zero in equation 2 and can be eliminated. In general, the use
of controlled transmission line techniques eliminates the
impact of the lumped capacitive loads at the end lines and
greatly reduces the power dissipation of the device. Equation
3 describes the die junction temperature TJ as a function of
the power consumption.
The MPC9448 AC specification is guaranteed for the
entire operating frequency range up to 350 MHz. The
MPC9448 power consumption and the associated long-term
reliability may decrease the maximum frequency limit,
depending on operating conditions such as clock frequency,
supply voltage, output loading, ambient temperture, vertical
convection and thermal conductivity of package and board.
This section describes the impact of these parameters on the
junction temperature and gives a guideline to estimate the
MPC9448 die junction temperature and the associated
device reliability. For a complete analysis of power
consumption as a function of operating conditions and
associated long term device reliability please refer to the
application note AN1545. According the AN1545, the
long-term device reliability is a function of the die junction
temperature:
P TOT = V CC ⋅
MTBF (Years)
Where ICCQ is the static current consumption of the
MPC9448, CPD is the power dissipation capacitance per
output, (Μ)ΣCL represents the external capacitive output
load, N is the number of active outputs (N is always 12 in
case of the MPC9448). The MPC9448 supports driving
transmission lines to maintain high signal integrity and tight
timing parameters. Any transmission line will hide the lumped
capacitive load at the end of the board trace, therefore, ΣCL is
zero for controlled transmission line systems and can be
eliminated from equation 1. Using parallel termination output
termination results in equation 2 for power dissipation.
17Ω + 16Ω k 16Ω = 50Ω k 50Ω
25Ω = 25Ω

Junction temperature (°C)
Increased power consumption will increase the die
junction temperature and impact the device reliability
(MTBF). According to the system-defined tolerable MTBF,
the die junction temperature of the MPC9448 needs to be
controlled and the thermal impedance of the board/package
should be optimized. The power dissipated in the MPC9448
is represented in equation 1.
17Ω
P TOT =
C
L
M

L
+
DC
Q

⋅ V CC
TIMING SOLUTIONS
Equation 1
⋅ I OH ⋅ V CC − V OH + 1 − DC Q ⋅ I OL ⋅ V OL Equation 2
P
Equation 3
T J = T A + P TOT ⋅ R thja
f CLOCK,MAX =
MPC9448

T J,MAX − T A
1
⋅
− I CCQ ⋅ V CC
R thja
C PD ⋅ N ⋅ V 2CC
7

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Equation 4
MOTOROLA
Freescale Semiconductor, Inc.
MPC9448
TJ,MAX should be selected according to the MTBF system
requirements and Table 9. Rthja can be derived from Table 10.
The Rthja represent data based on 1S2P boards, using 2S2P
boards will result in a lower thermal impedance than
indicated below.
If the calculated maximum frequency is below 350 MHz, it
becomes the upper clock speed limit for the given application
conditions. The following eight derating charts describe the
safe frequency operation range for the MPC9448. The charts
were calculated for a maximum tolerable die junction
temperature of 110°C (120°C), corresponding to an
estimated MTBF of 9.1 years (4 years), a supply voltage of
3.3V and series terminated transmission line or capacitive
loading. Depending on a given set of these operating
conditions and the available device convection a decision on
the maximum operating frequency can be made.
Freescale Semiconductor, Inc...
Table 10. Thermal package impedance of the 32LQFP
Convection, LFPM
Rthja (1P2S
board), °C/W
Rthja (2P2S
board), °C/W
Still air
86
61
100 lfpm
76
56
200 lfpm
71
54
300 lfpm
68
53
400 lfpm
66
52
500 lfpm
60
49
Figure 7. Maximum MPC9448 frequency, VCC = 3.3V, MTBF
9.1 years, driving series terminated transmission lines,
2s2p board
Figure 8. Maximum MPC9448 frequency, VCC = 3.3V,
MTBF 9.1 years, 4 pF load per line, 2s2p board
Figure 9. No maximum frequency limitation for VCC = 3.3V,
MTBF 4 years, driving series terminated transmission
lines, 2s2p board
Figure 10. Maximum MPC9448 frequency, VCC =
3.3V, MTBF 4 years, 4 pF load per line, 2s2p board
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MPC9448
The Following Figures Illustrate the Measurement Reference for the MPC9448 Clock Driver Circuit
MPC9448 DUT
Pulse
Generator
Z = 50 Ω
ZO = 50 Ω
ZO = 50 Ω
RT = 50 Ω
RT = 50 Ω
VTT
VTT
Freescale Semiconductor, Inc...
Figure 11. CCLK MPC9448 AC Test Reference for Vcc = 3.3V and Vcc = 2.5V
Differential
Pulse Generator
Z = 50 Ω
ZO = 50 Ω
MPC9448 DUT
ZO = 50 Ω
RT = 50 Ω
RT = 50 Ω
VTT
VTT
Figure 12. PCLK MPC9448 AC Test Reference
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MPC9448
PCLK
VPP
PCLK
VCC
CCLK
VCMR
VCC÷2
GND
VCC
VCC÷2
QX
VCC
VCC÷2
QX
GND
tP(LH)
GND
tP(HL)
tP(LH)
tP(HL)
Figure 14. Propagation Delay (tPD) Test Reference
Figure 13. Propagation Delay (tPD) Test Reference
VCC
VCC÷2
VCC
Freescale Semiconductor, Inc...
GND
CCLK
VCC÷2
VCC
VCC÷2
GND
GND
tSK(LH)
VCC
VCC÷2
QX
tSK(HL)
GND
tP(HL)
tP(LH)
The pin--to--pin skew is defined as the worst case difference in
propagation delay between any similar delay path within a
single device
tSK(P) = | tPLH -- tPHL |
Figure 15. Output--to--Output Skew tSK(LH, HL)
Figure 16. Output Pulse Skew (tSK(P)) Test Reference
VCC
VCC÷2
GND
tP
T0
DC = (tP ­ T0 x 100%)
tF
The time from the output controlled edge to the non--controlled
edge, divided by the time between output controlled edges,
expressed as a percentage
Figure 17. Output Duty Cycle (DC)
VCC=3.3V
VCC=2.5V
2.4
1.8V
0.55
0.6V
tR
Figure 18. Output Transition Time Test Reference
VCC
CCLK
PCLK
TN
TN+1
TJIT(CC) = |TN - TN+1 |
VCC
VCC÷2
CLK_STOP
GND
The variation in cycle time of a signal between adjacent cycles,
over a random sample of adjacent cycle pairs
tS
Figure 19. Cycle--to--Cycle Jitter
MOTOROLA
VCC÷2
GND
tH
Figure 20. Setup and Hold Time (tS, tH) Test Reference
10
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TIMING SOLUTIONS
Freescale Semiconductor, Inc.
MPC9448
OUTLINE DIMENSIONS
FA SUFFIX
LQFP PACKAGE
CASE 873A--03
ISSUE B
4X
0.20 H A--B D
6
D1
e/2
D1/2
PIN 1 INDEX
32
3
25
1
E1/2 A
F
B
Freescale Semiconductor, Inc...
6 E1
E
4
F
DETAIL G
17
8
9
7
E/2
DETAIL G
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
3. DATUMS A, B, AND D TO BE DETERMINED AT
DATUM PLANE H.
4. DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE C.
5. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED
THE MAXIMUM b DIMENSION BY MORE THAN
0.08--mm. DAMBAR CANNOT BE LOCATED ON THE
LOWER RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSION AND ADJACENT LEAD OR
PROTRUSION: 0.07--mm.
6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.25--mm PER SIDE. D1 AND E1 ARE MAXIMUM
PLASTIC BODY SIZE DIMENSIONS INCLUDING
MOLD MISMATCH.
7. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
8. THESE DIMENSIONS APPLY TO THE FLAT SECTION
OF THE LEAD BETWEEN 0.1--mm AND 0.25--mm
FROM THE LEAD TIP.
D
D/2
4
D
4X
0.20 C A--B D
H
SEATING
PLANE
28X
e
C
32X
0.1 C
DETAIL AD
BASE
METAL
PLATING
b1
c
8X
c1
b
( θ1_)
0.20
R R2
A2
0.25
GAUGE PLANE
A1
(S)
L
θ_
(L1)
DETAIL AD
TIMING SOLUTIONS
M
11
5
C A--B D
SECTION F--F
R R1
A
A, B, D
8
DIM
A
A1
A2
b
b1
c
c1
D
D1
e
E
E1
L
L1
θ
θ1
R1
R2
S
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MILLIMETERS
MIN
MAX
1.40
1.60
0.05
0.15
1.35
1.45
0.30
0.45
0.30
0.40
0.09
0.20
0.09
0.16
9.00 BSC
7.00 BSC
0.80 BSC
9.00 BSC
7.00 BSC
0.50
0.70
1.00 REF
0_
7_
12 _REF
0.08
0.20
0.08
-----0.20 REF
MOTOROLA
Freescale Semiconductor, Inc...
MPC9448
Freescale Semiconductor, Inc.
Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright
licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including
“Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the
rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part.
MOTOROLA and the Stylized M Logo are registered in the US Patent and Trademark Office. All other product or service names are the property of their respective
owners.
E Motorola Inc. 2003
HOW TO REACH US:
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre,
2, Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.
852--26668334
USA/EUROPE/LOCATIONS NOT LISTED:
TECHNICAL INFORMATION CENTER:
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81--3--3440--3569
MOTOROLA
HOME PAGE: http://motorola.com/semiconductors
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12
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MPC9448/D
TIMING
SOLUTIONS