MOTOROLA MPC980

SEMICONDUCTOR TECHNICAL DATA
The MPC980 is a 3.3V dual PLL clock generator targeted for high end
Pentium and PowerPC 603/604 personal computers. The MPC980
synthesizes processor as well as PCI clocks from a 14.31818MHz
external crystal. In addition the device provides two buffered outputs of
the 14.31818MHz crystal as well as a 40MHz SCSI clock, a 24MHz floppy
clock and a 12MHz keyboard clock. One of the buffered 14.31818MHz
outputs can be configured to provide a 16MHz output rather than the
second copy of the 14.31818MHz output.
DUAL 3.3V PLL
CLOCK GENERATOR
• Provides Processor and System Clocks for Pentium Designs
• Provides Processor and System Clocks for PowerPC 603/604
Designs
• Two Fully Integrated Phase–Locked Loops
• Cycle–to–Cycle Jitter of ±150ps
• Operates from 3.3V Supply
• 52–Lead LQFP Packaging
The processor clock outputs of the MPC980 can be programmed to
provide 50, 60 or 66MHz. Under all processor output frequencies the PCI
clock outputs will be equal to one half the processor clock outputs. The
PCI outputs will run synchronously to the processor clock outputs. There
are a total of ten output clocks which can be split into a group of four and a
group of six. Either group can be configured as processor or PCI clocks.
Each of the outputs can drive two series terminated transmission lines
allowing for the driving of up to twelve independent processor loads and
eight PCI clock loads. A pin selectable option is available to delay the PCI
clock outputs relative to the processor clocks. The amount of delay is a
function of the processor clock frequency and varies from 2ns to 6ns.
FA SUFFIX
52–LEAD LQFP PACKAGE
CASE 848D–03
The output jitter of the the PLL at 66MHz output is ±150ps peak–to–peak, cycle–to–cycle (the worst case deviation of the clock
period is guaranteed to be less than ±150ps). The skews between one processor clock and any other processor clock (or one
PCI clock to any other PCI clock) is 350ps. The worst case skew between the processor clocks and the PCI clocks is 500ps.
An output enable pin is provided to tristate all of the outputs for board level test. In addition a testing mode is provided to allow
for the bypass of the PLL’s for board level functional debug.
Pentium is a trademark of Intel Corporation. PowerPC is a trademark of International Business
Machines Corporation.
1/98
 Motorola, Inc. 1998
1
REV 2
MPC980
fsel2
Dly_PCI
fsel0:1
4
Processor
Clock PLL
Test Mode
2
2
÷2
4
÷4
14.31818MHz
QP4:5_QPCI4:5
÷2/÷4
TCLK_Sel
Xtal
Osc
QP0:3
QPCI0:3
0
Q14.3M
1
0
TCLK
Q14_16M
1
16M_Sel
Q12M
16MHz
12MHz
System
Clock PLL
Q24M
24MHz
40MHz
Q40M
OE
Figure 1. Logic Diagram
Table 1. Pin Descriptions
Pin
1
Label
Ω
VCCA
Description
Pin
Analog VCC for System PLL Use
Filter (Note 1.)
GNDI
System Ground Input
VCCO
VCC in for the CMOS Outputs
28
QP3
CMOS Output QP3
29
GND0
System Ground Input
30
GND0
System Ground Input
31
QP4_PCI4
CMOS Output QP4_PCI4
32
VCC0
VCC in for the CMOS Outputs
33
QP5_PCI5
CMOS Output QP5_PCI5
34
GND0
System Ground Input
35
GND0
System Ground Input
(See Function Table 1 on page 3.)
36
QPCI3
CMOS Output QPCI3
Most Bit for QP/QPI Output Function
37
VCCO
VCC in for the CMOS Outputs
38
QPCI2
CMOS Output QPCI2
39
GND0
System Ground Input
↓ 50K
Sel Ext’l TCLK or Internal Xtal Ref
3
TCLK
None
External LVCMOS Ref Signal
4
Xtal1
None
Xtal Pin 1
5
Xtal2
None
Xtal Pin 2
6
GND
7
DLY_PCI
System Ground Input
Sets QP & QPI Relationship
(See Function Table 2 on page 3.)
9
10
VCCI
fsel0
fsel1
VCC Pin for Internal Circuits
↑ 50K
↓ 50K
Least Bit for QP/QPI Output Funct
(See Function Table 1 on page 3.)
11
fsel2
↓ 50K
Selection of QP/QPI Output Funct
(See Function Table 4 on page 3.)
12
VCCA
13
GNDA
14
16M_SEL
40
VCCI
VCC for Internal Core Logic
(Note 1.)
41
GND0
System Ground Input
System Ground Input
42
QPCI1
CMOS Output QPCI1
Selects 16MHz / 14MHz for
Q14_16M Output
43
VCC0
VCC in for the CMOS Outputs
44
QPCI0
CMOS Output QPCI0
45
GND0
System Ground Input
46
QM12
CMOS Output QM12
47
VCC0
VCC in for the CMOS Outputs
48
Q40M
CMOS Output Q40M
49
GND0
System Ground Input
50
Q24M
51
OE
Analog VCC Proc’ssr PLL Use Filter
↓ 50K
15
Q14_16M
Output for 16MHz / 14MHz Xtal Osc
16
GND0
System Ground Input
17
VCC0
VCC in for the CMOS Outputs
18
Q14M
CMOS Output for 14.3MHz Xtal Osc
19
GND0
System Ground Input
20
QP0
CMOS Output QP0
21
VCC0
VCC in for the CMOS Outputs
22
QP1
CMOS Output QP1
23
GND0
System Ground Input
24
QP2
CMOS Output QP2
25
VCC0
VCC in for the CMOS Outputs
MOTOROLA
Description
27
TCLK_Sel
8
Ω
26
2
↓ 50K
Label
CMOS Output Q24M
↑ 50K
Select Output State
(See Function Table 1 on page 3.)
52 GND0
System Ground Input
1. The filter recommended for the analog power pins is found in
Figure 3 in the Applications Information section on page 5.
2
ECLinPS and ECLinPS Lite
DL140 — Rev 3
GND0
QPCI2
VCC0
QPCI3
GND0
GND0
QP5_PCI5
VCC0
QP4_PCI4
GND0
GND0
QP3
VCC0
MPC980
39
38
37
36
35
34
33
32
31
30
29
28
27
VCCI
40
26
GNDI
GND0
41
25
VCC0
QPCI1
42
24
QP2
VCC0
43
23
GND0
QPCI0
44
22
QP1
GND0
45
21
VCC0
Q12M
46
20
QP0
VCC0
47
19
GND0
Q40M
48
18
Q14M
GND0
49
17
VCC0
Q24M
50
16
GND0
OE
51
15
Q14_16M
GNDA
52
14
16M_Sel
Xtal2
9
10
11
12
13
GNDA
Xtal1
8
VCCA
TCLK
7
fsel2
TCLK_Sel
6
fsel1
5
fsel0
4
VCCI
3
Dly_PCI
2
GND
1
VCCA
MPC980
Figure 2. 52–Lead Pinout (Top View)
Function Table 1
OE
fsel0
fsel1
QP
QPCI
Q14M
Q16M
Q24M
Q12M
Q40M
0
1
1
1
1
X
0
0
1
1
X
0
1
0
1
High Impedance
50MHz
60MHz
66MHz
TCLK/2
High Impedance
25MHz
30MHz
33MHz
TCLK/4
Hi Z
14.31818
14.31818
14.31818
TCLK
Hi Z
16
16
16
TCLK/6
Hi Z
24
24
24
TCLK/4
Hi Z
12
12
12
TCLK/8
Hi Z
40
40
40
TCLK/2
Function Table 2
Dly_PCI
0
1
Function Table 4
QP/QPCI Relationship
fsel2
Synchronous Processor & PCI Clocks
PCI Clocks Lag Processor Clocks
0
1
Function Table 3
TCLK_Sel
0
1
Function Table 5
PLL Input Reference
16M_Sel
Crystal Oscillator
TCLK
ECLinPS and ECLinPS Lite
DL140 — Rev 3
QP/QPCI Output Configuration
6 Processor and 4 PCI Clocks
4 Processor and 6 PCI Clocks
0
1
3
Q14_16M Output Configuration
14.31818MHz to Q14_16M Out
16MHz to Q14_16M Out
MOTOROLA
MPC980
DC CHARACTERISTICS (TA = 0° to 70°C)
Symbol
Characteristic
VCC
Power Supply Voltage
VIL
Input LOW Voltage
VIH
Input HIGH Voltage
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
CIN
Input Capacitance
CPD
Power Dissipation Capacitance
ICC
Quiescent Supply Current
Min
Typ
Max
Unit
3.3–5%
3.3
3.3+5%
V
0.3VCC
V
VCC
V
0.7VCC
VCC –0.4
Condition
V
–20mA (Note 1.)
0.4
V
+20mA (Note 1.)
4.5
pF
25
pF
190
mA
ICCA
PLL Supply Current
20
mA
1. Output can drive two series terminated 50Ω transmission lines or a single 50Ω line terminated 50Ω into VCC/2.
AC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V ±5%)
Symbol
Characteristic
Min
fXtal
Input Crystal Frequency
fmax
Maximum Output Frequency
tdc
Output Duty Cycle
tjitter
Cycle–to–Cycle Jitter
(Peak–to–Peak)
tskew
Output–to–Output Skew
tdelay
Time Delay
tr, tf
Output Rise/Fall Time
tLOCK
PLL Lock Time
tPZL, tPZH
Output Enable Time
3
tPLZ, tPHZ
Output Disable Time
4
Typ
Max
14.31818
QP
QPCI
Unit
Condition
MHz
66
33
MHz
tCYCLE/2
+1000
ps
66/33MHz
60/30MHz
50/25MHz
±150
±200
±250
ps
QP to QP
QPCI to QPCI
QP to QPCI
350
350
500
ps
Rising Edges Only;
Dly_PCI = 0
ns
Dly_PCI = 1
0.8
ns
1.0 to 1.8V
10
ms
10
ns
50Ω to VCC/2
11
ns
50Ω to VCC/2
tCYCLE/2
–1000
QP to QPCI
2
tCYCLE/2
±500
1
4fQP
0.05
1
4fQP
)1
APPLICATIONS INFORMATION
The Oscillator circuit is a series resonant circuit as
opposed to the more common parallel resonant circuit, this
eliminates the need for large on–board capacitors. Because
the design is a series resonant design for the optimum
frequency accuracy a series resonant crystal should be used
(see specification table below). Unfortunately most off the
shelf crystals are characterized in a parallel resonant mode.
However a parallel resonant crystal is physically no different
than a series resonant crystal, a parallel resonant crystal is
simply a crystal which has been characterized in its parallel
Using the On–Board Crystal Oscillator
The MPC980 features an on–board crystal Oscillator to
allow for seed clock generation as well as final distribution.
The on–board Oscillator is completely self contained so that
the only external component required is the crystal. As the
Oscillator is somewhat sensitive to loading on its inputs the
user is advised to mount the crystal as close to the MPC980
as possible to avoid any board level parasitics. To facilitate
co–location surface mount crystals are recommended, but
not required.
MOTOROLA
4
ECLinPS and ECLinPS Lite
DL140 — Rev 3
MPC980
noise whose spectral content is above 20KHz. As the noise
frequency crosses the series resonant point of an individual
capacitor it’s overall impedance begins to look inductive and
thus increases with increasing frequency. The parallel
capacitor combination shown ensures that a low impedance
path to ground exists for frequencies well above the
bandwidth of the PLL. It is recommended that the user start
with an 8–10Ω resistor to avoid potential VCC drop problems
and only move to the higher value resistors when a higher
level of attenuation is shown to be needed.
resonant mode. Therefore in the majority of cases a parallel
specified crystal can be used with the MPC980 with just a
minor frequency error due to the actual series resonant
frequency of the parallel resonant specified crystal. Typically
a parallel specified crystal used in a series resonant mode
will exhibit an Oscillatory frequency a few hundred ppm lower
than the specified value. For most processor implementa–
tions a few hundred ppm translates into kHz inaccuracies, a
level which does not represent a major issue.
Table 2. Crystal Specifications
Parameter
3.3V
Value
Crystal Cut
Fundamental at Cut
Resonance
Series Resonance*
Frequency Tolerance
±75ppm at 25°C
Frequency/Temperature Stability
±150ppm 0 to 70°C
Operating Range
0 to 70°C
Shunt Capacitance
5–7pF
Equivalent Series Resistance (ESR)
50 to 80Ω Max
Correlation Drive Level
100µW
Aging
5ppm/Yr (First 3 Years)
RS=5–15Ω
PLL_VCC
22µF
MPC980
VCCA Pins 1 & 12
VCC
0.01µF
* See accompanying text for series versus parallel resonant
discussion.
Figure 3. Power Supply Filter
Although the MPC980 has several design features to
minimize the susceptibility to power supply noise (isolated
power and grounds and fully differential PLL) there still may
be applications in which overall performance is being
degraded due to system power supply noise. The power
supply filter schemes discussed in this section should be
adequate to eliminate power supply noise related problems
in most designs.
Power Supply Filtering
The MPC980 is a mixed analog/digital product and as
such it exhibits some sensitivities that would not necessarily
be seen on a fully digital product. Analog circuitry is naturally
susceptible to random noise, especially if this noise is seen
on the power supply pins. The MPC980 provides separate
power supplies for the output buffers (VCCO) and the
phase–locked loop (VCCA) of the device. The purpose of this
design technique is to try and isolate the high switching noise
digital outputs from the relatively sensitive internal analog
phase–locked loop. In a controlled environment such as an
evaluation board this level of isolation is sufficient. However,
in a digital system environment where it is more difficult to
minimize noise on the power supplies a second level of
isolation may be required. The simplest form of isolation is a
power supply filter on the VCCA pin for the MPC980.
Component Reliability Analysis Information
All inputs and outputs of the MPC980 clock generator are
LVCMOS and are not 5V tolerant. The quiescent current is
190mA maximum, so the maximum quiescent power is
(190mA) × (3.465V max–VCC) = 658.35mW. Total maximum
power must include the dynamic power of the outputs.
Dynamic Power/Output = [Logic Swing Out (volts)] ×
[VCC (volts)] × [Freq (MHz)] × [Cl + Cp (pF)]
Figure 3 illustrates a typical power supply filter scheme.
The MPC980 is most susceptible to noise with spectral
content in the 1KHz to 1MHz range. Therefore the filter
should be designed to target this range. The key parameter
that needs to be met in the final filter design is the DC voltage
drop that will be seen between the VCC supply and the VCCA
pin of the MPC980. From the data sheet the IVCCA current
(the current sourced per VCCA pin) is typically 15mA (20mA
maximum), assuming that a minimum of 3.0V must be
maintained on the VCCA pin very little DC voltage drop can
be tolerated when a 3.3V VCC supply is used. The resistor
shown in Figure 3 must have a resistance of 10–15Ω to meet
the voltage drop criteria. The RC filter pictured will provide a
broadband filter with approximately 100:1 attenuation for
ECLinPS and ECLinPS Lite
DL140 — Rev 3
0.01µF
where
CL = Load Capacitance
CP = Output Power Dissipation Capacitance
The MPC980 is packaged in a 52–lead LQFP to optimize
board space and power supply distribution. The LQFP
package occupies a 12mm x 12mm space on the PCB. The
52–Pin LQFP package has a ΘJA of 64 to 74°C/W in still air
and a ΘJA of 42 to 52°C/W in 500lfpm of moving air. The
maximum chip temperature for the device is 140°C. The
device component count is: NPN Bipolar devices 2,238;
NMOS devices 1,313; PMOS devices 281.
5
MOTOROLA
MPC980
OUTLINE DIMENSIONS
FA SUFFIX
PLASTIC LQFP PACKAGE
CASE 848D-03
ISSUE D
–X–
X=L, M, N
CL
AB
4X
4X 13 TIPS
0.20 (0.008) H L–M N
G
AB
0.20 (0.008) T L–M N
VIEW Y
52
40
1
39
3X
PLATING
VIEW Y
–L–
ÇÇÇÇ
ÉÉÉÉ
ÉÉÉÉ
ÇÇÇÇ
J
–M–
B
V
0.13 (0.005)
B1
13
M
D
T L–M
U
S
N
S
SECTION AB–AB
V1
ROTATED 90_ CLOCKWISE
27
14
26
–N–
A1
S1
A
S
4X
C
q2
0.10 (0.004) T
–H–
–T–
SEATING
PLANE
4X
q3
VIEW AA
0.05 (0.002)
S
W
2X R
q1
R1
0.25 (0.010)
C2
q
GAGE PLANE
K
C1
E
VIEW AA
MOTOROLA
BASE METAL
F
Z
6
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS –L–, –M– AND –N– TO BE DETERMINED
AT DATUM PLANE –H–.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –T–.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS A AND B DO
INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE -H-.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46
(0.018). MINIMUM SPACE BETWEEN
PROTRUSION AND ADJACENT LEAD OR
PROTRUSION 0.07 (0.003).
DIM
A
A1
B
B1
C
C1
C2
D
E
F
G
J
K
R1
S
S1
U
V
V1
W
Z
θ
θ1
θ2
θ3
MILLIMETERS
MIN
MAX
10.00 BSC
5.00 BSC
10.00 BSC
5.00 BSC
–––
1.70
0.05
0.20
1.30
1.50
0.20
0.40
0.45
0.75
0.22
0.35
0.65 BSC
0.07
0.20
0.50 REF
0.08
0.20
12.00 BSC
6.00 BSC
0.09
0.16
12.00 BSC
6.00 BSC
0.20 REF
1.00 REF
0_
7_
–––
0_
12 _ REF
12 _ REF
INCHES
MIN
MAX
0.394 BSC
0.197 BSC
0.394 BSC
0.197 BSC
–––
0.067
0.002
0.008
0.051
0.059
0.008
0.016
0.018
0.030
0.009
0.014
0.026 BSC
0.003
0.008
0.020 REF
0.003
0.008
0.472 BSC
0.236 BSC
0.004
0.006
0.472 BSC
0.236 BSC
0.008 REF
0.039 REF
0_
7_
–––
0_
12 _ REF
12 _ REF
ECLinPS and ECLinPS Lite
DL140 — Rev 3
MPC980
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MPC980/D
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