LT1425 Isolated Flyback Switching Regulator U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTION No Transformer “Third Winding” or Optoisolator Required ±5% Accurate Output Voltage Without User Trims (See Circuit Below) Resistor Programmable Output Voltage Regulation Maintained Well Into Discontinuous Mode (Light Load) Optional Load Compensation Operating Frequency: 285kHz Easily Synchronized to External Clock Available in 16-Pin Narrow SO Package U APPLICATIONS ■ ■ ■ ■ The LT ®1425 is a monolithic high power switching regulator specifically designed for the isolated flyback topology. No “third winding” or optoisolator is required; the integrated circuit senses the isolated output voltage directly from the primary side flyback waveform. A high current, high efficiency switch is included on the die along with all oscillator, control and protection circuitry. The LT1425 operates with input supply voltages from 3V to 20V and draws only 7mA quiescent current. It can deliver output power up to 6W with no external power devices. By utilizing current mode switching techniques, it provides excellent AC and DC line regulation. The LT1425 has a number of features not found on other switching regulator ICs. Its unique control circuitry can maintain regulation well into discontinuous mode in most applications. Optional load compensation circuitry allows for improved load regulation. An externally activated shutdown mode reduces total supply current to 15µA for standby operation. Isolated Flyback Switching Regulators Ethernet Isolated 5V to – 9V Converters Medical Instruments Isolated Telecom Supplies , LTC and LT are registered trademarks of Linear Technology Corporation. U TYPICAL APPLICATION 5V to Isolated – 9VOUT Load Regulation 500V ISOLATION BARRIER 9.5 5V 9.4 T1* D1 1N5819 12 VIN VSW LT1425 15 6 4 C3 1000pF SHDN RFB RREF ROCOMP RCCOMP SGND PGND 7 • R1 22.6k 3 1% SYNC VC • 11 5 C2 47µF 16V ISOLATED –9V ± 5% AT 20mA TO 200mA F *DALE LPE 4841-330MB R2 3.01k 1% 9.3 OUTPUT VOLTAGE (V) C1 100µF 10V + + V– 9.2 9.1 9.0 8.9 8.8 8.7 8.6 14 8.5 13 C4 0.1µF 0 R3 15k 50 100 150 OUTPUT CURRENT (mA) 200 1425 TA02 10 1425 TA01 1 LT1425 W U U U W W W ABSOLUTE MAXIMUM RATINGS PACKAGE/ORDER INFORMATION (Note 1) Supply Voltage ........................................................ 20V Switch Voltage ......................................................... 35V SHDN, SYNC Pin Voltage ........................................... 7V RFB Pin Current....................................................... 2mA Operating Junction Temperature Range Commercial .......................................... 0°C to 100°C Industrial ......................................... – 40°C to 100°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER TOP VIEW GND 1 NC 2 16 GND 15 SHDN RFB 3 14 ROCOMP VC 4 13 RCCOMP RREF 5 12 VIN SYNC 6 11 VSW SGND 7 10 PGND GND 8 9 LT1425CS LT1425IS GND S PACKAGE 16-LEAD PLASTIC SO TJMAX = 145°C, θJA = 75°C/ W Consult factory for Military grade parts. ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER VIN = 5V, TJ = 25°C, VSW open, VC = 1.4V, unless otherwise specified. CONDITIONS MIN TYP MAX UNITS 402 396 408 414 420 µA µA Feedback Amplifier IREF Reference Current Measured at RFB Pin with RREF = 3.000k ● IIN RREF Pin Input Current gm Feedback Amplifier Transconductance 500 ∆IC = ±10µA (Note 2) ISOURCE, ISINK Feedback Amplifier Source or Sink Current VCL nA ● 400 1000 1600 ● 30 50 80 Feedback Amplifier Clamp Voltage 1.9 Reference Voltage/Current Line Regulation 5V ≤ VIN ≤ 18V Voltage Gain (Note 3) VIN Sense Error 0.01 ● 10 µA V 0.04 500 ● µmho %/V V/V 25 mV Output Switch BV Output Switch Breakdown Voltage IC = 5mA ● V(VSW) Output Switch ON Voltage ISW = 1A ● ILIM Switch Current Limit Duty Cycle = 50%, 0°C ≤ TJ ≤ 100°C Duty Cycle = 50%, – 40°C ≤ TJ ≤ 100°C Duty Cycle = 80% ● ● ● 35 50 V 0.55 0.85 V 1.35 1.25 1.60 1.60 1.30 1.9 1.9 A A A 0.95 0.85 1.2 1.3 1.4 V V Current Amplifier Control Pin Threshold Duty Cycle = Minimum Control Voltage to Switch Transconductance 2 A/V Timing f Switching Frequency ● 260 240 285 300 320 kHz kHz 170 210 260 ns tON Minimum Switch ON Time tED Flyback Enable Delay Time 150 ns tEN Minimum Flyback Enable Time 180 ns Maximum Switch Duty Cycle 2 ● 85 90 95 % LT1425 ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER VIN = 5V, TJ = 25°C, VSW Open, VC = 1.4V, unless otherwise specified. CONDITIONS MIN TYP MAX UNITS Load Compensation ∆VRCCOMP/∆ISW Ω 0.45 SYNC Function Minimum SYNC Amplitude 1.5 ● Synchronization Range 320 SYNC Pin Input Resistance 2.2 V 450 kHz 40 kΩ Power Supply VIN(MIN) Minimum Input Voltage ● 2.8 3.1 V ICC Supply Current ● 7.0 9.5 mA Shutdown Mode Supply Current ● 15 40 µA Shutdown Mode Threshold ● 0.9 1.3 V The ● denotes the specifications which apply over the full operating temperature range. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. 0.4 Note 2: Feedback amplifier transconductance is RREF referred. Note 3: Voltage gain is RREF referred. U W TYPICAL PERFORMANCE CHARACTERISTICS Switch Saturation Voltage vs Switch Current Switch Current Limit vs Duty Cycle 1.2 Minimum Input Voltage vs Temperature 3.1 2.0 3.0 125°C 0.8 25°C 0.6 –55°C 0.4 1.5 INPUT VOLTAGE (V) 1.0 SWITCH CURRENT LIMIT (A) SWITCH SATURATION VOLTAGE (V) TA = 25°C 1.0 0.5 0.2 0 2.9 2.8 2.7 2.6 2.5 0 0.2 1.0 0.4 0.6 0.8 SWITCH CURRENT (A) 1.2 1.4 1425 G01 0 0 10 20 30 40 50 60 70 80 90 100 DUTY CYCLE (%) 1425 G02 2.4 –50 –25 50 25 75 0 TEMPERATURE (°C) 100 125 1425 G03 3 LT1425 U W TYPICAL PERFORMANCE CHARACTERISTICS 25°C 125°C –55°C 20 0 –20 –40 1400 2.50 1200 2.25 1000 2.00 VC PIN VOLTAGE (V) 60 40 800 600 400 200 –60 –80 1.05 1.10 1.15 1.20 1.25 1.30 1.35 RREF NODE VOLTAGE (V) 0 –50 –25 1.40 50 25 75 0 TEMPERATURE (°C) 100 285 280 275 270 100 125 TA = 25°C 2.25 2.00 1.75 1.50 1.25 1.00 0.75 –50 –25 0 –1 –2 –3 –4 50 25 75 0 TEMPERATURE (°C) 100 125 0 250 200 225 175 150 125 100 100 125 1425 G10 4 ENABLE TIME (ns) 225 ENABLE DELAY TIME (ns) 275 50 25 75 0 TEMPERATURE (°C) 75 –50 –25 5 Minimum Flyback Enable Time vs Temperature 275 125 –50 –25 3 4 2 SHDN PIN VOLTAGE (V) 1425 G09 250 150 1 1425 G08 300 175 125 1 Flyback Enable Delay Time vs Temperature 200 100 1425 G06 2.50 Minimum Switch ON Time vs Temperature 225 50 25 75 0 TEMPERATURE (°C) SHDN Pin Input Current vs Voltage 1425 G07 250 VC THRESHOLD 1.25 0.75 –50 –25 125 SHDN PIN INPUT CURRENT (µA) MINIMUM SYNCHRONIZATION VOLTAGE (VP-P) SWITCHING FREQUENCY (kHz) 290 50 25 75 0 TEMPERATURE (°C) 1.50 Minimum Synchronization Voltage vs Temperature 295 265 –50 –25 1.75 1425 G05 Switching Frequency vs Temperature 300 VC HIGH CLAMP 1.00 1425 G04 SWITCH ON TIME (ns) VC Pin Threshold and High Clamp Voltage vs Temperature Error Amplifier Transconductance vs Temperature (RREF Referred) TRANSCONDUCTANCE (µmho) FEEDBACK AMPLIFIER OUTPUT CURRENT (µA) Feedback Amplifier Output Current vs RREF Pin Voltage 200 175 150 125 50 25 75 0 TEMPERATURE (°C) 100 125 1425 G11 100 –50 –25 50 25 75 0 TEMPERATURE (°C) 100 125 1425 G12 LT1425 U U U PIN FUNCTIONS GND (Pins 1, 8, 9, 16): Ground. These pins connect to the substrate of the die and are separate from the power ground and signal ground. They should connect directly to a good quality ground plane. PGND (Pin 10): Power Ground. This pin is the emitter of the power switch device and has large currents flowing through it. It should be connected directly to a good quality ground plane. RFB (Pin 3): Input Pin for External “Feedback” Resistor Connected to Transformer Primary (VSW). The ratio of this resistor to the RREF resistor, times the internal bandgap (VBG) reference, is the primary determinant of the output voltage (plus the effect of any nonunity transformer turns ratio). The average current through this resistor during the flyback period should be approximately 400µA. See Applications Information for more details. VSW (Pin 11): This is the collector node of the output switch and has large currents flowing through it. Keep the traces to the switching components as short as possible to minimize electromagnetic radiation and voltage spikes. VC (Pin 4): Control Voltage. This pin is the output of the feedback amplifier and the input of the current comparator. Frequency compensation of the overall loop is effected by placing a capacitor between this node and ground. RREF (Pin 5): Input Pin for External Ground-Referred “Reference” Resistor. This resistor should be in the range of 3k, but for convenience, need not be this value precisely. See Applications Information for more details. SYNC (Pin 6): Pin to Synchronize Internal Oscillator to External Frequency Reference. It is directly logic compatible and can be driven with any signal between 10% and 90% duty cycle. If unused, this pin can be left floating; however, for best noise immunity the pin should be grounded. SGND (Pin 7): Signal Ground. This pin is a clean ground. The internal reference and feedback amplifier are referred to it. Keep the ground path connection to RREF and the VC compensation capacitor free of large ground currents. VIN (Pin 12): Supply Voltage. Bypass input supply pin with 10µF or more. The part goes into undervoltage lockout when VIN drops below 2.8V. Undervoltage lockout stops switching and pulls the VC pin low. RCCOMP (Pin 13): Pin for the External Filter Capacitor for Load Compensation Function. A common 0.1µF ceramic capacitor will suffice for most applications. See Applications Information for further details. ROCOMP (Pin 14): Input Pin for Optional External Load Compensation Resistor. Use of this pin allows nominal compensation for nonzero output impedance in the power transformer secondary circuit, including secondary winding impedance, output Schottky diode impedance and output capacitor ESR. In less demanding applications this resistor is not needed. See Applications Information for more details. SHDN (Pin 15): Shutdown. This pin is used to turn off the regulator and reduce VIN input current to a few tens of microamperes. The SHDN pin can be left floating when unused. 5 LT1425 W BLOCK DIAGRAM VIN RFB RREF 2.6V REGULATOR SHDN VSW FLYBACK ERROR AMPLIFIER 285kHz OSCILLATOR SYNC LOGIC DRIVER RCCOMP LOAD COMPENSATION COMP ROC0MP SGND VC + GND IS OMITTED FOR CLARITY CURRENT AMPLIFIER RSENSE – PGND 1425 BD W W FLYBACK ERROR A PLIFIER DIAGRA D1 VIN T1 + • VSW + ISOLATED VOUT C1 • – VIN RFB D2 Q4 IM RFB IFXD VC Q1 ENABLE Q2 Q3 CEXT VBG RREF I IM RREF 1425 EA 6 LT1425 WU W TI I G DIAGRA VSW VOLTAGE COLLAPSE DETECT VFLBK 0.80× VFLBK VIN GND SWITCH STATE OFF ON MINIMUM tON FLYBACK AMP STATE OFF ON ENABLE DELAY DISABLED ENABLED MINIMUM ENABLE TIME DISABLED 1425 TD U OPERATION The LT1425 is a current mode switching regulator IC that has been designed specifically for the isolated flyback topology. The special problem normally encountered in such circuits is that information relating to the output voltage on the isolated secondary side of the transformer must be communicated to the primary side in order to maintain regulation. Historically, this has been done with optoisolators or extra transformer windings. Optoisolator circuits waste output power and the extra components they require increase the cost and physical volume of the power supply. Optoisolators can also exhibit trouble due to limited dynamic response (temporal), nonlinearity, unit-to-unit variation and aging over life. Circuits employing extra transformer windings also exhibit deficiencies. The extra winding adds to the transformer’s physical size and cost. Dynamic response is often mediocre. There is usually no method for maintaining load regulation versus load. The LT1425 derives its information about the isolated output voltage by examining the primary side flyback pulse waveform. In this manner no optoisolator nor extra transformer winding is required. This IC is a quantum improvement over previous approaches because: target output voltage is directly resistor-programmable, regulation is maintained well into discontinuous mode and optional load compensation is available. The Block Diagram shows an overall view of the system. Many of the blocks are similar to those found in traditional designs including: internal bias regulator, oscillator, logic, current amplifier and comparator, driver and output switch. The novel sections include a special flyback error amplifier and a load compensation mechanism. Also, due to the special dynamic requirements of flyback control, the logic system contains additional functionality not found in conventional designs. 7 LT1425 U OPERATION Within the dashed lines in the Block Diagram can be found the RREF, RFB and ROCOMP resistors. They are external resistors on the user-programmable LT1425. The capacitor connected to the RCCOMP pin is also external. The LT1425 operates much the same as traditional current mode switchers, the major difference being a different type of error amplifier which derives its feedback information from the flyback pulse. Due to space constraints, this discussion will not reiterate the basics of current mode switcher/controllers and isolated flyback converters. A good source of information on these topics is LTC’s Application Note 19. ERROR AMPLIFIER—PSEUDO DC THEORY Please refer to the simplified diagram of the Flyback Error Amplifier. Operation is as follows: when output switch Q4 turns off, its collector voltage rises above the VIN rail. The amplitude of this flyback pulse, i.e., the difference between it and VIN, is given as: + VF + (ISEC)(ESR) V VFLBK = OUT NSP VF = D1 forward voltage ISEC = Transformer secondary current ESR = Total impedance of secondary circuit NSP = Transformer effective secondary-to-primary turns ratio The flyback voltage is then converted to a current by the action of RFB and Q1. Nearly all of this current flows through resistor RREF to form a ground-referred voltage. This is then compared to the internal bandgap reference by the differential transistor pair Q2/Q3. The collector current from Q2 is mirrored around and subtracted from fixed current source IFXD at the VC pin. An external capacitor integrates this net current to provide the control voltage to set the current mode trip point. The relatively high gain in the overall loop will then cause the voltage at the RREF resistor to be nearly equal to the bandgap reference VBG. (VBG is not present in final output voltage setting equation. See Applications Information section.) The relationship between VFLBK and VBG may then be expressed as: 8 V V α FLBK = BG or, RFB RREF VFLBK = VBG ) )) ) RFB RREF 1 α α = Ratio of Q1 IC to IE VBG = Internal bandgap reference Combination with the previous VFLBK expression yields an expression for VOUT, in terms of the internal reference, programming resistors, transformer turns ratio and diode forward voltage drop: VOUT = VBG ) )) ) RFB RREF NSP α – VF – ISEC (ESR) Additionally, it includes the effect of nonzero secondary output impedance. See Load Compensation for details. The practical aspects of applying this equation for VOUT are found in the Applications Information section. So far, this has been a pseudo-DC treatment of flyback error amplifier operation. But the flyback signal is a pulse, not a DC level. Provision must be made to enable the flyback amplifier only when the flyback pulse is present. This is accomplished by the dashed line connections to the block labeled “ENABLE.” Timing signals are then required to enable and disable the flyback amplifier. ERROR AMPLIFIER—DYNAMIC THEORY There are several timing signals that are required for proper LT1425 operation. Please refer to the Timing Diagram. Minimum Output Switch ON Time The LT1425 effects output voltage regulation via flyback pulse action. If the output switch is not turned on at all, there will be no flyback pulse, and output voltage information is no longer available. This would cause irregular loop response and start-up/latchup problems. The solution chosen is to require the output switch to be on for an absolute minimum time per each oscillator cycle. This in turn establishes a minimum load requirement to maintain LT1425 U OPERATION regulation. See Applications Information section for further details. Enable Delay When the output switch shuts off, the flyback pulse appears. However, it takes a finite time until the transformer primary side voltage waveform approximately represents the output voltage. This is partly due to rise time on the VSW node, but more importantly due to transformer leakage inductance. The latter causes a voltage spike on the primary side not directly related to output voltage. (Some time is also required for internal settling of the feedback amplifier circuitry.) In order to maintain immunity to these phenomena, a fixed delay is introduced between the switch turn-off command and the enabling of the feedback amplifier. This is termed “enable delay.” In certain cases where the leakage spike is not sufficiently settled by the end of the enable delay period, regulation error may result. See Applications Information section for further details. Collapse Detect Once the feedback amplifier is enabled, some mechanism is then required to disable it. This is accomplished by a collapse detect comparator, that compares the flyback voltage (RREF referred) to a fixed reference, nominally 80% of VBG. When the flyback waveform drops below this level, the feedback amplifier is disabled. This action accommodates both continuous and discontinuous mode operation. Minimum Enable Time The feedback amplifier, once enabled, stays enabled for a fixed minimum time period termed “minimum enable time.” This prevents lock-up, especially when the output voltage is abnormally low, e.g., during start-up. The minimum enable time period ensures that the VC node is able to “pump up” and increase the current mode trip point to the level where the collapse detect system exhibits proper operation. The “minimum enable time” often determines the low load level at which output voltage regulation is lost. See Applications Information section for details. Effects of Variable Enable Period It should now be clear that the flyback amplifier is enabled only during a portion of the cycle time. This can vary from the fixed “minimum enable time” described to a maximum of roughly the OFF switch time minus the enable delay time. Certain parameters of flyback amp behavior will then be directly affected by the variable enable period. These include effective transconductance and VC node slew rate. LOAD COMPENSATION THEORY The LT1425 uses the flyback pulse to obtain information about the isolated output voltage. A potential error source is caused by transformer secondary current flow through the real life nonzero impedances of the output rectifier, transformer secondary and output capacitor. This has been represented previously by the expression (ISEC)(ESR). However, it is generally more useful to convert this expression to an effective output impedance. Because the secondary current only flows during the off portion of the duty cycle, the effective output impedance equals the lumped secondary impedance times the inverse of the OFF duty cycle. That is, ROUT = ESR ) 1 DC OFF ) where, ROUT = Effective supply output impedance ESR = Lumped secondary impedance DC OFF = OFF duty cycle Expressing this in terms of the ON duty cycle, remembering DC OFF = 1 – DC, ROUT = ESR ) ) 1 1 – DC DC = ON duty cycle In less critical applications, or if output load current remains relatively constant, this output impedance error may be judged acceptable and the external RFB resistor value adjusted to compensate for nominal expected error. In more demanding applications, output impedance error 9 LT1425 U OPERATION may be minimized by the use of the load compensation function. To implement the load compensation function, a voltage is developed that is proportional to average output switch current. This voltage is then impressed across the external ROCOMP resistor and the resulting current is then subtracted from the RFB node. As output loading increases, average switch current increases to maintain rough output voltage regulation. This causes an increase in ROCOMP resistor current subtracted from the RFB node, through which feedback loop action causes a corresponding increase in target output voltage. Assuming a relatively fixed power supply efficiency, Eff, Power Out = (Eff)(Power In) (VOUT)(IOUT) = (Eff)(VIN)(IIN) Average primary side current may be expressed in terms of output current as follows: ) ) VOUT IIN = I (VIN)(Eff) OUT Combining the efficiency and voltage terms in a single variable, IIN = K1(IOUT) where, K1 = ) VOUT (VIN)(Eff) ) Switch current is converted to voltage by a sense resistor and amplified by the current sense amplifier with associated gain G. This voltage is then impressed across the 10 external ROCOMP resistor to form a current that is subtracted from the RFB node. So the effective change in VOUT target is: ∆VOUT = K1(∆IOUT) ) ) (RSENSE)(G) RFB ROCOMP Expressing the product of RSENSE and G as the data sheet value of ∆VRCCOMP/∆ISW, ROUT = K1 ) )) ) )) ) ∆VRCCOMP RFB and, ∆ISW ROCOMP ROCOMP = K1 ) ∆VRCCOMP RFB ROUT ∆ISW where, K1 = Dimensionless variable related to VIN, VOUT and efficiency as above ∆VRCCOMP = Data sheet value for RCCOMP pin ∆ISW action vs switch current RFB = External “feedback” resistor value ROUT = Uncompensated output impedance ) ) ) )) ∆VOUT ∆VRCCOMP RFB = K1 ∆IOUT ∆ISW ROCOMP ) Nominal output impedance cancellation is obtained by equating this expression with ROUT. The practical aspects of applying this equation to determine an appropriate value for the ROCOMP resistor are found in the Applications Information section. LT1425 U W U U APPLICATIONS INFORMATION SELECTING RFB AND RREF RESISTOR VALUES The expression for VOUT developed in the Operation section can be rearranged to yield the following expression for RFB: RFB = RREF ) )) ) VOUT + VF + ISEC(ESR) α VBG NSP The unknown parameter α, which represents the fraction of RFB current flowing into the RREF node, can be represented instead by specified data sheet values as follows: (IREF)(α)(3k) = VBG α= ) VBG (IREF)(3k) ) Allowing the expression for RFB to be rewritten as: RFB = RREF ) VOUT + VF + ISEC(ESR) IREF(3k)NSP ) where, VOUT = Desired output voltage VF = Switching diode forward voltage (ISEC)(ESR) = Secondary resistive losses IREF = Data sheet reference current value NSP = Effective secondary-to-primary turns ratio Strictly speaking, the above equation defines RFB not as an absolute value, but as a ratio of RREF. So the next question is, “What is the proper value for RREF?” The answer is that RREF should be approximately 3k. This is because the LT1425 is trimmed and specified using this value of RREF. If the impedance of RREF varies considerably from 3k, additional errors will result. However, a variation in RREF of several percent or so is perfectly acceptable. This yields a bit of freedom in selecting standard 1% resistor values to yield nominal RFB /RREF ratios. SELECTING ROCOMP RESISTOR VALUE The Operation section previously derived the following expressions for ROUT, i.e., effective output impedance and ROCOMP, the external resistor value required for its nominal compensation: ROUT = ESR ) 1 1 – DC ) ROCOMP = K1 ) )) ) ∆VRCCOMP RFB ∆ISW ROUT While the value for ROCOMP may therefore be theoretically determined, it is usually better in practice to employ empirical methods. This is because several of the required input variables are difficult to estimate precisely. For instance, the ESR term above includes that of the transformer secondary, but its effective ESR value depends on high frequency behavior, not simply DC winding resistance. Similarly, K1 appears to be a simple ratio of VIN to VOUT times (differential) efficiency, but theoretically estimating efficiency is not a simple calculation. The suggested empirical method is as follows: Build a prototype of the desired supply using the eventual secondary components. Temporarily ground the RCCOMP pin to disable the load compensation function. Operate the supply over the expected range of output current loading while measuring the output voltage deviation. Approximate this variation as a single value of ROUT (straight line approximation). Calculate a value for the K1 constant based on VIN, VOUT and the measured (differential) efficiency. They are then combined with the data sheet typical value for (∆VRCCOMP / ∆ISW ) to yield a value for ROCOMP. Verify this result by connecting a resistor of roughly this value from the ROCOMP pin to ground. (Disconnect the ground short to RCCOMP and connect the requisite 0.1µF filter capacitor to ground.) Measure the output impedance with the new compensation in place. Modify the original ROCOMP value if necessary to increase or decrease the effective compensation. Once the proper load compensation resistor has been chosen, it may be necessary to adjust the value of the RFB resistor. This is because the load compensation system exhibits some nonlinearity. In particular, the circuit can shift the reference current by a noticeable 11 LT1425 U W U U APPLICATIONS INFORMATION amount when output switch current is zero. Please refer to Figure 1 which shows nominal reference current shift at zero load for a range of ROCOMP values. Example: for a load compensation resistor of 12k, the graph indicates a 1.0% shift in reference current. The RFB resistor value should be adjusted down by about 1.0% to restore the original target output voltage. Leakage Inductance ∆IREF (%) 2 Transformer leakage inductance (on either the primary or secondary) causes a spike after output switch turn-off. This is increasingly prominent at higher load currents where more stored energy must be dissipated. In many cases a “snubber” circuit will be required to avoid overvoltage breakdown at the output switch node. LTC’s Application Note 19 is a good reference on snubber design. 1 0 1 10 100 ROCOMP (kΩ) 1000 1425 F01 Figure 1 In less critical applications, or when output current remains relatively constant, the load compensation function may be deemed unnecessary. In such cases, a reduced component solution may be obtained as follows: Leave the ROCOMP node open (ROCOMP = ∞), and replace the filter capacitor normally on the RCCOMP node with a short to ground. TRANSFORMER DESIGN CONSIDERATIONS Transformer specification and design is perhaps the most critical part of applying the LT1425 successfully. In addition to the usual list of caveats dealing with high frequency isolated power supply transformer design, the following information should prove useful. Turns Ratio Note that due to the use of an RFB/RREF resistor ratio to set output voltage, the user has relative freedom in selecting transformer turns ratio to suit a given application. In other words, “screwball” turns ratios like “1.736:1.0” can scrupulously be avoided! In contrast, simpler ratios of small 12 integers, e.g., 1:1, 2:1, 3:2, etc. can be employed which yield more freedom in setting total turns and mutual inductance. Turns ratio can then be chosen on the basis of desired duty cycle. However, remember that the input supply voltage plus the secondary-to-primary referred version of the flyback pulse (including leakage spike) must not exceed the allowed output switch breakdown rating. In situations where the flyback pulse extends beyond the enable delay time, the output voltage regulation will be affected to some degree. It is important to realize that the feedback system has a deliberately limited input range, roughly ±50mV referred to the RREF node, and this works to the user’s advantage in rejecting large, i.e., higher voltage leakage spikes. In other words, once a leakage spike is several volts in amplitude, a further increase in amplitude has little effect on the feedback system. So the user is generally advised to arrange the snubber circuit to clamp at as high a voltage as comfortably possible, observing switch breakdown, such that leakage spike duration is as short as possible. As a rough guide, total leakage inductances of several percent (of mutual inductance) or less may require a snubber, but exhibit little to no regulation error due to leakage spike behavior. Inductances from several percent up to perhaps ten percent cause increasing regulation error. Severe leakage inductances in the double digit percentage range should be avoided if at all possible as there is a potential for abrupt loss of control at high load current. This curious condition potentially occurs when the leakage spike becomes such a large portion of the flyback waveform that the processing circuitry is fooled into thinking that the leakage spike itself is the real flyback LT1425 U W U U APPLICATIONS INFORMATION signal! It then reverts to a potentially stable state whereby the top of the leakage spike is the control point, and the trailing edge of the leakage spike triggers the collapse detect circuitry. This will typically reduce the output voltage abruptly to a fraction, perhaps between one-third to two-thirds of its correct value. If load current is reduced sufficiently, the system will snap back to normal operation. When using transformers with considerable leakage inductance, it is important to exercise this worst-case check for potential bistability: 1. Operate the prototype supply at maximum expected load current. degrades load regulation (at least before load compensation is employed). Bifilar Winding A bifilar or similar winding technique is a good way to minimize troublesome leakage inductances. However, remember that this will increase primary-to-secondary capacitance and limit the primary-to-secondary breakdown voltage, so bifilar winding is not always practical. Finally, the LTC Applications group is available to assist in the choice and/or design of the transformer. Happy Winding! 2. Temporarily short circuit the output. 3. Observe that normal operation is restored. OUTPUT VOLTAGE ERROR SOURCES If the output voltage is found to hang up at an abnormally low value, the system has a problem. This will usually be evident by simultaneously monitoring the VSW waveform on an oscilloscope to observe leakage spike behavior firsthand. A final note, the susceptibility of the system to bistable behavior is somewhat a function of the load I/V characteristics. A load with resistive, i.e., I = V/R behavior is the most susceptible to bistability. Loads which exhibit “CMOSsy”, i.e., I = V 2/R behavior are less susceptible. Conventional nonisolated switching power supply ICs typically have only two substantial sources of output voltage error—the internal or external resistor divider network that connects to VOUT and the internal IC reference. The LT1425, which senses the output voltage in both a dynamic and an isolated manner, exhibits additional potential error sources to contend with. Some of these errors are proportional to output voltage, others are fixed in an absolute millivolt sense. Here is a list of possible error sources and their effective contribution: Secondary Leakage Inductance In addition to the previously described effects of leakage inductance in general, leakage inductance on the secondary in particular exhibits an additional phenomenon. It forms an inductive divider on the transformer secondary, that reduces the size of the primary-referred flyback pulse used for feedback. This will increase the output voltage target by a similar percentage. Note that unlike leakage spike behavior, this phenomenon is load independent. To the extent that the secondary leakage inductance is a constant percentage of mutual inductance (over manufacturing variations), this can be accommodated by adjusting the RFB /RREF resistor ratio. Winding Resistance Effects Resistance in either the primary or secondary will act to reduce overall efficiency (POUT/PIN). Resistance in the secondary increases effective output impedance which Internal Voltage Reference The internal bandgap voltage reference is, of course, imperfect. Its error, both at 25°C and over temperature is already included in the specifications for Reference Current. User Programming Resistors Output voltage is controlled by the ratio of RFB to RREF. Both are user supplied external resistors. To the extent that the resistor ratio differs from the ideal value, the output voltage will be proportionally affected. Schottky Diode Drop The LT1425 senses the output voltage from the transformer primary side during the flyback portion of the cycle. This sensed voltage therefore includes the forward drop, VF, of the rectifier (usually a Schottky diode). The nominal 13 LT1425 U W U U APPLICATIONS INFORMATION VF of this diode should therefore be included in RFB calculations. Lot-to-lot and ambient temperature variations will show up as output voltage shift/drift. Secondary Leakage Inductance Leakage inductance on the transformer secondary reduces the effective primary-to-secondary turns ratio (NP/NS) from its ideal value. This will increase the output voltage target by a similar percentage. To the extent that secondary leakage inductance is constant from part-topart, this can be accommodated by adjusting the RFB to RREF resistor ratio. “collapse,” thereby supporting operation well into discontinuous mode. Nevertheless, there still remain constraints to ultimate low load operation. They relate to the minimum switch ON time and the minimum enable time. Discontinuous mode operation will be assumed in the following theoretical derivations. As outlined in the Operation section, the LT1425 utilizes a minimum output switch ON time, tON. This value can be combined with expected VIN and switching frequency to yield an expression for minimum delivered power. Output Impedance Error An additional error source is caused by transformer secondary current flow through the real life nonzero impedances of the output rectifier, transformer secondary and output capacitor. Because the secondary current only flows during the off portion of the duty cycle, the effective output impedance equals the “DC” lumped secondary impedance times the inverse of the off duty cycle. If the output load current remains relatively constant, or, in less critical applications, the error may be judged acceptable and the RFB value adjusted for nominal expected error. In more demanding applications, output impedance error may be minimized by the use of the load compensation function (see Load Compensation). VIN Sense Error The LT1425 determines the size of the flyback pulse by comparing the VSW signal to VIN, through RFB. This comparison is not perfect, in the sense that an offset exists between the sensing mechanism and the actual VIN. This is expressed in the data sheet as VIN sense error. This error is fixed in absolute millivolt terms relative to VOUT (with the exception that it is reflected to VOUT by any nonunity secondary-to-primary turns ratio). MINIMUM LOAD CONSIDERATIONS The LT1425 generally provides better low load performance than previous generation switcher/controllers utilizing indirect output voltage sensing techniques. Specifically, it contains circuitry to detect flyback pulse 14 ) )) ) 1 f (V • t )2 2 LPRI IN ON = (VOUT)(IOUT) Min Power = This expression then yields a minimum output current constraint: IOUT(MIN) = ) )) ) f 1 (V • t )2 2 (LPRI)(VOUT) IN ON where, f = Switching frequency (nominally 285kHz) LPRI = Transformer primary side inductance VIN = Input voltage VOUT = Output voltage tON = Output switch minimum ON time An additional constraint has to do with the minimum enable time. The LT1425 derives its output voltage information from the flyback pulse. If the internal minimum enable time pulse extends beyond the flyback pulse, loss of regulation will occur. The onset of this condition can be determined by setting the width of the flyback pulse equal to the sum of the flyback enable delay, tED, plus the minimum enable time, tEN. Minimum power delivered to the load is then: ) )) ) 1 f [V • (t + t )]2 2 LSEC OUT EN ED = (VOUT)(IOUT) Min Power = which yields a minimum output constraint: LT1425 U U W U APPLICATIONS INFORMATION IOUT(MIN) = ) )) ) 1 f(VOUT) (tED + tEN)2 LSEC 2 where, f = Switching frequency (nominally 285kHz) LSEC = Transformer secondary side inductance VOUT = Output voltage tED = Enable delay time tEN = Minimum enable time Note that generally, depending on the particulars of input and output voltages and transformer inductance, one of the above constraints will prove more restrictive. In other words, the minimum load current in a particular application will be either “output switch minimum ON time” constrained, or “minimum flyback pulse time” constrained. (A final note—LPRI and LSEC refer to transformer inductance as seen from the primary or secondary side respectively. This general treatment allows these expressions to be used when the transformer turns ratio is nonunity.) MAXIMUM LOAD/SHORT-CIRCUIT CONSIDERATIONS The LT1425 is a current mode controller. It uses the VC node voltage as an input to a current comparator which turns off the output switch on a cycle-by-cycle basis as this peak current is reached. The internal clamp on the VC node, nominally 1.9V, then acts as an output switch peak current limit. This action becomes the switch current limit specification. The maximum available output power is then determined by the switch current limit, which is somewhat duty cycle dependent due to internal slope compensation action. Short-circuit conditions are handled by the same mechanism. The output switch turns on, peak current is quickly reached and the switch is turned off. Because the output switch is only on for a small fraction of the available period, internal power dissipation is controlled. (The LT1425 contains an internal overtemperature shutdown circuit, that disables switch action, just in case.) While the majority of users will not experience a problem, there is however, a possibility of loss of current limit under certain conditions. Remember that the LT1425 exhibits a minimum switch ON time, irrespective of current trip point. If the duty cycle exhibited by this minimum ON time is greater than the ratio of secondary winding voltage (referred-to-primary) divided by input voltage, then peak current will not be controlled at the nominal value, and will cycle-by-cycle ratchet up to some higher level. Expressed mathematically, the requirement to maintain short-circuit control is: (tON)(f) < ) ) VF + (ISC)(RSEC) (VIN)(NSP) where, tON = Output switch minimum ON time f = Switching frequency ISC = Short-circuit output current VF = Output diode forward voltage at ISC RSEC = Resistance of transformer secondary VIN = Input voltage NSP = Secondary-to-primary turns ratio (NSEC/NPRI) Trouble will typically only be encountered in applications with a relatively high product of input voltage times secondary-to-primary turns ratio. Additionally, several real world effects such as transformer leakage inductance, AC winding losses and output switch voltage drop combine to make this simple theoretical calculation a conservative estimate. In cases where short-circuit protection is mandatory and this theoretical calculation indicates cause for concern, the prototype should be observed directly as follows: short the output while observing the VSW signal with an oscilloscope. The measured output switch ON time can then be compared against the specifications for minimum tON. THERMAL CONSIDERATIONS Care should be taken to ensure that the worst-case input voltage and load current conditions do not cause excessive die temperatures. The narrow 16-pin package is rated at 75°C/W. 15 LT1425 U W U U APPLICATIONS INFORMATION Average supply current (including driver current) is: ) ) I IIN = 7mA + DC SW 35 where, ISW = Switch current DC = On switch duty cycle Switch power dissipation is given by: PSW = (ISW)2(RSW)(DC) RSW = Output switch ON resistance Total power dissipation of the die is the sum of supply current times supply voltage plus switch power: PD(TOTAL) = (IIN • VIN) + PSW FREQUENCY COMPENSATION Loop frequency compensation is performed by connecting a capacitor from the output of the error amplifier (VC pin) to ground. An additional series resistor, often required in traditional current mode switcher controllers is usually not required, and can even prove detrimental. The phase margin improvement traditionally offered by this extra resistor will usually be already accomplished by the nonzero secondary circuit impedance, which adds a “zero” to the loop response. In further contrast to traditional current mode switchers, VC pin ripple is generally not an issue with the LT1425. The dynamic nature of the clamped feedback amplifier forms an effective track/hold type response, whereby the VC voltage changes during the flyback pulse, but is then “held” during the subsequent “switch ON” portion of the 16 next cycle. This action naturally holds the VC voltage stable during the current comparator sense action (current mode switching). PCB LAYOUT CONSIDERATIONS For maximum efficiency, switch rise and fall times are made as short as practical. To prevent radiation and high frequency resonance problems, proper layout of the components connected to the IC is essential, especially the power paths (primary and secondary). B field (magnetic) radiation is minimized by keeping output diode, switch pin and output bypass capacitor leads as short as possible. E field radiation is kept low by minimizing the length and area of all traces connected to the switch pin. A ground plane should always be used under the switcher circuitry to prevent interplane coupling. The high speed switching current paths are shown schematically in Figure 2. Minimum lead length in these paths are essential to ensure clean switching and minimal EMI. The path containing the input capacitor, transformer primary, output switch, the path containing the transformer secondary, output diode and output capacitor are the only ones containing nanosecond rise and fall times. Keep these paths as short as possible. VOUT • VIN HIGH FREQUENCY CIRCULATING PATH • HIGH FREQUENCY CIRCULATING PATH ISOLATED LOAD F 1425 F02 Figure 2 LT1425 U TYPICAL APPLICATIONS The following are several application examples of the LT1425. The first shows an isolated LAN supply which provides – 9V with ±1% load regulation for output currents of 0mA to 250mA. An alternate transformer, the Coiltronics part, provides a complete PCMCIA Type II height solution. The LT1425 offers excellent load regulation and fast dynamic response not found in similar isolated flyback schemes. maximum input voltage, so a bootstrap winding is used. D1, D2, Q2 and Q3 and associated components for the necessary start-up circuitry with hysteresis. When C1 charges to 15V, switching begins and the bootstrap winding begins to supply power before C1 has a chance to discharge to 11V. Feedback voltage is fed directly through a resistor divider to the RREF pin. The load compensation circuitry is bypassed, resulting in ±5% load regulation. The next example shows a ±15V supply with 1.5kV of isolation. The sum of line/load/cross regulation is better than ±3%. Full load efficiency is between 72% (VIN = 5V) and 80% (VIN = 15V). The isolation is ultimately limited only by bobbin selection and transformer construction. Finally, the “12V to 5V Isolated Converter” is similar to the previous example in that a cascoded MOSFET is used to prevent voltage breakdown of the output switch. But because the nominal 12V input is well within the range of the VIN pin, no bootstrap winding is required and normal load compensation function is provided. Diode D1, transistor Q1 and associated components provide an undervoltage lockout function via the SHDN pin. The off-theshelf transformer provides up to 5W of isolated regulated power. The “– 48V to 5V Isolated Telecom Supply” uses an external cascoded 200V MOSFET to extend the LT1425’s 35V maximum switch voltage limit. The input voltage range (– 36V to – 72V) also exceeds the LT1425’s 20V – 9V Isolated LAN Supply R2 C6 5V C1 10µF 25V LT1425 0.1µF 1 C2 10µF 25V 22.1k 1% 2 3 4 5 100k 47pF 1000pF 3.01k 1% 6 7 8 GND D1 GND NC SHDN RFB ROCOMP VC RCCOMP RREF VIN SYNC VSW SGND PGND GND GND 16 MBRS130LT3 R1 15 C5 14 2 1 T1 OUT COM 7 C3 10µF 25V 13 R3 12 D2 4 11 3 C4 10µF 25V 1.8k 6 –9V 10 9 C1, C2, C3, C4 = MARCON THCS50E1E106Z CERAMIC CAPACITOR, SIZE 1812. (847) 696-2000 0.1µF INPUT COM 1424/25 TA03 Transformer T1 DALE LPE-4841-A307 COILTRONICS CTX02-13483 LPRI RATIO ISOLATION (L × W × H) IOUT EFFICIENCY D1 D2 R1, R2 C5, C6 R3 36µH 1:1:1 500VAC 10.7 × 11.5 × 6.3mm 250mA 76% NOT USED NOT USED 47Ω 330pF 13.3k 27µH 1:1 500VAC 14 × 14 × 2.2mm 200mA 70% 1N5248 MBR0540TL1 75Ω 220pF 5.9k 17 LT1425 U TYPICAL APPLICATIONS ±15V Isolated Power Supply 330pF 130Ω MBRS1100T3 T1* 5V TO 15V 1 + + 8 1µF 22µF 35V LT1425 1 0.1µF 18.4k 0.1% 2 3 4 5 1000pF 6 7 3.01k 1% 8 1N759 GND GND SHDN NC 75Ω RFB ROCOMP VC RCCOMP RREF VIN SYNC VSW SGND PGND GND GND 16 2 7 3 6 15V 60mA 15µF 35V 3k OUT COM MBRS1100T3 15 MBR0540LT1 14 13 + 220pF 12 4 5 15µF 35V 3k 11 10 1425 TA04 7.32k 1% 9 –15V 60mA *PHILIPS EFD-15-3F3 CORE GAP FOR PRIMARY L = 40µH 0.1µF INPUT COM PIN 3 TO 4, 7 TURNS BIFILAR 34AWG 3 LAYERS 2 MIL POLYESTER FILM PIN 7 TO 8, 28 TURNS 40AWG PIN 5 TO 6, 28 TURNS 40AWG PIN 1 TO 2, 7 TURNS BIFILAR 34AWG 0.12 INCH MARGIN TAPE – 48V to 5V Isolated Telecom Supply 470pF 18Ω 1 INPUT COM BAV21 R1 24k 3.3µF 5 BAV21 1 R2 18Ω 2 0.1µF + 30.1k 1% C1 27µF 35V 3 4 5 6 D1 7.5V 1N755 3.16k 1% 7 8 1000pF T1 LT1425 GND NC GND SHDN RFB ROCOMP VC RCCOMP RREF VIN SYNC VSW SGND PGND GND GND MBR745 5V 2A 2 510Ω 16 15 T1* 8 150µF 6.3V 3 6 + 4 7 13 10Ω 50Ω 1W OUT COM Q1 IRF620 11 10 150µF 6.3V 150pF 14 12 + MUR120 9 –36V TO –72V 2.4k Q2 2N3906 Q3 2N3904 5k 100k D2 7.5V 1N755 10k 0.1µF 1425 TA06 *PHILIPS EFD-15-3F3 CORE GAP FOR PRIMARY L = 100µH PIN 3 TO 4, 15 TURNS BIFILAR 31AWG PIN 7 TO 8, 6 TURNS QUADFILAR 29AWG PIN 5 TO 6, 15 TURNS BIFILAR 33AWG PIN 1 TO 2, 15 TURNS BIFILAR 31AWG 18 2 LAYERS 2 MIL POLYESTER FILM 1 LAYER 2 MIL POLYESTER FILM LT1425 U PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. S Package 16-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610) 0.386 – 0.394* (9.804 – 10.008) 16 15 14 13 12 11 10 9 0.150 – 0.157** (3.810 – 3.988) 0.228 – 0.244 (5.791 – 6.197) 1 0.010 – 0.020 × 45° (0.254 – 0.508) 0.008 – 0.010 (0.203 – 0.254) 2 3 4 5 6 0.053 – 0.069 (1.346 – 1.752) 0.014 – 0.019 (0.355 – 0.483) 8 0.004 – 0.010 (0.101 – 0.254) 0° – 8° TYP 0.016 – 0.050 0.406 – 1.270 7 0.050 (1.270) TYP S16 0695 *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LT1425 U TYPICAL APPLICATION 12V to 5V Isolated Converter 330pF 100Ω 4 12V 22µF 35V + 2.4k 25.5k 1% 0.1µF D1 1N755 7.5V 2 3 4 5 1000pF 6 7 3.01k 1% 8 GND NC GND SHDN RFB ROCOMP VC RCCOMP RREF VIN SYNC VSW SGND PGND GND GND 16 Q1 2N3906 8 MBRS340T3 9 220µF 10V 5 + 5V 1A 220µF 10V + 200Ω 15 14 2 6 10 11 12 OUT COM 13 10Ω 12 MMFT1N10E 11 10 MUR120 9 0.1µF INPUT COM 1.8k 7 1 LT1425 1 3 9.3k 1% COILTRONICS VP1-0190 TURNS RATIO 1 : 1 : 1 : 1 : 1 : 1 12µH PER WINDING 407-241-7876 1425 TA05 1000pF RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1105 Off-Line Switching Regulator Built-In Isolated Regulation Without Optoisolator LTC®1145/46 Isolated Digital Data Transceivers Up to 200kbps Data Rate, UL Listed LT1170/71/72 5A/3A/1.25A Flyback Regulators Isolated Flyback Mode for Higher Currents LT1372/77 500kHz/1MHz Boost/Flyback Regulators Uses Ultrasmall Magnetics LT1424 Application Specific Isolated Regulator 8-Pin Fixed Voltage Version of LT1425 20 Linear Technology Corporation 1425fa LT/TP 1198 2K REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com LINEAR TECHNOLOGY CORPORATION 1997