TI TPS2384

SLUS634A − NOVEMBER 2004 − REVISED DECEMBER 2004
QUAD INTEGRATED POWER SOURCING EQUIPMENT POWER
MANAGER
APPLICATIONS
D Ethernet Enterprise Switches
D Ethernet Hubs
D SOHO Hubs
D Ethernet Mid-Spans
D PSE Injectors
FEATURES
D Quad-Port Power Management With
D
D
D
D
D
D
D
D
D
D
D
D
D
Integrated Switches and Sense Resistors
Compliant to IEEE 802.3af Standard
Operates from a Single 48-V Input Supply
Individual Port 15-bit A/D
Auto, Semi-Auto and Manual Operating Modes
Controlled Current Ramps for Reduced EMI
and Charging of PD’s Bulk Capacitance
I2C Clock and Oscillator Watch Dog Timers
Over-Temperature Protection
DC and DC Modulated Disconnect
Supports Legacy Detection for Non-Compliant
PD
Supports AC Disconnect
High-Speed 400-kHz I2C Interface
Comprehensive Power Management Software
Available
Operating Temperature Range −40°C to 125°C
DESCRIPTION
The TPS2384 is a quad-port power sourcing equipment
power manager (PSEPM) and is compliant to the
Power-over-Ethernet (PoE) IEEE 802.3af standard.
The TPS2384 operates from a single 48-V supply and
over a wide temperature range (−40°C to +125°C). The
integrated output eliminates 2 external components per
port (FET and sense resistor) and will survive 100-V
transient. Four individual 15-bit A/D converters are used
to measure port voltage, current and die temperature
making PSE solution simple and robust. The TPS2384
comes with a comprehensive software solution to meet
the most demanding application which can serve as a
core for all PoE system designs.
TYPICAL APPLICATION
RJ45
4
Up to 100m RJ45
of CAT 5
4
Powered DTR
Switch/HUB
5
5
Spare Pair
+48V
1
1
P
Optional
MSP430
Micro−
Controller
T
P
S
2
SCL 3
SDA−I 8
SDA−O 4
Ret
N
Rx
Tx
VDD
2
2
T
P
S
2
3
ILIM 7
CLASS5
Signal Pair
DET
( )
3
PG
3
Rx
Tx
6
VEE
RTN
DC/DC
Converte
6
Signal Pair
+48V
Return
3
3
6
6
Spare Pair
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
!
" # $%! & % & !
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1
SLUS634A − NOVEMBER 2004 − REVISED DECEMBER 2004
DESCRIPTION (CONTINUED)
The TPS2384 has three internal supply buses (10 V, 6.3 V and 3.3 V) generated from the 48-V input supply.
These supplies are used to bias all internal digital and analog circuitry. Each supply has been brought out
separately for proper bypassing to insure high performance. The digital supply (3.3 V) is available for powering
external loads up to 2 mA. For more demanding loads it is highly recommended to use external buffers to prevent
system degradation. When the TPS2384 is initially powered up an internal Power-on-Reset (POR) circuit resets
all registers and sets all ports to the off state to ensure that the device is powered up in a known safe operating
state.
The TPS2384 has three modes of operation auto mode (AM), semi-auto mode (SAM) and power management
mode (PMM).
D In auto mode the TPS2384 performs discovery, classification and delivery of power autonomously to a
compliant PD without the need of a micro-controller.
D In semi-auto mode the TPS2384 operates in auto mode but users can access the contents of all read status
registers and A/D registers thru the I2C serial interface. All write control registers are active except for D0
thru D3 of port register 1 (Address 0010) for limited port control. The semi-auto mode allows the TPS2384
to detect valid PD without micro-controller intervention but adds a flexibility to perform power management
activities.
D Power management mode (with a micro-controller) allows users additional capabilities of discovering
non-compliant (legacy) PDs, performing ac disconnect and advanced power management system control
that are based on real time port voltages and currents. All functions in this mode are programmed and
controlled through read/write registers over the I2C interface. This allows users complete freedom in
detecting and powering devices. A comprehensive software package is available that mates the power of
the TPS2384 with the MSP430 micro-controller.
TPS2384 integrated output stage provides port power and low-side control. The internal low-side circuitry is
designed with internal current sensing so there are no external resistors required. The output design ensures
the power switches operate in the fully enhanced mode for low power dissipation.
The I2C interface allows easy application of opto-coupler circuitry to maintain Ethernet port isolation when a
ground based micro-controller is required. The TPS2384 has 5 address pins allowing individual control and
monitoring of up to 128 Ethernet ports from a single master I2C micro-controller. The I2C interface is set for group
broadcast on address 0 allowing simultaneous access to an entire bank of TPS2384 devices. Per-port write
registers separately control each port state (discovery, classification, legacy, power up etc) while the read
registers contain status information of the entire process along with parametric values of discovery,
classification, and real-time port operating current, voltage and die temperature.
The proprietary 15-bit integrating A/D converter is designed to meet the harsh environment where the PSEPM
resides. The converter is set for maximum rejection of power line noise allowing it to make accurate
measurements of line currents during discovery, classification and power delivery for reliable power
management decisions.
The TPS2384 is available in a 64-pin Power PADt package.
2
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SLUS634A − NOVEMBER 2004 − REVISED DECEMBER 2004
ORDERING INFORMATION
TEMPERATURE RANGE
TA = TJ
PACKAGED DEVICES{
TQFP − 64 (PAP)}
−40°C to 125°C
TPS2384
† The PAP package is available taped and reeled. Add R suffix to device type
(e.g.TPS2384PAPR) to order quantities of 2,500devices per reel.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature (unless otherwise noted)†}
PARAMETER
SYMBOL
V10 current sourced
RATING
UNITS
100
µA
5
mA
V3.3 current sourced
Applied voltage on #CINT, CT, RBIAS
−0.5 to +10
Applied voltage on SCL_I, SDA_I, SDA_O, INTB, A1, A2, A3, A4,
A5, MS, PORB, WD_DIS, ALT_A/B, AC_LO, AC_HI
−0.5 to +6
Applied voltage on V48, #P, #N
−0.5 to +80
Junction operating temperature
TJ
Tstg
Tsol
Storage temperature
V
−40 to 125
oC
−55 to 150
Lead temperature (soldering, 10 sec.)
260
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute−maximum−rated conditions for extended periods may affect device reliability.
‡ All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal. Consult Packaging Section of the Databook
for thermal limitations and considerations of packages.
RECOMMENDED OPERATION CONDITIONS
Parameter
MIN
TYP
MAX
Input voltage, VDD
44
48
57
UNITS
V
Junction temperature, TJ
−40
125
°C
ELECTRO STATIC DISCHARGE (ESD) PROTECTION
MAX
Human body model
UNITS
1.5
CDM
1
Machine model
kV
0.2
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3
SLUS634A − NOVEMBER 2004 − REVISED DECEMBER 2004
ELECTRICAL CHARACTERISTICS:
V48 = 48 V, RT = 124 kΩ, CT = 220 pf, CINT = 0.027 µF (low leakage), −40°C to −125°C and TA = Tj (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
4
9
12
10
14
9.75
10.5
11.5
3
3.3
3.7
UNITS
Power Supply
V48 quiescent current
Off mode (all ports)
V48 quiescent current
Powered mode (all ports)
V10, internal analog supply
V3.3, internal digital supply
ILOAD = 0
ILOAD = 0 to 3 mA
V3.3 short circuit current
V=0
3
V6.3, internal supply
Iload = 0
5
6.3
7
V2.5, internal reference supply
Iload = 0
2.46
2.5
2.54
26
32
Input UVLO
Internal POR time out(I2C)
After all supplies are good
I2C activity is valid
12
V
mA
V
8
Pulses
After all supplies are good
Internal POR time out (Port)
mA
66000
Port active to I2C commands
Port Discovery
Port off #P to #N input resistance
400
Discovery open circuit voltage
kΩ
22
Discovery 1 voltage loop control
70 µA < IPORT < 3 mA
Discovery 2 voltage loop control
70 µA < IPORT I < 3 mA
Discovery current limit
P = N = 48 V
2.8
3
30
4.4
V
8.8
10
4
5
mA
Auto-mode discovery resistance acceptance Band
19
26.5
Auto-mode discovery resistance low
end rejection
0
15
kΩ
Auto-mode discovery resistance high
end rejection
33
6.10
6.75
count/
µA
18
22
ms
Discovery1,2 A/D conversion scale
factor
10 µA < IPORT < 3 mA
Discovery1,2 A/D conversion time
IPORT= 120 µA
4
5.30
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SLUS634A − NOVEMBER 2004 − REVISED DECEMBER 2004
ELECTRICAL CHARACTERISTICS:
V48 = 48 V, RT = 124 kΩ, CT = 220 pf, CINT = 0.027 µF (low leakage), −40°C to −125°C and TA = Tj (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNITS
15
17.5
20
V
Port Classification
Classification voltage loop control
100 µA < IPORT < 50 mA
Classification current limit
P = N = 48 V
50
60
100
Class 0 to 1 detection threshold
5.5
6.5
7.5
Class 1 to 2 detection threshold
13
14.5
16
Class 2 to 3 detection threshold
21
23
25
Class 3 to 4 detection threshold
31
33
35
Class 4 to 0 detection threshold
45
48
51
Classification A/D conversion scale
factor
375
424
475
Count/
mA
18
22
ms
2.6
3.5
4.3
mA
1365
1400
1445
Count/V
22
ms
Classification A/D conversion time
IPORT = 50 mA
mA
Port Legacy Detection
Legacy current limit
P = N = 48 V
Legacy voltage A/D conversion scale
factor
100 mV < VPORT < 17.5 V
Legacy A/D conversion time
0 V < VPORT < 15 V
18
Port on resistance
20 mA < IPORT < 300 mA
1.3
Over current threshold
RBIAS = 124 kΩ, CT = 200 pF
Time > 75 ms, −25 ≤ Tj ≤ 105
Output current limit
Average min current trip
Port Powered Mode
350
Ω
375
400
RBIAS = 124 kΩ, CT = 200 pF
Time > 75 ms, −25 ≤ Tj ≤ 105
425
450
RBIAS = 124 kΩ, CT = 200 pF
Current pulse > 100 ms
7.5
10
Port output UV
42.0
42.7
44.0
Port output OV
54
55
56
Over current time Limit
RBIAS = 124 kΩ, CT = 200 pF
50
75
Short circuit time Limit
RBIAS = 124 kΩ, CT = 200 pF
50
75
Turn−off delay from UV/OV faults
RBIAS = 124 kΩ, CT = 200 pF
After port enabled and ramped up
Port current A/D conversion scale factor
20 mA < IPORT I < 300 mA
Port current A/D conversion time
IPORT < 300mA
Port voltage A/D conversion scale factor
45 V < VPORT < 56 V
Port voltage A/D conversion time
45 V < VPORT < 56 V
31
ms
36.41
40
Count/
mA
18
22
ms
353
370
Count/V
18
22
300
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V
3
335
Port temperature A/D conversion
scale factor
mA
ms
Count/
°C
5
SLUS634A − NOVEMBER 2004 − REVISED DECEMBER 2004
ELECTRICAL CHARACTERISTICS:
V48 = 48 V, RT = 124 kΩ, CT = 220 pf, CINT = 0.027 µF (low leakage), −40°C to −125°C and TA = Tj (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNITS
Port Disable Mode
Port N voltage
P = 48 V
47
V
AC Low & AC High Specification
AC_lo, AC_hi − low output voltage
0
0.5
AC_lo − high output voltage
3.0
5.0
AC_hi − high output voltage
Digital I2C DC Specifications
5.0
7.0
SCL, SDA_I, A1−A5 ,WD_DIS,
ALTA/B, MS, PORB logic input threshold
1.5
SCL, SDA_I input hysteresis
250
MS, PORB input hysteresis
150
WD_DIS,ALT A/B, MS, PORB input
pull-down resistance
V
V
mV
Input voltage 0.5 to 3 V
50
kΩ
10
µA
SDA_O logic high leakage
Drain = 5 V
100
nA
SDA_O logic low
ISINK = 10 mA
Drain = 6 V
200
mV
10
µA
ISINK = 10 mA
200
mV
A1−A5 pull-down current
INTB logic high leakage
INTB logic low
Digital I2C Timing
SCL clock frequency
0
Pulse duration
SCL high
0.6
Pulse duration
SCL low
1.3
Rise time, SCL toSDA
kHz
300
Fall time, SCL to SDA
300
Setup time, SDA to SCL
250
Hold time, SCL to SDA
300
Bus free time between start and stop
1.3
Setup time, SCL to Start condition
0.6
Hold time, start condition to SCL
0.6
Setup time, SCL to stop condition
0.6
NOTES: 1. Probe test only. TPx numbers are internal device test points only available at wafer probe
2. Ensured by design. Not 100% tested in production.
6
400
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900
µss
SLUS634A − NOVEMBER 2004 − REVISED DECEMBER 2004
TPS2384 SINGLE PORT BLOCK DIAGRAM
V48
UVLO
AG1
Internal Supply
Generator
6.3V
+6.3V Linear
Reg
10V
+10V Linear Reg
Vref
+2.5V Internal
Ref
Rbias
Ct
Syn
AC_
Hi
Diff Amp
(Fix Gain)
600K
ÎÎ
ÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎ
ÎÎ
ÎÎ ÎÎ
ÎÎÎÎÎÎÎÎÎÎ
Î
ÎÎ
ÎÎÎ ÎÎÎÎÎ
ÎÎ
ÎÎ ÎÎÎÎÎ
ÎÎ ÎÎÎÎÎ
ÎÎ ÎÎÎÎÎ
ÎÎ
Î
ÎÎ
Î
ÎÎÎÎÎÎÎÎÎÎÎ
PORB
AG2
WD_
dis
3.3V
Dgnd
Alt
A/B
SCL
Clk
Data_
In
Data_
Out
INTB
N
Bias Generator
Osc
AC Drivers
AC_
Lo
P
+
UV/OV
Comparators
POR
+
RGnd
1 of 4 Ports
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
Loop Cntrl Amp
Detect/Class Modes
Two
8 Bits
Status
Register
Two
8 Bits
Control
Register
Auto
Seq
Logic
Analog
Control
Circurtry
LCA
Power Mode
A2D
Registers
WatchDog
Thermal
Detector
Max I
Thld
Resistor
Voltage
Current
&
Die Temp
+3.3V Internal
Reg
LS Return
(Det/Class/Pwr)
+
T
A2D
V
I
8 Bit Common
Port Control
Register
OVI
8 Bit Common
Port Status
Register
I2C
Serial IO
Timer
+
OVI
Thld
8 Bit Common
Port Test
Register
A1
A2
A3
A4
A5
MS
Ret
Cint
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7
SLUS634A − NOVEMBER 2004 − REVISED DECEMBER 2004
TERMINAL FUNCTIONS
Power and Ground
Pin Name
Pin #
I/O
Description
I
48-V input to the device. This supply can have a range of 44 to 57 V. This pin should be de-coupled with
a 0.1-µF capacitor from V48 to AG1 placed as close to the device as possible.
V48
60
V10
58
O
10-V analog supply. The 10-V reference is generated internally and connects to the main internal analog
power bus. A 0.1-µF de-coupling capacitor should terminate as close to this node and the AG1 pin as
possible. Do not use for an external supply.
V6.3
59
O
6.3-V analog supply. A 0.1-µF de-coupling capacitor should terminate as close to this pin and the AG1
pin as possible. Do not use for an external supply.
V3.3
24
O
3.3-V logic supply. The 3.3-V supply is generated internally and connects to the internal logic power bus.
A 0.1-µF de-coupling capacitor should terminate as close to this node and the DG pin as possible. This
output can be used as a low current supply to external logic.
V2.5
54
O
2.5-V reference supply. The V2.5 is generated internally and connects to the internal reference power
bus. This pin should not be tied to any external supplies. A 0.1-µF de-coupling capacitor should terminate as close to this node and the RG pin as possible. Do not use for an external supply.
AG1
57
GND
Analog ground 1. This is the analog ground of the V6.3, V10 and V48 power systems. It should be externally tied to the common copper 48-V return plane. This pin should carry the low side of three de-coupling capacitors tied to V48, V10 and V6.3.
AG2
61
GND
Analog ground 2. This is the analog ground which ties to the substrate and ESD structures of the device.
It should be externally tied to the common copper 48-V return plane. AG1 and AG2 must be tied together directly for the best noise immunity.
DG
23
GND
Digital ground. This pin connects to the internal logic ground bus. It should be externally tied to the common copper 48-V return plane.
RG
56
GND
Reference ground. This is a precision sense of the external ground plane. The integration capacitor
(CINT#) and the biasing resistor (RBIAS pin) should be tied to this ground. This ground should also be
used to form a printed wiring board ground guard ring around the active node of the integration capacitor
(CINT#). It should tie to common copper 48-V return plane.
Description
Port Analog Signal
Pin #
I/O
1P
Pin Name
7
I
2P
10
I
3P
39
I
4P
42
I
1N
6
I
2N
11
I
3N
38
I
4N
43
I
1Ret
5
I
2Ret
12
I
3Ret
37
I
4Ret
44
I
1Cint
4
I
2Cint
13
I
3Cint
36
I
4Cint
45
I
8
Port Positive. 48-V load sense pin. Terminal voltage is monitored and controlled differentially with respect to each Port N pin. Optionally, if the application warrants, this high side path can be protected with
the use of a self−resetting poly fuse.
Port negative. 48-V load return pin. The low side of the load is switched and protected by internal circuitry that will limit the current.
48-V return pin
Integration capacitor. This capacitor is used for the ramp A/D converter signal integration. Connect a
0.027-µF capacitor from this pin to #RG. To minimize errors use a polycarbonate, polypropylene, polystyrene or teflon capacitor type to prevent leakage. Other types of capacitors can be used with increased conversion error.
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SLUS634A − NOVEMBER 2004 − REVISED DECEMBER 2004
TERMINAL FUNCTIONS
Analog Signals
Pin Name
CT
Pin #
53
I/O
Description
I
This is a dual-purpose pin. When tied to an external capacitor this pin sets the internal clock. When the CT
pin is grounded the SYN Pin turns from a output to an input (see SYN Pin description)
The timing capacitor and the resistor on the RBIAS pin sets the internal clock frequency of the device. This
internal clock is used for the internal state machine, integrating A/D counters, POR time out, faults and delay
timers of each port. Using a 220-pF capacitor for CT and a 124-kΩ resistor for RBIAS sets the internal clock
to 245 kHz and ensure IEEE 802.3af compliance along with maximizing the rejection of 60-Hz line frequency
noise from A/D measurements.
I
Bias set resistor. This resistor sets all precision bias currents within the chip. The RBIAS pin is control to
voltage of 1.25 V. This voltage and RBIAS generates a current which is replicated and used throughout the
chip. This resistor also works in conjunction with the capacitors on CT and CINT to set internal timing values. The RBIAS resistor should be connected RG. RBIAS is a high impedance input and care needs to be
taken to avoid signal injection from the SYN pin or I2C signals.
Rbias
55
SYN
52
AC_LO
51
O
Open drain output pin for ac disconnect excitation
AC_HI
50
O
Totem poll output pin for ac disconnect excitation.
I/O
This is a dual purpose pin. When the CT pin is connected to a timing capacitor this output pin is a 0 to 5 V
pulse of the internal clock which can be used to drive other TPS2384 SYN pins for elimination of a timing
capacitor. When the CT pin is grounded this pin becomes an input pin that can be driven from a master
TPS2384 or any other clock generate signal.
Digital Signals
Pin Name
Pin #
I/O
SCL
25
I
SDA_I
26
I
SDA_O
27
O
WD_DIS
22
I
This input pin when held high disables the watch dog timer monitoring the I2C clock and the OSC/SYN pins.
The WD pin has an internal 50-kΩ resistor pull-down to digital ground. Also the WD timer is automatically
shut off when the MS pin is set to 0 V (auto mode).
INTB
20
O
This is an open-drain output that goes low if a fault condition occurs on any of the 4 ports.
ALT A/B
21
I
When this input is set to logic low there is no back-off time after a discovery failure. When this pin set to a
logic high there is a back-off time (approximately 2 seconds) before initiating another discovery cycle. This
pin has an internal 50-kΩ resistor pull-down to digital ground.
A1
28
I
A2
29
I
A3
30
I
A4
31
I
A5
32
I
MS
PORB
63
I
I
Description
Serial clock input pin for the I2C interface.
Serial data input pin for the I2C interface. When tied to the SDA_O pin, this connection becomes the standard bi-directional serial data line (SDA)
Serial data open drain output for the I2C interface. When tied to the SDA_I pin, this connection becomes the
standard bi-directional serial data line (SDA). This is a open drain output that can drive opto-coupler LEDs
directly from the 48-V bus with an external, series current limiting resistor.
Address 1 through 5. This is the I2C address select input. Select the appropriate binary address on these
pins by connecting this pin to chip ground for a logic low and tying this pin to the V3.3 pin for a logic high.
Each address line has an internal current source pull-down to digital ground.
The MS pin selects either the auto mode (MS Low) or the power management mode, PMM, (MS High). This
pin can be held low for controller-less standalone applications. When MS is Low and the POR timing cycle is
complete the chip will sequentially Discover, Classify and Power on each port. When MS is set high the ports
are controlled by register setting via the I2C bus. The MS pin has an internal 50-kΩ resistor pull-down to
analog ground.
This pin can be used to override the internal POR. When held low, the I2C interface, all the state machines,
and registers are held in reset. When all internal and external supplies are within specification, and this pin is
set to a logic high level, the POR delay will begin. The I2C interface and registers will become active within
70 µs of this event and communications to read or preset registers can begin. The reset delay for the remainder of the chip then extinguishes in 1 second. This pin has an internal 50-kΩ resistor pull-down to analog ground.
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9
SLUS634A − NOVEMBER 2004 − REVISED DECEMBER 2004
CONNECTION DIAGRAM
PO R B
AG 2
V48
6.3V
V10
AG 1
RG
RBIAS
V2.5
CT
SYN
AC _lO
AC _HI
64
MS
tqfp PACKAGE (TQFP−64)
(TOP VIEW)
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
1
48
2
47
3
46
CINT1
4
45 CINT4
RET1
5
44 RET4
N1
6
43 N4
P1
7
42 P4
TPS2384
64 Pin Power Pad
8
41
TQFP
40
9
P2
10
39 P3
N2
11
38
RET2
12
37 RET3
CINT2 13
36 CINT3
33
10
25
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26
27
28
29
30
31
32
A5
24
A4
23
A3
22
A2
21
A1
20
SD A−O
19
S DA−I
18
IN TB
17
SC L
16
V3
34
DG
15
W D _DIS
35
AltA/B
14
N3
SLUS634A − NOVEMBER 2004 − REVISED DECEMBER 2004
AUTO MODE FUNCTIONAL DESCRIPTION
Auto Mode
Auto mode (MS = low) is a basic approach to building power sourcing equipment power manager systems
without a micro-controller. When AM has been selected the TPS2384 automatically performs the following
functions;
D
D
D
D
D
D
D
D
D
Discovery of IEEE 802.3af compliant power devices (PD)
Classification
Power delivery
Port over/under voltage detection
Port over current detection (350 mA < IPORT < 400 mA)
Port maximum current limit (400 mA < IPORT < 450 mA)
DC disconnect (5 mA < IPORT< 10 mA)
Thermal shutdown protection (Tj > 150° C)
Internal oscillator watch dog
In AM all the information in the read registers are available through the I2C interface along with controlling some
states by writing to the appropriate registers. This gives the user the ability to use the TPS2384 in a semi-auto
mode where the TPS2384 auto detects compliant PD’s and a host can access the A/D registers and class
information for power management, turn-on or off ports and disable dc disconnect or discovery faults.
The write registers that still active in AM are;
D
D
D
D
D
D
D
All ports disable – common write register 0001
Over/Under Voltage Faults − common write register 0001
Software reset − common write register 0001
Disconnect disable – write register 0001
Discovery fault disable – write register 0001
Port enable – write register 0011
Power mode class over current threshold enable − write register 0011
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SLUS634A − NOVEMBER 2004 − REVISED DECEMBER 2004
AUTO MODE FUNCTIONAL DESCRIPTION
0
Enable?
1
Detect
A
B
0
19<Rd<26.5
Alt AorB
2 Sec Timer
1
Due to Power only 1 Port can
be classifying at a time
OK_Classify?
0
1
Classification
Update
Class Register
Ramp Pwr
0
0
PortPwr
Update Reg
A2D V/I
Measurements
A2D Register
Update
Disconnect?
1
300mS<TMPDO
<
400 ms
1
Continuous Monitoring State
0
1
1
I > Isc or
I > P_Class
1
< U/O V >
>5 ms
0
0
1
TSD
0
RampPwrDwn
0
1
> 50 ms
RampPwrDwn
Figure 1. The Basic Flow for Auto Mode
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Ted > 750 ms
SLUS634A − NOVEMBER 2004 − REVISED DECEMBER 2004
AUTO MODE FUNCTIONAL DESCRIPTION
AM Discovery
The TPS2384 uses two low level probe signals (typically 4.4 V and 8.8 V) during the discovery process to
determine whether a valid PD is present. The use of multi point or slope detection method for the PD resistor
measurement allows accurate detection even when series steering diodes are present. The low level probe
voltages also prevent damage to non-802.3 devices. When a valid PD has been detected the TPS2384 moves
to the classification. If a valid PD has not been detected the TPS2384 continues to cycle through the discovery
process. The waveform in Figure 2 shows typical N-pin waveforms for the discovery of a valid PD and the failure
to discovery due to a discovery resistor of 15 kΩ and 33 kΩ.
Dis 1
Dis 1
Port 2 Voltage
Unsuccessful discovery
Rdiscovery = 15 kΩ
Dis 2
Dis 2
Dis 1
Port 3 Voltage
Unsuccessful discovery
Rdiscovery = 33 kΩ
Dis 2
Class
Port 1 Voltage
Successful discovery
Power On
Rdiscovery = 25 kΩ
t − Time − 20 ms/div.
Figure 2.
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SLUS634A − NOVEMBER 2004 − REVISED DECEMBER 2004
AUTO MODE FUNCTIONAL DESCRIPTION
AM Classification
After a successful discovery of a valid PD the TPS2384 enters the classification function that identifies the power
level based on the PD’s current signature. The classification current level is measured at a reduced terminal
voltage of 17.5 V and classified with 15 bits of resolution. During classification the power consumption can be
at its highest so to prevent over temperature shutdown in auto mode only one port classifies at a time. When
multi-ports successfully discovery and enter classification at the same time the auto sequencer processes each
request separately allowing only one port to enter classification. Figure 3 shows all 4 ports successfully
detecting a valid PD at the same time and than the classification of each port occurring separately.
Port waiting to classify
Port N1
Port N2
Port N3
10 V/div.
Port N4
Port Off
Dis1
Dis2
Class
t − Time − 20 ms/div.
Figure 3.
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SLUS634A − NOVEMBER 2004 − REVISED DECEMBER 2004
AUTO MODE FUNCTIONAL DESCRIPTION
Upon completion of classification the port classification register is updated. In AM mode this information is not
used but for semi-auto mode the class information can be used for power management and the over current
threshold can be set to correspond to the PD’s classification by setting the power mode class over current
threshold bit in the individual port control register (address 0011). The Figure 4 shows actual class currents and
the class assignment which where stored in the register. These assignments are compliant with the IEEE
802.3af Standard
4
0
0
or
1
1
0
or
1
or
2
2
Class
3
0
or
2
or
3
3
4
0
or
4
0
or
3
or
4
2
1
0
0
10
20
30
40
50
60
Measured IClass (mA)
Figure 4.
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SLUS634A − NOVEMBER 2004 − REVISED DECEMBER 2004
AUTO MODE FUNCTIONAL DESCRIPTION
AM Power Delivery
After successfully discovery and classification of a valid PD the power is delivered by controlling the current to
the PD until its current requirements are met or until the internal current limit is reached (approximately 425 mA).
The power switch is fully enhanced after 500 µs. Figure 5 show the voltage and the current that is being applied
to the PD during power-up and reaching the PD load of 250 mA.
Port current
50 mA/div.
N pin voltage
10 V/div.
t − Time − 100 µs/div.
Figure 5.
After power has been applied to the PD the TPS2384 automatically enters the current and voltage sample mode.
The sample mode performs 31 current measurements and a 1 voltage measurement. Each measurement takes
approximately 18 ms to complete. The port remains powered and the current/voltage measurement cycle
continues until a fault condition occurs. The current and voltage measurements are both stored in the A/D
current and voltage registers and can be access through the I2C pins. This allows power management in the
AM if it is desired.
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SLUS634A − NOVEMBER 2004 − REVISED DECEMBER 2004
AUTO MODE FUNCTIONAL DESCRIPTION
AM Faults
AM faults are;
D
D
D
D
D
Under and over voltage faults
Over current faults
Under current (dc modulated) fault
Thermal shutdown fault
Watch dog oscillator fault
Any one of these faults will cause the port to shutdown.
Over/Under Voltage Fault
Over/under voltage faults are only processed after power up has completed. The TPS2384 measures the
voltage between the P and N pin and if this voltage drops below the under voltage threshold (typical 43 V) or
the over voltage threshold (53 V) the voltage timer is turned on. When the voltage timer reaches its time out limit
that is set between 2 ms to 5 ms the corresponding port will be turned off and the UV/OV fault bit is set in the
port status register. If the over/under voltage condition goes away prior to the voltage timer reaching its limit the
timer is reset and waits for the next event. Figure 6 shows a voltage fault lasting for more then 2 ms that has
caused the port to shutdown.
Port P pin
Port turning
off
Port N pin
10 V/div.
t − Time − 2 ms/div.
Figure 6.
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SLUS634A − NOVEMBER 2004 − REVISED DECEMBER 2004
AUTO MODE FUNCTIONAL DESCRIPTION
Over Current or Current Limit Faults
Over current or current limit faults are conditions when the load current that is being sensed trips either the over
current comparator (350 mA to 400 mA) or the max current comparator (400 mA to 450 mA) and turns on the
over current timer. When the over current timer reaches its time out limit that is set between 50 ms to 80 ms the
corresponding port is turned off and the over current bit is set in the port status register. If the over current
condition goes away prior to the over current timer reaching its limit the timer is reset and waits for the next event.
Figure 7 shows an over current fault lasting more than 50 ms that has caused the port to shut off.
Port shuts off
Port 1
100 mA/div.
Port N pin
10 V/div.
t − Time − 10 ms/div.
Figure 7.
Under Current Fault (DC Modulated Disconnect)
Under current fault (dc modulated disconnect) is a condition when the load current that is being measured drops
below 7.5 mA and turns on the disconnect timer. If the disconnect timer reaches its time out limit that is set
between 300 ms to 400 ms the corresponding port is turned off and the load disconnect bit is set in the port status
register. If the under current condition goes away prior to the disconnect timer reaching its limit the timer is reset
and the port remains powered.
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SLUS634A − NOVEMBER 2004 − REVISED DECEMBER 2004
AUTO MODE FUNCTIONAL DESCRIPTION
Figure 8 shows dc disconnect event. In this setup the load current was set right above the 7.5 mA threshold.
The duty cycle of the load was then adjusted until the point within the disconnect window of 300 ms to 400 ms.
Port shuts off
N pin
10 V/div.
>300 ms
<300 ms
Port current
5 mA/div.
0 mA
0V
t − Time − 100 ms/div.
Figure 8.
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SLUS634A − NOVEMBER 2004 − REVISED DECEMBER 2004
POWER MANAGEMENT MODE FUNCTIONAL DESCRIPTION
Power Management Mode (PMM)
Power management mode (PMM) has been designed to work efficiently with simple low-cost micro controllers
such as those in the MPS430 family.
The power management mode has 13 self contain functions that are needed to perform all your power
management. You simply write/read through the I2C pins and wait for the function done bit to be set. If an A/D
measurement was performed during the function the results can be access by going to the read mode and
addressing the proper register.
13 Functions
D Disable: Disables the port.
D Discovery 1: Enables the discovery 1 condition which applies a 4.4 V across the PD and measure current
and store the resulting current.
D Discovery 2: Enables the discovery 2 condition which applies a 8.8 V across the PD and measure and store
the resulting current.
D V Sample: Measure the voltage between the P and N pins and store the result in the A/D voltage register.
D Legacy: Enables the 3.5-mA current source for measuring capacitance and measure the voltage across
the P and N terminals and store the result in the A/D voltage register.
D Classify: Enables the classification condition which applies 17.7 V across the PD and measure and store
the resulting current.
D Rup Pwr: Turn on the output switch while controlling the current beginning delivery to the PD until the PD
current needs are met or the max current is reached.
D C Sample: Continues sample mode cycle performing 31 current measurements and 1 voltage
measurement. After each measurement the contents for the appropriate register is updated.
D
D
D
D
D
20
Rdwn: Turn off the output switch while controlling current until output current reaches 0 mA.
AC Low: Turn on ac low driver circuit.
AC High: Turn on ac high driver circuit.
ISample: Measure the current and store the result in the A/D current register.
TSample: Measure the internal die temperature and store the result in the A/D temperature register.
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Wait for Next
Function Call
Set Done Bit
Apply 8.8V
(Imax 5mA)
To Chnl
4mS Delay
Start A2D
Measure Chnl I
(18mS)
Set Done Bit
Wait for Next
Function Call
Apply 4.4V
(Imax 5mA)
To Chnl
4mS Delay
Start A2D
Measure Chnl I
(18mS)
Set Done Bit
Wait for Next
Function Call
Enable
Control
Enable
Control
Power Down
Reset all
Functions
Discover 2
0010
Discover 1
0001
Disable
0000
Set Done Bit
Wait for Next
Function Call
Wait for Next
Function Call
Apply 18V
(Imax 100mA)
To Chnl
Measure Chnl I
(18mS)
Enable
Control
Classify
0101
Set Done Bit
Measure Chnl V
(18mS)
Set Done Bit
Wait for Next
Function Call
Apply 2.5mA
(Vmax 18) to
Chnl
Enable
Control
Enable
Diff Amp
Av 0.107
Measure Chnl V
(18mS)
Legacy
0100
V Sample
0011
Set Done Bit
Wait for Next
Function Call
Wait for Next
Function Call
Wait for Next
Function Call
Set Done Bit
Set Done Bit
Clear On Read
Enable
OVR I , Ovr V
& Und V
Comparators
If 0111
Repeat
Pwr Off
Ramp Down
Rdwn
1000
Measure Chnl V
(1 Sample)
Measure Chnl I
(31 Samples)
C Sample
0111
Wait for Next
Function Call
Set Done Bit
Measure Chnl V
(18mS)
Apply AC Low
Voltage
AC Low
1001
2. Times shown are typical and set by Rbias, and Ct.
and Resistor Register value is held.
Wait for Next
Function Call
Set Done Bit
Measure Chnl V
(18mS)
Apply AC High
Voltage
AC High
1010
called. Example Function 1 − Port Voltage remains at 4.4V
1. Each Function State remains set until a new function is
Notes:
Latch State
Power On
Ramp Pwr
1.4A/mSec
Rup/Pwr
0110
Decoder
Control Register
I2C
Wait for Next
Function Call
Set Done Bit
Measure Chnl I
(18mS)
I Sample
1011
Wait for Next
Function Call
Set Done Bit
Measure Die
Temperature
(18mS)
T Sample
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SLUS634A − NOVEMBER 2004 − REVISED DECEMBER 2004
POWER MANAGEMENT MODE FUNCTIONAL DESCRIPTION
Figure 9.
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SLUS634A − NOVEMBER 2004 − REVISED DECEMBER 2004
POWER MANAGEMENT MODE FUNCTIONAL DESCRIPTION
PMM Discovery 1
PMM discovery 1 function waveforms for the N and CINT pins are shown in Figure 10. The measurement is
being performed using 25 kΩ impedance between the P and N pin. The discovery 1 voltage is allowed to settle
for approximately 5 ms before the A/D begins integrating. The voltage on the CINT pin shows the A/D cycle.
There are 4 distinct regions to any A/D cycle, pre-charge to know starting voltage, charge time, coarse discharge
time and fine discharge time. CINT pin is very high impedance therefore extreme care must be taken to avoid
any noise or leakage affecting this pin. For the measurements where CINT voltage is shown a buffer was used
to prevent performance degradation. The A/D measurement time is approximately 18 ms. The entire discovery
1 function takes approximately 22 ms to complete. The function remains set and the data in the register remains
until another function is called. At the end of the fine discharge ramp the data is stored in the resistor register
and the done bit is set.
N pin voltage
10 V/div.
Coarse discharge
Charge
Fine discharge
Pre charge
CINT pin voltage
1 V/div.
2 V/offset
t − Time − 10 ms/div.
Figure 10.
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SLUS634A − NOVEMBER 2004 − REVISED DECEMBER 2004
POWER MANAGEMENT MODE FUNCTIONAL DESCRIPTION
PMM Discovery 2
PMM discovery 2 function waveforms for the N and CINT pins are shown in Figure 11. Again the measurement
is being performed using 25 kΩ impedance between the P and N pin. The discovery 2 function was call after
a discovery 1 function so the voltage ramps from 4.4 V to 8.8 V below the P pin. The discovery 2 voltage is given
5 ms to settle before the A/D begins to integrate. At the end of the fine discharge ramp the data is stored in the
resistor register and the done bit is set.
Coarse discharge
Charge
Fine discharge
Pre charge
CINT pin voltage
1 V/div.
2 V/offset
t − Time − 10 ms/div.
Figure 11.
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SLUS634A − NOVEMBER 2004 − REVISED DECEMBER 2004
POWER MANAGEMENT MODE FUNCTIONAL DESCRIPTION
PMM Classification
PMM classification function looks similar to discovery 1 and 2 except that the voltage between the P and N pins
regulates to approximately 17.5 V.
PMM Legacy
PMM legacy function is used to detect PDs that are non compliant. Legacy detection uses a current source
(typically 3.5 mA) as a test current while the A/D measures the average voltage for approximately 18 ms. The
waveform shown in Figure 12 is the legacy function charging a 10-µF capacitor. The capacitance charges to
a value that is no greater than 20 V below the P port voltage.
Port Voltage
10 V/div
VCINT 1 V/div
VOFFSET = 2 V
t − Time − 10 ms/div.
Figure 12.
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SLUS634A − NOVEMBER 2004 − REVISED DECEMBER 2004
POWER MANAGEMENT MODE FUNCTIONAL DESCRIPTION
5000
4500
4000
3500
Count
3000
2500
2000
1500
1000
y = 478x−1.0133
500
0
0
10
20
30
40 50 60 70
Capacitor − mF
80
90
100 110
Figure 13.
PMM Rup Pwr
PMM RUP power function turns on the port power by ramping up the current that is being delivered to the load
in a controlled fashion. The output current ramps from 0 mA to IMAX (typically 425 mA) in approximately 500 µs.
Figure 14 shows the output voltage and current turning on for a 250-mA load.
N pin voltage
10 V/div.
Port current
100 mA/div.
t − Time − 100 µs/div.
Figure 14.
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SLUS634A − NOVEMBER 2004 − REVISED DECEMBER 2004
POWER MANAGEMENT MODE FUNCTIONAL DESCRIPTION
PMM RDWN
PMM RDWN function turns off the port power by ramping down the current in a controlled fashion. The output
current ramps from IMAX (typically 425 mA) to 0 mA in approximately 500 µs. Figure 15 shows the output voltage
and current shutting down for a 250-mA load.
Port current
100 mA/div.
N pin voltage
10 V/div.
t − Time − 100 µs/div.
Figure 15.
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SLUS634A − NOVEMBER 2004 − REVISED DECEMBER 2004
MISCELLANEOUS FUNCTIONAL DESCRIPTION
Watch Dog Timer
TPS2384 has two watch dog timers. One monitors the I2C clock and the other monitors the internal clock. When
auto mode is selected and the watch dog timer has not been disable only the internal clock is monitored. When
in power management mode and the watch dog timer has not been disable than both the I2C and internal clocks
are monitored. If there is no I2C clock activity for approximately 2 seconds than all ports are disable. There are
three means to enable ports after a I2C clock fault and they are:
1. Hard power reset
2. PORB pulse
3. Writing a software reset to the common control register.
In both auto mode and power management mode if the internal oscillator is lost for more than 20 ms all ports
are disabled.
Loss of these signals is considered catastrophe since the system loses its ability talk to each port. Therefore
the WD timers disabling all ports protects the system from potential catastrophe failures.
This function can be easily over ridden by setting the WD_DIS pin high.
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SLUS634A − NOVEMBER 2004 − REVISED DECEMBER 2004
MISCELLANEOUS FUNCTIONAL DESCRIPTION
I2C Interface Description
The serial interface used in the TPS2384 is a standard 2-wire I2C slave architecture. The standard bi-directional
SDA lines of the I2C architecture are broken out into independent input and output data paths. This feature
simplifies earth grounded controller applications that require opto-isolators to keep the 48-V return of the
Ethernet power system floating. For applications where opto-isolation is not required, the bi-directional property
of the SDA line can be restored by connecting SDA_I to SDA_O. The SCL line is a unidirectional input only line
as the TPS2384 is always accessed as a slave device and it never masters the bus.
Data transfers that require a data-flow reversal on the SDA line are 4-byte operations. This occurs during a
TPS2384 port read cycle where a slave address byte is sent, followed by a port/register address byte write. A
second slave address byte is sent followed by the data byte read using the port/register setup from the second
byte in the sequence.
The I2C read cycle consists of the following steps 1 through 14 and is shown in Figure 20:
1. Start Sequence (S)
2. Device address field
3. Write
4. Acknowledge
5. Register/Port address
6. Acknowledge
7. Stop
8. Start
9. Device address field
10. Read
11. Aknowledge
12. Data Transfer
13. Acknowledge
14. Stop
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SLUS634A − NOVEMBER 2004 − REVISED DECEMBER 2004
MISCELLANEOUS FUNCTIONAL DESCRIPTION
Data write transfers to the TPS2384 do not require a data-flow reversal and as such only a 3-byte operation is
required. The sequence in this case would be to send a slave device address byte, followed by a write of the
port/register address followed by a write of the data byte for the addressed port. Figure 16 is an actual 3-byte
operation showing a function call to ramp on port 3.
Power on
N pin
1st byte
SCLK
SDA − in + out
2nd byte
ACK
3rd byte
SDA − in + out
ACK
t − Time − 500 µs/div.
Figure 16.
The I2C write cycle consists of the following steps 1 through 9 and is also shown in Figure 20:
1. Start Sequence (S)
2. Device address field
3. Write
4. Acknowledge
5. Register/Port address
6. Acknowledge
7. Data for TPS2384
8. Acknowledge
9. Stop
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SLUS634A − NOVEMBER 2004 − REVISED DECEMBER 2004
MISCELLANEOUS FUNCTIONAL DESCRIPTION
First Write Byte Magnified (Address Selection Byte, Table 1)
In Figure 17 the data line (SDA) high-to-low transition while the clock (SCL) is high generates a start condition.
In this example, a device address of 00 0000 1 is then transmitted. Data low during the eighth clock pulse signals
that this is a write operation. The SDA_O line goes low on the falling edge of the 8th clock pulse, as the device
acknowledges its address.
00001 = add 1
Start
D0
DATA
D7
SCLK
Not Used
Address
t − Time − 100 µs/div.
Figure 17.
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Write
ACK
SLUS634A − NOVEMBER 2004 − REVISED DECEMBER 2004
MISCELLANEOUS FUNCTIONAL DESCRIPTION
Second Write Byte Magnified (Port/Register Selection, Table 2)
Figure 18 shows the expansion of the second byte of operation. After the Port/Register acknowledge bit, the
host transmits the data 0 0010 0 10 selecting write control register 1 for port 3. If a common register is selected
than the port information is not used. This sets up the path for the 3rd byte during the write cycle which will be
directed to call a function for control of port 3.
D7 CLK
Byte 1 ACK
2rd byte
WRT CNTRL Reg1
Port 3
Byte 2 ACK
t − Time − 100 µs/div.
Figure 18.
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SLUS634A − NOVEMBER 2004 − REVISED DECEMBER 2004
MISCELLANEOUS FUNCTIONAL DESCRIPTION
Third Write Byte (Port Control Byte, Any Write Control Register)
Figure 20 shows an expansion of the third byte of the operation. After the Port/Register acknowledge bit, the
host transmits the data 00 00 0110, which is the TPS2384 Ramp−Up/Power Function. The TPS2384
acknowledges the data byte by pulling the SDA line low for one clock cycle. After the acknowledge pulse, the
host generates a Stop condition by releasing the data line while the clock line is high.
3rd byte
Port
Powers
D7 CLK
Byte 2 ACK
0110 = PWR Port
Byte 3 ACK
t − Time − 100 µs/div.
Figure 19.
The I2C interface and the port read write registers are held in active reset until input voltage is within specification
and the internal POR timer has timed out.
Start/Stop
The high-to-low transition of SDA while SCL is high defines the start condition. The low to high transition of SDA
while SCL is high defines the stop condition. The master device initiates all start and stop conditions.
A first serial packet enclosed within start and stop bits, consists of a 7-bit address field, read/write bit, and the
acknowledge bit. The acknowledge bit is always generated by the device receiving the address or data field.
Five of the seven address bits are used by the TPS2384. The sixth and seventh bits are placeholders for future
expansion. During a write operation to the TPS2384 from the master device, the data field is 8 bits long. During
a read operation where the TPS2384 is writing to the master device, the data field is also 8 bits long.
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SLUS634A − NOVEMBER 2004 − REVISED DECEMBER 2004
MISCELLANEOUS FUNCTIONAL DESCRIPTION
Chip Address
The address field of the TPS2384 is 8 bits long and contains 5 bits of device address select and a read/write
bit as and two spare bits per Table 1. The leading two bits are not used and are reserved for future port
expansion. The five device address select bits follow this plan. These bits are compared against the hard-wired
state of the corresponding device address select pins (A1−A5). When the field contents are equivalent to the
pin logic states, the device is addressed. These bits are followed by LSB bit, which is used to set the read or
write condition (1 for read and 0 for write). Following a start condition and an address field, the TPS2384
responds with an acknowledge by pulling the SDA line low during the 9th clock cycle if the address field is
equivalent to the value programmed by the pins. The SDA line remains a stable low while the 9th clock pulse
is high.
START/STOP SEQUENCE
Clock Data 1 Value
’
R/W
Bit
Clock Data 0 Value
START
CONDITION (S)
Clock Data 1 Value
SDA
Clock Data 1 Value
SCL
STOP
CONDITION (P)
Write Cycle
Data from
Master to
TPS2384
Stop Bit
Register/Port
Address
D7 D6 D5 D4 D3 D2 D1 D0
Ack Bit
R/W
Bit
R/W
Bit
Device Address
R/W=1
Data from
TPS2384 to
Master
StopB it
Register/Port
Address
Ack Bit
Device Address
R/W=0
A7 A6 A5 A4 A3 A2 A1 A0
Start Bit
D7 R3 R2 R1 R0 P2 P1 P0
Ack Bit
A7 A6 A5 A4 A3 A2 A1 A0
Ack Bit
SDA_O
Start Bit
Read Cycle
SDA_I
Ack Bit
Device Address
R/W=0
D7 R3 R2 R1 R0 P2 P1 P0
Ack Bit
Start Bit
SDA_O
A7 A6 A5 A4 A3 A2 A1 A0
Ack Bit
SDA_I
D7 D6 D5 D4 D3 D2 D1 D0
Figure 20. I2C Read/Write Cycles
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SLUS634A − NOVEMBER 2004 − REVISED DECEMBER 2004
MISCELLANEOUS FUNCTIONAL DESCRIPTION
Chip Addressing
Table 1 shows the bit assignments during the addressing cycle.
Table 1. Address Selection Field
BIT
FUNCTION
A7
Future expansion (not used)
A6
Future expansion (not used)
A5
Device address. Compared with pin A5
A4
Device address. Compared with pin A4
A3
Device address. Compared with pin A3
A2
Device address. Compared with pin A2
A1
Device address LSB. Compared with pin A1
A0
Read/Write
Port/Register Cycle
After the chip address cycle, the TPS2384 accepts eight bits of port/register select data as defined in Table 2.
The SCL line high-to-low transition after the eighth data bit then latches the selection of the appropriate internal
register for the follow on data read or write operation. After latching the eight-bit data field, the TPS2384 pulls
the SDA line low for one clock cycle, for the acknowledge pulse.
Data Write Cycle
For a data write sequence, after the Port/Register address cycle, the TPS2384 accepts the eight bits of data
as defined in the tables below. The data is latched into the previously selected Write Register, and the TPS2384
generates a data acknowledge pulse by pulling the SDA line low for one clock cycle. Common register functions
act on all ports simultaneously. Per port registers are specific to the target port only.
To reset the interface, the host or master subsequently generates a stop bit by releasing the SDA line during
the clock-high portion of an SCL pulse.
Data Read Cycle
For a data read sequence, after the register acknowledge bit, the master device generates a stop condition. This
is followed by a second start condition, and retransmitting the device address as described in chip address
above. For this cycle, however, the R/W bit is set to a 1 to signal the read operation. The TPS2384 again
responds with an acknowledge pulse. The address acknowledge is then followed by sequentially presenting
each of the eight data bits on the SDA line (MSB first), to be read by the host device on the rising edges of SCL.
After eight bits are transmitted, the host acknowledges by pulling the SDA line high for one clock pulse. The
completed data transfer is terminated with the host generating a stop condition.
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SLUS634A − NOVEMBER 2004 − REVISED DECEMBER 2004
MISCELLANEOUS FUNCTIONAL DESCRIPTION
Table 2. Common Write Register Port /Register Addressing
BIT
D7
FUNCTION
STATE
PRESET STATE
Future expansion
D6
Register select MSB
D5
Register select Bit 3
D4
Register select Bit 2
D3
Register select LSB
D2
Future expansion
D1
Port address MSB
D0
Port address
0
0000 = common read − port fault status, ID and rev
0001 = common control write – software reset, ports shutdown and ac disc
0010 = write control reg 1 − function calls and discovery, disable fault disable
0011 = write control reg 2 – classify current limit, power over I cntrl & AD abort
0100 = read status reg 1 – fault status, class Infor, power Infor
0101 = read status reg 2 – detection status
0110 = read R result reg 1 – A/D resistor register (lower bits)
0111 = read R result reg 2 – A/D resistor register (upper bits)
1000 = read V result reg 1 – A/D voltage register (lower bits)
1001 = read V result reg 2 – A/D voltage register (upper bits)
1010 = read I result reg 1– A/D current register (lower bits)
1011 = read I result reg 2 – A/D current register (upper bits)
1100 = read T result reg 1 – A/D temperature register (lower bits)
1101 = read T result reg 2 – A/D temperature register (upper bits)
1110 = spare
1111 = common write – test disable timer, discovery loop
0000
0
00 = port 1
01 = port 2
10 = port 3
11 = port 4
00
Table 3. Common Register Read Register, Address = 0000 Port Fault Status &Chip ID/Rev
BIT
FUNCTION
STATE
PRESET STATE
D7
Port 4 general
Fault status
0 = no fault
1 = port fault
0
D6
Port 3 general
Fault status
0 = no fault
1 = port fault
0
D5
Port 2 general
Fault status
0 = no fault
1 = port fault
0
D4
Port 1 general
Fault status
0 = no fault
1 = port fault
0
Chip rev
00 = rev −
01 = rev 1
10 = rev 2
11 = rev 3
00
Chip ID
00 = TPS2383
01= TPS2383A
10 = TPS2384
11 = reserve
10
D3
D2
D1
D0
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35
SLUS634A − NOVEMBER 2004 − REVISED DECEMBER 2004
MISCELLANEOUS FUNCTIONAL DESCRIPTION
Table 4. Common Register Write Register, Address = 1111 Test Register
BIT
FUNCTION
STATE
PRESET STATE
D7
Spare
0
D6
TSD Test
0 = normal
1 = Force TSD condition
0
D5
Discovery 1 & 2
0 = normal
1 = all 4-port discovery 1 and discovery 2 − halt
0
D4
Discovery timers
0 = normal (4-ms discovery 1 & discovery 2)
1 = timers Disable
0
D3
POR disable
0 = normal POR timing
1 = force POR to a non-reset state
0
D2
DC disconnect timer
0 = normal
1 = 300-ms disconnect timer disable
0
D1
TED timer
0 = normal
1 = 750-ms ted timer disable
0
D0
Spare
0
Table 5. Common Control RegisterWrite Register, address = 0001
BIT
Spare
D6
Spare
STATE
PRESET STATE
0
0
D5
TSD fault
0 = Normal
1 = Fault Disable
D4
AC high
0 = Off
1 = Osc Hi Driver On
0
D3
AC low
0 = Off
1 = Osc Lo Driver On On
0
D2
Over/under voltage
faults
0 = Normal
1 = Faults Disable
0
D1
All Ports Disable
0 = Normal
1 = All Ports shut down (no ramp)
0
D0
36
FUNCTION
D7
Software RESET
0 = Normal operation
1 = Reset all circuits and start a POR timing cycle
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0
0
SLUS634A − NOVEMBER 2004 − REVISED DECEMBER 2004
MISCELLANEOUS FUNCTIONAL DESCRIPTION
Table 6. Individual Port Write Control Register 1 Address 0010 (One per port)
Bit
FUNCTION
D7
Spare
D6
Spare
State
PRESET STATE
0
0
D5
Discovery Fault Disable
0 = Normal mode
1 = Disable internal Discovery Fault Limits
D4
Disconnect Disable
0 = Normal mode
1 = Disable the effect of the logic signal from the Disconnect detection circuits
(used for test only)
D3
Function Bit 3
D2
Function Bit 2
D1
Function Bit 1
D0
Function Bit 0
0000 = Disable Function (Power Down & reset all functions)
0001 = Discovery 1 Function
0010 = Discovery 2 Function
0011 = Port Voltage Sample Function
0100 = Legacy Detection Function
0101 = Classification Function
0110 = Ramp Up/Power Function
0111 = Continuous Sample Function
1000 = Ramp Power Down Function
1001 = AC Low
1010 = AC High
1011 = Port Current Sample Function
1100 = Die Temperature Sample Function
1101 = Spare
1110 = Spare
1111 = Spare
0
0
0000
Table 7. Individual Port Write Control 2 Write register, address = 0011 (One per port)
BIT
FUNCTION
STATE
PRESET STATE
D7
Spare
0
D6
Spare
0
D5
Spare
0
D4
Port Enable
0 = Normal
1 = Port Disable
D3
A/D Start
0 = Normal
1 = Start A/D (self Clearing)
0
D2
A/D Abort
0 = Normal
1 = Abort
0
D1
Power Mode
Class Over Current
Threshold Enable
0 = Full Current (375mA) Over Current Threshold
1 = Deny Current Beyond Class 1 (90mA) or Class 2 (160mA) depending on
Class contents in Register 4.
D0
Spare
0
0
0
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37
SLUS634A − NOVEMBER 2004 − REVISED DECEMBER 2004
MISCELLANEOUS FUNCTIONAL DESCRIPTION
Table 8. Port Status Port 1 through 4 Read Register, address = 0100 (One per port)
BIT
FUNCTION
D7
Discovery Status
D6
Function Done Bit
D5
Port Class
D4
Port Class
D3
Port Class
D2
Fault status (MSB)
D1
Fault status
D0
Fault status (LSB)
STATE
PRESET STATE
0 = Normal
1 = Discovery Fail
0
0 = Normal
1 = Function Complete (Self Clearing by new a function Write)
000 = Class 0
001 = Class 1
010 = Class 2
011 = Class 3
100 = Class 4
000
000 = No Faults
001 = UV/OV fault
010 = Thermal Fault
011 = Overload Current > 50mS fault
100 = Load disconnect
101 = Reserved for future
110 = Reserved for future
111 = Reserved for future
000
0
Table 9. Port Mode Status Port 1 through 4 Read Register, address = 0101 (One per port)
BIT
38
FUNCTION
STATE
PRESET STATE
D7
Spare
0
D6
Spare
0
D5
Spare
0
D4
Watch dog timer
0 = Not Active
1 = Active
D3
A/D status
0 = Not Active
1 = Active
D2
Detection status (MSB)
D1
Detection status
D0
Detection status (LSB)
000 = Disable
001 = Searching
010 = Power Delivery
011 = Fault
100 = Test
101= Other Fault
110 = undefined
111 = undefined
0
0
000
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SLUS634A − NOVEMBER 2004 − REVISED DECEMBER 2004
MISCELLANEOUS FUNCTIONAL DESCRIPTION
A/D Register ( Resistance, Voltage, Current & Temperature)
Table 10. Analog to Digital Lower Bits Resistor Register Read Register, Address = 0110 (One per port)
Bit
Function
D7
A/D bit 7
D6
A/D bit 6
D5
A/D bit 5
D4
A/D bit 4
D3
A/D bit 3
D2
A/D bit 2
D1
A/D bit 1
D0
A/D bit 0
State
PRESET STATE
A/D Lower Bits
0
Table 11. Common Analog to Digital Upper Bits Resistor Register/Read Register,
Address = 0111 (One per port)
Bit
Function
State
D7
Resistor measurement
complete
0 = Measurement active (Bit set low at the start of Discovery 1 or Discovery 2)
1 = Measurement complete (Bit set high after A/D is completed during Discovery 1
or Discovery 2)
PRESET STATE
0
D6
A/D bit 14
D5
A/D bit 13
D4
A/D bit 12
D3
A/D bit 11
A/D Upper bits
0
D2
A/D bit 10
D1
A/D bit 9
D0
A/D bit 8
Table 12. Analog to Digital Lower Bits Voltage Register/Read Register, Address = 1000 (One per port)
Bit
Function
D7
A/D bit 7
D6
A/D bit 6
D5
A/D bit 5
D4
A/D bit 4
D3
A/D bit 3
D2
A/D bit 2
D1
A/D bit 1
D0
A/D bit 0
State
PRESET STATE
A/D lower bits
0
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39
SLUS634A − NOVEMBER 2004 − REVISED DECEMBER 2004
MISCELLANEOUS FUNCTIONAL DESCRIPTION
Table 13. Common Analog to Digital Upper Bits Voltage Register/Read Register,
Address = 1001 (One per port)
BIT
FUNCTION
D7
Voltage measure complete
D6
A/D bit 14
D5
A/D bit 13
D4
A/D bit 12
D3
A/D bit 11
D2
A/D bit 10
D1
A/D bit 9
D0
A/D bit 8
STATE
PRESET STATE
0 = Measurement active (Bit set low when A/D begins a voltage measurement)
1 = Measurement complete (Bit set high after A/D has completed a voltage measurement)
0
A/D upper bits
0
Table 14. Analog to Digital Lower Bits Current Register/Read Register, Address = 1010 (One per port)
BIT
FUNCTION
D7
A/D bit 7
D6
A/D bit 6
D5
A/D bit 5
D4
A/D bit 4
D3
A/D bit 3
D2
A/D bit 2
D1
A/D bit 1
D0
A/D bit 0
STATE
PRESET STATE
A/D Lower Bits
0
Table 15. Common Analog to Digital Upper Bits Current Register/Read Register,
Address = 1011 (One per port)
BIT
40
FUNCTION
D7
Current Measure Complete
D6
A/D bit 14
D5
A/D bit 13
D4
A/D bit 12
D3
A/D bit 11
D2
A/D bit 10
D1
A/D bit 9
D0
A/D bit 8
STATE
PRESET STATE
0 = Measurement active (Bit set low when A/D begins a current measurement)
1 = Measurement complete (Bit set high after A/D has completed a current measurement)
0
A/D upper bits
0
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SLUS634A − NOVEMBER 2004 − REVISED DECEMBER 2004
MISCELLANEOUS FUNCTIONAL DESCRIPTION
Table 16. Analog to Digital Lower Bits Temperature Register/Read Register, Address = 1100 (One per port)
BIT
FUNCTION
D7
A/D bit 7
D6
A/D bit 6
D5
A/D bit 5
D4
A/D bit 4
D3
A/D bit 3
D2
A/D bit 2
D1
A/D bit 1
D0
A/D bit 0
STATE
PRESET STATE
A/D lower bits
0
Table 17. Common Analog to Digital Upper Bits Temperature Register/Read Register,
Address = 1101 (One per port)
BIT
FUNCTION
D7
Temperature Measure
Complete
D6
A/D bit 14
D5
A/D bit 13
D4
A/D bit 12
D3
A/D bit 11
D2
A/D bit 10
D1
A/D bit 9
D0
A/D bit 8
STATE
PRESET STATE
0 = Measurement active (Bit set low when A/D begins a temperature measurement)
1 = Measurement complete (Bit set high after A/D has completed a temperature
measurement)
0
A/D upper bits
0
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41
SLUS634A − NOVEMBER 2004 − REVISED DECEMBER 2004
TPS 2384 AC DRIVE APPLICATION SCHEMATIC
AC_Hi & Low W/O External FET Configurations
6.3 V
59
Function call
AC high 1010
AC_HI
50
Common reg 0001
Bit D4 AC high
V48
60
Function call
AC low 1001
To pin 1
+
Common reg 0001
Bit D3 AC low
3.3 V
Figure 21.
42
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AC_LO
51
To pin N
SLUS634A − NOVEMBER 2004 − REVISED DECEMBER 2004
TPS2384 SYSTEM BLOCK DIAGRAM
SWITCH/HUB
CT CHOKE
1
TX
2
CT CHOKE
3
RX
6
PPTC
FUSE
RJ−45
RJ−45
4
5
W/GRN
GRN
W/ORG
ORG
BLUE
W/BLUE
CT CHOKE
1
RX
2
3
6
4
5
8
568A
−
W/BRN
BRN
UP TO 350ft
CATEGORY 5 CABLE
7
PD
SIGNATURE
PD
DC−DC
SUPPLY
8
568A
Optically Coupled
I2C Serial Bus
48V
SUPPLY
+
7
CT CHOKE
TX
P
V48 TPS2384
N
GND
PSE
(1 PORT)
RET
POWERED DTE
MSP430
CONTROLLER
Figure 22.
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43
SLUS634A − NOVEMBER 2004 − REVISED DECEMBER 2004
TPS2384 BASIC 4 PORT (PMM) ISOLATED CONFIGURATION WITH AC DISCONNECT
TPS2384 basic 4-port isolated configuration with ac disconnect.
Function
7.5K
Auto
68uF
0.1uF
220pF
124K
0.1uF
0.1uF
0.1uF
− +
7.5K
7.5K
7.5K
MS
470nF
Cint4
45
Ret4
44
TPS2384
Quad PSE Controller
41
40
P3 39
N3 38
12 Ret2
Ret3
37
13 Cint2
14
Cint3
36
15
34
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
9.1K
0.5W
48V
BUS
9.1K
0.1uF
3.9K
0.5W
270
270
3.9K
3.9K
SDA_Out
INT
SCL
Open Drain
SDA_In
Open Drain
POR
Open Drain
GND CPU
Figure 23.
44
3.9K
NEG
270
VDD CPU
0.027uF
35
3.9K
POS
0.027uF
N4 43
P4 42
SDA−I
SDA−O
A1
A2
A3
A4
A5
0.027uF
470nF
46
RJ45−5
Xformer
RJ45−5
Xformer
0.027uF
47
INT
AltA/B
WD_Dis
DG
V3
SCL
RJ45−5
Xformer
470nF
48
RJ45−5
Xformer
1
2
3
4 Cint1
5 Ret1
6 N1
7 P1
8
9
10
P2
11 N2
PORB
AG2
V48
V6.3
V10
AG1
RG
Rbias
V2.5
Ct
SYN
AC_hi
AC_lo
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
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470nF
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